TODO
====

x UART
x Timer
x mx51-pins
x efikamx.c initialization yikes!
x MMU, interrupts, cache initializations
o Add AAI mode to write.  Not critical, but we'll probably appreciate
  it if we write Apex to SPI flash.  
x Test on target to working console.
x MMC, adequate for booting
x Linking FAT and EXT2 drivers to MMC.  This ought to work as the
  underlying driver has a simple block interface
x Fix writing of APEX image to SD card as to skip the partition
  table.  Need to make a partition table with room for APEX.
o Construct a kernel image that we can use to boot.
x Initialize PMIC. No need to since we cannot control it on the most
  recent hardware.
o Go!
x Booting stock and armhf, though armhf doesn't initialize video.
x Add IDE driver
x Fix platform init of IDE driver.  (some improvement)
x Fix baudrate calc for MXC driver. (some improvement)
o Fix ATA timing setup


NOTES
=====

o 2011.sep.16
  o Some cleaup and feature fixes
  o Added alternative setup via DCD

o 2011.sep.15
  o ATA/IDE driver working.
    o Forked from CF driver.
    o Work done to integrate ideas form the CF driver.
    o Need to do more since the CF driver is inherently more complex
      due to register access limitations.
    o Still need to move the platform specific initialization out of
      the driver.
  o Need to fixup the baudrate calc for the serial driver.  It's
    staticly defined at the moment.

o 2011.sep.9
  o Looking into IDE driver
    o Looks like they use a generic IDE PIO driver
    o There is a more complex PATA driver that is defined in the code of UB
    o Seems like a simple thing to use the old CF driver and
      genericize it a little 
    o Should do some work to share code on this one since there is
      some real logic in there  
  o Also, should move the generic portions of the esdhc driver into a
    common location so that other platforms can gain access to HC
    cards

o 2011.sep.02
  o Booting armhf.  Video doesn't initialize.  Ouch.  We do have
    support for HC cards, though.
  o Interesting observations based on dmesgs.
    o No ethernet device available when APEX boots
    o No detection of other USB devices attached to the system such as
      keyboard and mouse
    o There is a DMA sound buffer allocation made for armhf that
      doesn't appear for the APEX boot.


im load ext2://1/uImage-2.6.31.14.23-efikamx
im load -l 0x94000000 ext2://1/uInitrd-2.6.31.14.23-efikamx
boot console=ttymxc0,115200 root=/dev/mmcblk0p2 rootwait rw video=imx-ipuv3-fb:1024x600M-16@60 rootfstype=ext4 lpj=3997696


o 2011.aug.30
  o Working OK.  Fixed environment write which was an error in flash read. 

o 2011.aug.29
  o First boot!  Not reproducible, though.
  o apex load commands:

im load               ext2://3/uImage-2.6.31.14.24-efikamx
im load -l 0x92000040 ext2://3/uInitrd-2.6.31.14.24-efikamx
boot console=ttymxc0,115200 root=/dev/sda2 rootwait rw splash



o 2011.aug.26
  o Received replacement device and debug board.  SD slot works again.
  o Booting Linux from uboot yields the following atags:

90000100 : 00000005 54410001 00000000 00000000  ......AT........
90000110 : 00000000 00000003 54410007 00051030  ..........AT0...
90000120 : 00000004 54410002 20000000 90000000  ......AT... ....
90000130 : 00000010 54410009 736e6f63 3d656c6f  ......ATconsole=
90000140 : 31797474 6f6f7220 642f3d74 732f7665  tty1 root=/dev/s
90000150 : 20326164 746f6f72 74696177 20777220  da2 rootwait rw 
90000160 : 65697571 70732074 6873616c 000ca500  quiet splash....
90000170 : 00000004 54420005 92000040 00653919  ......BT@....9e.
90000180 : 00000000 00000000 08106182 b6418040  .........a..@.A.

 5 w, ATAG_CORE		zeroes
 3 w, ATAG_REVISION	rev: 0x00051030
 4 w, ATAG_MEM		size: 0x20000000, start: 0x90000000
16 w, ATAG_CMDLINE	console=tty1 root=/dev/sda2 rootwait rw quiet splash
 4 w, ATAG_INITRD2	start: 0x92000040, size: 0x00653919
 0 w, ATAG_NONE

    Registers:
    r0: 0x00000000
    r1: 0x00000920
    r2: 0x90000100

  o We're using the following ATAGS.

90000100 : 00000002 54410001 00000004 54410002  ......AT......AT
90000110 : 10000000 90000000 00000004 54410002  ..............AT
90000120 : 10000000 a0000000 00000012 54410009  ..............AT
90000130 : 736e6f63 3d656c6f 6d797474 2c306378  console=ttymxc0,
90000140 : 31797474 6f6f7220 642f3d74 732f7665  tty1 root=/dev/s
90000150 : 20326164 746f6f72 74696177 20777220  da2 rootwait rw 
90000160 : 65697571 70732074 6873616c 000ca500  quiet splash....
90000170 : 00000003 54410007 00000000 00000004  ......AT........
90000180 : 54410006 00000000 00000000 00000004  ..AT............
90000190 : 54420005 94000000 00800000 00000000  ..BT............
900001a0 : 00000000 1c401800 99404090 087f3218  ......@..@@..2..

 2 w, ATAG_CORE
 4 w, ATAG_MEM		size: 0x10000000, 0x90000000
 4 w, ATAG_MEM		size: 0x10000000, 0xa0000000
18 w, ATAG_CMDLINE	console=ttymxc0,tty1 root=/dev/sda2 rootwait rw quiet splash
 3 w, ATAG_REVISION	rev: 0
 4 w, ATAG_SERIAL	low: 0, high: 0
 4 w, ATAG_INITRD2	start: 0x94000000, size: 0x00800000
 0 w, ATAG_NONE

    Registers:
    r0: 0x00000000
    r1: 0x00000920
    r2: 0x90000100

  o The kernel halts in a loop at 0x80014138

  o We have MMU enbled and we're getting into the calibration loop and
    crashing.  It may be the case that we're taking an interrupt withint
    being ready for it.

o 2011.aug.13
  o Started on PMIC.  May need to power-up before reading ID?  Really?
  o Verified the PMIC interface setup.

o 2011.aug.12
  o SD/MMC read working, no DMA and 512 block only 
  o Still, SD/MMC is working and should be adequate for booting.
  o Need to make sure that the DOS driver and such can work.
  o ubuntu boots with

    console=tty1 root=/dev/sda2 rootwait rw quiet splash

o 2011.aug.10
  o SD identify working

o 2011.aug.08
  o Thoughts on MMC driver
  o It would be clever to separate an MMC interface that meets the
    'driver' model and a hardware interface that presents a normalized
    view of the essential MMC/SD functionality.
    o Command execute.
    o Setup, clocking, IO path width

o 2011.aug.06
  o clocks derive as shown below...unsatisfactorily
  o The CCM module allows, for example, the derivation of peripheral
    clocks from any of the PLLs.  The ESDHC defaults to PLL3, but it
    could come from PLL1 or PLL2.  This should not be assumed.

o 2011.jul.18
  x spi flash driver needs to cope with small reads.  A read of 1
    bytes doesn't yield any data.  In fact, if the read is anything
    less than an even number of words the result won't be read at
    all.  I believe that the problem is that the odd sized write
    occurs in the first transaction.  It may be worthwhile special
    casing this first exchange as the read as well as the write are
    likely to be misaligned.
  o Preparing erase and program logic.
  o Write working though it is not using the AAI mode.
  o Erase working well.
  o Still need AAI version of write for better performance.

o 2011.jul.17
  x Need to restrict the number of bytes in a single SPI transaction
    to the extent of the field within the SPI control register that
    defines in.
  x May want to have a secondary limit based on the size of the FIFO
    s.t. we write in one go all of the bytes that we can write to the
    transmit FIFO and let the receive FIFO hold the received bytes.
    Then we read them all at once.

o 2011.jul.16
  o Worked through a lot of IOMUX differences.  Seems to be OK except
    for some entries that we don't have documentation to explain.
  o SPI driver working.  Able to reliably read ID and data.
  o Fixed bug in dump that caused infinite dump when size wasn't a
    multiple of 16 bytes.
  o Pushed dump fix to remotes
  o Discovered that flash read to RAM isn't reliable.  Copying from
    RAM to RAM is OK.  copy flash:0+512 0x90000000 doesn't copy the
    first four bytes.  Dump is always OK.  Even checksum appears to
    work because it uses the same region_ functions that copy uses.
    The FIFO is 64 words.

o 2011.jul.14

  From uboot

    JEDEC ID: 0xbf:0x25:0x4a
    Reading SPI NOR flash 0x40000 [0x10000 bytes] -> ram 0x975f06e8

U-Boot# md 0x70010000
70010000: 00000000 00000000 00000000 00000000    ................
70010010: 00000000 00000000 00000003 00000000    ................

  Using bdi2000, the control and config registers receive
  0x00042020 and 0x00220022
  0x01f42021

  Control
  1 Channel select
  0 DRCTRL
  2 Pre-divider
  0 Post-divider
  2 Channel mode
  0 SMC
  0 XCH
  0 HW
  0 EN

  Control, later
  1f Burst length
  1 EN

  Control, later
  1 XCH

  Config
  0 HT length
  2 SCLK CTL (inactive low)
  2 DATA CTL (inactive low)
  0 SSB POL  (active low)
  0 SSB CTL  (single burst)
  2 SCLK POL (active low, idle high)
  2 SCLK PHA (phase 1 operation)



o 2011.jul.12
  o Boot mode switches

   +---+---+---+---+
   | 3 | 2 | 1 | 0 |
   +---+---+---+---+
     |   |   |   |
     |   |   |   +-- BT_SRC[0]            
     |   |   +------ BUS_WIDTH
     |   +---------- BT_MEM_TYPE[0]
     +-------------- BT_MEM_TYPE[1]

    o The normal system boot has the value 1110.  This boots to the
      SPI flash.
    o Normal boot is SPI Flash BT_MEM_TYPE 11 and 3 address
      BT_BUS_WIDTH 1.
    o SD memory card boot has the value 0000 on the most recent
      boards.  Earlier designs used the second SDHC device so on those
      boards the value is 0001.  SDHC boot has BT_MEM_TYPE 00 and
      BT_BUS_WIDTH 0.  The BT_SRC is 0 for SDHC1 and 1 for SDHC2.

/*
 * SPI Configs
 * */
#define CONFIG_FSL_SF                   1
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH_IMX_SST
#define CONFIG_SPI_FLASH_CS             1
#define CONFIG_IMX_ECSPI
#define IMX_CSPI_VER_2_3
#define CONFIG_IMX_SPI_PMIC
#define CONFIG_IMX_SPI_PMIC_CS  0

#define MAX_SPI_BYTES           (64 * 4)




o 2011.jul.06
  o GPIO implementations complete.
  o Missing some cache initialization, especially l2

o 2011.jul.02
  o B3.12 CP15 registers for VMSA implementation, p B3-64 p1337 (really), p1339

  o Questions unanswered
    o What is the encoding for cp15 c9 wrt. Level 2 cache?
    o What is the PLATFORM block?  It's used to initialize some clock
      dividers.  There is a field called ICGC to set the dividers and
      it is set to 0x725 on our Efika and 0x124 on the EVK.
    o What is cp15 c0 c1 2,  L1NEON bit set based on ARM errata?
    o Where are the AIPS[0] and AIPS[4] registers documented?
    o This is in the efikamx.c initialization after some of the GPIO
      inits are done.  What does it do? 
	/* Setup GPIO group 2 */
	writel(0x01025200, 0x73f88000);
	/* Setup GPIO group 1 */
	writel(0x00000020, 0x73f84000);


o 2011.jul.01

  o watchdog should be a peripheral.  I suppose we could be paranoid
    and want to get it enabled really early, but what is the point?
    We're going to have more obvious problems if something in the very
    early setup fails.  Putting watchdog in a peripheral/service makes
    for nice modularity.
