/*
 * Copyright (c) 2020, MediaTek Inc. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#ifndef PLL_H
#define PLL_H

/* APMIXEDSYS Register */
#define AP_PLL_CON6		(APMIXED_BASE + 0x18)
#define CLKSQ_STB_CON0		(APMIXED_BASE + 0x20)
#define PLL_ISO_CON0		(APMIXED_BASE + 0x2C)

#define ARMPLL_CON0		(APMIXED_BASE + 0x200)
#define ARMPLL_CON1		(APMIXED_BASE + 0x204)
#define ARMPLL_CON2		(APMIXED_BASE + 0x208)
#define ARMPLL_PWR_CON0		(APMIXED_BASE + 0x20C)

#define MAINPLL_CON0		(APMIXED_BASE + 0x210)
#define MAINPLL_CON1		(APMIXED_BASE + 0x214)
#define MAINPLL_PWR_CON0	(APMIXED_BASE + 0x21C)

#define UNIVPLL_CON0		(APMIXED_BASE + 0x220)
#define UNIVPLL_CON1		(APMIXED_BASE + 0x224)
#define UNIVPLL_PWR_CON0	(APMIXED_BASE + 0x22C)

#define ETH1PLL_CON0		(APMIXED_BASE + 0x300)
#define ETH1PLL_CON1		(APMIXED_BASE + 0x304)
#define ETH1PLL_CON2		(APMIXED_BASE + 0x308)
#define ETH1PLL_CON3		(APMIXED_BASE + 0x30C)
#define ETH1PLL_PWR_CON0	(APMIXED_BASE + 0x310)

#define ETH2PLL_CON0		(APMIXED_BASE + 0x314)
#define ETH2PLL_CON1		(APMIXED_BASE + 0x318)
#define ETH2PLL_CON2		(APMIXED_BASE + 0x31C)
#define ETH2PLL_PWR_CON0	(APMIXED_BASE + 0x320)

#define SGMIPLL_CON0		(APMIXED_BASE + 0x358)
#define SGMIPLL_CON1		(APMIXED_BASE + 0x35C)
#define SGMIPLL_CON2		(APMIXED_BASE + 0x360)
#define SGMIPLL_CON3		(APMIXED_BASE + 0x364)
#define SGMIPLL_PWR_CON0	(APMIXED_BASE + 0x368)

#define CON0_BASE_EN		BIT(0)
#define CON0_PWR_ON		BIT(0)
#define CON0_ISO_EN		BIT(1)
#define CON0_RST_BAR		BIT(24)
#define CON0_POST_DIV(x)	((x) << 1)
#define CON1_PCW_CHG		BIT(31)
#define UNIV_48M_EN		BIT(27)

/* INFRASYS Register */
#define INFRA_TOP_CKMUXSEL		(INFRACFG_AO_BASE + 0x00)
#define INFRA_TOP_CKDIV1		(INFRACFG_AO_BASE + 0x08)
#define INFRA_TOP_DCMCTL		(INFRACFG_AO_BASE + 0x10)

#define INFRA_TOP_CKDIV1_SEL(x)		((x) << 0)
#define INFRA_TOP_MUX_SEL(x)		((x) << 2)
#define INFRA_TOP_DCM_EN		BIT(0)

#define INFRA_PDN_CLR0			(INFRACFG_AO_BASE + 0x44)
#define	INFRA_GLOBALCON_DCMCTL		(INFRACFG_AO_BASE + 0x50)
#define INFRA_GLOBALCON_DCMCTL_MASK	0x303
#define INFRA_GLOBALCON_DCMCTL_ON	0x303

#define INFRA_GLOBALCON_DCMDBC		(INFRACFG_AO_BASE + 0x054)
#define INFRA_GLOBALCON_DCMDBC_MASK	((0x7f << 0) | (1 << 8) | \
					(0x7f << 16) | (1 << 24))
#define INFRA_GLOBALCON_DCMDBC_ON	((0 << 0) | (1 << 8) | \
					(0 << 16) | (1 << 24))

#define INFRA_GLOBALCON_DCMFSEL		(INFRACFG_AO_BASE + 0x058)
#define INFRA_GLOBALCON_DCMFSEL_MASK	((0x7 << 0) | (0xf << 8) | \
					(0x1f << 16) | (0x1f << 24))
#define INFRA_GLOBALCON_DCMFSEL_ON	((0 << 0) | (0 << 8) | \
					(0x10 << 16) | (0x10 << 24))

/* PERI Register */
#define PERI_PDN_CLR0			(PERICFG_BASE + 0x10)
#define PERI_PDN_CLR1			(PERICFG_BASE + 0x14)

/* Top-Clock Generator */
#define CLK_CFG_0			(TOPCKGEN_BASE + 0x40)
#define CLK_CFG_1			(TOPCKGEN_BASE + 0x50)
#define CLK_CFG_2			(TOPCKGEN_BASE + 0x60)
#define CLK_CFG_3			(TOPCKGEN_BASE + 0x70)
#define CLK_CFG_4			(TOPCKGEN_BASE + 0x80)
#define CLK_CFG_5			(TOPCKGEN_BASE + 0x90)
#define CLK_CFG_6			(TOPCKGEN_BASE + 0xa0)
#define CLK_CFG_7			(TOPCKGEN_BASE + 0xb0)
#define CLK_CFG_8			(TOPCKGEN_BASE + 0xc0)
#define CLK_SCP_CFG_0			(TOPCKGEN_BASE + 0x200)
#define CLK_SCP_CFG_1			(TOPCKGEN_BASE + 0x204)

#define SCP_ARMCK_OFF_EN		0x3ff
#define SCP_AXICK_26M_SEL_EN		BIT(4)
#define SCP_AXICK_DCM_DIS_EN		BIT(0)

/* Topckgen MUX */
#define CLK_TOP_AXI_SEL_MUX_SYSPLL1_D2		(0x1 << 0)
#define CLK_TOP_MEM_SEL_MUX_DMPLL1_CK		(0x1 << 8)
#define CLK_TOP_DDRPHYCFG_SEL_MUX_SYSLL1_D8	(0x1 << 16)
#define CLK_TOP_ETH_SEL_MUX_UNIVPLL1_D2		(0x2 << 24)

#define CLK_TOP_PWM_SEL_MUX_UNIVPLL2_D4		(0x1 << 0)
#define CLK_TOP_F10M_REF_SEL_MUX_SYSPLL4_D16	(0x1 << 8)
#define CLK_TOP_NFI_INFRA_SEL_MUX_XTAL_CLK	(0x6 << 16)

#define CLK_TOP_UART_SEL_MUX_MASK		(0x1 << 0)
#define CLK_TOP_UART_SEL_MUX_CLKXTAL		(0x0 << 0)
#define CLK_TOP_SPI0_SEL_MUX_SYSPLL3_D2		(0x1 << 8)
#define CLK_TOP_SPI1_SEL_MUX_SYSPLL3_D2		(0x1 << 16)
#define CLK_TOP_MSDC50_0_SEL_MUX_UNIVPLL2_D8	(0x1 << 24)

#define CLK_TOP_MSDC30_0_SEL_MUX_UNIV48M	(0x2 << 0)
#define CLK_TOP_MSDC30_1_SEL_MUX_UNIV200M	(0x7 << 8)
#define CLK_TOP_A1SYS_HP_SEL_MUX_XTAL		(0x3 << 16)
#define CLK_TOP_A2SYS_HP_SEL_MUX_XTAL		(0x3 << 24)

#define CLK_TOP_INTDIR_SEL_MUX_UNIVPLL_D2	(0x2 << 0)
#define CLK_TOP_AUD_INTBUS_SEL_MUX_SYSPLL1_D4	(0x1 << 8)
#define CLK_TOP_PMICSPI_SEL_MUX_UNIVPLL2_D4	(0x6 << 16)
#define CLK_TOP_SCP_SEL_MUX_SYSPLL1_D8		(0x1 << 24)

#define CLK_TOP_ATB_SEL_MUX_SYSPLL_D2		(0x1 << 0)
#define CLK_TOP_HIF_SEL_MUX_SYSPLL1_D2		(0x2 << 8)
#define CLK_TOP_AUDIO_SEL_MUX_SYSPLL3_D4	(0x1 << 16)
#define CLK_TOP_U2_SEL_MUX_SYSPLL1_D4		(0x1 << 24)

#define CLK_TOP_IRRX_SEL_MUX_SYSPLL4_D16	(0x1 << 16)
#define CLK_TOP_IRTX_SEL_MUX_SYSPLL4_D16	(0x1 << 24)

#define CLK_TOP_ASM_L_SEL_MUX_SYSPLL_D5		(0x1 << 0)
#define CLK_TOP_ASM_M_SEL_MUX_SYSPLL_D5		(0x1 << 8)
#define CLK_TOP_ASM_H_SEL_MUX_SYSPLL_D5		(0x1 << 16)

#define CLK_TOP_CRYPTO_SEL_MUX_UNIVPLL_D3	(0x1 << 0)
#define CLK_TOP_SGMII_SEL_MUX_SGMIIPLL_D3	(0x1 << 8)
#define CLK_TOP_10M_SEL_MUX_XTAL_D4		(0x1 << 16)

#ifndef __ASSEMBLER__
void mtk_pll_init(void);
#endif

#endif
