/*
 * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

/* This file is autogenerated by cml-utils 2024-05-22 11:49:08 +0200.
 * Commit ID: 4970194b94e8b8ddc76bf1c463ac25c279fb0c7c
 */

/* LAN969X registers */

#ifndef LAN969X_REGS_A0_H
#define LAN969X_REGS_A0_H

#if !defined(GENMASK)
#include <lib/utils_def.h>
#endif

/*      AES:AES_REGS:AES_CR */
#define AES_AES_CR(t)             ((t) + 0x00U)

#define AES_AES_CR_UNLOCK(x)                (((x) << 24U) & GENMASK(24U, 24U))
#define AES_AES_CR_UNLOCK_M                 GENMASK(24U, 24U)
#define AES_AES_CR_UNLOCK_X(x)              (((x) & GENMASK(24U, 24U)) >> 24U)

#define AES_AES_CR_LOADSEED(x)              (((x) << 16U) & GENMASK(16U, 16U))
#define AES_AES_CR_LOADSEED_M               GENMASK(16U, 16U)
#define AES_AES_CR_LOADSEED_X(x)            (((x) & GENMASK(16U, 16U)) >> 16U)

#define AES_AES_CR_SWRST(x)                 (((x) << 8U) & GENMASK(8U, 8U))
#define AES_AES_CR_SWRST_M                  GENMASK(8U, 8U)
#define AES_AES_CR_SWRST_X(x)               (((x) & GENMASK(8U, 8U)) >> 8U)

#define AES_AES_CR_KSWP(x)                  (((x) << 1U) & GENMASK(1U, 1U))
#define AES_AES_CR_KSWP_M                   GENMASK(1U, 1U)
#define AES_AES_CR_KSWP_X(x)                (((x) & GENMASK(1U, 1U)) >> 1U)

#define AES_AES_CR_START(x)                 ((x) & GENMASK(0U, 0U))
#define AES_AES_CR_START_M                  GENMASK(0U, 0U)
#define AES_AES_CR_START_X(x)               ((x) & GENMASK(0U, 0U))

/*      AES:AES_REGS:AES_MR */
#define AES_AES_MR(t)             ((t) + 0x04U)

#define AES_AES_MR_TAMPCLR(x)               (((x) << 31U) & GENMASK(31U, 31U))
#define AES_AES_MR_TAMPCLR_M                GENMASK(31U, 31U)
#define AES_AES_MR_TAMPCLR_X(x)             (((x) & GENMASK(31U, 31U)) >> 31U)

#define AES_AES_MR_CMTYP7(x)                (((x) << 30U) & GENMASK(30U, 30U))
#define AES_AES_MR_CMTYP7_M                 GENMASK(30U, 30U)
#define AES_AES_MR_CMTYP7_X(x)              (((x) & GENMASK(30U, 30U)) >> 30U)

#define AES_AES_MR_CMTYP6(x)                (((x) << 29U) & GENMASK(29U, 29U))
#define AES_AES_MR_CMTYP6_M                 GENMASK(29U, 29U)
#define AES_AES_MR_CMTYP6_X(x)              (((x) & GENMASK(29U, 29U)) >> 29U)

#define AES_AES_MR_CMTYP5(x)                (((x) << 28U) & GENMASK(28U, 28U))
#define AES_AES_MR_CMTYP5_M                 GENMASK(28U, 28U)
#define AES_AES_MR_CMTYP5_X(x)              (((x) & GENMASK(28U, 28U)) >> 28U)

#define AES_AES_MR_CMTYP4(x)                (((x) << 27U) & GENMASK(27U, 27U))
#define AES_AES_MR_CMTYP4_M                 GENMASK(27U, 27U)
#define AES_AES_MR_CMTYP4_X(x)              (((x) & GENMASK(27U, 27U)) >> 27U)

#define AES_AES_MR_CMTYP3(x)                (((x) << 26U) & GENMASK(26U, 26U))
#define AES_AES_MR_CMTYP3_M                 GENMASK(26U, 26U)
#define AES_AES_MR_CMTYP3_X(x)              (((x) & GENMASK(26U, 26U)) >> 26U)

#define AES_AES_MR_CMTYP2(x)                (((x) << 25U) & GENMASK(25U, 25U))
#define AES_AES_MR_CMTYP2_M                 GENMASK(25U, 25U)
#define AES_AES_MR_CMTYP2_X(x)              (((x) & GENMASK(25U, 25U)) >> 25U)

#define AES_AES_MR_CMTYP1(x)                (((x) << 24U) & GENMASK(24U, 24U))
#define AES_AES_MR_CMTYP1_M                 GENMASK(24U, 24U)
#define AES_AES_MR_CMTYP1_X(x)              (((x) & GENMASK(24U, 24U)) >> 24U)

#define AES_AES_MR_CKEY(x)                  (((x) << 20U) & GENMASK(23U, 20U))
#define AES_AES_MR_CKEY_M                   GENMASK(23U, 20U)
#define AES_AES_MR_CKEY_X(x)                (((x) & GENMASK(23U, 20U)) >> 20U)

#define AES_AES_MR_CFBS(x)                  (((x) << 16U) & GENMASK(18U, 16U))
#define AES_AES_MR_CFBS_M                   GENMASK(18U, 16U)
#define AES_AES_MR_CFBS_X(x)                (((x) & GENMASK(18U, 16U)) >> 16U)

#define AES_AES_MR_LOD(x)                   (((x) << 15U) & GENMASK(15U, 15U))
#define AES_AES_MR_LOD_M                    GENMASK(15U, 15U)
#define AES_AES_MR_LOD_X(x)                 (((x) & GENMASK(15U, 15U)) >> 15U)

#define AES_AES_MR_OPMOD(x)                 (((x) << 12U) & GENMASK(14U, 12U))
#define AES_AES_MR_OPMOD_M                  GENMASK(14U, 12U)
#define AES_AES_MR_OPMOD_X(x)               (((x) & GENMASK(14U, 12U)) >> 12U)

#define AES_AES_MR_KEYSIZE(x)               (((x) << 10U) & GENMASK(11U, 10U))
#define AES_AES_MR_KEYSIZE_M                GENMASK(11U, 10U)
#define AES_AES_MR_KEYSIZE_X(x)             (((x) & GENMASK(11U, 10U)) >> 10U)

#define AES_AES_MR_SMOD(x)                  (((x) << 8U) & GENMASK(9U, 8U))
#define AES_AES_MR_SMOD_M                   GENMASK(9U, 8U)
#define AES_AES_MR_SMOD_X(x)                (((x) & GENMASK(9U, 8U)) >> 8U)

#define AES_AES_MR_PROCDLY(x)               (((x) << 4U) & GENMASK(7U, 4U))
#define AES_AES_MR_PROCDLY_M                GENMASK(7U, 4U)
#define AES_AES_MR_PROCDLY_X(x)             (((x) & GENMASK(7U, 4U)) >> 4U)

#define AES_AES_MR_DUALBUFF(x)              (((x) << 3U) & GENMASK(3U, 3U))
#define AES_AES_MR_DUALBUFF_M               GENMASK(3U, 3U)
#define AES_AES_MR_DUALBUFF_X(x)            (((x) & GENMASK(3U, 3U)) >> 3U)

#define AES_AES_MR_GTAGEN(x)                (((x) << 1U) & GENMASK(1U, 1U))
#define AES_AES_MR_GTAGEN_M                 GENMASK(1U, 1U)
#define AES_AES_MR_GTAGEN_X(x)              (((x) & GENMASK(1U, 1U)) >> 1U)

#define AES_AES_MR_CIPHER(x)                ((x) & GENMASK(0U, 0U))
#define AES_AES_MR_CIPHER_M                 GENMASK(0U, 0U)
#define AES_AES_MR_CIPHER_X(x)              ((x) & GENMASK(0U, 0U))

/*      AES:AES_REGS:AES_IER */
#define AES_AES_IER(t)            ((t) + 0x10U)

#define AES_AES_IER_SECE(x)                 (((x) << 19U) & GENMASK(19U, 19U))
#define AES_AES_IER_SECE_M                  GENMASK(19U, 19U)
#define AES_AES_IER_SECE_X(x)               (((x) & GENMASK(19U, 19U)) >> 19U)

#define AES_AES_IER_PLENERR(x)              (((x) << 18U) & GENMASK(18U, 18U))
#define AES_AES_IER_PLENERR_M               GENMASK(18U, 18U)
#define AES_AES_IER_PLENERR_X(x)            (((x) & GENMASK(18U, 18U)) >> 18U)

#define AES_AES_IER_EOPAD(x)                (((x) << 17U) & GENMASK(17U, 17U))
#define AES_AES_IER_EOPAD_M                 GENMASK(17U, 17U)
#define AES_AES_IER_EOPAD_X(x)              (((x) & GENMASK(17U, 17U)) >> 17U)

#define AES_AES_IER_TAGRDY(x)               (((x) << 16U) & GENMASK(16U, 16U))
#define AES_AES_IER_TAGRDY_M                GENMASK(16U, 16U)
#define AES_AES_IER_TAGRDY_X(x)             (((x) & GENMASK(16U, 16U)) >> 16U)

#define AES_AES_IER_URAD(x)                 (((x) << 8U) & GENMASK(8U, 8U))
#define AES_AES_IER_URAD_M                  GENMASK(8U, 8U)
#define AES_AES_IER_URAD_X(x)               (((x) & GENMASK(8U, 8U)) >> 8U)

#define AES_AES_IER_DATRDY(x)               ((x) & GENMASK(0U, 0U))
#define AES_AES_IER_DATRDY_M                GENMASK(0U, 0U)
#define AES_AES_IER_DATRDY_X(x)             ((x) & GENMASK(0U, 0U))

/*      AES:AES_REGS:AES_IDR */
#define AES_AES_IDR(t)            ((t) + 0x14U)

#define AES_AES_IDR_SECE_IDR(x)             (((x) << 19U) & GENMASK(19U, 19U))
#define AES_AES_IDR_SECE_IDR_M              GENMASK(19U, 19U)
#define AES_AES_IDR_SECE_IDR_X(x)           (((x) & GENMASK(19U, 19U)) >> 19U)

#define AES_AES_IDR_PLENERR_IDR(x)          (((x) << 18U) & GENMASK(18U, 18U))
#define AES_AES_IDR_PLENERR_IDR_M           GENMASK(18U, 18U)
#define AES_AES_IDR_PLENERR_IDR_X(x)        (((x) & GENMASK(18U, 18U)) >> 18U)

#define AES_AES_IDR_EOPAD_IDR(x)            (((x) << 17U) & GENMASK(17U, 17U))
#define AES_AES_IDR_EOPAD_IDR_M             GENMASK(17U, 17U)
#define AES_AES_IDR_EOPAD_IDR_X(x)          (((x) & GENMASK(17U, 17U)) >> 17U)

#define AES_AES_IDR_TAGRDY_IDR(x)           (((x) << 16U) & GENMASK(16U, 16U))
#define AES_AES_IDR_TAGRDY_IDR_M            GENMASK(16U, 16U)
#define AES_AES_IDR_TAGRDY_IDR_X(x)         (((x) & GENMASK(16U, 16U)) >> 16U)

#define AES_AES_IDR_URAD_IDR(x)             (((x) << 8U) & GENMASK(8U, 8U))
#define AES_AES_IDR_URAD_IDR_M              GENMASK(8U, 8U)
#define AES_AES_IDR_URAD_IDR_X(x)           (((x) & GENMASK(8U, 8U)) >> 8U)

#define AES_AES_IDR_DATRDY_IDR(x)           ((x) & GENMASK(0U, 0U))
#define AES_AES_IDR_DATRDY_IDR_M            GENMASK(0U, 0U)
#define AES_AES_IDR_DATRDY_IDR_X(x)         ((x) & GENMASK(0U, 0U))

/*      AES:AES_REGS:AES_IMR */
#define AES_AES_IMR(t)            ((t) + 0x18U)

#define AES_AES_IMR_SECE_IMR(x)             (((x) << 19U) & GENMASK(19U, 19U))
#define AES_AES_IMR_SECE_IMR_M              GENMASK(19U, 19U)
#define AES_AES_IMR_SECE_IMR_X(x)           (((x) & GENMASK(19U, 19U)) >> 19U)

#define AES_AES_IMR_PLENERR_IMR(x)          (((x) << 18U) & GENMASK(18U, 18U))
#define AES_AES_IMR_PLENERR_IMR_M           GENMASK(18U, 18U)
#define AES_AES_IMR_PLENERR_IMR_X(x)        (((x) & GENMASK(18U, 18U)) >> 18U)

#define AES_AES_IMR_EOPAD_IMR(x)            (((x) << 17U) & GENMASK(17U, 17U))
#define AES_AES_IMR_EOPAD_IMR_M             GENMASK(17U, 17U)
#define AES_AES_IMR_EOPAD_IMR_X(x)          (((x) & GENMASK(17U, 17U)) >> 17U)

#define AES_AES_IMR_TAGRDY_IMR(x)           (((x) << 16U) & GENMASK(16U, 16U))
#define AES_AES_IMR_TAGRDY_IMR_M            GENMASK(16U, 16U)
#define AES_AES_IMR_TAGRDY_IMR_X(x)         (((x) & GENMASK(16U, 16U)) >> 16U)

#define AES_AES_IMR_URAD_IMR(x)             (((x) << 8U) & GENMASK(8U, 8U))
#define AES_AES_IMR_URAD_IMR_M              GENMASK(8U, 8U)
#define AES_AES_IMR_URAD_IMR_X(x)           (((x) & GENMASK(8U, 8U)) >> 8U)

#define AES_AES_IMR_DATRDY_IMR(x)           ((x) & GENMASK(0U, 0U))
#define AES_AES_IMR_DATRDY_IMR_M            GENMASK(0U, 0U)
#define AES_AES_IMR_DATRDY_IMR_X(x)         ((x) & GENMASK(0U, 0U))

/*      AES:AES_REGS:AES_ISR */
#define AES_AES_ISR(t)            ((t) + 0x1cU)

#define AES_AES_ISR_SECE_ISR(x)             (((x) << 19U) & GENMASK(19U, 19U))
#define AES_AES_ISR_SECE_ISR_M              GENMASK(19U, 19U)
#define AES_AES_ISR_SECE_ISR_X(x)           (((x) & GENMASK(19U, 19U)) >> 19U)

#define AES_AES_ISR_PLENERR_ISR(x)          (((x) << 18U) & GENMASK(18U, 18U))
#define AES_AES_ISR_PLENERR_ISR_M           GENMASK(18U, 18U)
#define AES_AES_ISR_PLENERR_ISR_X(x)        (((x) & GENMASK(18U, 18U)) >> 18U)

#define AES_AES_ISR_EOPAD_ISR(x)            (((x) << 17U) & GENMASK(17U, 17U))
#define AES_AES_ISR_EOPAD_ISR_M             GENMASK(17U, 17U)
#define AES_AES_ISR_EOPAD_ISR_X(x)          (((x) & GENMASK(17U, 17U)) >> 17U)

#define AES_AES_ISR_TAGRDY_ISR(x)           (((x) << 16U) & GENMASK(16U, 16U))
#define AES_AES_ISR_TAGRDY_ISR_M            GENMASK(16U, 16U)
#define AES_AES_ISR_TAGRDY_ISR_X(x)         (((x) & GENMASK(16U, 16U)) >> 16U)

#define AES_AES_ISR_URAT_ISR(x)             (((x) << 12U) & GENMASK(15U, 12U))
#define AES_AES_ISR_URAT_ISR_M              GENMASK(15U, 12U)
#define AES_AES_ISR_URAT_ISR_X(x)           (((x) & GENMASK(15U, 12U)) >> 12U)

#define AES_AES_ISR_URAD_ISR(x)             (((x) << 8U) & GENMASK(8U, 8U))
#define AES_AES_ISR_URAD_ISR_M              GENMASK(8U, 8U)
#define AES_AES_ISR_URAD_ISR_X(x)           (((x) & GENMASK(8U, 8U)) >> 8U)

#define AES_AES_ISR_DATRDY_ISR(x)           ((x) & GENMASK(0U, 0U))
#define AES_AES_ISR_DATRDY_ISR_M            GENMASK(0U, 0U)
#define AES_AES_ISR_DATRDY_ISR_X(x)         ((x) & GENMASK(0U, 0U))

/*      AES:AES_REGS:AES_KEYWR0 */
#define AES_AES_KEYWR0(t)         ((t) + 0x20U)

/*      AES:AES_REGS:AES_KEYWR1 */
#define AES_AES_KEYWR1(t)         ((t) + 0x24U)

/*      AES:AES_REGS:AES_KEYWR2 */
#define AES_AES_KEYWR2(t)         ((t) + 0x28U)

/*      AES:AES_REGS:AES_KEYWR3 */
#define AES_AES_KEYWR3(t)         ((t) + 0x2cU)

/*      AES:AES_REGS:AES_KEYWR4 */
#define AES_AES_KEYWR4(t)         ((t) + 0x30U)

/*      AES:AES_REGS:AES_KEYWR5 */
#define AES_AES_KEYWR5(t)         ((t) + 0x34U)

/*      AES:AES_REGS:AES_KEYWR6 */
#define AES_AES_KEYWR6(t)         ((t) + 0x38U)

/*      AES:AES_REGS:AES_KEYWR7 */
#define AES_AES_KEYWR7(t)         ((t) + 0x3cU)

/*      AES:AES_REGS:AES_IDATAR0 */
#define AES_AES_IDATAR0(t)        ((t) + 0x40U)

/*      AES:AES_REGS:AES_IDATAR1 */
#define AES_AES_IDATAR1(t)        ((t) + 0x44U)

/*      AES:AES_REGS:AES_IDATAR2 */
#define AES_AES_IDATAR2(t)        ((t) + 0x48U)

/*      AES:AES_REGS:AES_IDATAR3 */
#define AES_AES_IDATAR3(t)        ((t) + 0x4cU)

/*      AES:AES_REGS:AES_ODATAR0 */
#define AES_AES_ODATAR0(t)        ((t) + 0x50U)

/*      AES:AES_REGS:AES_ODATAR1 */
#define AES_AES_ODATAR1(t)        ((t) + 0x54U)

/*      AES:AES_REGS:AES_ODATAR2 */
#define AES_AES_ODATAR2(t)        ((t) + 0x58U)

/*      AES:AES_REGS:AES_ODATAR3 */
#define AES_AES_ODATAR3(t)        ((t) + 0x5cU)

/*      AES:AES_REGS:AES_IVR0 */
#define AES_AES_IVR0(t)           ((t) + 0x60U)

/*      AES:AES_REGS:AES_IVR1 */
#define AES_AES_IVR1(t)           ((t) + 0x64U)

/*      AES:AES_REGS:AES_IVR2 */
#define AES_AES_IVR2(t)           ((t) + 0x68U)

/*      AES:AES_REGS:AES_IVR3 */
#define AES_AES_IVR3(t)           ((t) + 0x6cU)

/*      AES:AES_REGS:AES_AADLENR */
#define AES_AES_AADLENR(t)        ((t) + 0x70U)

/*      AES:AES_REGS:AES_CLENR */
#define AES_AES_CLENR(t)          ((t) + 0x74U)

/*      AES:AES_REGS:AES_GHASHR0 */
#define AES_AES_GHASHR0(t)        ((t) + 0x78U)

/*      AES:AES_REGS:AES_GHASHR1 */
#define AES_AES_GHASHR1(t)        ((t) + 0x7cU)

/*      AES:AES_REGS:AES_GHASHR2 */
#define AES_AES_GHASHR2(t)        ((t) + 0x80U)

/*      AES:AES_REGS:AES_GHASHR3 */
#define AES_AES_GHASHR3(t)        ((t) + 0x84U)

/*      AES:AES_REGS:AES_TAGR0 */
#define AES_AES_TAGR0(t)          ((t) + 0x88U)

/*      AES:AES_REGS:AES_TAGR1 */
#define AES_AES_TAGR1(t)          ((t) + 0x8cU)

/*      AES:AES_REGS:AES_TAGR2 */
#define AES_AES_TAGR2(t)          ((t) + 0x90U)

/*      AES:AES_REGS:AES_TAGR3 */
#define AES_AES_TAGR3(t)          ((t) + 0x94U)

/*      AES:AES_REGS:AES_CTRR */
#define AES_AES_CTRR(t)           ((t) + 0x98U)

/*      AES:AES_REGS:AES_GCMHR0 */
#define AES_AES_GCMHR0(t)         ((t) + 0x9cU)

/*      AES:AES_REGS:AES_GCMHR1 */
#define AES_AES_GCMHR1(t)         ((t) + 0xa0U)

/*      AES:AES_REGS:AES_GCMHR2 */
#define AES_AES_GCMHR2(t)         ((t) + 0xa4U)

/*      AES:AES_REGS:AES_GCMHR3 */
#define AES_AES_GCMHR3(t)         ((t) + 0xa8U)

/*      AES:AES_REGS:AES_EMR */
#define AES_AES_EMR(t)            ((t) + 0xb0U)

#define AES_AES_EMR_BPE(x)                  (((x) << 31U) & GENMASK(31U, 31U))
#define AES_AES_EMR_BPE_M                   GENMASK(31U, 31U)
#define AES_AES_EMR_BPE_X(x)                (((x) & GENMASK(31U, 31U)) >> 31U)

#define AES_AES_EMR_NHEAD(x)                (((x) << 16U) & GENMASK(23U, 16U))
#define AES_AES_EMR_NHEAD_M                 GENMASK(23U, 16U)
#define AES_AES_EMR_NHEAD_X(x)              (((x) & GENMASK(23U, 16U)) >> 16U)

#define AES_AES_EMR_PADLEN(x)               (((x) << 8U) & GENMASK(15U, 8U))
#define AES_AES_EMR_PADLEN_M                GENMASK(15U, 8U)
#define AES_AES_EMR_PADLEN_X(x)             (((x) & GENMASK(15U, 8U)) >> 8U)

#define AES_AES_EMR_PKRS(x)                 (((x) << 7U) & GENMASK(7U, 7U))
#define AES_AES_EMR_PKRS_M                  GENMASK(7U, 7U)
#define AES_AES_EMR_PKRS_X(x)               (((x) & GENMASK(7U, 7U)) >> 7U)

#define AES_AES_EMR_PKWL(x)                 (((x) << 6U) & GENMASK(6U, 6U))
#define AES_AES_EMR_PKWL_M                  GENMASK(6U, 6U)
#define AES_AES_EMR_PKWL_X(x)               (((x) & GENMASK(6U, 6U)) >> 6U)

#define AES_AES_EMR_PLIPD(x)                (((x) << 5U) & GENMASK(5U, 5U))
#define AES_AES_EMR_PLIPD_M                 GENMASK(5U, 5U)
#define AES_AES_EMR_PLIPD_X(x)              (((x) & GENMASK(5U, 5U)) >> 5U)

#define AES_AES_EMR_PLIPEN(x)               (((x) << 4U) & GENMASK(4U, 4U))
#define AES_AES_EMR_PLIPEN_M                GENMASK(4U, 4U)
#define AES_AES_EMR_PLIPEN_X(x)             (((x) & GENMASK(4U, 4U)) >> 4U)

#define AES_AES_EMR_APM(x)                  (((x) << 1U) & GENMASK(1U, 1U))
#define AES_AES_EMR_APM_M                   GENMASK(1U, 1U)
#define AES_AES_EMR_APM_X(x)                (((x) & GENMASK(1U, 1U)) >> 1U)

#define AES_AES_EMR_APEN(x)                 ((x) & GENMASK(0U, 0U))
#define AES_AES_EMR_APEN_M                  GENMASK(0U, 0U)
#define AES_AES_EMR_APEN_X(x)               ((x) & GENMASK(0U, 0U))

/*      AES:AES_REGS:AES_BCNT */
#define AES_AES_BCNT(t)           ((t) + 0xb4U)

#define AES_AES_BCNT_BCNT(x)                ((x) & GENMASK(30U, 0U))
#define AES_AES_BCNT_BCNT_M                 GENMASK(30U, 0U)
#define AES_AES_BCNT_BCNT_X(x)              ((x) & GENMASK(30U, 0U))

/*      AES:AES_REGS:AES_TWR0 */
#define AES_AES_TWR0(t)           ((t) + 0xc0U)

/*      AES:AES_REGS:AES_TWR1 */
#define AES_AES_TWR1(t)           ((t) + 0xc4U)

/*      AES:AES_REGS:AES_TWR2 */
#define AES_AES_TWR2(t)           ((t) + 0xc8U)

/*      AES:AES_REGS:AES_TWR3 */
#define AES_AES_TWR3(t)           ((t) + 0xccU)

/*      AES:AES_REGS:AES_ALPHAR0 */
#define AES_AES_ALPHAR0(t)        ((t) + 0xd0U)

/*      AES:AES_REGS:AES_ALPHAR1 */
#define AES_AES_ALPHAR1(t)        ((t) + 0xd4U)

/*      AES:AES_REGS:AES_ALPHAR2 */
#define AES_AES_ALPHAR2(t)        ((t) + 0xd8U)

/*      AES:AES_REGS:AES_ALPHAR3 */
#define AES_AES_ALPHAR3(t)        ((t) + 0xdcU)

/*      AES:AES_REGS:AES_WPMR */
#define AES_AES_WPMR(t)           ((t) + 0xe4U)

#define AES_AES_WPMR_WPKEY(x)               (((x) << 8U) & GENMASK(31U, 8U))
#define AES_AES_WPMR_WPKEY_M                GENMASK(31U, 8U)
#define AES_AES_WPMR_WPKEY_X(x)             (((x) & GENMASK(31U, 8U)) >> 8U)

#define AES_AES_WPMR_ACTION(x)              (((x) << 5U) & GENMASK(7U, 5U))
#define AES_AES_WPMR_ACTION_M               GENMASK(7U, 5U)
#define AES_AES_WPMR_ACTION_X(x)            (((x) & GENMASK(7U, 5U)) >> 5U)

#define AES_AES_WPMR_FIRSTE(x)              (((x) << 4U) & GENMASK(4U, 4U))
#define AES_AES_WPMR_FIRSTE_M               GENMASK(4U, 4U)
#define AES_AES_WPMR_FIRSTE_X(x)            (((x) & GENMASK(4U, 4U)) >> 4U)

#define AES_AES_WPMR_WPCREN(x)              (((x) << 2U) & GENMASK(2U, 2U))
#define AES_AES_WPMR_WPCREN_M               GENMASK(2U, 2U)
#define AES_AES_WPMR_WPCREN_X(x)            (((x) & GENMASK(2U, 2U)) >> 2U)

#define AES_AES_WPMR_WPITEN(x)              (((x) << 1U) & GENMASK(1U, 1U))
#define AES_AES_WPMR_WPITEN_M               GENMASK(1U, 1U)
#define AES_AES_WPMR_WPITEN_X(x)            (((x) & GENMASK(1U, 1U)) >> 1U)

#define AES_AES_WPMR_WPEN(x)                ((x) & GENMASK(0U, 0U))
#define AES_AES_WPMR_WPEN_M                 GENMASK(0U, 0U)
#define AES_AES_WPMR_WPEN_X(x)              ((x) & GENMASK(0U, 0U))

/*      AES:AES_REGS:AES_WPSR */
#define AES_AES_WPSR(t)           ((t) + 0xe8U)

#define AES_AES_WPSR_ECLASS(x)              (((x) << 31U) & GENMASK(31U, 31U))
#define AES_AES_WPSR_ECLASS_M               GENMASK(31U, 31U)
#define AES_AES_WPSR_ECLASS_X(x)            (((x) & GENMASK(31U, 31U)) >> 31U)

#define AES_AES_WPSR_SWETYP(x)              (((x) << 24U) & GENMASK(27U, 24U))
#define AES_AES_WPSR_SWETYP_M               GENMASK(27U, 24U)
#define AES_AES_WPSR_SWETYP_X(x)            (((x) & GENMASK(27U, 24U)) >> 24U)

#define AES_AES_WPSR_WPVSRC(x)              (((x) << 8U) & GENMASK(15U, 8U))
#define AES_AES_WPSR_WPVSRC_M               GENMASK(15U, 8U)
#define AES_AES_WPSR_WPVSRC_X(x)            (((x) & GENMASK(15U, 8U)) >> 8U)

#define AES_AES_WPSR_PKRPVS(x)              (((x) << 4U) & GENMASK(4U, 4U))
#define AES_AES_WPSR_PKRPVS_M               GENMASK(4U, 4U)
#define AES_AES_WPSR_PKRPVS_X(x)            (((x) & GENMASK(4U, 4U)) >> 4U)

#define AES_AES_WPSR_SWE(x)                 (((x) << 3U) & GENMASK(3U, 3U))
#define AES_AES_WPSR_SWE_M                  GENMASK(3U, 3U)
#define AES_AES_WPSR_SWE_X(x)               (((x) & GENMASK(3U, 3U)) >> 3U)

#define AES_AES_WPSR_SEQE(x)                (((x) << 2U) & GENMASK(2U, 2U))
#define AES_AES_WPSR_SEQE_M                 GENMASK(2U, 2U)
#define AES_AES_WPSR_SEQE_X(x)              (((x) & GENMASK(2U, 2U)) >> 2U)

#define AES_AES_WPSR_CGD(x)                 (((x) << 1U) & GENMASK(1U, 1U))
#define AES_AES_WPSR_CGD_M                  GENMASK(1U, 1U)
#define AES_AES_WPSR_CGD_X(x)               (((x) & GENMASK(1U, 1U)) >> 1U)

#define AES_AES_WPSR_WPVS(x)                ((x) & GENMASK(0U, 0U))
#define AES_AES_WPSR_WPVS_M                 GENMASK(0U, 0U)
#define AES_AES_WPSR_WPVS_X(x)              ((x) & GENMASK(0U, 0U))

/*      AES:AES_REGS:AES_VERSION */
#define AES_AES_VERSION(t)        ((t) + 0xfcU)

#define AES_AES_VERSION_MFN(x)              (((x) << 16U) & GENMASK(18U, 16U))
#define AES_AES_VERSION_MFN_M               GENMASK(18U, 16U)
#define AES_AES_VERSION_MFN_X(x)            (((x) & GENMASK(18U, 16U)) >> 16U)

#define AES_AES_VERSION_VERSION(x)          ((x) & GENMASK(11U, 0U))
#define AES_AES_VERSION_VERSION_M           GENMASK(11U, 0U)
#define AES_AES_VERSION_VERSION_X(x)        ((x) & GENMASK(11U, 0U))

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RBAR0 */
#define AESB_ASC_TZAESBASC_RBAR0(t) ((t) + 0x00U)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RTAR0 */
#define AESB_ASC_TZAESBASC_RTAR0(t) ((t) + 0x04U)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RBAR1 */
#define AESB_ASC_TZAESBASC_RBAR1(t) ((t) + 0x08U)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RTAR1 */
#define AESB_ASC_TZAESBASC_RTAR1(t) ((t) + 0x0cU)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RBAR2 */
#define AESB_ASC_TZAESBASC_RBAR2(t) ((t) + 0x10U)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RTAR2 */
#define AESB_ASC_TZAESBASC_RTAR2(t) ((t) + 0x14U)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RBAR3 */
#define AESB_ASC_TZAESBASC_RBAR3(t) ((t) + 0x18U)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RTAR3 */
#define AESB_ASC_TZAESBASC_RTAR3(t) ((t) + 0x1cU)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RBAR4 */
#define AESB_ASC_TZAESBASC_RBAR4(t) ((t) + 0x20U)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RTAR4 */
#define AESB_ASC_TZAESBASC_RTAR4(t) ((t) + 0x24U)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RBAR5 */
#define AESB_ASC_TZAESBASC_RBAR5(t) ((t) + 0x28U)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RTAR5 */
#define AESB_ASC_TZAESBASC_RTAR5(t) ((t) + 0x2cU)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RBAR6 */
#define AESB_ASC_TZAESBASC_RBAR6(t) ((t) + 0x30U)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RTAR6 */
#define AESB_ASC_TZAESBASC_RTAR6(t) ((t) + 0x34U)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RBAR7 */
#define AESB_ASC_TZAESBASC_RBAR7(t) ((t) + 0x38U)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RTAR7 */
#define AESB_ASC_TZAESBASC_RTAR7(t) ((t) + 0x3cU)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RSECR */
#define AESB_ASC_TZAESBASC_RSECR(t) ((t) + 0x80U)

#define AESB_ASC_TZAESBASC_RSECR_SECX(x)    ((x) & GENMASK(7U, 0U))
#define AESB_ASC_TZAESBASC_RSECR_SECX_M     GENMASK(7U, 0U)
#define AESB_ASC_TZAESBASC_RSECR_SECX_X(x)  ((x) & GENMASK(7U, 0U))

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RER */
#define AESB_ASC_TZAESBASC_RER(t) ((t) + 0x84U)

#define AESB_ASC_TZAESBASC_RER_ENX(x)       ((x) & GENMASK(7U, 0U))
#define AESB_ASC_TZAESBASC_RER_ENX_M        GENMASK(7U, 0U)
#define AESB_ASC_TZAESBASC_RER_ENX_X(x)     ((x) & GENMASK(7U, 0U))

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RDR */
#define AESB_ASC_TZAESBASC_RDR(t) ((t) + 0x88U)

#define AESB_ASC_TZAESBASC_RDR_DISX(x)      ((x) & GENMASK(7U, 0U))
#define AESB_ASC_TZAESBASC_RDR_DISX_M       GENMASK(7U, 0U)
#define AESB_ASC_TZAESBASC_RDR_DISX_X(x)    ((x) & GENMASK(7U, 0U))

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RSR */
#define AESB_ASC_TZAESBASC_RSR(t) ((t) + 0x8cU)

#define AESB_ASC_TZAESBASC_RSR_ESX(x)       ((x) & GENMASK(7U, 0U))
#define AESB_ASC_TZAESBASC_RSR_ESX_M        GENMASK(7U, 0U)
#define AESB_ASC_TZAESBASC_RSR_ESX_X(x)     ((x) & GENMASK(7U, 0U))

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RESR */
#define AESB_ASC_TZAESBASC_RESR(t) ((t) + 0x90U)

#define AESB_ASC_TZAESBASC_RESR_AERX(x)     ((x) & GENMASK(7U, 0U))
#define AESB_ASC_TZAESBASC_RESR_AERX_M      GENMASK(7U, 0U)
#define AESB_ASC_TZAESBASC_RESR_AERX_X(x)   ((x) & GENMASK(7U, 0U))

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RSSR */
#define AESB_ASC_TZAESBASC_RSSR(t) ((t) + 0x94U)

#define AESB_ASC_TZAESBASC_RSSR_SYNC(x)     ((x) & GENMASK(0U, 0U))
#define AESB_ASC_TZAESBASC_RSSR_SYNC_M      GENMASK(0U, 0U)
#define AESB_ASC_TZAESBASC_RSSR_SYNC_X(x)   ((x) & GENMASK(0U, 0U))

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_WPMR */
#define AESB_ASC_TZAESBASC_WPMR(t) ((t) + 0xe4U)

#define AESB_ASC_TZAESBASC_WPMR_WPKEY(x)    (((x) << 8U) & GENMASK(31U, 8U))
#define AESB_ASC_TZAESBASC_WPMR_WPKEY_M     GENMASK(31U, 8U)
#define AESB_ASC_TZAESBASC_WPMR_WPKEY_X(x)  (((x) & GENMASK(31U, 8U)) >> 8U)

#define AESB_ASC_TZAESBASC_WPMR_WPEN(x)     ((x) & GENMASK(0U, 0U))
#define AESB_ASC_TZAESBASC_WPMR_WPEN_M      GENMASK(0U, 0U)
#define AESB_ASC_TZAESBASC_WPMR_WPEN_X(x)   ((x) & GENMASK(0U, 0U))

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_WPSR */
#define AESB_ASC_TZAESBASC_WPSR(t) ((t) + 0xe8U)

#define AESB_ASC_TZAESBASC_WPSR_WPSRC(x)    (((x) << 8U) & GENMASK(23U, 8U))
#define AESB_ASC_TZAESBASC_WPSR_WPSRC_M     GENMASK(23U, 8U)
#define AESB_ASC_TZAESBASC_WPSR_WPSRC_X(x)  (((x) & GENMASK(23U, 8U)) >> 8U)

#define AESB_ASC_TZAESBASC_WPSR_WPVS(x)     ((x) & GENMASK(0U, 0U))
#define AESB_ASC_TZAESBASC_WPSR_WPVS_M      GENMASK(0U, 0U)
#define AESB_ASC_TZAESBASC_WPSR_WPVS_X(x)   ((x) & GENMASK(0U, 0U))

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_VERSION */
#define AESB_ASC_TZAESBASC_VERSION(t) ((t) + 0xfcU)

#define AESB_ASC_TZAESBASC_VERSION_MFN(x)   (((x) << 16U) & GENMASK(18U, 16U))
#define AESB_ASC_TZAESBASC_VERSION_MFN_M    GENMASK(18U, 16U)
#define AESB_ASC_TZAESBASC_VERSION_MFN_X(x) (((x) & GENMASK(18U, 16U)) >> 16U)

#define AESB_ASC_TZAESBASC_VERSION_VERSION(x) ((x) & GENMASK(11U, 0U))
#define AESB_ASC_TZAESBASC_VERSION_VERSION_M GENMASK(11U, 0U)
#define AESB_ASC_TZAESBASC_VERSION_VERSION_X(x) ((x) & GENMASK(11U, 0U))

/*      CHIP_TOP:HW_STAT:HW_STAT */
#define CHIP_TOP_HW_STAT(t)       ((t) + 0x5cU)

#define CHIP_TOP_HW_STAT_JTAG_SEL(x)        (((x) << 2U) & GENMASK(2U, 2U))
#define CHIP_TOP_HW_STAT_JTAG_SEL_M         GENMASK(2U, 2U)
#define CHIP_TOP_HW_STAT_JTAG_SEL_X(x)      (((x) & GENMASK(2U, 2U)) >> 2U)

#define CHIP_TOP_HW_STAT_REFCLK_SEL(x)      (((x) << 1U) & GENMASK(1U, 1U))
#define CHIP_TOP_HW_STAT_REFCLK_SEL_M       GENMASK(1U, 1U)
#define CHIP_TOP_HW_STAT_REFCLK_SEL_X(x)    (((x) & GENMASK(1U, 1U)) >> 1U)

#define CHIP_TOP_HW_STAT_PLL_NBYPASS(x)     ((x) & GENMASK(0U, 0U))
#define CHIP_TOP_HW_STAT_PLL_NBYPASS_M      GENMASK(0U, 0U)
#define CHIP_TOP_HW_STAT_PLL_NBYPASS_X(x)   ((x) & GENMASK(0U, 0U))

/*      CHIP_TOP:DDR_PLL_CFG:DDR_PLL_CFG */
#define CHIP_TOP_DDR_PLL_CFG(t)   ((t) + 0xccU)

#define CHIP_TOP_DDR_PLL_CFG_DIVACK(x)      (((x) << 27U) & GENMASK(27U, 27U))
#define CHIP_TOP_DDR_PLL_CFG_DIVACK_M       GENMASK(27U, 27U)
#define CHIP_TOP_DDR_PLL_CFG_DIVACK_X(x)    (((x) & GENMASK(27U, 27U)) >> 27U)

#define CHIP_TOP_DDR_PLL_CFG_NEWDIV(x)      (((x) << 26U) & GENMASK(26U, 26U))
#define CHIP_TOP_DDR_PLL_CFG_NEWDIV_M       GENMASK(26U, 26U)
#define CHIP_TOP_DDR_PLL_CFG_NEWDIV_X(x)    (((x) & GENMASK(26U, 26U)) >> 26U)

#define CHIP_TOP_DDR_PLL_CFG_FILTER_RANGE(x) (((x) << 23U) & GENMASK(25U, 23U))
#define CHIP_TOP_DDR_PLL_CFG_FILTER_RANGE_M GENMASK(25U, 23U)
#define CHIP_TOP_DDR_PLL_CFG_FILTER_RANGE_X(x)\
	(((x) & GENMASK(25U, 23U)) >> 23U)

#define CHIP_TOP_DDR_PLL_CFG_DIVQ(x)        (((x) << 8U) & GENMASK(22U, 8U))
#define CHIP_TOP_DDR_PLL_CFG_DIVQ_M         GENMASK(22U, 8U)
#define CHIP_TOP_DDR_PLL_CFG_DIVQ_X(x)      (((x) & GENMASK(22U, 8U)) >> 8U)

#define CHIP_TOP_DDR_PLL_CFG_DIVR(x)        (((x) << 2U) & GENMASK(7U, 2U))
#define CHIP_TOP_DDR_PLL_CFG_DIVR_M         GENMASK(7U, 2U)
#define CHIP_TOP_DDR_PLL_CFG_DIVR_X(x)      (((x) & GENMASK(7U, 2U)) >> 2U)

#define CHIP_TOP_DDR_PLL_CFG_ENA_CFG(x)     (((x) << 1U) & GENMASK(1U, 1U))
#define CHIP_TOP_DDR_PLL_CFG_ENA_CFG_M      GENMASK(1U, 1U)
#define CHIP_TOP_DDR_PLL_CFG_ENA_CFG_X(x)   (((x) & GENMASK(1U, 1U)) >> 1U)

#define CHIP_TOP_DDR_PLL_CFG_LOCK_STAT(x)   ((x) & GENMASK(0U, 0U))
#define CHIP_TOP_DDR_PLL_CFG_LOCK_STAT_M    GENMASK(0U, 0U)
#define CHIP_TOP_DDR_PLL_CFG_LOCK_STAT_X(x) ((x) & GENMASK(0U, 0U))

/*      CHIP_TOP:DDR_PLL_CFG:DDR_PLL_FREQ_CFG */
#define CHIP_TOP_DDR_PLL_FREQ_CFG(t) ((t) + 0xd0U)

#define CHIP_TOP_DDR_PLL_FREQ_CFG_BYPASS_ENA(x)\
	(((x) << 31U) & GENMASK(31U, 31U))
#define CHIP_TOP_DDR_PLL_FREQ_CFG_BYPASS_ENA_M GENMASK(31U, 31U)
#define CHIP_TOP_DDR_PLL_FREQ_CFG_BYPASS_ENA_X(x)\
	(((x) & GENMASK(31U, 31U)) >> 31U)

#define CHIP_TOP_DDR_PLL_FREQ_CFG_DIVFI(x)  (((x) << 24U) & GENMASK(30U, 24U))
#define CHIP_TOP_DDR_PLL_FREQ_CFG_DIVFI_M   GENMASK(30U, 24U)
#define CHIP_TOP_DDR_PLL_FREQ_CFG_DIVFI_X(x) (((x) & GENMASK(30U, 24U)) >> 24U)

#define CHIP_TOP_DDR_PLL_FREQ_CFG_DIVFF(x)  ((x) & GENMASK(23U, 0U))
#define CHIP_TOP_DDR_PLL_FREQ_CFG_DIVFF_M   GENMASK(23U, 0U)
#define CHIP_TOP_DDR_PLL_FREQ_CFG_DIVFF_X(x) ((x) & GENMASK(23U, 0U))

/*      CPU:CPU_REGS:GPR */
#define CPU_GPR(t, r)             ((t) + (0x00U + ((r) * 4U)))

/*      CPU:CPU_REGS:BUILDID */
#define CPU_BUILDID(t)            ((t) + 0x80U)

/*      CPU:CPU_REGS:RESET */
#define CPU_RESET(t)              ((t) + 0x84U)

#define CPU_RESET_VCORE_RST(x)              (((x) << 7U) & GENMASK(7U, 7U))
#define CPU_RESET_VCORE_RST_M               GENMASK(7U, 7U)
#define CPU_RESET_VCORE_RST_X(x)            (((x) & GENMASK(7U, 7U)) >> 7U)

#define CPU_RESET_CPU_CORE_0_WARM_RST(x)    (((x) << 6U) & GENMASK(6U, 6U))
#define CPU_RESET_CPU_CORE_0_WARM_RST_M     GENMASK(6U, 6U)
#define CPU_RESET_CPU_CORE_0_WARM_RST_X(x)  (((x) & GENMASK(6U, 6U)) >> 6U)

#define CPU_RESET_PROC_DBG_RST(x)           (((x) << 5U) & GENMASK(5U, 5U))
#define CPU_RESET_PROC_DBG_RST_M            GENMASK(5U, 5U)
#define CPU_RESET_PROC_DBG_RST_X(x)         (((x) & GENMASK(5U, 5U)) >> 5U)

#define CPU_RESET_JTAG_RST(x)               (((x) << 4U) & GENMASK(4U, 4U))
#define CPU_RESET_JTAG_RST_M                GENMASK(4U, 4U)
#define CPU_RESET_JTAG_RST_X(x)             (((x) & GENMASK(4U, 4U)) >> 4U)

#define CPU_RESET_CPU_L2_RST(x)             (((x) << 3U) & GENMASK(3U, 3U))
#define CPU_RESET_CPU_L2_RST_M              GENMASK(3U, 3U)
#define CPU_RESET_CPU_L2_RST_X(x)           (((x) & GENMASK(3U, 3U)) >> 3U)

#define CPU_RESET_MEM_RST(x)                (((x) << 2U) & GENMASK(2U, 2U))
#define CPU_RESET_MEM_RST_M                 GENMASK(2U, 2U)
#define CPU_RESET_MEM_RST_X(x)              (((x) & GENMASK(2U, 2U)) >> 2U)

#define CPU_RESET_WDT_FORCE_RST(x)          (((x) << 1U) & GENMASK(1U, 1U))
#define CPU_RESET_WDT_FORCE_RST_M           GENMASK(1U, 1U)
#define CPU_RESET_WDT_FORCE_RST_X(x)        (((x) & GENMASK(1U, 1U)) >> 1U)

#define CPU_RESET_CPU_CORE_0_COLD_RST(x)    ((x) & GENMASK(0U, 0U))
#define CPU_RESET_CPU_CORE_0_COLD_RST_M     GENMASK(0U, 0U)
#define CPU_RESET_CPU_CORE_0_COLD_RST_X(x)  ((x) & GENMASK(0U, 0U))

/*      CPU:CPU_REGS:RESET_PROT_STAT */
#define CPU_RESET_PROT_STAT(t)    ((t) + 0x88U)

#define CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE(x)\
	(((x) << 5U) & GENMASK(5U, 5U))
#define CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE_M GENMASK(5U, 5U)
#define CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE_X(x)\
	(((x) & GENMASK(5U, 5U)) >> 5U)

#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_AMBA(x)\
	(((x) << 4U) & GENMASK(4U, 4U))
#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_AMBA_M GENMASK(4U, 4U)
#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_AMBA_X(x)\
	(((x) & GENMASK(4U, 4U)) >> 4U)

#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_WDT(x)\
	(((x) << 3U) & GENMASK(3U, 3U))
#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_WDT_M GENMASK(3U, 3U)
#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_WDT_X(x)\
	(((x) & GENMASK(3U, 3U)) >> 3U)

#define CPU_RESET_PROT_STAT_VCORE_WDT_RST_PROT_WDT(x)\
	(((x) << 2U) & GENMASK(2U, 2U))
#define CPU_RESET_PROT_STAT_VCORE_WDT_RST_PROT_WDT_M GENMASK(2U, 2U)
#define CPU_RESET_PROT_STAT_VCORE_WDT_RST_PROT_WDT_X(x)\
	(((x) & GENMASK(2U, 2U)) >> 2U)

#define CPU_RESET_PROT_STAT_VCORE_WDT_RST_STAT(x)\
	(((x) << 1U) & GENMASK(1U, 1U))
#define CPU_RESET_PROT_STAT_VCORE_WDT_RST_STAT_M GENMASK(1U, 1U)
#define CPU_RESET_PROT_STAT_VCORE_WDT_RST_STAT_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_PCIE(x) ((x) & GENMASK(0U, 0U))
#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_PCIE_M GENMASK(0U, 0U)
#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_PCIE_X(x) ((x) & GENMASK(0U, 0U))

/*      CPU:CPU_REGS:GENERAL_CTRL */
#define CPU_GENERAL_CTRL(t)       ((t) + 0x8cU)

#define CPU_GENERAL_CTRL_IF_MIIM_SLV_ENA(x) (((x) << 2U) & GENMASK(2U, 2U))
#define CPU_GENERAL_CTRL_IF_MIIM_SLV_ENA_M  GENMASK(2U, 2U)
#define CPU_GENERAL_CTRL_IF_MIIM_SLV_ENA_X(x) (((x) & GENMASK(2U, 2U)) >> 2U)

#define CPU_GENERAL_CTRL_VCORE_CPU_DIS(x)   (((x) << 1U) & GENMASK(1U, 1U))
#define CPU_GENERAL_CTRL_VCORE_CPU_DIS_M    GENMASK(1U, 1U)
#define CPU_GENERAL_CTRL_VCORE_CPU_DIS_X(x) (((x) & GENMASK(1U, 1U)) >> 1U)

#define CPU_GENERAL_CTRL_IF_SI_OWNER(x)     ((x) & GENMASK(0U, 0U))
#define CPU_GENERAL_CTRL_IF_SI_OWNER_M      GENMASK(0U, 0U)
#define CPU_GENERAL_CTRL_IF_SI_OWNER_X(x)   ((x) & GENMASK(0U, 0U))

/*      CPU:CPU_REGS:GENERAL_STAT */
#define CPU_GENERAL_STAT(t)       ((t) + 0x90U)

#define CPU_GENERAL_STAT_REG_IF_ERR(x)      (((x) << 7U) & GENMASK(9U, 7U))
#define CPU_GENERAL_STAT_REG_IF_ERR_M       GENMASK(9U, 7U)
#define CPU_GENERAL_STAT_REG_IF_ERR_X(x)    (((x) & GENMASK(9U, 7U)) >> 7U)

#define CPU_GENERAL_STAT_CSR_REG_IF_ERR(x)  (((x) << 4U) & GENMASK(6U, 4U))
#define CPU_GENERAL_STAT_CSR_REG_IF_ERR_M   GENMASK(6U, 4U)
#define CPU_GENERAL_STAT_CSR_REG_IF_ERR_X(x) (((x) & GENMASK(6U, 4U)) >> 4U)

#define CPU_GENERAL_STAT_VCORE_CFG(x)       ((x) & GENMASK(3U, 0U))
#define CPU_GENERAL_STAT_VCORE_CFG_M        GENMASK(3U, 0U)
#define CPU_GENERAL_STAT_VCORE_CFG_X(x)     ((x) & GENMASK(3U, 0U))

/*      CPU:CPU_REGS:OTP_STAT */
#define CPU_OTP_STAT(t)           ((t) + 0x94U)

#define CPU_OTP_STAT_OTP_DDR_DISABLED(x)    (((x) << 6U) & GENMASK(6U, 6U))
#define CPU_OTP_STAT_OTP_DDR_DISABLED_M     GENMASK(6U, 6U)
#define CPU_OTP_STAT_OTP_DDR_DISABLED_X(x)  (((x) & GENMASK(6U, 6U)) >> 6U)

#define CPU_OTP_STAT_OTP_HSR_PRP_DISABLED(x) (((x) << 5U) & GENMASK(5U, 5U))
#define CPU_OTP_STAT_OTP_HSR_PRP_DISABLED_M GENMASK(5U, 5U)
#define CPU_OTP_STAT_OTP_HSR_PRP_DISABLED_X(x) (((x) & GENMASK(5U, 5U)) >> 5U)

#define CPU_OTP_STAT_OTP_PROGRAMMED(x)      (((x) << 4U) & GENMASK(4U, 4U))
#define CPU_OTP_STAT_OTP_PROGRAMMED_M       GENMASK(4U, 4U)
#define CPU_OTP_STAT_OTP_PROGRAMMED_X(x)    (((x) & GENMASK(4U, 4U)) >> 4U)

#define CPU_OTP_STAT_OTP_CPU_DISABLED(x)    (((x) << 3U) & GENMASK(3U, 3U))
#define CPU_OTP_STAT_OTP_CPU_DISABLED_M     GENMASK(3U, 3U)
#define CPU_OTP_STAT_OTP_CPU_DISABLED_X(x)  (((x) & GENMASK(3U, 3U)) >> 3U)

#define CPU_OTP_STAT_OTP_CPU_DBG_DISABLED(x) (((x) << 2U) & GENMASK(2U, 2U))
#define CPU_OTP_STAT_OTP_CPU_DBG_DISABLED_M GENMASK(2U, 2U)
#define CPU_OTP_STAT_OTP_CPU_DBG_DISABLED_X(x) (((x) & GENMASK(2U, 2U)) >> 2U)

#define CPU_OTP_STAT_OTP_CPU_SEC_DBG_DISABLED(x) (((x) << 1U) & GENMASK(1U, 1U))
#define CPU_OTP_STAT_OTP_CPU_SEC_DBG_DISABLED_M GENMASK(1U, 1U)
#define CPU_OTP_STAT_OTP_CPU_SEC_DBG_DISABLED_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

#define CPU_OTP_STAT_OTP_CAN_DISABLED(x)    ((x) & GENMASK(0U, 0U))
#define CPU_OTP_STAT_OTP_CAN_DISABLED_M     GENMASK(0U, 0U)
#define CPU_OTP_STAT_OTP_CAN_DISABLED_X(x)  ((x) & GENMASK(0U, 0U))

/*      CPU:CPU_REGS:CPU_DBG */
#define CPU_CPU_DBG(t)            ((t) + 0x98U)

#define CPU_CPU_DBG_ENABLE_PROT_DEBUG_BIT(x) (((x) << 5U) & GENMASK(5U, 5U))
#define CPU_CPU_DBG_ENABLE_PROT_DEBUG_BIT_M GENMASK(5U, 5U)
#define CPU_CPU_DBG_ENABLE_PROT_DEBUG_BIT_X(x) (((x) & GENMASK(5U, 5U)) >> 5U)

#define CPU_CPU_DBG_DBGEN(x)                (((x) << 4U) & GENMASK(4U, 4U))
#define CPU_CPU_DBG_DBGEN_M                 GENMASK(4U, 4U)
#define CPU_CPU_DBG_DBGEN_X(x)              (((x) & GENMASK(4U, 4U)) >> 4U)

#define CPU_CPU_DBG_SPIDEN(x)               (((x) << 3U) & GENMASK(3U, 3U))
#define CPU_CPU_DBG_SPIDEN_M                GENMASK(3U, 3U)
#define CPU_CPU_DBG_SPIDEN_X(x)             (((x) & GENMASK(3U, 3U)) >> 3U)

#define CPU_CPU_DBG_NIDEN(x)                (((x) << 2U) & GENMASK(2U, 2U))
#define CPU_CPU_DBG_NIDEN_M                 GENMASK(2U, 2U)
#define CPU_CPU_DBG_NIDEN_X(x)              (((x) & GENMASK(2U, 2U)) >> 2U)

#define CPU_CPU_DBG_SPNIDEN(x)              (((x) << 1U) & GENMASK(1U, 1U))
#define CPU_CPU_DBG_SPNIDEN_M               GENMASK(1U, 1U)
#define CPU_CPU_DBG_SPNIDEN_X(x)            (((x) & GENMASK(1U, 1U)) >> 1U)

#define CPU_CPU_DBG_CORE_IN_DBG(x)          ((x) & GENMASK(0U, 0U))
#define CPU_CPU_DBG_CORE_IN_DBG_M           GENMASK(0U, 0U)
#define CPU_CPU_DBG_CORE_IN_DBG_X(x)        ((x) & GENMASK(0U, 0U))

/*      CPU:CPU_REGS:ENDIANNESS */
#define CPU_ENDIANNESS(t)         ((t) + 0x9cU)

#define CPU_ENDIANNESS_REG_IF_BIGENDIAN(x)  ((x) & GENMASK(0U, 0U))
#define CPU_ENDIANNESS_REG_IF_BIGENDIAN_M   GENMASK(0U, 0U)
#define CPU_ENDIANNESS_REG_IF_BIGENDIAN_X(x) ((x) & GENMASK(0U, 0U))

/*      CPU:CPU_REGS:PROC_CTRL */
#define CPU_PROC_CTRL(t)          ((t) + 0xa0U)

#define CPU_PROC_CTRL_L2_FLUSH_REQ(x)       (((x) << 8U) & GENMASK(8U, 8U))
#define CPU_PROC_CTRL_L2_FLUSH_REQ_M        GENMASK(8U, 8U)
#define CPU_PROC_CTRL_L2_FLUSH_REQ_X(x)     (((x) & GENMASK(8U, 8U)) >> 8U)

#define CPU_PROC_CTRL_AARCH64_MODE_ENA(x)   (((x) << 7U) & GENMASK(7U, 7U))
#define CPU_PROC_CTRL_AARCH64_MODE_ENA_M    GENMASK(7U, 7U)
#define CPU_PROC_CTRL_AARCH64_MODE_ENA_X(x) (((x) & GENMASK(7U, 7U)) >> 7U)

#define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS(x) (((x) << 6U) & GENMASK(6U, 6U))
#define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_M GENMASK(6U, 6U)
#define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_X(x) (((x) & GENMASK(6U, 6U)) >> 6U)

#define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS(x) (((x) << 5U) & GENMASK(5U, 5U))
#define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_M GENMASK(5U, 5U)
#define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_X(x) (((x) & GENMASK(5U, 5U)) >> 5U)

#define CPU_PROC_CTRL_BE_EXCEP_MODE(x)      (((x) << 4U) & GENMASK(4U, 4U))
#define CPU_PROC_CTRL_BE_EXCEP_MODE_M       GENMASK(4U, 4U)
#define CPU_PROC_CTRL_BE_EXCEP_MODE_X(x)    (((x) & GENMASK(4U, 4U)) >> 4U)

#define CPU_PROC_CTRL_VINITHI(x)            (((x) << 3U) & GENMASK(3U, 3U))
#define CPU_PROC_CTRL_VINITHI_M             GENMASK(3U, 3U)
#define CPU_PROC_CTRL_VINITHI_X(x)          (((x) & GENMASK(3U, 3U)) >> 3U)

#define CPU_PROC_CTRL_CFGTE(x)              (((x) << 2U) & GENMASK(2U, 2U))
#define CPU_PROC_CTRL_CFGTE_M               GENMASK(2U, 2U)
#define CPU_PROC_CTRL_CFGTE_X(x)            (((x) & GENMASK(2U, 2U)) >> 2U)

#define CPU_PROC_CTRL_CP15S_DISABLE(x)      (((x) << 1U) & GENMASK(1U, 1U))
#define CPU_PROC_CTRL_CP15S_DISABLE_M       GENMASK(1U, 1U)
#define CPU_PROC_CTRL_CP15S_DISABLE_X(x)    (((x) & GENMASK(1U, 1U)) >> 1U)

#define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE(x) ((x) & GENMASK(0U, 0U))
#define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_M GENMASK(0U, 0U)
#define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_X(x) ((x) & GENMASK(0U, 0U))

/*      CPU:CPU_REGS:PROC_STAT */
#define CPU_PROC_STAT(t)          ((t) + 0xa4U)

#define CPU_PROC_STAT_DAP_JTAG_SW_MODE(x)   (((x) << 3U) & GENMASK(3U, 3U))
#define CPU_PROC_STAT_DAP_JTAG_SW_MODE_M    GENMASK(3U, 3U)
#define CPU_PROC_STAT_DAP_JTAG_SW_MODE_X(x) (((x) & GENMASK(3U, 3U)) >> 3U)

#define CPU_PROC_STAT_WFI(x)                (((x) << 2U) & GENMASK(2U, 2U))
#define CPU_PROC_STAT_WFI_M                 GENMASK(2U, 2U)
#define CPU_PROC_STAT_WFI_X(x)              (((x) & GENMASK(2U, 2U)) >> 2U)

#define CPU_PROC_STAT_WFIL2(x)              (((x) << 1U) & GENMASK(1U, 1U))
#define CPU_PROC_STAT_WFIL2_M               GENMASK(1U, 1U)
#define CPU_PROC_STAT_WFIL2_X(x)            (((x) & GENMASK(1U, 1U)) >> 1U)

#define CPU_PROC_STAT_WFE(x)                ((x) & GENMASK(0U, 0U))
#define CPU_PROC_STAT_WFE_M                 GENMASK(0U, 0U)
#define CPU_PROC_STAT_WFE_X(x)              ((x) & GENMASK(0U, 0U))

/*      CPU:CPU_REGS:CPU0_RVBAR_LSB */
#define CPU_CPU0_RVBAR_LSB(t)     ((t) + 0xa8U)

/*      CPU:CPU_REGS:CPU0_RVBAR_MSB */
#define CPU_CPU0_RVBAR_MSB(t)     ((t) + 0xacU)

#define CPU_CPU0_RVBAR_MSB_CPU0_RVBAR_MSB(x) ((x) & GENMASK(5U, 0U))
#define CPU_CPU0_RVBAR_MSB_CPU0_RVBAR_MSB_M GENMASK(5U, 0U)
#define CPU_CPU0_RVBAR_MSB_CPU0_RVBAR_MSB_X(x) ((x) & GENMASK(5U, 0U))

/*      CPU:CPU_REGS:CFG_INTR_INV */
#define CPU_CFG_INTR_INV(t)       ((t) + 0xb0U)

#define CPU_CFG_INTR_INV_CFG_INTR_INV(x)    ((x) & GENMASK(5U, 0U))
#define CPU_CFG_INTR_INV_CFG_INTR_INV_M     GENMASK(5U, 0U)
#define CPU_CFG_INTR_INV_CFG_INTR_INV_X(x)  ((x) & GENMASK(5U, 0U))

/*      CPU:GCK_REGS:GCK_CFG */
#define CPU_GCK_CFG(t, r)         ((t) + (0xb4U + ((r) * 4U)))

#define CPU_GCK_CFG_GCK_PRESCALER(x)        (((x) << 16U) & GENMASK(23U, 16U))
#define CPU_GCK_CFG_GCK_PRESCALER_M         GENMASK(23U, 16U)
#define CPU_GCK_CFG_GCK_PRESCALER_X(x)      (((x) & GENMASK(23U, 16U)) >> 16U)

#define CPU_GCK_CFG_GCK_SRC_SEL(x)          (((x) << 8U) & GENMASK(9U, 8U))
#define CPU_GCK_CFG_GCK_SRC_SEL_M           GENMASK(9U, 8U)
#define CPU_GCK_CFG_GCK_SRC_SEL_X(x)        (((x) & GENMASK(9U, 8U)) >> 8U)

#define CPU_GCK_CFG_GCK_ENA(x)              ((x) & GENMASK(0U, 0U))
#define CPU_GCK_CFG_GCK_ENA_M               GENMASK(0U, 0U)
#define CPU_GCK_CFG_GCK_ENA_X(x)            ((x) & GENMASK(0U, 0U))

/*      CPU:SFR_REGS:CLK_GATING */
#define CPU_CLK_GATING(t)         ((t) + 0x308U)

#define CPU_CLK_GATING_USB_DRD_CLK_GATING(x) (((x) << 10U) & GENMASK(10U, 10U))
#define CPU_CLK_GATING_USB_DRD_CLK_GATING_M GENMASK(10U, 10U)
#define CPU_CLK_GATING_USB_DRD_CLK_GATING_X(x)\
	(((x) & GENMASK(10U, 10U)) >> 10U)

#define CPU_CLK_GATING_MCRAMC_CLK_GATING(x) (((x) << 9U) & GENMASK(9U, 9U))
#define CPU_CLK_GATING_MCRAMC_CLK_GATING_M  GENMASK(9U, 9U)
#define CPU_CLK_GATING_MCRAMC_CLK_GATING_X(x) (((x) & GENMASK(9U, 9U)) >> 9U)

#define CPU_CLK_GATING_HMATRIX_CLK_GATING(x) (((x) << 8U) & GENMASK(8U, 8U))
#define CPU_CLK_GATING_HMATRIX_CLK_GATING_M GENMASK(8U, 8U)
#define CPU_CLK_GATING_HMATRIX_CLK_GATING_X(x) (((x) & GENMASK(8U, 8U)) >> 8U)

#define CPU_CLK_GATING_HBRIDGE_CLK_GATING(x) ((x) & GENMASK(3U, 0U))
#define CPU_CLK_GATING_HBRIDGE_CLK_GATING_M GENMASK(3U, 0U)
#define CPU_CLK_GATING_HBRIDGE_CLK_GATING_X(x) ((x) & GENMASK(3U, 0U))

/*      CPU:SFR_REGS:TZAESB */
#define CPU_TZAESB(t)             ((t) + 0x310U)

#define CPU_TZAESB_TZAESB_LITE_EN(x)        ((x) & GENMASK(0U, 0U))
#define CPU_TZAESB_TZAESB_LITE_EN_M         GENMASK(0U, 0U)
#define CPU_TZAESB_TZAESB_LITE_EN_X(x)      ((x) & GENMASK(0U, 0U))

/*      CPU_SYSCNT:CXTSGEN_REGISTERS:CNTCR */
#define CPU_SYSCNT_CNTCR(t)       ((t) + 0x00U)

#define CPU_SYSCNT_CNTCR_CNTCR_EN(x)        ((x) & GENMASK(0U, 0U))
#define CPU_SYSCNT_CNTCR_CNTCR_EN_M         GENMASK(0U, 0U)
#define CPU_SYSCNT_CNTCR_CNTCR_EN_X(x)      ((x) & GENMASK(0U, 0U))

#define CPU_SYSCNT_CNTCR_CNTCR_HDBG(x)      (((x) << 1U) & GENMASK(1U, 1U))
#define CPU_SYSCNT_CNTCR_CNTCR_HDBG_M       GENMASK(1U, 1U)
#define CPU_SYSCNT_CNTCR_CNTCR_HDBG_X(x)    (((x) & GENMASK(1U, 1U)) >> 1U)

/*      CPU_SYSCNT:CXTSGEN_REGISTERS:CNTSR */
#define CPU_SYSCNT_CNTSR(t)       ((t) + 0x04U)

#define CPU_SYSCNT_CNTSR_CNTSR_DBGH(x)      (((x) << 1U) & GENMASK(1U, 1U))
#define CPU_SYSCNT_CNTSR_CNTSR_DBGH_M       GENMASK(1U, 1U)
#define CPU_SYSCNT_CNTSR_CNTSR_DBGH_X(x)    (((x) & GENMASK(1U, 1U)) >> 1U)

/*      CPU_SYSCNT:CXTSGEN_REGISTERS:CNTCVL */
#define CPU_SYSCNT_CNTCVL(t)      ((t) + 0x08U)

/*      CPU_SYSCNT:CXTSGEN_REGISTERS:CNTCVU */
#define CPU_SYSCNT_CNTCVU(t)      ((t) + 0x0cU)

/*      CPU_SYSCNT:CXTSGEN_REGISTERS:CNTFID0 */
#define CPU_SYSCNT_CNTFID0(t)     ((t) + 0x20U)

/*      CPU_SYSCNT:CXTSGEN_REGISTERS:PIDR0 */
#define CPU_SYSCNT_PIDR0(t)       ((t) + 0xfe0U)

#define CPU_SYSCNT_PIDR0_PART_0(x)          ((x) & GENMASK(7U, 0U))
#define CPU_SYSCNT_PIDR0_PART_0_M           GENMASK(7U, 0U)
#define CPU_SYSCNT_PIDR0_PART_0_X(x)        ((x) & GENMASK(7U, 0U))

/*      CPU_SYSCNT:CXTSGEN_REGISTERS:PIDR1 */
#define CPU_SYSCNT_PIDR1(t)       ((t) + 0xfe4U)

#define CPU_SYSCNT_PIDR1_PART_1(x)          ((x) & GENMASK(3U, 0U))
#define CPU_SYSCNT_PIDR1_PART_1_M           GENMASK(3U, 0U)
#define CPU_SYSCNT_PIDR1_PART_1_X(x)        ((x) & GENMASK(3U, 0U))

#define CPU_SYSCNT_PIDR1_DES_0(x)           (((x) << 4U) & GENMASK(7U, 4U))
#define CPU_SYSCNT_PIDR1_DES_0_M            GENMASK(7U, 4U)
#define CPU_SYSCNT_PIDR1_DES_0_X(x)         (((x) & GENMASK(7U, 4U)) >> 4U)

/*      CPU_SYSCNT:CXTSGEN_REGISTERS:PIDR2 */
#define CPU_SYSCNT_PIDR2(t)       ((t) + 0xfe8U)

#define CPU_SYSCNT_PIDR2_DES_1(x)           ((x) & GENMASK(2U, 0U))
#define CPU_SYSCNT_PIDR2_DES_1_M            GENMASK(2U, 0U)
#define CPU_SYSCNT_PIDR2_DES_1_X(x)         ((x) & GENMASK(2U, 0U))

#define CPU_SYSCNT_PIDR2_JEDEC(x)           (((x) << 3U) & GENMASK(3U, 3U))
#define CPU_SYSCNT_PIDR2_JEDEC_M            GENMASK(3U, 3U)
#define CPU_SYSCNT_PIDR2_JEDEC_X(x)         (((x) & GENMASK(3U, 3U)) >> 3U)

#define CPU_SYSCNT_PIDR2_REVISION(x)        (((x) << 4U) & GENMASK(7U, 4U))
#define CPU_SYSCNT_PIDR2_REVISION_M         GENMASK(7U, 4U)
#define CPU_SYSCNT_PIDR2_REVISION_X(x)      (((x) & GENMASK(7U, 4U)) >> 4U)

/*      CPU_SYSCNT:CXTSGEN_REGISTERS:PIDR3 */
#define CPU_SYSCNT_PIDR3(t)       ((t) + 0xfecU)

#define CPU_SYSCNT_PIDR3_CMOD(x)            ((x) & GENMASK(3U, 0U))
#define CPU_SYSCNT_PIDR3_CMOD_M             GENMASK(3U, 0U)
#define CPU_SYSCNT_PIDR3_CMOD_X(x)          ((x) & GENMASK(3U, 0U))

#define CPU_SYSCNT_PIDR3_REVAND(x)          (((x) << 4U) & GENMASK(7U, 4U))
#define CPU_SYSCNT_PIDR3_REVAND_M           GENMASK(7U, 4U)
#define CPU_SYSCNT_PIDR3_REVAND_X(x)        (((x) & GENMASK(7U, 4U)) >> 4U)

/*      CPU_SYSCNT:CXTSGEN_REGISTERS:PIDR4 */
#define CPU_SYSCNT_PIDR4(t)       ((t) + 0xfd0U)

#define CPU_SYSCNT_PIDR4_DES_2(x)           ((x) & GENMASK(3U, 0U))
#define CPU_SYSCNT_PIDR4_DES_2_M            GENMASK(3U, 0U)
#define CPU_SYSCNT_PIDR4_DES_2_X(x)         ((x) & GENMASK(3U, 0U))

#define CPU_SYSCNT_PIDR4_SIZE(x)            (((x) << 4U) & GENMASK(7U, 4U))
#define CPU_SYSCNT_PIDR4_SIZE_M             GENMASK(7U, 4U)
#define CPU_SYSCNT_PIDR4_SIZE_X(x)          (((x) & GENMASK(7U, 4U)) >> 4U)

/*      CPU_SYSCNT:CXTSGEN_REGISTERS:CIDR0 */
#define CPU_SYSCNT_CIDR0(t)       ((t) + 0xff0U)

#define CPU_SYSCNT_CIDR0_PRMBL_0(x)         ((x) & GENMASK(7U, 0U))
#define CPU_SYSCNT_CIDR0_PRMBL_0_M          GENMASK(7U, 0U)
#define CPU_SYSCNT_CIDR0_PRMBL_0_X(x)       ((x) & GENMASK(7U, 0U))

/*      CPU_SYSCNT:CXTSGEN_REGISTERS:CIDR1 */
#define CPU_SYSCNT_CIDR1(t)       ((t) + 0xff4U)

#define CPU_SYSCNT_CIDR1_PRMBL_1(x)         ((x) & GENMASK(3U, 0U))
#define CPU_SYSCNT_CIDR1_PRMBL_1_M          GENMASK(3U, 0U)
#define CPU_SYSCNT_CIDR1_PRMBL_1_X(x)       ((x) & GENMASK(3U, 0U))

#define CPU_SYSCNT_CIDR1_CLASS(x)           (((x) << 4U) & GENMASK(7U, 4U))
#define CPU_SYSCNT_CIDR1_CLASS_M            GENMASK(7U, 4U)
#define CPU_SYSCNT_CIDR1_CLASS_X(x)         (((x) & GENMASK(7U, 4U)) >> 4U)

/*      CPU_SYSCNT:CXTSGEN_REGISTERS:CIDR2 */
#define CPU_SYSCNT_CIDR2(t)       ((t) + 0xff8U)

#define CPU_SYSCNT_CIDR2_PRMBL_2(x)         ((x) & GENMASK(7U, 0U))
#define CPU_SYSCNT_CIDR2_PRMBL_2_M          GENMASK(7U, 0U)
#define CPU_SYSCNT_CIDR2_PRMBL_2_X(x)       ((x) & GENMASK(7U, 0U))

/*      CPU_SYSCNT:CXTSGEN_REGISTERS:CIDR3 */
#define CPU_SYSCNT_CIDR3(t)       ((t) + 0xffcU)

#define CPU_SYSCNT_CIDR3_PRMBL_3(x)         ((x) & GENMASK(7U, 0U))
#define CPU_SYSCNT_CIDR3_PRMBL_3_M          GENMASK(7U, 0U)
#define CPU_SYSCNT_CIDR3_PRMBL_3_X(x)       ((x) & GENMASK(7U, 0U))

/*      CPU_SYSCNT_RO:CXTSGEN_READ_REGISTERS:CNTCVL */
#define CPU_SYSCNT_RO_CNTCVL(t)   ((t) + 0x1000U)

/*      CPU_SYSCNT_RO:CXTSGEN_READ_REGISTERS:CNTCVU */
#define CPU_SYSCNT_RO_CNTCVU(t)   ((t) + 0x1004U)

/*      CPU_SYSCNT_RO:CXTSGEN_READ_REGISTERS:PIDR0 */
#define CPU_SYSCNT_RO_PIDR0(t)    ((t) + 0x1fe0U)

#define CPU_SYSCNT_RO_PIDR0_PART_0(x)       ((x) & GENMASK(7U, 0U))
#define CPU_SYSCNT_RO_PIDR0_PART_0_M        GENMASK(7U, 0U)
#define CPU_SYSCNT_RO_PIDR0_PART_0_X(x)     ((x) & GENMASK(7U, 0U))

/*      CPU_SYSCNT_RO:CXTSGEN_READ_REGISTERS:PIDR1 */
#define CPU_SYSCNT_RO_PIDR1(t)    ((t) + 0x1fe4U)

#define CPU_SYSCNT_RO_PIDR1_PART_1(x)       ((x) & GENMASK(3U, 0U))
#define CPU_SYSCNT_RO_PIDR1_PART_1_M        GENMASK(3U, 0U)
#define CPU_SYSCNT_RO_PIDR1_PART_1_X(x)     ((x) & GENMASK(3U, 0U))

#define CPU_SYSCNT_RO_PIDR1_DES_0(x)        (((x) << 4U) & GENMASK(7U, 4U))
#define CPU_SYSCNT_RO_PIDR1_DES_0_M         GENMASK(7U, 4U)
#define CPU_SYSCNT_RO_PIDR1_DES_0_X(x)      (((x) & GENMASK(7U, 4U)) >> 4U)

/*      CPU_SYSCNT_RO:CXTSGEN_READ_REGISTERS:PIDR2 */
#define CPU_SYSCNT_RO_PIDR2(t)    ((t) + 0x1fe8U)

#define CPU_SYSCNT_RO_PIDR2_DES_1(x)        ((x) & GENMASK(2U, 0U))
#define CPU_SYSCNT_RO_PIDR2_DES_1_M         GENMASK(2U, 0U)
#define CPU_SYSCNT_RO_PIDR2_DES_1_X(x)      ((x) & GENMASK(2U, 0U))

#define CPU_SYSCNT_RO_PIDR2_JEDEC(x)        (((x) << 3U) & GENMASK(3U, 3U))
#define CPU_SYSCNT_RO_PIDR2_JEDEC_M         GENMASK(3U, 3U)
#define CPU_SYSCNT_RO_PIDR2_JEDEC_X(x)      (((x) & GENMASK(3U, 3U)) >> 3U)

#define CPU_SYSCNT_RO_PIDR2_REVISION(x)     (((x) << 4U) & GENMASK(7U, 4U))
#define CPU_SYSCNT_RO_PIDR2_REVISION_M      GENMASK(7U, 4U)
#define CPU_SYSCNT_RO_PIDR2_REVISION_X(x)   (((x) & GENMASK(7U, 4U)) >> 4U)

/*      CPU_SYSCNT_RO:CXTSGEN_READ_REGISTERS:PIDR3 */
#define CPU_SYSCNT_RO_PIDR3(t)    ((t) + 0x1fecU)

#define CPU_SYSCNT_RO_PIDR3_CMOD(x)         ((x) & GENMASK(3U, 0U))
#define CPU_SYSCNT_RO_PIDR3_CMOD_M          GENMASK(3U, 0U)
#define CPU_SYSCNT_RO_PIDR3_CMOD_X(x)       ((x) & GENMASK(3U, 0U))

#define CPU_SYSCNT_RO_PIDR3_REVAND(x)       (((x) << 4U) & GENMASK(7U, 4U))
#define CPU_SYSCNT_RO_PIDR3_REVAND_M        GENMASK(7U, 4U)
#define CPU_SYSCNT_RO_PIDR3_REVAND_X(x)     (((x) & GENMASK(7U, 4U)) >> 4U)

/*      CPU_SYSCNT_RO:CXTSGEN_READ_REGISTERS:PIDR4 */
#define CPU_SYSCNT_RO_PIDR4(t)    ((t) + 0x1fd0U)

#define CPU_SYSCNT_RO_PIDR4_DES_2(x)        ((x) & GENMASK(3U, 0U))
#define CPU_SYSCNT_RO_PIDR4_DES_2_M         GENMASK(3U, 0U)
#define CPU_SYSCNT_RO_PIDR4_DES_2_X(x)      ((x) & GENMASK(3U, 0U))

#define CPU_SYSCNT_RO_PIDR4_SIZE(x)         (((x) << 4U) & GENMASK(7U, 4U))
#define CPU_SYSCNT_RO_PIDR4_SIZE_M          GENMASK(7U, 4U)
#define CPU_SYSCNT_RO_PIDR4_SIZE_X(x)       (((x) & GENMASK(7U, 4U)) >> 4U)

/*      CPU_SYSCNT_RO:CXTSGEN_READ_REGISTERS:CIDR0 */
#define CPU_SYSCNT_RO_CIDR0(t)    ((t) + 0x1ff0U)

#define CPU_SYSCNT_RO_CIDR0_PRMBL_0(x)      ((x) & GENMASK(7U, 0U))
#define CPU_SYSCNT_RO_CIDR0_PRMBL_0_M       GENMASK(7U, 0U)
#define CPU_SYSCNT_RO_CIDR0_PRMBL_0_X(x)    ((x) & GENMASK(7U, 0U))

/*      CPU_SYSCNT_RO:CXTSGEN_READ_REGISTERS:CIDR1 */
#define CPU_SYSCNT_RO_CIDR1(t)    ((t) + 0x1ff4U)

#define CPU_SYSCNT_RO_CIDR1_PRMBL_1(x)      ((x) & GENMASK(3U, 0U))
#define CPU_SYSCNT_RO_CIDR1_PRMBL_1_M       GENMASK(3U, 0U)
#define CPU_SYSCNT_RO_CIDR1_PRMBL_1_X(x)    ((x) & GENMASK(3U, 0U))

#define CPU_SYSCNT_RO_CIDR1_CLASS(x)        (((x) << 4U) & GENMASK(7U, 4U))
#define CPU_SYSCNT_RO_CIDR1_CLASS_M         GENMASK(7U, 4U)
#define CPU_SYSCNT_RO_CIDR1_CLASS_X(x)      (((x) & GENMASK(7U, 4U)) >> 4U)

/*      CPU_SYSCNT_RO:CXTSGEN_READ_REGISTERS:CIDR2 */
#define CPU_SYSCNT_RO_CIDR2(t)    ((t) + 0x1ff8U)

#define CPU_SYSCNT_RO_CIDR2_PRMBL_2(x)      ((x) & GENMASK(7U, 0U))
#define CPU_SYSCNT_RO_CIDR2_PRMBL_2_M       GENMASK(7U, 0U)
#define CPU_SYSCNT_RO_CIDR2_PRMBL_2_X(x)    ((x) & GENMASK(7U, 0U))

/*      CPU_SYSCNT_RO:CXTSGEN_READ_REGISTERS:CIDR3 */
#define CPU_SYSCNT_RO_CIDR3(t)    ((t) + 0x1ffcU)

#define CPU_SYSCNT_RO_CIDR3_PRMBL_3(x)      ((x) & GENMASK(7U, 0U))
#define CPU_SYSCNT_RO_CIDR3_PRMBL_3_M       GENMASK(7U, 0U)
#define CPU_SYSCNT_RO_CIDR3_PRMBL_3_X(x)    ((x) & GENMASK(7U, 0U))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_CR */
#define FLEXCOM_FLEX_US_CR(t)     ((t) + 0x200U)

#define FLEXCOM_FLEX_US_CR_FIFODIS(x)       (((x) << 31U) & GENMASK(31U, 31U))
#define FLEXCOM_FLEX_US_CR_FIFODIS_M        GENMASK(31U, 31U)
#define FLEXCOM_FLEX_US_CR_FIFODIS_X(x)     (((x) & GENMASK(31U, 31U)) >> 31U)

#define FLEXCOM_FLEX_US_CR_FIFOEN(x)        (((x) << 30U) & GENMASK(30U, 30U))
#define FLEXCOM_FLEX_US_CR_FIFOEN_M         GENMASK(30U, 30U)
#define FLEXCOM_FLEX_US_CR_FIFOEN_X(x)      (((x) & GENMASK(30U, 30U)) >> 30U)

#define FLEXCOM_FLEX_US_CR_USART_REQCLR(x)  (((x) << 28U) & GENMASK(28U, 28U))
#define FLEXCOM_FLEX_US_CR_USART_REQCLR_M   GENMASK(28U, 28U)
#define FLEXCOM_FLEX_US_CR_USART_REQCLR_X(x) (((x) & GENMASK(28U, 28U)) >> 28U)

#define FLEXCOM_FLEX_US_CR_TXFLCLR(x)       (((x) << 26U) & GENMASK(26U, 26U))
#define FLEXCOM_FLEX_US_CR_TXFLCLR_M        GENMASK(26U, 26U)
#define FLEXCOM_FLEX_US_CR_TXFLCLR_X(x)     (((x) & GENMASK(26U, 26U)) >> 26U)

#define FLEXCOM_FLEX_US_CR_RXFCLR(x)        (((x) << 25U) & GENMASK(25U, 25U))
#define FLEXCOM_FLEX_US_CR_RXFCLR_M         GENMASK(25U, 25U)
#define FLEXCOM_FLEX_US_CR_RXFCLR_X(x)      (((x) & GENMASK(25U, 25U)) >> 25U)

#define FLEXCOM_FLEX_US_CR_TXFCLR(x)        (((x) << 24U) & GENMASK(24U, 24U))
#define FLEXCOM_FLEX_US_CR_TXFCLR_M         GENMASK(24U, 24U)
#define FLEXCOM_FLEX_US_CR_TXFCLR_X(x)      (((x) & GENMASK(24U, 24U)) >> 24U)

#define FLEXCOM_FLEX_US_CR_LINWKUP(x)       (((x) << 21U) & GENMASK(21U, 21U))
#define FLEXCOM_FLEX_US_CR_LINWKUP_M        GENMASK(21U, 21U)
#define FLEXCOM_FLEX_US_CR_LINWKUP_X(x)     (((x) & GENMASK(21U, 21U)) >> 21U)

#define FLEXCOM_FLEX_US_CR_LINABT(x)        (((x) << 20U) & GENMASK(20U, 20U))
#define FLEXCOM_FLEX_US_CR_LINABT_M         GENMASK(20U, 20U)
#define FLEXCOM_FLEX_US_CR_LINABT_X(x)      (((x) & GENMASK(20U, 20U)) >> 20U)

#define FLEXCOM_FLEX_US_CR_RTSDIS(x)        (((x) << 19U) & GENMASK(19U, 19U))
#define FLEXCOM_FLEX_US_CR_RTSDIS_M         GENMASK(19U, 19U)
#define FLEXCOM_FLEX_US_CR_RTSDIS_X(x)      (((x) & GENMASK(19U, 19U)) >> 19U)

#define FLEXCOM_FLEX_US_CR_RTSEN(x)         (((x) << 18U) & GENMASK(18U, 18U))
#define FLEXCOM_FLEX_US_CR_RTSEN_M          GENMASK(18U, 18U)
#define FLEXCOM_FLEX_US_CR_RTSEN_X(x)       (((x) & GENMASK(18U, 18U)) >> 18U)

#define FLEXCOM_FLEX_US_CR_DTRDIS(x)        (((x) << 17U) & GENMASK(17U, 17U))
#define FLEXCOM_FLEX_US_CR_DTRDIS_M         GENMASK(17U, 17U)
#define FLEXCOM_FLEX_US_CR_DTRDIS_X(x)      (((x) & GENMASK(17U, 17U)) >> 17U)

#define FLEXCOM_FLEX_US_CR_DTREN(x)         (((x) << 16U) & GENMASK(16U, 16U))
#define FLEXCOM_FLEX_US_CR_DTREN_M          GENMASK(16U, 16U)
#define FLEXCOM_FLEX_US_CR_DTREN_X(x)       (((x) & GENMASK(16U, 16U)) >> 16U)

#define FLEXCOM_FLEX_US_CR_RETTO(x)         (((x) << 15U) & GENMASK(15U, 15U))
#define FLEXCOM_FLEX_US_CR_RETTO_M          GENMASK(15U, 15U)
#define FLEXCOM_FLEX_US_CR_RETTO_X(x)       (((x) & GENMASK(15U, 15U)) >> 15U)

#define FLEXCOM_FLEX_US_CR_RSTNACK(x)       (((x) << 14U) & GENMASK(14U, 14U))
#define FLEXCOM_FLEX_US_CR_RSTNACK_M        GENMASK(14U, 14U)
#define FLEXCOM_FLEX_US_CR_RSTNACK_X(x)     (((x) & GENMASK(14U, 14U)) >> 14U)

#define FLEXCOM_FLEX_US_CR_RSTIT(x)         (((x) << 13U) & GENMASK(13U, 13U))
#define FLEXCOM_FLEX_US_CR_RSTIT_M          GENMASK(13U, 13U)
#define FLEXCOM_FLEX_US_CR_RSTIT_X(x)       (((x) & GENMASK(13U, 13U)) >> 13U)

#define FLEXCOM_FLEX_US_CR_SENDA(x)         (((x) << 12U) & GENMASK(12U, 12U))
#define FLEXCOM_FLEX_US_CR_SENDA_M          GENMASK(12U, 12U)
#define FLEXCOM_FLEX_US_CR_SENDA_X(x)       (((x) & GENMASK(12U, 12U)) >> 12U)

#define FLEXCOM_FLEX_US_CR_STTTO(x)         (((x) << 11U) & GENMASK(11U, 11U))
#define FLEXCOM_FLEX_US_CR_STTTO_M          GENMASK(11U, 11U)
#define FLEXCOM_FLEX_US_CR_STTTO_X(x)       (((x) & GENMASK(11U, 11U)) >> 11U)

#define FLEXCOM_FLEX_US_CR_STPBRK(x)        (((x) << 10U) & GENMASK(10U, 10U))
#define FLEXCOM_FLEX_US_CR_STPBRK_M         GENMASK(10U, 10U)
#define FLEXCOM_FLEX_US_CR_STPBRK_X(x)      (((x) & GENMASK(10U, 10U)) >> 10U)

#define FLEXCOM_FLEX_US_CR_STTBRK(x)        (((x) << 9U) & GENMASK(9U, 9U))
#define FLEXCOM_FLEX_US_CR_STTBRK_M         GENMASK(9U, 9U)
#define FLEXCOM_FLEX_US_CR_STTBRK_X(x)      (((x) & GENMASK(9U, 9U)) >> 9U)

#define FLEXCOM_FLEX_US_CR_RSTSTA(x)        (((x) << 8U) & GENMASK(8U, 8U))
#define FLEXCOM_FLEX_US_CR_RSTSTA_M         GENMASK(8U, 8U)
#define FLEXCOM_FLEX_US_CR_RSTSTA_X(x)      (((x) & GENMASK(8U, 8U)) >> 8U)

#define FLEXCOM_FLEX_US_CR_TXDIS(x)         (((x) << 7U) & GENMASK(7U, 7U))
#define FLEXCOM_FLEX_US_CR_TXDIS_M          GENMASK(7U, 7U)
#define FLEXCOM_FLEX_US_CR_TXDIS_X(x)       (((x) & GENMASK(7U, 7U)) >> 7U)

#define FLEXCOM_FLEX_US_CR_TXEN(x)          (((x) << 6U) & GENMASK(6U, 6U))
#define FLEXCOM_FLEX_US_CR_TXEN_M           GENMASK(6U, 6U)
#define FLEXCOM_FLEX_US_CR_TXEN_X(x)        (((x) & GENMASK(6U, 6U)) >> 6U)

#define FLEXCOM_FLEX_US_CR_RXDIS(x)         (((x) << 5U) & GENMASK(5U, 5U))
#define FLEXCOM_FLEX_US_CR_RXDIS_M          GENMASK(5U, 5U)
#define FLEXCOM_FLEX_US_CR_RXDIS_X(x)       (((x) & GENMASK(5U, 5U)) >> 5U)

#define FLEXCOM_FLEX_US_CR_RXEN(x)          (((x) << 4U) & GENMASK(4U, 4U))
#define FLEXCOM_FLEX_US_CR_RXEN_M           GENMASK(4U, 4U)
#define FLEXCOM_FLEX_US_CR_RXEN_X(x)        (((x) & GENMASK(4U, 4U)) >> 4U)

#define FLEXCOM_FLEX_US_CR_RSTTX(x)         (((x) << 3U) & GENMASK(3U, 3U))
#define FLEXCOM_FLEX_US_CR_RSTTX_M          GENMASK(3U, 3U)
#define FLEXCOM_FLEX_US_CR_RSTTX_X(x)       (((x) & GENMASK(3U, 3U)) >> 3U)

#define FLEXCOM_FLEX_US_CR_RSTRX(x)         (((x) << 2U) & GENMASK(2U, 2U))
#define FLEXCOM_FLEX_US_CR_RSTRX_M          GENMASK(2U, 2U)
#define FLEXCOM_FLEX_US_CR_RSTRX_X(x)       (((x) & GENMASK(2U, 2U)) >> 2U)

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_MR */
#define FLEXCOM_FLEX_US_MR(t)     ((t) + 0x204U)

#define FLEXCOM_FLEX_US_MR_ONEBIT(x)        (((x) << 31U) & GENMASK(31U, 31U))
#define FLEXCOM_FLEX_US_MR_ONEBIT_M         GENMASK(31U, 31U)
#define FLEXCOM_FLEX_US_MR_ONEBIT_X(x)      (((x) & GENMASK(31U, 31U)) >> 31U)

#define FLEXCOM_FLEX_US_MR_MODSYNC(x)       (((x) << 30U) & GENMASK(30U, 30U))
#define FLEXCOM_FLEX_US_MR_MODSYNC_M        GENMASK(30U, 30U)
#define FLEXCOM_FLEX_US_MR_MODSYNC_X(x)     (((x) & GENMASK(30U, 30U)) >> 30U)

#define FLEXCOM_FLEX_US_MR_MAN(x)           (((x) << 29U) & GENMASK(29U, 29U))
#define FLEXCOM_FLEX_US_MR_MAN_M            GENMASK(29U, 29U)
#define FLEXCOM_FLEX_US_MR_MAN_X(x)         (((x) & GENMASK(29U, 29U)) >> 29U)

#define FLEXCOM_FLEX_US_MR_FILTER(x)        (((x) << 28U) & GENMASK(28U, 28U))
#define FLEXCOM_FLEX_US_MR_FILTER_M         GENMASK(28U, 28U)
#define FLEXCOM_FLEX_US_MR_FILTER_X(x)      (((x) & GENMASK(28U, 28U)) >> 28U)

#define FLEXCOM_FLEX_US_MR_MAX_ITERATION(x) (((x) << 24U) & GENMASK(26U, 24U))
#define FLEXCOM_FLEX_US_MR_MAX_ITERATION_M  GENMASK(26U, 24U)
#define FLEXCOM_FLEX_US_MR_MAX_ITERATION_X(x) (((x) & GENMASK(26U, 24U)) >> 24U)

#define FLEXCOM_FLEX_US_MR_INVDATA(x)       (((x) << 23U) & GENMASK(23U, 23U))
#define FLEXCOM_FLEX_US_MR_INVDATA_M        GENMASK(23U, 23U)
#define FLEXCOM_FLEX_US_MR_INVDATA_X(x)     (((x) & GENMASK(23U, 23U)) >> 23U)

#define FLEXCOM_FLEX_US_MR_VAR_SYNC(x)      (((x) << 22U) & GENMASK(22U, 22U))
#define FLEXCOM_FLEX_US_MR_VAR_SYNC_M       GENMASK(22U, 22U)
#define FLEXCOM_FLEX_US_MR_VAR_SYNC_X(x)    (((x) & GENMASK(22U, 22U)) >> 22U)

#define FLEXCOM_FLEX_US_MR_DSNACK(x)        (((x) << 21U) & GENMASK(21U, 21U))
#define FLEXCOM_FLEX_US_MR_DSNACK_M         GENMASK(21U, 21U)
#define FLEXCOM_FLEX_US_MR_DSNACK_X(x)      (((x) & GENMASK(21U, 21U)) >> 21U)

#define FLEXCOM_FLEX_US_MR_INACK(x)         (((x) << 20U) & GENMASK(20U, 20U))
#define FLEXCOM_FLEX_US_MR_INACK_M          GENMASK(20U, 20U)
#define FLEXCOM_FLEX_US_MR_INACK_X(x)       (((x) & GENMASK(20U, 20U)) >> 20U)

#define FLEXCOM_FLEX_US_MR_OVER(x)          (((x) << 19U) & GENMASK(19U, 19U))
#define FLEXCOM_FLEX_US_MR_OVER_M           GENMASK(19U, 19U)
#define FLEXCOM_FLEX_US_MR_OVER_X(x)        (((x) & GENMASK(19U, 19U)) >> 19U)

#define FLEXCOM_FLEX_US_MR_CLKO(x)          (((x) << 18U) & GENMASK(18U, 18U))
#define FLEXCOM_FLEX_US_MR_CLKO_M           GENMASK(18U, 18U)
#define FLEXCOM_FLEX_US_MR_CLKO_X(x)        (((x) & GENMASK(18U, 18U)) >> 18U)

#define FLEXCOM_FLEX_US_MR_MODE9(x)         (((x) << 17U) & GENMASK(17U, 17U))
#define FLEXCOM_FLEX_US_MR_MODE9_M          GENMASK(17U, 17U)
#define FLEXCOM_FLEX_US_MR_MODE9_X(x)       (((x) & GENMASK(17U, 17U)) >> 17U)

#define FLEXCOM_FLEX_US_MR_MSBF(x)          (((x) << 16U) & GENMASK(16U, 16U))
#define FLEXCOM_FLEX_US_MR_MSBF_M           GENMASK(16U, 16U)
#define FLEXCOM_FLEX_US_MR_MSBF_X(x)        (((x) & GENMASK(16U, 16U)) >> 16U)

#define FLEXCOM_FLEX_US_MR_CHMODE(x)        (((x) << 14U) & GENMASK(15U, 14U))
#define FLEXCOM_FLEX_US_MR_CHMODE_M         GENMASK(15U, 14U)
#define FLEXCOM_FLEX_US_MR_CHMODE_X(x)      (((x) & GENMASK(15U, 14U)) >> 14U)

#define FLEXCOM_FLEX_US_MR_NBSTOP(x)        (((x) << 12U) & GENMASK(13U, 12U))
#define FLEXCOM_FLEX_US_MR_NBSTOP_M         GENMASK(13U, 12U)
#define FLEXCOM_FLEX_US_MR_NBSTOP_X(x)      (((x) & GENMASK(13U, 12U)) >> 12U)

#define FLEXCOM_FLEX_US_MR_PAR(x)           (((x) << 9U) & GENMASK(11U, 9U))
#define FLEXCOM_FLEX_US_MR_PAR_M            GENMASK(11U, 9U)
#define FLEXCOM_FLEX_US_MR_PAR_X(x)         (((x) & GENMASK(11U, 9U)) >> 9U)

#define FLEXCOM_FLEX_US_MR_SYNC(x)          (((x) << 8U) & GENMASK(8U, 8U))
#define FLEXCOM_FLEX_US_MR_SYNC_M           GENMASK(8U, 8U)
#define FLEXCOM_FLEX_US_MR_SYNC_X(x)        (((x) & GENMASK(8U, 8U)) >> 8U)

#define FLEXCOM_FLEX_US_MR_CHRL(x)          (((x) << 6U) & GENMASK(7U, 6U))
#define FLEXCOM_FLEX_US_MR_CHRL_M           GENMASK(7U, 6U)
#define FLEXCOM_FLEX_US_MR_CHRL_X(x)        (((x) & GENMASK(7U, 6U)) >> 6U)

#define FLEXCOM_FLEX_US_MR_USCLKS(x)        (((x) << 4U) & GENMASK(5U, 4U))
#define FLEXCOM_FLEX_US_MR_USCLKS_M         GENMASK(5U, 4U)
#define FLEXCOM_FLEX_US_MR_USCLKS_X(x)      (((x) & GENMASK(5U, 4U)) >> 4U)

#define FLEXCOM_FLEX_US_MR_USART_MODE(x)    ((x) & GENMASK(3U, 0U))
#define FLEXCOM_FLEX_US_MR_USART_MODE_M     GENMASK(3U, 0U)
#define FLEXCOM_FLEX_US_MR_USART_MODE_X(x)  ((x) & GENMASK(3U, 0U))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_IER */
#define FLEXCOM_FLEX_US_IER(t)    ((t) + 0x208U)

#define FLEXCOM_FLEX_US_IER_MANE_IE(x)      (((x) << 24U) & GENMASK(24U, 24U))
#define FLEXCOM_FLEX_US_IER_MANE_IE_M       GENMASK(24U, 24U)
#define FLEXCOM_FLEX_US_IER_MANE_IE_X(x)    (((x) & GENMASK(24U, 24U)) >> 24U)

#define FLEXCOM_FLEX_US_IER_CMP_IE(x)       (((x) << 22U) & GENMASK(22U, 22U))
#define FLEXCOM_FLEX_US_IER_CMP_IE_M        GENMASK(22U, 22U)
#define FLEXCOM_FLEX_US_IER_CMP_IE_X(x)     (((x) & GENMASK(22U, 22U)) >> 22U)

#define FLEXCOM_FLEX_US_IER_CTSIC_IE(x)     (((x) << 19U) & GENMASK(19U, 19U))
#define FLEXCOM_FLEX_US_IER_CTSIC_IE_M      GENMASK(19U, 19U)
#define FLEXCOM_FLEX_US_IER_CTSIC_IE_X(x)   (((x) & GENMASK(19U, 19U)) >> 19U)

#define FLEXCOM_FLEX_US_IER_DCDIC_IE(x)     (((x) << 18U) & GENMASK(18U, 18U))
#define FLEXCOM_FLEX_US_IER_DCDIC_IE_M      GENMASK(18U, 18U)
#define FLEXCOM_FLEX_US_IER_DCDIC_IE_X(x)   (((x) & GENMASK(18U, 18U)) >> 18U)

#define FLEXCOM_FLEX_US_IER_DSRIC_IE(x)     (((x) << 17U) & GENMASK(17U, 17U))
#define FLEXCOM_FLEX_US_IER_DSRIC_IE_M      GENMASK(17U, 17U)
#define FLEXCOM_FLEX_US_IER_DSRIC_IE_X(x)   (((x) & GENMASK(17U, 17U)) >> 17U)

#define FLEXCOM_FLEX_US_IER_RIIC_IE(x)      (((x) << 16U) & GENMASK(16U, 16U))
#define FLEXCOM_FLEX_US_IER_RIIC_IE_M       GENMASK(16U, 16U)
#define FLEXCOM_FLEX_US_IER_RIIC_IE_X(x)    (((x) & GENMASK(16U, 16U)) >> 16U)

#define FLEXCOM_FLEX_US_IER_NACK_IE(x)      (((x) << 13U) & GENMASK(13U, 13U))
#define FLEXCOM_FLEX_US_IER_NACK_IE_M       GENMASK(13U, 13U)
#define FLEXCOM_FLEX_US_IER_NACK_IE_X(x)    (((x) & GENMASK(13U, 13U)) >> 13U)

#define FLEXCOM_FLEX_US_IER_RXBUFF_IE(x)    (((x) << 12U) & GENMASK(12U, 12U))
#define FLEXCOM_FLEX_US_IER_RXBUFF_IE_M     GENMASK(12U, 12U)
#define FLEXCOM_FLEX_US_IER_RXBUFF_IE_X(x)  (((x) & GENMASK(12U, 12U)) >> 12U)

#define FLEXCOM_FLEX_US_IER_TXBUFE_IE(x)    (((x) << 11U) & GENMASK(11U, 11U))
#define FLEXCOM_FLEX_US_IER_TXBUFE_IE_M     GENMASK(11U, 11U)
#define FLEXCOM_FLEX_US_IER_TXBUFE_IE_X(x)  (((x) & GENMASK(11U, 11U)) >> 11U)

#define FLEXCOM_FLEX_US_IER_ITER_IE(x)      (((x) << 10U) & GENMASK(10U, 10U))
#define FLEXCOM_FLEX_US_IER_ITER_IE_M       GENMASK(10U, 10U)
#define FLEXCOM_FLEX_US_IER_ITER_IE_X(x)    (((x) & GENMASK(10U, 10U)) >> 10U)

#define FLEXCOM_FLEX_US_IER_TXEMPTY_IE(x)   (((x) << 9U) & GENMASK(9U, 9U))
#define FLEXCOM_FLEX_US_IER_TXEMPTY_IE_M    GENMASK(9U, 9U)
#define FLEXCOM_FLEX_US_IER_TXEMPTY_IE_X(x) (((x) & GENMASK(9U, 9U)) >> 9U)

#define FLEXCOM_FLEX_US_IER_TIMEOUT_IE(x)   (((x) << 8U) & GENMASK(8U, 8U))
#define FLEXCOM_FLEX_US_IER_TIMEOUT_IE_M    GENMASK(8U, 8U)
#define FLEXCOM_FLEX_US_IER_TIMEOUT_IE_X(x) (((x) & GENMASK(8U, 8U)) >> 8U)

#define FLEXCOM_FLEX_US_IER_PARE_IE(x)      (((x) << 7U) & GENMASK(7U, 7U))
#define FLEXCOM_FLEX_US_IER_PARE_IE_M       GENMASK(7U, 7U)
#define FLEXCOM_FLEX_US_IER_PARE_IE_X(x)    (((x) & GENMASK(7U, 7U)) >> 7U)

#define FLEXCOM_FLEX_US_IER_FRAME_IE(x)     (((x) << 6U) & GENMASK(6U, 6U))
#define FLEXCOM_FLEX_US_IER_FRAME_IE_M      GENMASK(6U, 6U)
#define FLEXCOM_FLEX_US_IER_FRAME_IE_X(x)   (((x) & GENMASK(6U, 6U)) >> 6U)

#define FLEXCOM_FLEX_US_IER_OVRE_IE(x)      (((x) << 5U) & GENMASK(5U, 5U))
#define FLEXCOM_FLEX_US_IER_OVRE_IE_M       GENMASK(5U, 5U)
#define FLEXCOM_FLEX_US_IER_OVRE_IE_X(x)    (((x) & GENMASK(5U, 5U)) >> 5U)

#define FLEXCOM_FLEX_US_IER_ENDTX_IE(x)     (((x) << 4U) & GENMASK(4U, 4U))
#define FLEXCOM_FLEX_US_IER_ENDTX_IE_M      GENMASK(4U, 4U)
#define FLEXCOM_FLEX_US_IER_ENDTX_IE_X(x)   (((x) & GENMASK(4U, 4U)) >> 4U)

#define FLEXCOM_FLEX_US_IER_ENDRX_IE(x)     (((x) << 3U) & GENMASK(3U, 3U))
#define FLEXCOM_FLEX_US_IER_ENDRX_IE_M      GENMASK(3U, 3U)
#define FLEXCOM_FLEX_US_IER_ENDRX_IE_X(x)   (((x) & GENMASK(3U, 3U)) >> 3U)

#define FLEXCOM_FLEX_US_IER_RXBRK_IE(x)     (((x) << 2U) & GENMASK(2U, 2U))
#define FLEXCOM_FLEX_US_IER_RXBRK_IE_M      GENMASK(2U, 2U)
#define FLEXCOM_FLEX_US_IER_RXBRK_IE_X(x)   (((x) & GENMASK(2U, 2U)) >> 2U)

#define FLEXCOM_FLEX_US_IER_TXRDY_IE(x)     (((x) << 1U) & GENMASK(1U, 1U))
#define FLEXCOM_FLEX_US_IER_TXRDY_IE_M      GENMASK(1U, 1U)
#define FLEXCOM_FLEX_US_IER_TXRDY_IE_X(x)   (((x) & GENMASK(1U, 1U)) >> 1U)

#define FLEXCOM_FLEX_US_IER_RXRDY_IE(x)     ((x) & GENMASK(0U, 0U))
#define FLEXCOM_FLEX_US_IER_RXRDY_IE_M      GENMASK(0U, 0U)
#define FLEXCOM_FLEX_US_IER_RXRDY_IE_X(x)   ((x) & GENMASK(0U, 0U))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_IDR */
#define FLEXCOM_FLEX_US_IDR(t)    ((t) + 0x20cU)

#define FLEXCOM_FLEX_US_IDR_MANE_ID(x)      (((x) << 24U) & GENMASK(24U, 24U))
#define FLEXCOM_FLEX_US_IDR_MANE_ID_M       GENMASK(24U, 24U)
#define FLEXCOM_FLEX_US_IDR_MANE_ID_X(x)    (((x) & GENMASK(24U, 24U)) >> 24U)

#define FLEXCOM_FLEX_US_IDR_CMP_ID(x)       (((x) << 22U) & GENMASK(22U, 22U))
#define FLEXCOM_FLEX_US_IDR_CMP_ID_M        GENMASK(22U, 22U)
#define FLEXCOM_FLEX_US_IDR_CMP_ID_X(x)     (((x) & GENMASK(22U, 22U)) >> 22U)

#define FLEXCOM_FLEX_US_IDR_CTSIC_ID(x)     (((x) << 19U) & GENMASK(19U, 19U))
#define FLEXCOM_FLEX_US_IDR_CTSIC_ID_M      GENMASK(19U, 19U)
#define FLEXCOM_FLEX_US_IDR_CTSIC_ID_X(x)   (((x) & GENMASK(19U, 19U)) >> 19U)

#define FLEXCOM_FLEX_US_IDR_DCDIC_ID(x)     (((x) << 18U) & GENMASK(18U, 18U))
#define FLEXCOM_FLEX_US_IDR_DCDIC_ID_M      GENMASK(18U, 18U)
#define FLEXCOM_FLEX_US_IDR_DCDIC_ID_X(x)   (((x) & GENMASK(18U, 18U)) >> 18U)

#define FLEXCOM_FLEX_US_IDR_DSRIC_ID(x)     (((x) << 17U) & GENMASK(17U, 17U))
#define FLEXCOM_FLEX_US_IDR_DSRIC_ID_M      GENMASK(17U, 17U)
#define FLEXCOM_FLEX_US_IDR_DSRIC_ID_X(x)   (((x) & GENMASK(17U, 17U)) >> 17U)

#define FLEXCOM_FLEX_US_IDR_RIIC_ID(x)      (((x) << 16U) & GENMASK(16U, 16U))
#define FLEXCOM_FLEX_US_IDR_RIIC_ID_M       GENMASK(16U, 16U)
#define FLEXCOM_FLEX_US_IDR_RIIC_ID_X(x)    (((x) & GENMASK(16U, 16U)) >> 16U)

#define FLEXCOM_FLEX_US_IDR_NACK_ID(x)      (((x) << 13U) & GENMASK(13U, 13U))
#define FLEXCOM_FLEX_US_IDR_NACK_ID_M       GENMASK(13U, 13U)
#define FLEXCOM_FLEX_US_IDR_NACK_ID_X(x)    (((x) & GENMASK(13U, 13U)) >> 13U)

#define FLEXCOM_FLEX_US_IDR_RXBUFF_ID(x)    (((x) << 12U) & GENMASK(12U, 12U))
#define FLEXCOM_FLEX_US_IDR_RXBUFF_ID_M     GENMASK(12U, 12U)
#define FLEXCOM_FLEX_US_IDR_RXBUFF_ID_X(x)  (((x) & GENMASK(12U, 12U)) >> 12U)

#define FLEXCOM_FLEX_US_IDR_TXBUFE_ID(x)    (((x) << 11U) & GENMASK(11U, 11U))
#define FLEXCOM_FLEX_US_IDR_TXBUFE_ID_M     GENMASK(11U, 11U)
#define FLEXCOM_FLEX_US_IDR_TXBUFE_ID_X(x)  (((x) & GENMASK(11U, 11U)) >> 11U)

#define FLEXCOM_FLEX_US_IDR_ITER_ID(x)      (((x) << 10U) & GENMASK(10U, 10U))
#define FLEXCOM_FLEX_US_IDR_ITER_ID_M       GENMASK(10U, 10U)
#define FLEXCOM_FLEX_US_IDR_ITER_ID_X(x)    (((x) & GENMASK(10U, 10U)) >> 10U)

#define FLEXCOM_FLEX_US_IDR_TXEMPTY_ID(x)   (((x) << 9U) & GENMASK(9U, 9U))
#define FLEXCOM_FLEX_US_IDR_TXEMPTY_ID_M    GENMASK(9U, 9U)
#define FLEXCOM_FLEX_US_IDR_TXEMPTY_ID_X(x) (((x) & GENMASK(9U, 9U)) >> 9U)

#define FLEXCOM_FLEX_US_IDR_TIMEOUT_ID(x)   (((x) << 8U) & GENMASK(8U, 8U))
#define FLEXCOM_FLEX_US_IDR_TIMEOUT_ID_M    GENMASK(8U, 8U)
#define FLEXCOM_FLEX_US_IDR_TIMEOUT_ID_X(x) (((x) & GENMASK(8U, 8U)) >> 8U)

#define FLEXCOM_FLEX_US_IDR_PARE_ID(x)      (((x) << 7U) & GENMASK(7U, 7U))
#define FLEXCOM_FLEX_US_IDR_PARE_ID_M       GENMASK(7U, 7U)
#define FLEXCOM_FLEX_US_IDR_PARE_ID_X(x)    (((x) & GENMASK(7U, 7U)) >> 7U)

#define FLEXCOM_FLEX_US_IDR_FRAME_ID(x)     (((x) << 6U) & GENMASK(6U, 6U))
#define FLEXCOM_FLEX_US_IDR_FRAME_ID_M      GENMASK(6U, 6U)
#define FLEXCOM_FLEX_US_IDR_FRAME_ID_X(x)   (((x) & GENMASK(6U, 6U)) >> 6U)

#define FLEXCOM_FLEX_US_IDR_OVRE_ID(x)      (((x) << 5U) & GENMASK(5U, 5U))
#define FLEXCOM_FLEX_US_IDR_OVRE_ID_M       GENMASK(5U, 5U)
#define FLEXCOM_FLEX_US_IDR_OVRE_ID_X(x)    (((x) & GENMASK(5U, 5U)) >> 5U)

#define FLEXCOM_FLEX_US_IDR_ENDTX_ID(x)     (((x) << 4U) & GENMASK(4U, 4U))
#define FLEXCOM_FLEX_US_IDR_ENDTX_ID_M      GENMASK(4U, 4U)
#define FLEXCOM_FLEX_US_IDR_ENDTX_ID_X(x)   (((x) & GENMASK(4U, 4U)) >> 4U)

#define FLEXCOM_FLEX_US_IDR_ENDRX_ID(x)     (((x) << 3U) & GENMASK(3U, 3U))
#define FLEXCOM_FLEX_US_IDR_ENDRX_ID_M      GENMASK(3U, 3U)
#define FLEXCOM_FLEX_US_IDR_ENDRX_ID_X(x)   (((x) & GENMASK(3U, 3U)) >> 3U)

#define FLEXCOM_FLEX_US_IDR_RXBRK_ID(x)     (((x) << 2U) & GENMASK(2U, 2U))
#define FLEXCOM_FLEX_US_IDR_RXBRK_ID_M      GENMASK(2U, 2U)
#define FLEXCOM_FLEX_US_IDR_RXBRK_ID_X(x)   (((x) & GENMASK(2U, 2U)) >> 2U)

#define FLEXCOM_FLEX_US_IDR_TXRDY_ID(x)     (((x) << 1U) & GENMASK(1U, 1U))
#define FLEXCOM_FLEX_US_IDR_TXRDY_ID_M      GENMASK(1U, 1U)
#define FLEXCOM_FLEX_US_IDR_TXRDY_ID_X(x)   (((x) & GENMASK(1U, 1U)) >> 1U)

#define FLEXCOM_FLEX_US_IDR_RXRDY_ID(x)     ((x) & GENMASK(0U, 0U))
#define FLEXCOM_FLEX_US_IDR_RXRDY_ID_M      GENMASK(0U, 0U)
#define FLEXCOM_FLEX_US_IDR_RXRDY_ID_X(x)   ((x) & GENMASK(0U, 0U))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_IMR */
#define FLEXCOM_FLEX_US_IMR(t)    ((t) + 0x210U)

#define FLEXCOM_FLEX_US_IMR_MANE_IM(x)      (((x) << 24U) & GENMASK(24U, 24U))
#define FLEXCOM_FLEX_US_IMR_MANE_IM_M       GENMASK(24U, 24U)
#define FLEXCOM_FLEX_US_IMR_MANE_IM_X(x)    (((x) & GENMASK(24U, 24U)) >> 24U)

#define FLEXCOM_FLEX_US_IMR_CMP_IM(x)       (((x) << 22U) & GENMASK(22U, 22U))
#define FLEXCOM_FLEX_US_IMR_CMP_IM_M        GENMASK(22U, 22U)
#define FLEXCOM_FLEX_US_IMR_CMP_IM_X(x)     (((x) & GENMASK(22U, 22U)) >> 22U)

#define FLEXCOM_FLEX_US_IMR_CTSIC_IM(x)     (((x) << 19U) & GENMASK(19U, 19U))
#define FLEXCOM_FLEX_US_IMR_CTSIC_IM_M      GENMASK(19U, 19U)
#define FLEXCOM_FLEX_US_IMR_CTSIC_IM_X(x)   (((x) & GENMASK(19U, 19U)) >> 19U)

#define FLEXCOM_FLEX_US_IMR_DCDIC_IM(x)     (((x) << 18U) & GENMASK(18U, 18U))
#define FLEXCOM_FLEX_US_IMR_DCDIC_IM_M      GENMASK(18U, 18U)
#define FLEXCOM_FLEX_US_IMR_DCDIC_IM_X(x)   (((x) & GENMASK(18U, 18U)) >> 18U)

#define FLEXCOM_FLEX_US_IMR_DSRIC_IM(x)     (((x) << 17U) & GENMASK(17U, 17U))
#define FLEXCOM_FLEX_US_IMR_DSRIC_IM_M      GENMASK(17U, 17U)
#define FLEXCOM_FLEX_US_IMR_DSRIC_IM_X(x)   (((x) & GENMASK(17U, 17U)) >> 17U)

#define FLEXCOM_FLEX_US_IMR_RIIC_IM(x)      (((x) << 16U) & GENMASK(16U, 16U))
#define FLEXCOM_FLEX_US_IMR_RIIC_IM_M       GENMASK(16U, 16U)
#define FLEXCOM_FLEX_US_IMR_RIIC_IM_X(x)    (((x) & GENMASK(16U, 16U)) >> 16U)

#define FLEXCOM_FLEX_US_IMR_NACK_IM(x)      (((x) << 13U) & GENMASK(13U, 13U))
#define FLEXCOM_FLEX_US_IMR_NACK_IM_M       GENMASK(13U, 13U)
#define FLEXCOM_FLEX_US_IMR_NACK_IM_X(x)    (((x) & GENMASK(13U, 13U)) >> 13U)

#define FLEXCOM_FLEX_US_IMR_RXBUFF_IM(x)    (((x) << 12U) & GENMASK(12U, 12U))
#define FLEXCOM_FLEX_US_IMR_RXBUFF_IM_M     GENMASK(12U, 12U)
#define FLEXCOM_FLEX_US_IMR_RXBUFF_IM_X(x)  (((x) & GENMASK(12U, 12U)) >> 12U)

#define FLEXCOM_FLEX_US_IMR_TXBUFE_IM(x)    (((x) << 11U) & GENMASK(11U, 11U))
#define FLEXCOM_FLEX_US_IMR_TXBUFE_IM_M     GENMASK(11U, 11U)
#define FLEXCOM_FLEX_US_IMR_TXBUFE_IM_X(x)  (((x) & GENMASK(11U, 11U)) >> 11U)

#define FLEXCOM_FLEX_US_IMR_ITER_IM(x)      (((x) << 10U) & GENMASK(10U, 10U))
#define FLEXCOM_FLEX_US_IMR_ITER_IM_M       GENMASK(10U, 10U)
#define FLEXCOM_FLEX_US_IMR_ITER_IM_X(x)    (((x) & GENMASK(10U, 10U)) >> 10U)

#define FLEXCOM_FLEX_US_IMR_TXEMPTY_IM(x)   (((x) << 9U) & GENMASK(9U, 9U))
#define FLEXCOM_FLEX_US_IMR_TXEMPTY_IM_M    GENMASK(9U, 9U)
#define FLEXCOM_FLEX_US_IMR_TXEMPTY_IM_X(x) (((x) & GENMASK(9U, 9U)) >> 9U)

#define FLEXCOM_FLEX_US_IMR_TIMEOUT_IM(x)   (((x) << 8U) & GENMASK(8U, 8U))
#define FLEXCOM_FLEX_US_IMR_TIMEOUT_IM_M    GENMASK(8U, 8U)
#define FLEXCOM_FLEX_US_IMR_TIMEOUT_IM_X(x) (((x) & GENMASK(8U, 8U)) >> 8U)

#define FLEXCOM_FLEX_US_IMR_PARE_IM(x)      (((x) << 7U) & GENMASK(7U, 7U))
#define FLEXCOM_FLEX_US_IMR_PARE_IM_M       GENMASK(7U, 7U)
#define FLEXCOM_FLEX_US_IMR_PARE_IM_X(x)    (((x) & GENMASK(7U, 7U)) >> 7U)

#define FLEXCOM_FLEX_US_IMR_FRAME_IM(x)     (((x) << 6U) & GENMASK(6U, 6U))
#define FLEXCOM_FLEX_US_IMR_FRAME_IM_M      GENMASK(6U, 6U)
#define FLEXCOM_FLEX_US_IMR_FRAME_IM_X(x)   (((x) & GENMASK(6U, 6U)) >> 6U)

#define FLEXCOM_FLEX_US_IMR_OVRE_IM(x)      (((x) << 5U) & GENMASK(5U, 5U))
#define FLEXCOM_FLEX_US_IMR_OVRE_IM_M       GENMASK(5U, 5U)
#define FLEXCOM_FLEX_US_IMR_OVRE_IM_X(x)    (((x) & GENMASK(5U, 5U)) >> 5U)

#define FLEXCOM_FLEX_US_IMR_ENDTX_IM(x)     (((x) << 4U) & GENMASK(4U, 4U))
#define FLEXCOM_FLEX_US_IMR_ENDTX_IM_M      GENMASK(4U, 4U)
#define FLEXCOM_FLEX_US_IMR_ENDTX_IM_X(x)   (((x) & GENMASK(4U, 4U)) >> 4U)

#define FLEXCOM_FLEX_US_IMR_ENDRX_IM(x)     (((x) << 3U) & GENMASK(3U, 3U))
#define FLEXCOM_FLEX_US_IMR_ENDRX_IM_M      GENMASK(3U, 3U)
#define FLEXCOM_FLEX_US_IMR_ENDRX_IM_X(x)   (((x) & GENMASK(3U, 3U)) >> 3U)

#define FLEXCOM_FLEX_US_IMR_RXBRK_IM(x)     (((x) << 2U) & GENMASK(2U, 2U))
#define FLEXCOM_FLEX_US_IMR_RXBRK_IM_M      GENMASK(2U, 2U)
#define FLEXCOM_FLEX_US_IMR_RXBRK_IM_X(x)   (((x) & GENMASK(2U, 2U)) >> 2U)

#define FLEXCOM_FLEX_US_IMR_TXRDY_IM(x)     (((x) << 1U) & GENMASK(1U, 1U))
#define FLEXCOM_FLEX_US_IMR_TXRDY_IM_M      GENMASK(1U, 1U)
#define FLEXCOM_FLEX_US_IMR_TXRDY_IM_X(x)   (((x) & GENMASK(1U, 1U)) >> 1U)

#define FLEXCOM_FLEX_US_IMR_RXRDY_IM(x)     ((x) & GENMASK(0U, 0U))
#define FLEXCOM_FLEX_US_IMR_RXRDY_IM_M      GENMASK(0U, 0U)
#define FLEXCOM_FLEX_US_IMR_RXRDY_IM_X(x)   ((x) & GENMASK(0U, 0U))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_CSR */
#define FLEXCOM_FLEX_US_CSR(t)    ((t) + 0x214U)

#define FLEXCOM_FLEX_US_CSR_MANE(x)         (((x) << 24U) & GENMASK(24U, 24U))
#define FLEXCOM_FLEX_US_CSR_MANE_M          GENMASK(24U, 24U)
#define FLEXCOM_FLEX_US_CSR_MANE_X(x)       (((x) & GENMASK(24U, 24U)) >> 24U)

#define FLEXCOM_FLEX_US_CSR_CTS(x)          (((x) << 23U) & GENMASK(23U, 23U))
#define FLEXCOM_FLEX_US_CSR_CTS_M           GENMASK(23U, 23U)
#define FLEXCOM_FLEX_US_CSR_CTS_X(x)        (((x) & GENMASK(23U, 23U)) >> 23U)

#define FLEXCOM_FLEX_US_CSR_CMP(x)          (((x) << 22U) & GENMASK(22U, 22U))
#define FLEXCOM_FLEX_US_CSR_CMP_M           GENMASK(22U, 22U)
#define FLEXCOM_FLEX_US_CSR_CMP_X(x)        (((x) & GENMASK(22U, 22U)) >> 22U)

#define FLEXCOM_FLEX_US_CSR_CTSIC(x)        (((x) << 19U) & GENMASK(19U, 19U))
#define FLEXCOM_FLEX_US_CSR_CTSIC_M         GENMASK(19U, 19U)
#define FLEXCOM_FLEX_US_CSR_CTSIC_X(x)      (((x) & GENMASK(19U, 19U)) >> 19U)

#define FLEXCOM_FLEX_US_CSR_DCDIC(x)        (((x) << 18U) & GENMASK(18U, 18U))
#define FLEXCOM_FLEX_US_CSR_DCDIC_M         GENMASK(18U, 18U)
#define FLEXCOM_FLEX_US_CSR_DCDIC_X(x)      (((x) & GENMASK(18U, 18U)) >> 18U)

#define FLEXCOM_FLEX_US_CSR_DSRIC(x)        (((x) << 17U) & GENMASK(17U, 17U))
#define FLEXCOM_FLEX_US_CSR_DSRIC_M         GENMASK(17U, 17U)
#define FLEXCOM_FLEX_US_CSR_DSRIC_X(x)      (((x) & GENMASK(17U, 17U)) >> 17U)

#define FLEXCOM_FLEX_US_CSR_RIIC(x)         (((x) << 16U) & GENMASK(16U, 16U))
#define FLEXCOM_FLEX_US_CSR_RIIC_M          GENMASK(16U, 16U)
#define FLEXCOM_FLEX_US_CSR_RIIC_X(x)       (((x) & GENMASK(16U, 16U)) >> 16U)

#define FLEXCOM_FLEX_US_CSR_NACK(x)         (((x) << 13U) & GENMASK(13U, 13U))
#define FLEXCOM_FLEX_US_CSR_NACK_M          GENMASK(13U, 13U)
#define FLEXCOM_FLEX_US_CSR_NACK_X(x)       (((x) & GENMASK(13U, 13U)) >> 13U)

#define FLEXCOM_FLEX_US_CSR_RXBUFF(x)       (((x) << 12U) & GENMASK(12U, 12U))
#define FLEXCOM_FLEX_US_CSR_RXBUFF_M        GENMASK(12U, 12U)
#define FLEXCOM_FLEX_US_CSR_RXBUFF_X(x)     (((x) & GENMASK(12U, 12U)) >> 12U)

#define FLEXCOM_FLEX_US_CSR_TXBUFE(x)       (((x) << 11U) & GENMASK(11U, 11U))
#define FLEXCOM_FLEX_US_CSR_TXBUFE_M        GENMASK(11U, 11U)
#define FLEXCOM_FLEX_US_CSR_TXBUFE_X(x)     (((x) & GENMASK(11U, 11U)) >> 11U)

#define FLEXCOM_FLEX_US_CSR_ITER(x)         (((x) << 10U) & GENMASK(10U, 10U))
#define FLEXCOM_FLEX_US_CSR_ITER_M          GENMASK(10U, 10U)
#define FLEXCOM_FLEX_US_CSR_ITER_X(x)       (((x) & GENMASK(10U, 10U)) >> 10U)

#define FLEXCOM_FLEX_US_CSR_TXEMPTY(x)      (((x) << 9U) & GENMASK(9U, 9U))
#define FLEXCOM_FLEX_US_CSR_TXEMPTY_M       GENMASK(9U, 9U)
#define FLEXCOM_FLEX_US_CSR_TXEMPTY_X(x)    (((x) & GENMASK(9U, 9U)) >> 9U)

#define FLEXCOM_FLEX_US_CSR_TIMEOUT(x)      (((x) << 8U) & GENMASK(8U, 8U))
#define FLEXCOM_FLEX_US_CSR_TIMEOUT_M       GENMASK(8U, 8U)
#define FLEXCOM_FLEX_US_CSR_TIMEOUT_X(x)    (((x) & GENMASK(8U, 8U)) >> 8U)

#define FLEXCOM_FLEX_US_CSR_PARE(x)         (((x) << 7U) & GENMASK(7U, 7U))
#define FLEXCOM_FLEX_US_CSR_PARE_M          GENMASK(7U, 7U)
#define FLEXCOM_FLEX_US_CSR_PARE_X(x)       (((x) & GENMASK(7U, 7U)) >> 7U)

#define FLEXCOM_FLEX_US_CSR_FRAME(x)        (((x) << 6U) & GENMASK(6U, 6U))
#define FLEXCOM_FLEX_US_CSR_FRAME_M         GENMASK(6U, 6U)
#define FLEXCOM_FLEX_US_CSR_FRAME_X(x)      (((x) & GENMASK(6U, 6U)) >> 6U)

#define FLEXCOM_FLEX_US_CSR_OVRE(x)         (((x) << 5U) & GENMASK(5U, 5U))
#define FLEXCOM_FLEX_US_CSR_OVRE_M          GENMASK(5U, 5U)
#define FLEXCOM_FLEX_US_CSR_OVRE_X(x)       (((x) & GENMASK(5U, 5U)) >> 5U)

#define FLEXCOM_FLEX_US_CSR_ENDTX(x)        (((x) << 4U) & GENMASK(4U, 4U))
#define FLEXCOM_FLEX_US_CSR_ENDTX_M         GENMASK(4U, 4U)
#define FLEXCOM_FLEX_US_CSR_ENDTX_X(x)      (((x) & GENMASK(4U, 4U)) >> 4U)

#define FLEXCOM_FLEX_US_CSR_ENDRX(x)        (((x) << 3U) & GENMASK(3U, 3U))
#define FLEXCOM_FLEX_US_CSR_ENDRX_M         GENMASK(3U, 3U)
#define FLEXCOM_FLEX_US_CSR_ENDRX_X(x)      (((x) & GENMASK(3U, 3U)) >> 3U)

#define FLEXCOM_FLEX_US_CSR_RXBRK(x)        (((x) << 2U) & GENMASK(2U, 2U))
#define FLEXCOM_FLEX_US_CSR_RXBRK_M         GENMASK(2U, 2U)
#define FLEXCOM_FLEX_US_CSR_RXBRK_X(x)      (((x) & GENMASK(2U, 2U)) >> 2U)

#define FLEXCOM_FLEX_US_CSR_TXRDY(x)        (((x) << 1U) & GENMASK(1U, 1U))
#define FLEXCOM_FLEX_US_CSR_TXRDY_M         GENMASK(1U, 1U)
#define FLEXCOM_FLEX_US_CSR_TXRDY_X(x)      (((x) & GENMASK(1U, 1U)) >> 1U)

#define FLEXCOM_FLEX_US_CSR_RXRDY(x)        ((x) & GENMASK(0U, 0U))
#define FLEXCOM_FLEX_US_CSR_RXRDY_M         GENMASK(0U, 0U)
#define FLEXCOM_FLEX_US_CSR_RXRDY_X(x)      ((x) & GENMASK(0U, 0U))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_RHR */
#define FLEXCOM_FLEX_US_RHR(t)    ((t) + 0x218U)

#define FLEXCOM_FLEX_US_RHR_RXSYNH(x)       (((x) << 15U) & GENMASK(15U, 15U))
#define FLEXCOM_FLEX_US_RHR_RXSYNH_M        GENMASK(15U, 15U)
#define FLEXCOM_FLEX_US_RHR_RXSYNH_X(x)     (((x) & GENMASK(15U, 15U)) >> 15U)

#define FLEXCOM_FLEX_US_RHR_RXCHR(x)        ((x) & GENMASK(7U, 0U))
#define FLEXCOM_FLEX_US_RHR_RXCHR_M         GENMASK(7U, 0U)
#define FLEXCOM_FLEX_US_RHR_RXCHR_X(x)      ((x) & GENMASK(7U, 0U))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_FMT_RHR */
#define FLEXCOM_FLEX_US_FMT_RHR(t) ((t) + 0x218U)

#define FLEXCOM_FLEX_US_FMT_RHR_RXCHR3(x)   (((x) << 24U) & GENMASK(31U, 24U))
#define FLEXCOM_FLEX_US_FMT_RHR_RXCHR3_M    GENMASK(31U, 24U)
#define FLEXCOM_FLEX_US_FMT_RHR_RXCHR3_X(x) (((x) & GENMASK(31U, 24U)) >> 24U)

#define FLEXCOM_FLEX_US_FMT_RHR_RXCHR2(x)   (((x) << 16U) & GENMASK(23U, 16U))
#define FLEXCOM_FLEX_US_FMT_RHR_RXCHR2_M    GENMASK(23U, 16U)
#define FLEXCOM_FLEX_US_FMT_RHR_RXCHR2_X(x) (((x) & GENMASK(23U, 16U)) >> 16U)

#define FLEXCOM_FLEX_US_FMT_RHR_RXCHR1(x)   (((x) << 8U) & GENMASK(15U, 8U))
#define FLEXCOM_FLEX_US_FMT_RHR_RXCHR1_M    GENMASK(15U, 8U)
#define FLEXCOM_FLEX_US_FMT_RHR_RXCHR1_X(x) (((x) & GENMASK(15U, 8U)) >> 8U)

#define FLEXCOM_FLEX_US_FMT_RHR_RXCHR0(x)   ((x) & GENMASK(7U, 0U))
#define FLEXCOM_FLEX_US_FMT_RHR_RXCHR0_M    GENMASK(7U, 0U)
#define FLEXCOM_FLEX_US_FMT_RHR_RXCHR0_X(x) ((x) & GENMASK(7U, 0U))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_THR */
#define FLEXCOM_FLEX_US_THR(t)    ((t) + 0x21cU)

#define FLEXCOM_FLEX_US_THR_TXSYNH(x)       (((x) << 15U) & GENMASK(15U, 15U))
#define FLEXCOM_FLEX_US_THR_TXSYNH_M        GENMASK(15U, 15U)
#define FLEXCOM_FLEX_US_THR_TXSYNH_X(x)     (((x) & GENMASK(15U, 15U)) >> 15U)

#define FLEXCOM_FLEX_US_THR_TXCHR(x)        ((x) & GENMASK(8U, 0U))
#define FLEXCOM_FLEX_US_THR_TXCHR_M         GENMASK(8U, 0U)
#define FLEXCOM_FLEX_US_THR_TXCHR_X(x)      ((x) & GENMASK(8U, 0U))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_FMT_THR */
#define FLEXCOM_FLEX_US_FMT_THR(t) ((t) + 0x21cU)

#define FLEXCOM_FLEX_US_FMT_THR_TXCHR3(x)   (((x) << 24U) & GENMASK(31U, 24U))
#define FLEXCOM_FLEX_US_FMT_THR_TXCHR3_M    GENMASK(31U, 24U)
#define FLEXCOM_FLEX_US_FMT_THR_TXCHR3_X(x) (((x) & GENMASK(31U, 24U)) >> 24U)

#define FLEXCOM_FLEX_US_FMT_THR_TXCHR2(x)   (((x) << 16U) & GENMASK(23U, 16U))
#define FLEXCOM_FLEX_US_FMT_THR_TXCHR2_M    GENMASK(23U, 16U)
#define FLEXCOM_FLEX_US_FMT_THR_TXCHR2_X(x) (((x) & GENMASK(23U, 16U)) >> 16U)

#define FLEXCOM_FLEX_US_FMT_THR_TXCHR1(x)   (((x) << 8U) & GENMASK(15U, 8U))
#define FLEXCOM_FLEX_US_FMT_THR_TXCHR1_M    GENMASK(15U, 8U)
#define FLEXCOM_FLEX_US_FMT_THR_TXCHR1_X(x) (((x) & GENMASK(15U, 8U)) >> 8U)

#define FLEXCOM_FLEX_US_FMT_THR_TXCHR0(x)   ((x) & GENMASK(7U, 0U))
#define FLEXCOM_FLEX_US_FMT_THR_TXCHR0_M    GENMASK(7U, 0U)
#define FLEXCOM_FLEX_US_FMT_THR_TXCHR0_X(x) ((x) & GENMASK(7U, 0U))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_BRGR */
#define FLEXCOM_FLEX_US_BRGR(t)   ((t) + 0x220U)

#define FLEXCOM_FLEX_US_BRGR_FP(x)          (((x) << 16U) & GENMASK(18U, 16U))
#define FLEXCOM_FLEX_US_BRGR_FP_M           GENMASK(18U, 16U)
#define FLEXCOM_FLEX_US_BRGR_FP_X(x)        (((x) & GENMASK(18U, 16U)) >> 16U)

#define FLEXCOM_FLEX_US_BRGR_CD(x)          ((x) & GENMASK(15U, 0U))
#define FLEXCOM_FLEX_US_BRGR_CD_M           GENMASK(15U, 0U)
#define FLEXCOM_FLEX_US_BRGR_CD_X(x)        ((x) & GENMASK(15U, 0U))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_RTOR */
#define FLEXCOM_FLEX_US_RTOR(t)   ((t) + 0x224U)

#define FLEXCOM_FLEX_US_RTOR_TO(x)          ((x) & GENMASK(7U, 0U))
#define FLEXCOM_FLEX_US_RTOR_TO_M           GENMASK(7U, 0U)
#define FLEXCOM_FLEX_US_RTOR_TO_X(x)        ((x) & GENMASK(7U, 0U))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_TTGR */
#define FLEXCOM_FLEX_US_TTGR(t)   ((t) + 0x228U)

#define FLEXCOM_FLEX_US_TTGR_TG(x)          ((x) & GENMASK(7U, 0U))
#define FLEXCOM_FLEX_US_TTGR_TG_M           GENMASK(7U, 0U)
#define FLEXCOM_FLEX_US_TTGR_TG_X(x)        ((x) & GENMASK(7U, 0U))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_MAN */
#define FLEXCOM_FLEX_US_MAN(t)    ((t) + 0x250U)

#define FLEXCOM_FLEX_US_MAN_RXIDLEV(x)      (((x) << 31U) & GENMASK(31U, 31U))
#define FLEXCOM_FLEX_US_MAN_RXIDLEV_M       GENMASK(31U, 31U)
#define FLEXCOM_FLEX_US_MAN_RXIDLEV_X(x)    (((x) & GENMASK(31U, 31U)) >> 31U)

#define FLEXCOM_FLEX_US_MAN_DRIFT(x)        (((x) << 30U) & GENMASK(30U, 30U))
#define FLEXCOM_FLEX_US_MAN_DRIFT_M         GENMASK(30U, 30U)
#define FLEXCOM_FLEX_US_MAN_DRIFT_X(x)      (((x) & GENMASK(30U, 30U)) >> 30U)

#define FLEXCOM_FLEX_US_MAN_ONE(x)          (((x) << 29U) & GENMASK(29U, 29U))
#define FLEXCOM_FLEX_US_MAN_ONE_M           GENMASK(29U, 29U)
#define FLEXCOM_FLEX_US_MAN_ONE_X(x)        (((x) & GENMASK(29U, 29U)) >> 29U)

#define FLEXCOM_FLEX_US_MAN_RX_MPOL(x)      (((x) << 28U) & GENMASK(28U, 28U))
#define FLEXCOM_FLEX_US_MAN_RX_MPOL_M       GENMASK(28U, 28U)
#define FLEXCOM_FLEX_US_MAN_RX_MPOL_X(x)    (((x) & GENMASK(28U, 28U)) >> 28U)

#define FLEXCOM_FLEX_US_MAN_RX_PP(x)        (((x) << 24U) & GENMASK(25U, 24U))
#define FLEXCOM_FLEX_US_MAN_RX_PP_M         GENMASK(25U, 24U)
#define FLEXCOM_FLEX_US_MAN_RX_PP_X(x)      (((x) & GENMASK(25U, 24U)) >> 24U)

#define FLEXCOM_FLEX_US_MAN_RX_PL(x)        (((x) << 16U) & GENMASK(19U, 16U))
#define FLEXCOM_FLEX_US_MAN_RX_PL_M         GENMASK(19U, 16U)
#define FLEXCOM_FLEX_US_MAN_RX_PL_X(x)      (((x) & GENMASK(19U, 16U)) >> 16U)

#define FLEXCOM_FLEX_US_MAN_TX_MPOL(x)      (((x) << 12U) & GENMASK(12U, 12U))
#define FLEXCOM_FLEX_US_MAN_TX_MPOL_M       GENMASK(12U, 12U)
#define FLEXCOM_FLEX_US_MAN_TX_MPOL_X(x)    (((x) & GENMASK(12U, 12U)) >> 12U)

#define FLEXCOM_FLEX_US_MAN_TX_PP(x)        (((x) << 8U) & GENMASK(9U, 8U))
#define FLEXCOM_FLEX_US_MAN_TX_PP_M         GENMASK(9U, 8U)
#define FLEXCOM_FLEX_US_MAN_TX_PP_X(x)      (((x) & GENMASK(9U, 8U)) >> 8U)

#define FLEXCOM_FLEX_US_MAN_TX_PL(x)        ((x) & GENMASK(3U, 0U))
#define FLEXCOM_FLEX_US_MAN_TX_PL_M         GENMASK(3U, 0U)
#define FLEXCOM_FLEX_US_MAN_TX_PL_X(x)      ((x) & GENMASK(3U, 0U))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_CMPR */
#define FLEXCOM_FLEX_US_CMPR(t)   ((t) + 0x290U)

#define FLEXCOM_FLEX_US_CMPR_VAL2(x)        (((x) << 16U) & GENMASK(24U, 16U))
#define FLEXCOM_FLEX_US_CMPR_VAL2_M         GENMASK(24U, 16U)
#define FLEXCOM_FLEX_US_CMPR_VAL2_X(x)      (((x) & GENMASK(24U, 16U)) >> 16U)

#define FLEXCOM_FLEX_US_CMPR_CMPPAR(x)      (((x) << 14U) & GENMASK(14U, 14U))
#define FLEXCOM_FLEX_US_CMPR_CMPPAR_M       GENMASK(14U, 14U)
#define FLEXCOM_FLEX_US_CMPR_CMPPAR_X(x)    (((x) & GENMASK(14U, 14U)) >> 14U)

#define FLEXCOM_FLEX_US_CMPR_CMPMODE(x)     (((x) << 12U) & GENMASK(13U, 12U))
#define FLEXCOM_FLEX_US_CMPR_CMPMODE_M      GENMASK(13U, 12U)
#define FLEXCOM_FLEX_US_CMPR_CMPMODE_X(x)   (((x) & GENMASK(13U, 12U)) >> 12U)

#define FLEXCOM_FLEX_US_CMPR_VAL1(x)        ((x) & GENMASK(8U, 0U))
#define FLEXCOM_FLEX_US_CMPR_VAL1_M         GENMASK(8U, 0U)
#define FLEXCOM_FLEX_US_CMPR_VAL1_X(x)      ((x) & GENMASK(8U, 0U))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_FMR */
#define FLEXCOM_FLEX_US_FMR(t)    ((t) + 0x2a0U)

#define FLEXCOM_FLEX_US_FMR_RXFTHRES2(x)    (((x) << 24U) & GENMASK(29U, 24U))
#define FLEXCOM_FLEX_US_FMR_RXFTHRES2_M     GENMASK(29U, 24U)
#define FLEXCOM_FLEX_US_FMR_RXFTHRES2_X(x)  (((x) & GENMASK(29U, 24U)) >> 24U)

#define FLEXCOM_FLEX_US_FMR_RXFTHRES(x)     (((x) << 16U) & GENMASK(21U, 16U))
#define FLEXCOM_FLEX_US_FMR_RXFTHRES_M      GENMASK(21U, 16U)
#define FLEXCOM_FLEX_US_FMR_RXFTHRES_X(x)   (((x) & GENMASK(21U, 16U)) >> 16U)

#define FLEXCOM_FLEX_US_FMR_TXFTHRES(x)     (((x) << 8U) & GENMASK(13U, 8U))
#define FLEXCOM_FLEX_US_FMR_TXFTHRES_M      GENMASK(13U, 8U)
#define FLEXCOM_FLEX_US_FMR_TXFTHRES_X(x)   (((x) & GENMASK(13U, 8U)) >> 8U)

#define FLEXCOM_FLEX_US_FMR_FRTSC(x)        (((x) << 7U) & GENMASK(7U, 7U))
#define FLEXCOM_FLEX_US_FMR_FRTSC_M         GENMASK(7U, 7U)
#define FLEXCOM_FLEX_US_FMR_FRTSC_X(x)      (((x) & GENMASK(7U, 7U)) >> 7U)

#define FLEXCOM_FLEX_US_FMR_RXRDYM(x)       (((x) << 4U) & GENMASK(5U, 4U))
#define FLEXCOM_FLEX_US_FMR_RXRDYM_M        GENMASK(5U, 4U)
#define FLEXCOM_FLEX_US_FMR_RXRDYM_X(x)     (((x) & GENMASK(5U, 4U)) >> 4U)

#define FLEXCOM_FLEX_US_FMR_TXRDYM(x)       ((x) & GENMASK(1U, 0U))
#define FLEXCOM_FLEX_US_FMR_TXRDYM_M        GENMASK(1U, 0U)
#define FLEXCOM_FLEX_US_FMR_TXRDYM_X(x)     ((x) & GENMASK(1U, 0U))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_FLR */
#define FLEXCOM_FLEX_US_FLR(t)    ((t) + 0x2a4U)

#define FLEXCOM_FLEX_US_FLR_RXFL(x)         (((x) << 16U) & GENMASK(21U, 16U))
#define FLEXCOM_FLEX_US_FLR_RXFL_M          GENMASK(21U, 16U)
#define FLEXCOM_FLEX_US_FLR_RXFL_X(x)       (((x) & GENMASK(21U, 16U)) >> 16U)

#define FLEXCOM_FLEX_US_FLR_TXFL(x)         ((x) & GENMASK(5U, 0U))
#define FLEXCOM_FLEX_US_FLR_TXFL_M          GENMASK(5U, 0U)
#define FLEXCOM_FLEX_US_FLR_TXFL_X(x)       ((x) & GENMASK(5U, 0U))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_FIER */
#define FLEXCOM_FLEX_US_FIER(t)   ((t) + 0x2a8U)

#define FLEXCOM_FLEX_US_FIER_RXFTHF2_IE(x)  (((x) << 9U) & GENMASK(9U, 9U))
#define FLEXCOM_FLEX_US_FIER_RXFTHF2_IE_M   GENMASK(9U, 9U)
#define FLEXCOM_FLEX_US_FIER_RXFTHF2_IE_X(x) (((x) & GENMASK(9U, 9U)) >> 9U)

#define FLEXCOM_FLEX_US_FIER_RXFPTEF_IE(x)  (((x) << 7U) & GENMASK(7U, 7U))
#define FLEXCOM_FLEX_US_FIER_RXFPTEF_IE_M   GENMASK(7U, 7U)
#define FLEXCOM_FLEX_US_FIER_RXFPTEF_IE_X(x) (((x) & GENMASK(7U, 7U)) >> 7U)

#define FLEXCOM_FLEX_US_FIER_TXFPTEF_IE(x)  (((x) << 6U) & GENMASK(6U, 6U))
#define FLEXCOM_FLEX_US_FIER_TXFPTEF_IE_M   GENMASK(6U, 6U)
#define FLEXCOM_FLEX_US_FIER_TXFPTEF_IE_X(x) (((x) & GENMASK(6U, 6U)) >> 6U)

#define FLEXCOM_FLEX_US_FIER_RXFTHF_IE(x)   (((x) << 5U) & GENMASK(5U, 5U))
#define FLEXCOM_FLEX_US_FIER_RXFTHF_IE_M    GENMASK(5U, 5U)
#define FLEXCOM_FLEX_US_FIER_RXFTHF_IE_X(x) (((x) & GENMASK(5U, 5U)) >> 5U)

#define FLEXCOM_FLEX_US_FIER_RXFFF_IE(x)    (((x) << 4U) & GENMASK(4U, 4U))
#define FLEXCOM_FLEX_US_FIER_RXFFF_IE_M     GENMASK(4U, 4U)
#define FLEXCOM_FLEX_US_FIER_RXFFF_IE_X(x)  (((x) & GENMASK(4U, 4U)) >> 4U)

#define FLEXCOM_FLEX_US_FIER_RXFEF_IE(x)    (((x) << 3U) & GENMASK(3U, 3U))
#define FLEXCOM_FLEX_US_FIER_RXFEF_IE_M     GENMASK(3U, 3U)
#define FLEXCOM_FLEX_US_FIER_RXFEF_IE_X(x)  (((x) & GENMASK(3U, 3U)) >> 3U)

#define FLEXCOM_FLEX_US_FIER_TXFTHF_IE(x)   (((x) << 2U) & GENMASK(2U, 2U))
#define FLEXCOM_FLEX_US_FIER_TXFTHF_IE_M    GENMASK(2U, 2U)
#define FLEXCOM_FLEX_US_FIER_TXFTHF_IE_X(x) (((x) & GENMASK(2U, 2U)) >> 2U)

#define FLEXCOM_FLEX_US_FIER_TXFFF_IE(x)    (((x) << 1U) & GENMASK(1U, 1U))
#define FLEXCOM_FLEX_US_FIER_TXFFF_IE_M     GENMASK(1U, 1U)
#define FLEXCOM_FLEX_US_FIER_TXFFF_IE_X(x)  (((x) & GENMASK(1U, 1U)) >> 1U)

#define FLEXCOM_FLEX_US_FIER_TXFEF_IE(x)    ((x) & GENMASK(0U, 0U))
#define FLEXCOM_FLEX_US_FIER_TXFEF_IE_M     GENMASK(0U, 0U)
#define FLEXCOM_FLEX_US_FIER_TXFEF_IE_X(x)  ((x) & GENMASK(0U, 0U))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_FIDR */
#define FLEXCOM_FLEX_US_FIDR(t)   ((t) + 0x2acU)

#define FLEXCOM_FLEX_US_FIDR_RXFTHF2_ID(x)  (((x) << 9U) & GENMASK(9U, 9U))
#define FLEXCOM_FLEX_US_FIDR_RXFTHF2_ID_M   GENMASK(9U, 9U)
#define FLEXCOM_FLEX_US_FIDR_RXFTHF2_ID_X(x) (((x) & GENMASK(9U, 9U)) >> 9U)

#define FLEXCOM_FLEX_US_FIDR_RXFPTEF_ID(x)  (((x) << 7U) & GENMASK(7U, 7U))
#define FLEXCOM_FLEX_US_FIDR_RXFPTEF_ID_M   GENMASK(7U, 7U)
#define FLEXCOM_FLEX_US_FIDR_RXFPTEF_ID_X(x) (((x) & GENMASK(7U, 7U)) >> 7U)

#define FLEXCOM_FLEX_US_FIDR_TXFPTEF_ID(x)  (((x) << 6U) & GENMASK(6U, 6U))
#define FLEXCOM_FLEX_US_FIDR_TXFPTEF_ID_M   GENMASK(6U, 6U)
#define FLEXCOM_FLEX_US_FIDR_TXFPTEF_ID_X(x) (((x) & GENMASK(6U, 6U)) >> 6U)

#define FLEXCOM_FLEX_US_FIDR_RXFTHF_ID(x)   (((x) << 5U) & GENMASK(5U, 5U))
#define FLEXCOM_FLEX_US_FIDR_RXFTHF_ID_M    GENMASK(5U, 5U)
#define FLEXCOM_FLEX_US_FIDR_RXFTHF_ID_X(x) (((x) & GENMASK(5U, 5U)) >> 5U)

#define FLEXCOM_FLEX_US_FIDR_RXFFF_ID(x)    (((x) << 4U) & GENMASK(4U, 4U))
#define FLEXCOM_FLEX_US_FIDR_RXFFF_ID_M     GENMASK(4U, 4U)
#define FLEXCOM_FLEX_US_FIDR_RXFFF_ID_X(x)  (((x) & GENMASK(4U, 4U)) >> 4U)

#define FLEXCOM_FLEX_US_FIDR_RXFEF_ID(x)    (((x) << 3U) & GENMASK(3U, 3U))
#define FLEXCOM_FLEX_US_FIDR_RXFEF_ID_M     GENMASK(3U, 3U)
#define FLEXCOM_FLEX_US_FIDR_RXFEF_ID_X(x)  (((x) & GENMASK(3U, 3U)) >> 3U)

#define FLEXCOM_FLEX_US_FIDR_TXFTHF_ID(x)   (((x) << 2U) & GENMASK(2U, 2U))
#define FLEXCOM_FLEX_US_FIDR_TXFTHF_ID_M    GENMASK(2U, 2U)
#define FLEXCOM_FLEX_US_FIDR_TXFTHF_ID_X(x) (((x) & GENMASK(2U, 2U)) >> 2U)

#define FLEXCOM_FLEX_US_FIDR_TXFFF_ID(x)    (((x) << 1U) & GENMASK(1U, 1U))
#define FLEXCOM_FLEX_US_FIDR_TXFFF_ID_M     GENMASK(1U, 1U)
#define FLEXCOM_FLEX_US_FIDR_TXFFF_ID_X(x)  (((x) & GENMASK(1U, 1U)) >> 1U)

#define FLEXCOM_FLEX_US_FIDR_TXFEF_ID(x)    ((x) & GENMASK(0U, 0U))
#define FLEXCOM_FLEX_US_FIDR_TXFEF_ID_M     GENMASK(0U, 0U)
#define FLEXCOM_FLEX_US_FIDR_TXFEF_ID_X(x)  ((x) & GENMASK(0U, 0U))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_FIMR */
#define FLEXCOM_FLEX_US_FIMR(t)   ((t) + 0x2b0U)

#define FLEXCOM_FLEX_US_FIMR_RXFTHF2_IM(x)  (((x) << 9U) & GENMASK(9U, 9U))
#define FLEXCOM_FLEX_US_FIMR_RXFTHF2_IM_M   GENMASK(9U, 9U)
#define FLEXCOM_FLEX_US_FIMR_RXFTHF2_IM_X(x) (((x) & GENMASK(9U, 9U)) >> 9U)

#define FLEXCOM_FLEX_US_FIMR_RXFPTEF_IM(x)  (((x) << 7U) & GENMASK(7U, 7U))
#define FLEXCOM_FLEX_US_FIMR_RXFPTEF_IM_M   GENMASK(7U, 7U)
#define FLEXCOM_FLEX_US_FIMR_RXFPTEF_IM_X(x) (((x) & GENMASK(7U, 7U)) >> 7U)

#define FLEXCOM_FLEX_US_FIMR_TXFPTEF_IM(x)  (((x) << 6U) & GENMASK(6U, 6U))
#define FLEXCOM_FLEX_US_FIMR_TXFPTEF_IM_M   GENMASK(6U, 6U)
#define FLEXCOM_FLEX_US_FIMR_TXFPTEF_IM_X(x) (((x) & GENMASK(6U, 6U)) >> 6U)

#define FLEXCOM_FLEX_US_FIMR_RXFTHF_IM(x)   (((x) << 5U) & GENMASK(5U, 5U))
#define FLEXCOM_FLEX_US_FIMR_RXFTHF_IM_M    GENMASK(5U, 5U)
#define FLEXCOM_FLEX_US_FIMR_RXFTHF_IM_X(x) (((x) & GENMASK(5U, 5U)) >> 5U)

#define FLEXCOM_FLEX_US_FIMR_RXFFF_IM(x)    (((x) << 4U) & GENMASK(4U, 4U))
#define FLEXCOM_FLEX_US_FIMR_RXFFF_IM_M     GENMASK(4U, 4U)
#define FLEXCOM_FLEX_US_FIMR_RXFFF_IM_X(x)  (((x) & GENMASK(4U, 4U)) >> 4U)

#define FLEXCOM_FLEX_US_FIMR_RXFEF_IM(x)    (((x) << 3U) & GENMASK(3U, 3U))
#define FLEXCOM_FLEX_US_FIMR_RXFEF_IM_M     GENMASK(3U, 3U)
#define FLEXCOM_FLEX_US_FIMR_RXFEF_IM_X(x)  (((x) & GENMASK(3U, 3U)) >> 3U)

#define FLEXCOM_FLEX_US_FIMR_TXFTHF_IM(x)   (((x) << 2U) & GENMASK(2U, 2U))
#define FLEXCOM_FLEX_US_FIMR_TXFTHF_IM_M    GENMASK(2U, 2U)
#define FLEXCOM_FLEX_US_FIMR_TXFTHF_IM_X(x) (((x) & GENMASK(2U, 2U)) >> 2U)

#define FLEXCOM_FLEX_US_FIMR_TXFFF_IM(x)    (((x) << 1U) & GENMASK(1U, 1U))
#define FLEXCOM_FLEX_US_FIMR_TXFFF_IM_M     GENMASK(1U, 1U)
#define FLEXCOM_FLEX_US_FIMR_TXFFF_IM_X(x)  (((x) & GENMASK(1U, 1U)) >> 1U)

#define FLEXCOM_FLEX_US_FIMR_TXFEF_IM(x)    ((x) & GENMASK(0U, 0U))
#define FLEXCOM_FLEX_US_FIMR_TXFEF_IM_M     GENMASK(0U, 0U)
#define FLEXCOM_FLEX_US_FIMR_TXFEF_IM_X(x)  ((x) & GENMASK(0U, 0U))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_FESR */
#define FLEXCOM_FLEX_US_FESR(t)   ((t) + 0x2b4U)

#define FLEXCOM_FLEX_US_FESR_RXFTHF2(x)     (((x) << 9U) & GENMASK(9U, 9U))
#define FLEXCOM_FLEX_US_FESR_RXFTHF2_M      GENMASK(9U, 9U)
#define FLEXCOM_FLEX_US_FESR_RXFTHF2_X(x)   (((x) & GENMASK(9U, 9U)) >> 9U)

#define FLEXCOM_FLEX_US_FESR_TXFLOCK(x)     (((x) << 8U) & GENMASK(8U, 8U))
#define FLEXCOM_FLEX_US_FESR_TXFLOCK_M      GENMASK(8U, 8U)
#define FLEXCOM_FLEX_US_FESR_TXFLOCK_X(x)   (((x) & GENMASK(8U, 8U)) >> 8U)

#define FLEXCOM_FLEX_US_FESR_RXFPTEF(x)     (((x) << 7U) & GENMASK(7U, 7U))
#define FLEXCOM_FLEX_US_FESR_RXFPTEF_M      GENMASK(7U, 7U)
#define FLEXCOM_FLEX_US_FESR_RXFPTEF_X(x)   (((x) & GENMASK(7U, 7U)) >> 7U)

#define FLEXCOM_FLEX_US_FESR_TXFPTEF(x)     (((x) << 6U) & GENMASK(6U, 6U))
#define FLEXCOM_FLEX_US_FESR_TXFPTEF_M      GENMASK(6U, 6U)
#define FLEXCOM_FLEX_US_FESR_TXFPTEF_X(x)   (((x) & GENMASK(6U, 6U)) >> 6U)

#define FLEXCOM_FLEX_US_FESR_RXFTHF(x)      (((x) << 5U) & GENMASK(5U, 5U))
#define FLEXCOM_FLEX_US_FESR_RXFTHF_M       GENMASK(5U, 5U)
#define FLEXCOM_FLEX_US_FESR_RXFTHF_X(x)    (((x) & GENMASK(5U, 5U)) >> 5U)

#define FLEXCOM_FLEX_US_FESR_RXFFF(x)       (((x) << 4U) & GENMASK(4U, 4U))
#define FLEXCOM_FLEX_US_FESR_RXFFF_M        GENMASK(4U, 4U)
#define FLEXCOM_FLEX_US_FESR_RXFFF_X(x)     (((x) & GENMASK(4U, 4U)) >> 4U)

#define FLEXCOM_FLEX_US_FESR_RXFEF(x)       (((x) << 3U) & GENMASK(3U, 3U))
#define FLEXCOM_FLEX_US_FESR_RXFEF_M        GENMASK(3U, 3U)
#define FLEXCOM_FLEX_US_FESR_RXFEF_X(x)     (((x) & GENMASK(3U, 3U)) >> 3U)

#define FLEXCOM_FLEX_US_FESR_TXFTHF(x)      (((x) << 2U) & GENMASK(2U, 2U))
#define FLEXCOM_FLEX_US_FESR_TXFTHF_M       GENMASK(2U, 2U)
#define FLEXCOM_FLEX_US_FESR_TXFTHF_X(x)    (((x) & GENMASK(2U, 2U)) >> 2U)

#define FLEXCOM_FLEX_US_FESR_TXFFF(x)       (((x) << 1U) & GENMASK(1U, 1U))
#define FLEXCOM_FLEX_US_FESR_TXFFF_M        GENMASK(1U, 1U)
#define FLEXCOM_FLEX_US_FESR_TXFFF_X(x)     (((x) & GENMASK(1U, 1U)) >> 1U)

#define FLEXCOM_FLEX_US_FESR_TXFEF(x)       ((x) & GENMASK(0U, 0U))
#define FLEXCOM_FLEX_US_FESR_TXFEF_M        GENMASK(0U, 0U)
#define FLEXCOM_FLEX_US_FESR_TXFEF_X(x)     ((x) & GENMASK(0U, 0U))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_WPMR */
#define FLEXCOM_FLEX_US_WPMR(t)   ((t) + 0x2e4U)

#define FLEXCOM_FLEX_US_WPMR_WPKEY(x)       (((x) << 8U) & GENMASK(31U, 8U))
#define FLEXCOM_FLEX_US_WPMR_WPKEY_M        GENMASK(31U, 8U)
#define FLEXCOM_FLEX_US_WPMR_WPKEY_X(x)     (((x) & GENMASK(31U, 8U)) >> 8U)

#define FLEXCOM_FLEX_US_WPMR_WPCREN(x)      (((x) << 2U) & GENMASK(2U, 2U))
#define FLEXCOM_FLEX_US_WPMR_WPCREN_M       GENMASK(2U, 2U)
#define FLEXCOM_FLEX_US_WPMR_WPCREN_X(x)    (((x) & GENMASK(2U, 2U)) >> 2U)

#define FLEXCOM_FLEX_US_WPMR_WPITEN(x)      (((x) << 1U) & GENMASK(1U, 1U))
#define FLEXCOM_FLEX_US_WPMR_WPITEN_M       GENMASK(1U, 1U)
#define FLEXCOM_FLEX_US_WPMR_WPITEN_X(x)    (((x) & GENMASK(1U, 1U)) >> 1U)

#define FLEXCOM_FLEX_US_WPMR_WPEN(x)        ((x) & GENMASK(0U, 0U))
#define FLEXCOM_FLEX_US_WPMR_WPEN_M         GENMASK(0U, 0U)
#define FLEXCOM_FLEX_US_WPMR_WPEN_X(x)      ((x) & GENMASK(0U, 0U))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_WPSR */
#define FLEXCOM_FLEX_US_WPSR(t)   ((t) + 0x2e8U)

#define FLEXCOM_FLEX_US_WPSR_WPVSRC(x)      (((x) << 8U) & GENMASK(23U, 8U))
#define FLEXCOM_FLEX_US_WPSR_WPVSRC_M       GENMASK(23U, 8U)
#define FLEXCOM_FLEX_US_WPSR_WPVSRC_X(x)    (((x) & GENMASK(23U, 8U)) >> 8U)

#define FLEXCOM_FLEX_US_WPSR_WPVS(x)        ((x) & GENMASK(0U, 0U))
#define FLEXCOM_FLEX_US_WPSR_WPVS_M         GENMASK(0U, 0U)
#define FLEXCOM_FLEX_US_WPSR_WPVS_X(x)      ((x) & GENMASK(0U, 0U))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_VERSION */
#define FLEXCOM_FLEX_US_VERSION(t) ((t) + 0x2fcU)

#define FLEXCOM_FLEX_US_VERSION_USART_MFN(x) (((x) << 16U) & GENMASK(18U, 16U))
#define FLEXCOM_FLEX_US_VERSION_USART_MFN_M GENMASK(18U, 16U)
#define FLEXCOM_FLEX_US_VERSION_USART_MFN_X(x)\
	(((x) & GENMASK(18U, 16U)) >> 16U)

#define FLEXCOM_FLEX_US_VERSION_USART_VERSION(x) ((x) & GENMASK(11U, 0U))
#define FLEXCOM_FLEX_US_VERSION_USART_VERSION_M GENMASK(11U, 0U)
#define FLEXCOM_FLEX_US_VERSION_USART_VERSION_X(x) ((x) & GENMASK(11U, 0U))

/*      GCB:CHIP_REGS:CHIP_ID */
#define GCB_CHIP_ID(t)            ((t) + 0x00U)

#define GCB_CHIP_ID_REV_ID(x)               (((x) << 28U) & GENMASK(31U, 28U))
#define GCB_CHIP_ID_REV_ID_M                GENMASK(31U, 28U)
#define GCB_CHIP_ID_REV_ID_X(x)             (((x) & GENMASK(31U, 28U)) >> 28U)

#define GCB_CHIP_ID_PART_ID(x)              (((x) << 12U) & GENMASK(27U, 12U))
#define GCB_CHIP_ID_PART_ID_M               GENMASK(27U, 12U)
#define GCB_CHIP_ID_PART_ID_X(x)            (((x) & GENMASK(27U, 12U)) >> 12U)

#define GCB_CHIP_ID_MFG_ID(x)               (((x) << 1U) & GENMASK(11U, 1U))
#define GCB_CHIP_ID_MFG_ID_M                GENMASK(11U, 1U)
#define GCB_CHIP_ID_MFG_ID_X(x)             (((x) & GENMASK(11U, 1U)) >> 1U)

#define GCB_CHIP_ID_ONE(x)                  ((x) & GENMASK(0U, 0U))
#define GCB_CHIP_ID_ONE_M                   GENMASK(0U, 0U)
#define GCB_CHIP_ID_ONE_X(x)                ((x) & GENMASK(0U, 0U))

/*      GCB:CHIP_REGS:SOFT_RST */
#define GCB_SOFT_RST(t)           ((t) + 0x0cU)

#define GCB_SOFT_RST_SOFT_SWC_RST(x)        (((x) << 1U) & GENMASK(1U, 1U))
#define GCB_SOFT_RST_SOFT_SWC_RST_M         GENMASK(1U, 1U)
#define GCB_SOFT_RST_SOFT_SWC_RST_X(x)      (((x) & GENMASK(1U, 1U)) >> 1U)

#define GCB_SOFT_RST_SOFT_CHIP_RST(x)       ((x) & GENMASK(0U, 0U))
#define GCB_SOFT_RST_SOFT_CHIP_RST_M        GENMASK(0U, 0U)
#define GCB_SOFT_RST_SOFT_CHIP_RST_X(x)     ((x) & GENMASK(0U, 0U))

/*      GCB:GPIO:GPIO_OUT_SET */
#define GCB_GPIO_OUT_SET(t)       ((t) + 0xd4U)

/*      GCB:GPIO:GPIO_OUT_SET1 */
#define GCB_GPIO_OUT_SET1(t)      ((t) + 0xd8U)

/*      GCB:GPIO:GPIO_OUT_SET2 */
#define GCB_GPIO_OUT_SET2(t)      ((t) + 0xdcU)

#define GCB_GPIO_OUT_SET2_G_OUT_SET2(x)     ((x) & GENMASK(2U, 0U))
#define GCB_GPIO_OUT_SET2_G_OUT_SET2_M      GENMASK(2U, 0U)
#define GCB_GPIO_OUT_SET2_G_OUT_SET2_X(x)   ((x) & GENMASK(2U, 0U))

/*      GCB:GPIO:GPIO_OUT_CLR */
#define GCB_GPIO_OUT_CLR(t)       ((t) + 0xe0U)

/*      GCB:GPIO:GPIO_OUT_CLR1 */
#define GCB_GPIO_OUT_CLR1(t)      ((t) + 0xe4U)

/*      GCB:GPIO:GPIO_OUT_CLR2 */
#define GCB_GPIO_OUT_CLR2(t)      ((t) + 0xe8U)

#define GCB_GPIO_OUT_CLR2_G_OUT_CLR2(x)     ((x) & GENMASK(2U, 0U))
#define GCB_GPIO_OUT_CLR2_G_OUT_CLR2_M      GENMASK(2U, 0U)
#define GCB_GPIO_OUT_CLR2_G_OUT_CLR2_X(x)   ((x) & GENMASK(2U, 0U))

/*      GCB:GPIO:GPIO_OUT */
#define GCB_GPIO_OUT(t)           ((t) + 0xecU)

/*      GCB:GPIO:GPIO_OUT1 */
#define GCB_GPIO_OUT1(t)          ((t) + 0xf0U)

/*      GCB:GPIO:GPIO_OUT2 */
#define GCB_GPIO_OUT2(t)          ((t) + 0xf4U)

#define GCB_GPIO_OUT2_G_OUT2(x)             ((x) & GENMASK(2U, 0U))
#define GCB_GPIO_OUT2_G_OUT2_M              GENMASK(2U, 0U)
#define GCB_GPIO_OUT2_G_OUT2_X(x)           ((x) & GENMASK(2U, 0U))

/*      GCB:GPIO:GPIO_IN */
#define GCB_GPIO_IN(t)            ((t) + 0xf8U)

/*      GCB:GPIO:GPIO_IN1 */
#define GCB_GPIO_IN1(t)           ((t) + 0xfcU)

/*      GCB:GPIO:GPIO_IN2 */
#define GCB_GPIO_IN2(t)           ((t) + 0x100U)

#define GCB_GPIO_IN2_G_IN2(x)               ((x) & GENMASK(2U, 0U))
#define GCB_GPIO_IN2_G_IN2_M                GENMASK(2U, 0U)
#define GCB_GPIO_IN2_G_IN2_X(x)             ((x) & GENMASK(2U, 0U))

/*      GCB:GPIO:GPIO_OE */
#define GCB_GPIO_OE(t)            ((t) + 0x104U)

/*      GCB:GPIO:GPIO_OE1 */
#define GCB_GPIO_OE1(t)           ((t) + 0x108U)

/*      GCB:GPIO:GPIO_OE2 */
#define GCB_GPIO_OE2(t)           ((t) + 0x10cU)

#define GCB_GPIO_OE2_G_OE2(x)               ((x) & GENMASK(2U, 0U))
#define GCB_GPIO_OE2_G_OE2_M                GENMASK(2U, 0U)
#define GCB_GPIO_OE2_G_OE2_X(x)             ((x) & GENMASK(2U, 0U))

/*      GCB:GPIO:GPIO_INTR */
#define GCB_GPIO_INTR(t)          ((t) + 0x110U)

/*      GCB:GPIO:GPIO_INTR1 */
#define GCB_GPIO_INTR1(t)         ((t) + 0x114U)

/*      GCB:GPIO:GPIO_INTR2 */
#define GCB_GPIO_INTR2(t)         ((t) + 0x118U)

#define GCB_GPIO_INTR2_G_INTR2(x)           ((x) & GENMASK(2U, 0U))
#define GCB_GPIO_INTR2_G_INTR2_M            GENMASK(2U, 0U)
#define GCB_GPIO_INTR2_G_INTR2_X(x)         ((x) & GENMASK(2U, 0U))

/*      GCB:GPIO:GPIO_INTR_ENA */
#define GCB_GPIO_INTR_ENA(t)      ((t) + 0x11cU)

/*      GCB:GPIO:GPIO_INTR_ENA1 */
#define GCB_GPIO_INTR_ENA1(t)     ((t) + 0x120U)

/*      GCB:GPIO:GPIO_INTR_ENA2 */
#define GCB_GPIO_INTR_ENA2(t)     ((t) + 0x124U)

#define GCB_GPIO_INTR_ENA2_G_INTR_ENA2(x)   ((x) & GENMASK(2U, 0U))
#define GCB_GPIO_INTR_ENA2_G_INTR_ENA2_M    GENMASK(2U, 0U)
#define GCB_GPIO_INTR_ENA2_G_INTR_ENA2_X(x) ((x) & GENMASK(2U, 0U))

/*      GCB:GPIO:GPIO_INTR_IDENT */
#define GCB_GPIO_INTR_IDENT(t)    ((t) + 0x128U)

/*      GCB:GPIO:GPIO_INTR_IDENT1 */
#define GCB_GPIO_INTR_IDENT1(t)   ((t) + 0x12cU)

/*      GCB:GPIO:GPIO_INTR_IDENT2 */
#define GCB_GPIO_INTR_IDENT2(t)   ((t) + 0x130U)

#define GCB_GPIO_INTR_IDENT2_G_INTR_IDENT2(x) ((x) & GENMASK(2U, 0U))
#define GCB_GPIO_INTR_IDENT2_G_INTR_IDENT2_M GENMASK(2U, 0U)
#define GCB_GPIO_INTR_IDENT2_G_INTR_IDENT2_X(x) ((x) & GENMASK(2U, 0U))

/*      GCB:GPIO:GPIO_ALT */
#define GCB_GPIO_ALT(t, r)        ((t) + (0x134U + ((r) * 4U)))

/*      GCB:GPIO:GPIO_ALT1 */
#define GCB_GPIO_ALT1(t, r)       ((t) + (0x140U + ((r) * 4U)))

/*      GCB:GPIO:GPIO_ALT2 */
#define GCB_GPIO_ALT2(t, r)       ((t) + (0x14cU + ((r) * 4U)))

#define GCB_GPIO_ALT2_G_ALT2(x)             ((x) & GENMASK(2U, 0U))
#define GCB_GPIO_ALT2_G_ALT2_M              GENMASK(2U, 0U)
#define GCB_GPIO_ALT2_G_ALT2_X(x)           ((x) & GENMASK(2U, 0U))

/*      GCB:GPIO:GPIO_SD_DEV_MAP */
#define GCB_GPIO_SD_DEV_MAP(t, r) ((t) + (0x158U + ((r) * 4U)))

#define GCB_GPIO_SD_DEV_MAP_G_SD_DEV_MAP(x) ((x) & GENMASK(4U, 0U))
#define GCB_GPIO_SD_DEV_MAP_G_SD_DEV_MAP_M  GENMASK(4U, 0U)
#define GCB_GPIO_SD_DEV_MAP_G_SD_DEV_MAP_X(x) ((x) & GENMASK(4U, 0U))

/*      GCB:GPIO:GPIO_SD_SERDES_MAP */
#define GCB_GPIO_SD_SERDES_MAP(t, r) ((t) + (0x180U + ((r) * 4U)))

#define GCB_GPIO_SD_SERDES_MAP_G_SD_SERDES_MAP(x) ((x) & GENMASK(3U, 0U))
#define GCB_GPIO_SD_SERDES_MAP_G_SD_SERDES_MAP_M GENMASK(3U, 0U)
#define GCB_GPIO_SD_SERDES_MAP_G_SD_SERDES_MAP_X(x) ((x) & GENMASK(3U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:PERIPH_ID_4 */
#define GPV_PERIPH_ID_4(t)        ((t) + 0x1fd0U)

#define GPV_PERIPH_ID_4_PERIPH_ID_4(x)      ((x) & GENMASK(7U, 0U))
#define GPV_PERIPH_ID_4_PERIPH_ID_4_M       GENMASK(7U, 0U)
#define GPV_PERIPH_ID_4_PERIPH_ID_4_X(x)    ((x) & GENMASK(7U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:PERIPH_ID_5 */
#define GPV_PERIPH_ID_5(t)        ((t) + 0x1fd4U)

#define GPV_PERIPH_ID_5_PERIPH_ID_5(x)      ((x) & GENMASK(7U, 0U))
#define GPV_PERIPH_ID_5_PERIPH_ID_5_M       GENMASK(7U, 0U)
#define GPV_PERIPH_ID_5_PERIPH_ID_5_X(x)    ((x) & GENMASK(7U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:PERIPH_ID_6 */
#define GPV_PERIPH_ID_6(t)        ((t) + 0x1fd8U)

#define GPV_PERIPH_ID_6_PERIPH_ID_6(x)      ((x) & GENMASK(7U, 0U))
#define GPV_PERIPH_ID_6_PERIPH_ID_6_M       GENMASK(7U, 0U)
#define GPV_PERIPH_ID_6_PERIPH_ID_6_X(x)    ((x) & GENMASK(7U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:PERIPH_ID_7 */
#define GPV_PERIPH_ID_7(t)        ((t) + 0x1fdcU)

#define GPV_PERIPH_ID_7_PERIPH_ID_7(x)      ((x) & GENMASK(7U, 0U))
#define GPV_PERIPH_ID_7_PERIPH_ID_7_M       GENMASK(7U, 0U)
#define GPV_PERIPH_ID_7_PERIPH_ID_7_X(x)    ((x) & GENMASK(7U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:PERIPH_ID_0 */
#define GPV_PERIPH_ID_0(t)        ((t) + 0x1fe0U)

#define GPV_PERIPH_ID_0_PERIPH_ID_0(x)      ((x) & GENMASK(7U, 0U))
#define GPV_PERIPH_ID_0_PERIPH_ID_0_M       GENMASK(7U, 0U)
#define GPV_PERIPH_ID_0_PERIPH_ID_0_X(x)    ((x) & GENMASK(7U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:PERIPH_ID_1 */
#define GPV_PERIPH_ID_1(t)        ((t) + 0x1fe4U)

#define GPV_PERIPH_ID_1_PERIPH_ID_1(x)      ((x) & GENMASK(7U, 0U))
#define GPV_PERIPH_ID_1_PERIPH_ID_1_M       GENMASK(7U, 0U)
#define GPV_PERIPH_ID_1_PERIPH_ID_1_X(x)    ((x) & GENMASK(7U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:PERIPH_ID_2 */
#define GPV_PERIPH_ID_2(t)        ((t) + 0x1fe8U)

#define GPV_PERIPH_ID_2_PERIPH_ID_2(x)      ((x) & GENMASK(7U, 0U))
#define GPV_PERIPH_ID_2_PERIPH_ID_2_M       GENMASK(7U, 0U)
#define GPV_PERIPH_ID_2_PERIPH_ID_2_X(x)    ((x) & GENMASK(7U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:PERIPH_ID_3 */
#define GPV_PERIPH_ID_3(t)        ((t) + 0x1fecU)

#define GPV_PERIPH_ID_3_CUST_MOD_NUM(x)     ((x) & GENMASK(3U, 0U))
#define GPV_PERIPH_ID_3_CUST_MOD_NUM_M      GENMASK(3U, 0U)
#define GPV_PERIPH_ID_3_CUST_MOD_NUM_X(x)   ((x) & GENMASK(3U, 0U))

#define GPV_PERIPH_ID_3_REV_AND(x)          (((x) << 4U) & GENMASK(7U, 4U))
#define GPV_PERIPH_ID_3_REV_AND_M           GENMASK(7U, 4U)
#define GPV_PERIPH_ID_3_REV_AND_X(x)        (((x) & GENMASK(7U, 4U)) >> 4U)

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:COMP_ID_0 */
#define GPV_COMP_ID_0(t)          ((t) + 0x1ff0U)

#define GPV_COMP_ID_0_COMP_ID_0(x)          ((x) & GENMASK(7U, 0U))
#define GPV_COMP_ID_0_COMP_ID_0_M           GENMASK(7U, 0U)
#define GPV_COMP_ID_0_COMP_ID_0_X(x)        ((x) & GENMASK(7U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:COMP_ID_1 */
#define GPV_COMP_ID_1(t)          ((t) + 0x1ff4U)

#define GPV_COMP_ID_1_COMP_ID_1(x)          ((x) & GENMASK(7U, 0U))
#define GPV_COMP_ID_1_COMP_ID_1_M           GENMASK(7U, 0U)
#define GPV_COMP_ID_1_COMP_ID_1_X(x)        ((x) & GENMASK(7U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:COMP_ID_2 */
#define GPV_COMP_ID_2(t)          ((t) + 0x1ff8U)

#define GPV_COMP_ID_2_COMP_ID_2(x)          ((x) & GENMASK(7U, 0U))
#define GPV_COMP_ID_2_COMP_ID_2_M           GENMASK(7U, 0U)
#define GPV_COMP_ID_2_COMP_ID_2_X(x)        ((x) & GENMASK(7U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:COMP_ID_3 */
#define GPV_COMP_ID_3(t)          ((t) + 0x1ffcU)

#define GPV_COMP_ID_3_COMP_ID_3(x)          ((x) & GENMASK(7U, 0U))
#define GPV_COMP_ID_3_COMP_ID_3_M           GENMASK(7U, 0U)
#define GPV_COMP_ID_3_COMP_ID_3_X(x)        ((x) & GENMASK(7U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:SECURITY_BOOT_RAM */
#define GPV_SECURITY_BOOT_RAM(t)  ((t) + 0x0cU)

#define GPV_SECURITY_BOOT_RAM_SECURITY_BOOT_RAM(x) ((x) & GENMASK(0U, 0U))
#define GPV_SECURITY_BOOT_RAM_SECURITY_BOOT_RAM_M GENMASK(0U, 0U)
#define GPV_SECURITY_BOOT_RAM_SECURITY_BOOT_RAM_X(x) ((x) & GENMASK(0U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:SECURITY_DDR_CSS */
#define GPV_SECURITY_DDR_CSS(t)   ((t) + 0x14U)

#define GPV_SECURITY_DDR_CSS_SECURITY_DDR_CSS(x) ((x) & GENMASK(0U, 0U))
#define GPV_SECURITY_DDR_CSS_SECURITY_DDR_CSS_M GENMASK(0U, 0U)
#define GPV_SECURITY_DDR_CSS_SECURITY_DDR_CSS_X(x) ((x) & GENMASK(0U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:SECURITY_CSR_REGS */
#define GPV_SECURITY_CSR_REGS(t)  ((t) + 0x1cU)

#define GPV_SECURITY_CSR_REGS_SECURITY_CSR_REGS(x) ((x) & GENMASK(0U, 0U))
#define GPV_SECURITY_CSR_REGS_SECURITY_CSR_REGS_M GENMASK(0U, 0U)
#define GPV_SECURITY_CSR_REGS_SECURITY_CSR_REGS_X(x) ((x) & GENMASK(0U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:SECURITY_CPU_REGS */
#define GPV_SECURITY_CPU_REGS(t)  ((t) + 0x20U)

#define GPV_SECURITY_CPU_REGS_SECURITY_CPU_REGS(x) ((x) & GENMASK(0U, 0U))
#define GPV_SECURITY_CPU_REGS_SECURITY_CPU_REGS_M GENMASK(0U, 0U)
#define GPV_SECURITY_CPU_REGS_SECURITY_CPU_REGS_X(x) ((x) & GENMASK(0U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:SECURITY_PCIE_DBI */
#define GPV_SECURITY_PCIE_DBI(t)  ((t) + 0x34U)

#define GPV_SECURITY_PCIE_DBI_SECURITY_PCIE_DBI(x) ((x) & GENMASK(0U, 0U))
#define GPV_SECURITY_PCIE_DBI_SECURITY_PCIE_DBI_M GENMASK(0U, 0U)
#define GPV_SECURITY_PCIE_DBI_SECURITY_PCIE_DBI_X(x) ((x) & GENMASK(0U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:SECURITY_PCIE_OB */
#define GPV_SECURITY_PCIE_OB(t)   ((t) + 0x38U)

#define GPV_SECURITY_PCIE_OB_SECURITY_PCIE_OB(x) ((x) & GENMASK(0U, 0U))
#define GPV_SECURITY_PCIE_OB_SECURITY_PCIE_OB_M GENMASK(0U, 0U)
#define GPV_SECURITY_PCIE_OB_SECURITY_PCIE_OB_X(x) ((x) & GENMASK(0U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:SECURITY_PCIE_CFG */
#define GPV_SECURITY_PCIE_CFG(t)  ((t) + 0x3cU)

#define GPV_SECURITY_PCIE_CFG_SECURITY_PCIE_CFG(x) ((x) & GENMASK(0U, 0U))
#define GPV_SECURITY_PCIE_CFG_SECURITY_PCIE_CFG_M GENMASK(0U, 0U)
#define GPV_SECURITY_PCIE_CFG_SECURITY_PCIE_CFG_X(x) ((x) & GENMASK(0U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:SECURITY_APB_CSS3 */
#define GPV_SECURITY_APB_CSS3(t)  ((t) + 0x44U)

#define GPV_SECURITY_APB_CSS3_SECURITY_APB_CSS3(x) ((x) & GENMASK(15U, 0U))
#define GPV_SECURITY_APB_CSS3_SECURITY_APB_CSS3_M GENMASK(15U, 0U)
#define GPV_SECURITY_APB_CSS3_SECURITY_APB_CSS3_X(x) ((x) & GENMASK(15U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:SECURITY_APB_MAIN3 */
#define GPV_SECURITY_APB_MAIN3(t) ((t) + 0x48U)

#define GPV_SECURITY_APB_MAIN3_SECURITY_APB_MAIN3(x) ((x) & GENMASK(15U, 0U))
#define GPV_SECURITY_APB_MAIN3_SECURITY_APB_MAIN3_M GENMASK(15U, 0U)
#define GPV_SECURITY_APB_MAIN3_SECURITY_APB_MAIN3_X(x) ((x) & GENMASK(15U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:SECURITY_APB_CSS2 */
#define GPV_SECURITY_APB_CSS2(t)  ((t) + 0x4cU)

#define GPV_SECURITY_APB_CSS2_SECURITY_APB_CSS2(x) ((x) & GENMASK(15U, 0U))
#define GPV_SECURITY_APB_CSS2_SECURITY_APB_CSS2_M GENMASK(15U, 0U)
#define GPV_SECURITY_APB_CSS2_SECURITY_APB_CSS2_X(x) ((x) & GENMASK(15U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:CA53_FN_MOD */
#define GPV_CA53_FN_MOD(t)        ((t) + 0x42108U)

#define GPV_CA53_FN_MOD_CA53_FN_MOD_FN_MOD(x) ((x) & GENMASK(1U, 0U))
#define GPV_CA53_FN_MOD_CA53_FN_MOD_FN_MOD_M GENMASK(1U, 0U)
#define GPV_CA53_FN_MOD_CA53_FN_MOD_FN_MOD_X(x) ((x) & GENMASK(1U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:SECURITY_DDR_MAIN */
#define GPV_SECURITY_DDR_MAIN(t)  ((t) + 0x2cU)

#define GPV_SECURITY_DDR_MAIN_SECURITY_DDR_MAIN(x) ((x) & GENMASK(0U, 0U))
#define GPV_SECURITY_DDR_MAIN_SECURITY_DDR_MAIN_M GENMASK(0U, 0U)
#define GPV_SECURITY_DDR_MAIN_SECURITY_DDR_MAIN_X(x) ((x) & GENMASK(0U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:EXT_INITIATOR_IB_FN_MOD2 */
#define GPV_EXT_INITIATOR_IB_FN_MOD2(t) ((t) + 0x43024U)

#define GPV_EXT_INITIATOR_IB_FN_MOD2_EXT_INITIATOR_IB_FN_MOD2_BYPASS_MERGE(x)\
	((x) & GENMASK(0U, 0U))
#define GPV_EXT_INITIATOR_IB_FN_MOD2_EXT_INITIATOR_IB_FN_MOD2_BYPASS_MERGE_M\
	GENMASK(0U, 0U)
#define GPV_EXT_INITIATOR_IB_FN_MOD2_EXT_INITIATOR_IB_FN_MOD2_BYPASS_MERGE_X(x)\
	((x) & GENMASK(0U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:EXT_INITIATOR_IB_FN_MOD */
#define GPV_EXT_INITIATOR_IB_FN_MOD(t) ((t) + 0x43108U)

#define GPV_EXT_INITIATOR_IB_FN_MOD_EXT_INITIATOR_IB_FN_MOD_FN_MOD(x)\
	((x) & GENMASK(1U, 0U))
#define GPV_EXT_INITIATOR_IB_FN_MOD_EXT_INITIATOR_IB_FN_MOD_FN_MOD_M\
	GENMASK(1U, 0U)
#define GPV_EXT_INITIATOR_IB_FN_MOD_EXT_INITIATOR_IB_FN_MOD_FN_MOD_X(x)\
	((x) & GENMASK(1U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:FDMA_IB_FN_MOD2 */
#define GPV_FDMA_IB_FN_MOD2(t)    ((t) + 0x44024U)

#define GPV_FDMA_IB_FN_MOD2_FDMA_IB_FN_MOD2_BYPASS_MERGE(x)\
	((x) & GENMASK(0U, 0U))
#define GPV_FDMA_IB_FN_MOD2_FDMA_IB_FN_MOD2_BYPASS_MERGE_M GENMASK(0U, 0U)
#define GPV_FDMA_IB_FN_MOD2_FDMA_IB_FN_MOD2_BYPASS_MERGE_X(x)\
	((x) & GENMASK(0U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:FDMA_IB_FN_MOD */
#define GPV_FDMA_IB_FN_MOD(t)     ((t) + 0x44108U)

#define GPV_FDMA_IB_FN_MOD_FDMA_IB_FN_MOD_FN_MOD(x) ((x) & GENMASK(1U, 0U))
#define GPV_FDMA_IB_FN_MOD_FDMA_IB_FN_MOD_FN_MOD_M GENMASK(1U, 0U)
#define GPV_FDMA_IB_FN_MOD_FDMA_IB_FN_MOD_FN_MOD_X(x) ((x) & GENMASK(1U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:PCIE_IB_FN_MOD */
#define GPV_PCIE_IB_FN_MOD(t)     ((t) + 0x45108U)

#define GPV_PCIE_IB_FN_MOD_PCIE_IB_FN_MOD_FN_MOD(x) ((x) & GENMASK(1U, 0U))
#define GPV_PCIE_IB_FN_MOD_PCIE_IB_FN_MOD_FN_MOD_M GENMASK(1U, 0U)
#define GPV_PCIE_IB_FN_MOD_PCIE_IB_FN_MOD_FN_MOD_X(x) ((x) & GENMASK(1U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:XDMAC_FN_MOD */
#define GPV_XDMAC_FN_MOD(t)       ((t) + 0x46108U)

#define GPV_XDMAC_FN_MOD_XDMAC_FN_MOD_FN_MOD(x) ((x) & GENMASK(1U, 0U))
#define GPV_XDMAC_FN_MOD_XDMAC_FN_MOD_FN_MOD_M GENMASK(1U, 0U)
#define GPV_XDMAC_FN_MOD_XDMAC_FN_MOD_FN_MOD_X(x) ((x) & GENMASK(1U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:APB_CSS_AHB_CNTL */
#define GPV_APB_CSS_AHB_CNTL(t)   ((t) + 0x2044U)

#define GPV_APB_CSS_AHB_CNTL_APB_CSS_AHB_CNTL_DECERR_EN(x)\
	((x) & GENMASK(0U, 0U))
#define GPV_APB_CSS_AHB_CNTL_APB_CSS_AHB_CNTL_DECERR_EN_M GENMASK(0U, 0U)
#define GPV_APB_CSS_AHB_CNTL_APB_CSS_AHB_CNTL_DECERR_EN_X(x)\
	((x) & GENMASK(0U, 0U))

#define GPV_APB_CSS_AHB_CNTL_APB_CSS_AHB_CNTL_FORCE_INCR(x)\
	(((x) << 1U) & GENMASK(1U, 1U))
#define GPV_APB_CSS_AHB_CNTL_APB_CSS_AHB_CNTL_FORCE_INCR_M GENMASK(1U, 1U)
#define GPV_APB_CSS_AHB_CNTL_APB_CSS_AHB_CNTL_FORCE_INCR_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:APB_CSS_IB_FN_MOD2 */
#define GPV_APB_CSS_IB_FN_MOD2(t) ((t) + 0x2024U)

#define GPV_APB_CSS_IB_FN_MOD2_APB_CSS_IB_FN_MOD2_BYPASS_MERGE(x)\
	((x) & GENMASK(0U, 0U))
#define GPV_APB_CSS_IB_FN_MOD2_APB_CSS_IB_FN_MOD2_BYPASS_MERGE_M GENMASK(0U, 0U)
#define GPV_APB_CSS_IB_FN_MOD2_APB_CSS_IB_FN_MOD2_BYPASS_MERGE_X(x)\
	((x) & GENMASK(0U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:APB_CSS_IB_FN_MOD_ISS_BM */
#define GPV_APB_CSS_IB_FN_MOD_ISS_BM(t) ((t) + 0x2008U)

#define GPV_APB_CSS_IB_FN_MOD_ISS_BM_APB_CSS_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1U, 0U))
#define GPV_APB_CSS_IB_FN_MOD_ISS_BM_APB_CSS_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1U, 0U)
#define GPV_APB_CSS_IB_FN_MOD_ISS_BM_APB_CSS_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:BOOT_RAM_FN_MOD_ISS_BM */
#define GPV_BOOT_RAM_FN_MOD_ISS_BM(t) ((t) + 0x3008U)

#define GPV_BOOT_RAM_FN_MOD_ISS_BM_BOOT_RAM_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1U, 0U))
#define GPV_BOOT_RAM_FN_MOD_ISS_BM_BOOT_RAM_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1U, 0U)
#define GPV_BOOT_RAM_FN_MOD_ISS_BM_BOOT_RAM_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:BOOT_RAM_AHB_CNTL */
#define GPV_BOOT_RAM_AHB_CNTL(t)  ((t) + 0x3044U)

#define GPV_BOOT_RAM_AHB_CNTL_BOOT_RAM_AHB_CNTL_DECERR_EN(x)\
	((x) & GENMASK(0U, 0U))
#define GPV_BOOT_RAM_AHB_CNTL_BOOT_RAM_AHB_CNTL_DECERR_EN_M GENMASK(0U, 0U)
#define GPV_BOOT_RAM_AHB_CNTL_BOOT_RAM_AHB_CNTL_DECERR_EN_X(x)\
	((x) & GENMASK(0U, 0U))

#define GPV_BOOT_RAM_AHB_CNTL_BOOT_RAM_AHB_CNTL_FORCE_INCR(x)\
	(((x) << 1U) & GENMASK(1U, 1U))
#define GPV_BOOT_RAM_AHB_CNTL_BOOT_RAM_AHB_CNTL_FORCE_INCR_M GENMASK(1U, 1U)
#define GPV_BOOT_RAM_AHB_CNTL_BOOT_RAM_AHB_CNTL_FORCE_INCR_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:PKE_AHB_CNTL */
#define GPV_PKE_AHB_CNTL(t)       ((t) + 0x4044U)

#define GPV_PKE_AHB_CNTL_PKE_AHB_CNTL_DECERR_EN(x) ((x) & GENMASK(0U, 0U))
#define GPV_PKE_AHB_CNTL_PKE_AHB_CNTL_DECERR_EN_M GENMASK(0U, 0U)
#define GPV_PKE_AHB_CNTL_PKE_AHB_CNTL_DECERR_EN_X(x) ((x) & GENMASK(0U, 0U))

#define GPV_PKE_AHB_CNTL_PKE_AHB_CNTL_FORCE_INCR(x)\
	(((x) << 1U) & GENMASK(1U, 1U))
#define GPV_PKE_AHB_CNTL_PKE_AHB_CNTL_FORCE_INCR_M GENMASK(1U, 1U)
#define GPV_PKE_AHB_CNTL_PKE_AHB_CNTL_FORCE_INCR_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:PKE_IB_FN_MOD2 */
#define GPV_PKE_IB_FN_MOD2(t)     ((t) + 0x4024U)

#define GPV_PKE_IB_FN_MOD2_PKE_IB_FN_MOD2_BYPASS_MERGE(x)\
	((x) & GENMASK(0U, 0U))
#define GPV_PKE_IB_FN_MOD2_PKE_IB_FN_MOD2_BYPASS_MERGE_M GENMASK(0U, 0U)
#define GPV_PKE_IB_FN_MOD2_PKE_IB_FN_MOD2_BYPASS_MERGE_X(x)\
	((x) & GENMASK(0U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:PKE_IB_FN_MOD_ISS_BM */
#define GPV_PKE_IB_FN_MOD_ISS_BM(t) ((t) + 0x4008U)

#define GPV_PKE_IB_FN_MOD_ISS_BM_PKE_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1U, 0U))
#define GPV_PKE_IB_FN_MOD_ISS_BM_PKE_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1U, 0U)
#define GPV_PKE_IB_FN_MOD_ISS_BM_PKE_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:DDR_CSS_FN_MOD_ISS_BM */
#define GPV_DDR_CSS_FN_MOD_ISS_BM(t) ((t) + 0x5008U)

#define GPV_DDR_CSS_FN_MOD_ISS_BM_DDR_CSS_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1U, 0U))
#define GPV_DDR_CSS_FN_MOD_ISS_BM_DDR_CSS_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1U, 0U)
#define GPV_DDR_CSS_FN_MOD_ISS_BM_DDR_CSS_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:CSS2HSS_IB_FN_MOD2 */
#define GPV_CSS2HSS_IB_FN_MOD2(t) ((t) + 0x6024U)

#define GPV_CSS2HSS_IB_FN_MOD2_CSS2HSS_IB_FN_MOD2_BYPASS_MERGE(x)\
	((x) & GENMASK(0U, 0U))
#define GPV_CSS2HSS_IB_FN_MOD2_CSS2HSS_IB_FN_MOD2_BYPASS_MERGE_M GENMASK(0U, 0U)
#define GPV_CSS2HSS_IB_FN_MOD2_CSS2HSS_IB_FN_MOD2_BYPASS_MERGE_X(x)\
	((x) & GENMASK(0U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:CSS2HSS_IB_FN_MOD_LB */
#define GPV_CSS2HSS_IB_FN_MOD_LB(t) ((t) + 0x602cU)

#define GPV_CSS2HSS_IB_FN_MOD_LB_CSS2HSS_IB_FN_MOD_LB_FN_MOD_LB(x)\
	((x) & GENMASK(0U, 0U))
#define GPV_CSS2HSS_IB_FN_MOD_LB_CSS2HSS_IB_FN_MOD_LB_FN_MOD_LB_M\
	GENMASK(0U, 0U)
#define GPV_CSS2HSS_IB_FN_MOD_LB_CSS2HSS_IB_FN_MOD_LB_FN_MOD_LB_X(x)\
	((x) & GENMASK(0U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:CSS2HSS_IB_FN_MOD_ISS_BM */
#define GPV_CSS2HSS_IB_FN_MOD_ISS_BM(t) ((t) + 0x6008U)

#define GPV_CSS2HSS_IB_FN_MOD_ISS_BM_CSS2HSS_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1U, 0U))
#define GPV_CSS2HSS_IB_FN_MOD_ISS_BM_CSS2HSS_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1U, 0U)
#define GPV_CSS2HSS_IB_FN_MOD_ISS_BM_CSS2HSS_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:CSR_REGS_AHB_CNTL */
#define GPV_CSR_REGS_AHB_CNTL(t)  ((t) + 0x7044U)

#define GPV_CSR_REGS_AHB_CNTL_CSR_REGS_AHB_CNTL_DECERR_EN(x)\
	((x) & GENMASK(0U, 0U))
#define GPV_CSR_REGS_AHB_CNTL_CSR_REGS_AHB_CNTL_DECERR_EN_M GENMASK(0U, 0U)
#define GPV_CSR_REGS_AHB_CNTL_CSR_REGS_AHB_CNTL_DECERR_EN_X(x)\
	((x) & GENMASK(0U, 0U))

#define GPV_CSR_REGS_AHB_CNTL_CSR_REGS_AHB_CNTL_FORCE_INCR(x)\
	(((x) << 1U) & GENMASK(1U, 1U))
#define GPV_CSR_REGS_AHB_CNTL_CSR_REGS_AHB_CNTL_FORCE_INCR_M GENMASK(1U, 1U)
#define GPV_CSR_REGS_AHB_CNTL_CSR_REGS_AHB_CNTL_FORCE_INCR_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:CSR_REGS_IB_FN_MOD2 */
#define GPV_CSR_REGS_IB_FN_MOD2(t) ((t) + 0x7024U)

#define GPV_CSR_REGS_IB_FN_MOD2_CSR_REGS_IB_FN_MOD2_BYPASS_MERGE(x)\
	((x) & GENMASK(0U, 0U))
#define GPV_CSR_REGS_IB_FN_MOD2_CSR_REGS_IB_FN_MOD2_BYPASS_MERGE_M\
	GENMASK(0U, 0U)
#define GPV_CSR_REGS_IB_FN_MOD2_CSR_REGS_IB_FN_MOD2_BYPASS_MERGE_X(x)\
	((x) & GENMASK(0U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:CSR_REGS_IB_FN_MOD_ISS_BM */
#define GPV_CSR_REGS_IB_FN_MOD_ISS_BM(t) ((t) + 0x7008U)

#define GPV_CSR_REGS_IB_FN_MOD_ISS_BM_CSR_REGS_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1U, 0U))
#define GPV_CSR_REGS_IB_FN_MOD_ISS_BM_CSR_REGS_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1U, 0U)
#define GPV_CSR_REGS_IB_FN_MOD_ISS_BM_CSR_REGS_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:CPU_REGS_AHB_CNTL */
#define GPV_CPU_REGS_AHB_CNTL(t)  ((t) + 0x8044U)

#define GPV_CPU_REGS_AHB_CNTL_CPU_REGS_AHB_CNTL_DECERR_EN(x)\
	((x) & GENMASK(0U, 0U))
#define GPV_CPU_REGS_AHB_CNTL_CPU_REGS_AHB_CNTL_DECERR_EN_M GENMASK(0U, 0U)
#define GPV_CPU_REGS_AHB_CNTL_CPU_REGS_AHB_CNTL_DECERR_EN_X(x)\
	((x) & GENMASK(0U, 0U))

#define GPV_CPU_REGS_AHB_CNTL_CPU_REGS_AHB_CNTL_FORCE_INCR(x)\
	(((x) << 1U) & GENMASK(1U, 1U))
#define GPV_CPU_REGS_AHB_CNTL_CPU_REGS_AHB_CNTL_FORCE_INCR_M GENMASK(1U, 1U)
#define GPV_CPU_REGS_AHB_CNTL_CPU_REGS_AHB_CNTL_FORCE_INCR_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:CPU_REGS_IB_FN_MOD2 */
#define GPV_CPU_REGS_IB_FN_MOD2(t) ((t) + 0x8024U)

#define GPV_CPU_REGS_IB_FN_MOD2_CPU_REGS_IB_FN_MOD2_BYPASS_MERGE(x)\
	((x) & GENMASK(0U, 0U))
#define GPV_CPU_REGS_IB_FN_MOD2_CPU_REGS_IB_FN_MOD2_BYPASS_MERGE_M\
	GENMASK(0U, 0U)
#define GPV_CPU_REGS_IB_FN_MOD2_CPU_REGS_IB_FN_MOD2_BYPASS_MERGE_X(x)\
	((x) & GENMASK(0U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:CPU_REGS_IB_FN_MOD_ISS_BM */
#define GPV_CPU_REGS_IB_FN_MOD_ISS_BM(t) ((t) + 0x8008U)

#define GPV_CPU_REGS_IB_FN_MOD_ISS_BM_CPU_REGS_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1U, 0U))
#define GPV_CPU_REGS_IB_FN_MOD_ISS_BM_CPU_REGS_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1U, 0U)
#define GPV_CPU_REGS_IB_FN_MOD_ISS_BM_CPU_REGS_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:APB_MAIN1_FN_MOD_ISS_BM */
#define GPV_APB_MAIN1_FN_MOD_ISS_BM(t) ((t) + 0x9008U)

#define GPV_APB_MAIN1_FN_MOD_ISS_BM_APB_MAIN1_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1U, 0U))
#define GPV_APB_MAIN1_FN_MOD_ISS_BM_APB_MAIN1_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1U, 0U)
#define GPV_APB_MAIN1_FN_MOD_ISS_BM_APB_MAIN1_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:APB_MAIN1_AHB_CNTL */
#define GPV_APB_MAIN1_AHB_CNTL(t) ((t) + 0x9044U)

#define GPV_APB_MAIN1_AHB_CNTL_APB_MAIN1_AHB_CNTL_DECERR_EN(x)\
	((x) & GENMASK(0U, 0U))
#define GPV_APB_MAIN1_AHB_CNTL_APB_MAIN1_AHB_CNTL_DECERR_EN_M GENMASK(0U, 0U)
#define GPV_APB_MAIN1_AHB_CNTL_APB_MAIN1_AHB_CNTL_DECERR_EN_X(x)\
	((x) & GENMASK(0U, 0U))

#define GPV_APB_MAIN1_AHB_CNTL_APB_MAIN1_AHB_CNTL_FORCE_INCR(x)\
	(((x) << 1U) & GENMASK(1U, 1U))
#define GPV_APB_MAIN1_AHB_CNTL_APB_MAIN1_AHB_CNTL_FORCE_INCR_M GENMASK(1U, 1U)
#define GPV_APB_MAIN1_AHB_CNTL_APB_MAIN1_AHB_CNTL_FORCE_INCR_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:APB_MAIN2_FN_MOD_ISS_BM */
#define GPV_APB_MAIN2_FN_MOD_ISS_BM(t) ((t) + 0xa008U)

#define GPV_APB_MAIN2_FN_MOD_ISS_BM_APB_MAIN2_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1U, 0U))
#define GPV_APB_MAIN2_FN_MOD_ISS_BM_APB_MAIN2_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1U, 0U)
#define GPV_APB_MAIN2_FN_MOD_ISS_BM_APB_MAIN2_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:APB_MAIN2_AHB_CNTL */
#define GPV_APB_MAIN2_AHB_CNTL(t) ((t) + 0xa044U)

#define GPV_APB_MAIN2_AHB_CNTL_APB_MAIN2_AHB_CNTL_DECERR_EN(x)\
	((x) & GENMASK(0U, 0U))
#define GPV_APB_MAIN2_AHB_CNTL_APB_MAIN2_AHB_CNTL_DECERR_EN_M GENMASK(0U, 0U)
#define GPV_APB_MAIN2_AHB_CNTL_APB_MAIN2_AHB_CNTL_DECERR_EN_X(x)\
	((x) & GENMASK(0U, 0U))

#define GPV_APB_MAIN2_AHB_CNTL_APB_MAIN2_AHB_CNTL_FORCE_INCR(x)\
	(((x) << 1U) & GENMASK(1U, 1U))
#define GPV_APB_MAIN2_AHB_CNTL_APB_MAIN2_AHB_CNTL_FORCE_INCR_M GENMASK(1U, 1U)
#define GPV_APB_MAIN2_AHB_CNTL_APB_MAIN2_AHB_CNTL_FORCE_INCR_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:DDR_MAIN_FN_MOD_ISS_BM */
#define GPV_DDR_MAIN_FN_MOD_ISS_BM(t) ((t) + 0xb008U)

#define GPV_DDR_MAIN_FN_MOD_ISS_BM_DDR_MAIN_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1U, 0U))
#define GPV_DDR_MAIN_FN_MOD_ISS_BM_DDR_MAIN_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1U, 0U)
#define GPV_DDR_MAIN_FN_MOD_ISS_BM_DDR_MAIN_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:MAIN2HSS_FN_MOD_ISS_BM */
#define GPV_MAIN2HSS_FN_MOD_ISS_BM(t) ((t) + 0xc008U)

#define GPV_MAIN2HSS_FN_MOD_ISS_BM_MAIN2HSS_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1U, 0U))
#define GPV_MAIN2HSS_FN_MOD_ISS_BM_MAIN2HSS_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1U, 0U)
#define GPV_MAIN2HSS_FN_MOD_ISS_BM_MAIN2HSS_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:PCIE_DBI_IB_FN_MOD2 */
#define GPV_PCIE_DBI_IB_FN_MOD2(t) ((t) + 0xd024U)

#define GPV_PCIE_DBI_IB_FN_MOD2_PCIE_DBI_IB_FN_MOD2_BYPASS_MERGE(x)\
	((x) & GENMASK(0U, 0U))
#define GPV_PCIE_DBI_IB_FN_MOD2_PCIE_DBI_IB_FN_MOD2_BYPASS_MERGE_M\
	GENMASK(0U, 0U)
#define GPV_PCIE_DBI_IB_FN_MOD2_PCIE_DBI_IB_FN_MOD2_BYPASS_MERGE_X(x)\
	((x) & GENMASK(0U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:PCIE_DBI_IB_FN_MOD_ISS_BM */
#define GPV_PCIE_DBI_IB_FN_MOD_ISS_BM(t) ((t) + 0xd008U)

#define GPV_PCIE_DBI_IB_FN_MOD_ISS_BM_PCIE_DBI_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1U, 0U))
#define GPV_PCIE_DBI_IB_FN_MOD_ISS_BM_PCIE_DBI_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1U, 0U)
#define GPV_PCIE_DBI_IB_FN_MOD_ISS_BM_PCIE_DBI_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:PCIE_OB_FN_MOD_ISS_BM */
#define GPV_PCIE_OB_FN_MOD_ISS_BM(t) ((t) + 0xe008U)

#define GPV_PCIE_OB_FN_MOD_ISS_BM_PCIE_OB_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1U, 0U))
#define GPV_PCIE_OB_FN_MOD_ISS_BM_PCIE_OB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1U, 0U)
#define GPV_PCIE_OB_FN_MOD_ISS_BM_PCIE_OB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:PCIE_CFG_AHB_CNTL */
#define GPV_PCIE_CFG_AHB_CNTL(t)  ((t) + 0xf044U)

#define GPV_PCIE_CFG_AHB_CNTL_PCIE_CFG_AHB_CNTL_DECERR_EN(x)\
	((x) & GENMASK(0U, 0U))
#define GPV_PCIE_CFG_AHB_CNTL_PCIE_CFG_AHB_CNTL_DECERR_EN_M GENMASK(0U, 0U)
#define GPV_PCIE_CFG_AHB_CNTL_PCIE_CFG_AHB_CNTL_DECERR_EN_X(x)\
	((x) & GENMASK(0U, 0U))

#define GPV_PCIE_CFG_AHB_CNTL_PCIE_CFG_AHB_CNTL_FORCE_INCR(x)\
	(((x) << 1U) & GENMASK(1U, 1U))
#define GPV_PCIE_CFG_AHB_CNTL_PCIE_CFG_AHB_CNTL_FORCE_INCR_M GENMASK(1U, 1U)
#define GPV_PCIE_CFG_AHB_CNTL_PCIE_CFG_AHB_CNTL_FORCE_INCR_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:PCIE_CFG_IB_FN_MOD2 */
#define GPV_PCIE_CFG_IB_FN_MOD2(t) ((t) + 0xf024U)

#define GPV_PCIE_CFG_IB_FN_MOD2_PCIE_CFG_IB_FN_MOD2_BYPASS_MERGE(x)\
	((x) & GENMASK(0U, 0U))
#define GPV_PCIE_CFG_IB_FN_MOD2_PCIE_CFG_IB_FN_MOD2_BYPASS_MERGE_M\
	GENMASK(0U, 0U)
#define GPV_PCIE_CFG_IB_FN_MOD2_PCIE_CFG_IB_FN_MOD2_BYPASS_MERGE_X(x)\
	((x) & GENMASK(0U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:PCIE_CFG_IB_FN_MOD_ISS_BM */
#define GPV_PCIE_CFG_IB_FN_MOD_ISS_BM(t) ((t) + 0xf008U)

#define GPV_PCIE_CFG_IB_FN_MOD_ISS_BM_PCIE_CFG_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1U, 0U))
#define GPV_PCIE_CFG_IB_FN_MOD_ISS_BM_PCIE_CFG_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1U, 0U)
#define GPV_PCIE_CFG_IB_FN_MOD_ISS_BM_PCIE_CFG_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:GIC400_CFG_IB_FN_MOD2 */
#define GPV_GIC400_CFG_IB_FN_MOD2(t) ((t) + 0x10024U)

#define GPV_GIC400_CFG_IB_FN_MOD2_GIC400_CFG_IB_FN_MOD2_BYPASS_MERGE(x)\
	((x) & GENMASK(0U, 0U))
#define GPV_GIC400_CFG_IB_FN_MOD2_GIC400_CFG_IB_FN_MOD2_BYPASS_MERGE_M\
	GENMASK(0U, 0U)
#define GPV_GIC400_CFG_IB_FN_MOD2_GIC400_CFG_IB_FN_MOD2_BYPASS_MERGE_X(x)\
	((x) & GENMASK(0U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:GIC400_CFG_IB_FN_MOD_LB */
#define GPV_GIC400_CFG_IB_FN_MOD_LB(t) ((t) + 0x1002cU)

#define GPV_GIC400_CFG_IB_FN_MOD_LB_GIC400_CFG_IB_FN_MOD_LB_FN_MOD_LB(x)\
	((x) & GENMASK(0U, 0U))
#define GPV_GIC400_CFG_IB_FN_MOD_LB_GIC400_CFG_IB_FN_MOD_LB_FN_MOD_LB_M\
	GENMASK(0U, 0U)
#define GPV_GIC400_CFG_IB_FN_MOD_LB_GIC400_CFG_IB_FN_MOD_LB_FN_MOD_LB_X(x)\
	((x) & GENMASK(0U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:GIC400_CFG_IB_FN_MOD_ISS_BM */
#define GPV_GIC400_CFG_IB_FN_MOD_ISS_BM(t) ((t) + 0x10008U)

#define GPV_GIC400_CFG_IB_FN_MOD_ISS_BM_GIC400_CFG_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1U, 0U))
#define GPV_GIC400_CFG_IB_FN_MOD_ISS_BM_GIC400_CFG_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1U, 0U)
#define GPV_GIC400_CFG_IB_FN_MOD_ISS_BM_GIC400_CFG_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:APB_CSS3_IB_FN_MOD2 */
#define GPV_APB_CSS3_IB_FN_MOD2(t) ((t) + 0x11024U)

#define GPV_APB_CSS3_IB_FN_MOD2_APB_CSS3_IB_FN_MOD2_BYPASS_MERGE(x)\
	((x) & GENMASK(0U, 0U))
#define GPV_APB_CSS3_IB_FN_MOD2_APB_CSS3_IB_FN_MOD2_BYPASS_MERGE_M\
	GENMASK(0U, 0U)
#define GPV_APB_CSS3_IB_FN_MOD2_APB_CSS3_IB_FN_MOD2_BYPASS_MERGE_X(x)\
	((x) & GENMASK(0U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:APB_CSS3_IB_FN_MOD_ISS_BM */
#define GPV_APB_CSS3_IB_FN_MOD_ISS_BM(t) ((t) + 0x11008U)

#define GPV_APB_CSS3_IB_FN_MOD_ISS_BM_APB_CSS3_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1U, 0U))
#define GPV_APB_CSS3_IB_FN_MOD_ISS_BM_APB_CSS3_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1U, 0U)
#define GPV_APB_CSS3_IB_FN_MOD_ISS_BM_APB_CSS3_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:APB_MAIN3_IB_FN_MOD2 */
#define GPV_APB_MAIN3_IB_FN_MOD2(t) ((t) + 0x12024U)

#define GPV_APB_MAIN3_IB_FN_MOD2_APB_MAIN3_IB_FN_MOD2_BYPASS_MERGE(x)\
	((x) & GENMASK(0U, 0U))
#define GPV_APB_MAIN3_IB_FN_MOD2_APB_MAIN3_IB_FN_MOD2_BYPASS_MERGE_M\
	GENMASK(0U, 0U)
#define GPV_APB_MAIN3_IB_FN_MOD2_APB_MAIN3_IB_FN_MOD2_BYPASS_MERGE_X(x)\
	((x) & GENMASK(0U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:APB_MAIN3_IB_FN_MOD_ISS_BM */
#define GPV_APB_MAIN3_IB_FN_MOD_ISS_BM(t) ((t) + 0x12008U)

#define GPV_APB_MAIN3_IB_FN_MOD_ISS_BM_APB_MAIN3_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1U, 0U))
#define GPV_APB_MAIN3_IB_FN_MOD_ISS_BM_APB_MAIN3_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1U, 0U)
#define GPV_APB_MAIN3_IB_FN_MOD_ISS_BM_APB_MAIN3_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:APB_CSS2_IB_FN_MOD2 */
#define GPV_APB_CSS2_IB_FN_MOD2(t) ((t) + 0x13024U)

#define GPV_APB_CSS2_IB_FN_MOD2_APB_CSS2_IB_FN_MOD2_BYPASS_MERGE(x)\
	((x) & GENMASK(0U, 0U))
#define GPV_APB_CSS2_IB_FN_MOD2_APB_CSS2_IB_FN_MOD2_BYPASS_MERGE_M\
	GENMASK(0U, 0U)
#define GPV_APB_CSS2_IB_FN_MOD2_APB_CSS2_IB_FN_MOD2_BYPASS_MERGE_X(x)\
	((x) & GENMASK(0U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:APB_CSS2_IB_FN_MOD_ISS_BM */
#define GPV_APB_CSS2_IB_FN_MOD_ISS_BM(t) ((t) + 0x13008U)

#define GPV_APB_CSS2_IB_FN_MOD_ISS_BM_APB_CSS2_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1U, 0U))
#define GPV_APB_CSS2_IB_FN_MOD_ISS_BM_APB_CSS2_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1U, 0U)
#define GPV_APB_CSS2_IB_FN_MOD_ISS_BM_APB_CSS2_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:CSS2HSS_IB_FN_MOD */
#define GPV_CSS2HSS_IB_FN_MOD(t)  ((t) + 0x6108U)

#define GPV_CSS2HSS_IB_FN_MOD_CSS2HSS_IB_FN_MOD_FN_MOD(x)\
	((x) & GENMASK(1U, 0U))
#define GPV_CSS2HSS_IB_FN_MOD_CSS2HSS_IB_FN_MOD_FN_MOD_M GENMASK(1U, 0U)
#define GPV_CSS2HSS_IB_FN_MOD_CSS2HSS_IB_FN_MOD_FN_MOD_X(x)\
	((x) & GENMASK(1U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:PCIE_DBI_IB_FN_MOD */
#define GPV_PCIE_DBI_IB_FN_MOD(t) ((t) + 0xd108U)

#define GPV_PCIE_DBI_IB_FN_MOD_PCIE_DBI_IB_FN_MOD_FN_MOD(x)\
	((x) & GENMASK(1U, 0U))
#define GPV_PCIE_DBI_IB_FN_MOD_PCIE_DBI_IB_FN_MOD_FN_MOD_M GENMASK(1U, 0U)
#define GPV_PCIE_DBI_IB_FN_MOD_PCIE_DBI_IB_FN_MOD_FN_MOD_X(x)\
	((x) & GENMASK(1U, 0U))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA53:GIC400_CFG_IB_FN_MOD */
#define GPV_GIC400_CFG_IB_FN_MOD(t) ((t) + 0x10108U)

#define GPV_GIC400_CFG_IB_FN_MOD_GIC400_CFG_IB_FN_MOD_FN_MOD(x)\
	((x) & GENMASK(1U, 0U))
#define GPV_GIC400_CFG_IB_FN_MOD_GIC400_CFG_IB_FN_MOD_FN_MOD_M GENMASK(1U, 0U)
#define GPV_GIC400_CFG_IB_FN_MOD_GIC400_CFG_IB_FN_MOD_FN_MOD_X(x)\
	((x) & GENMASK(1U, 0U))

/*      HMATRIX2:HMATRIX2_REGS:MATRIX_SRTSR0 */
#define HMATRIX2_MATRIX_SRTSR0(t) ((t) + 0x280U)

#define HMATRIX2_MATRIX_SRTSR0_SRTOP7_SRTSR0(x)\
	(((x) << 28U) & GENMASK(31U, 28U))
#define HMATRIX2_MATRIX_SRTSR0_SRTOP7_SRTSR0_M GENMASK(31U, 28U)
#define HMATRIX2_MATRIX_SRTSR0_SRTOP7_SRTSR0_X(x)\
	(((x) & GENMASK(31U, 28U)) >> 28U)

#define HMATRIX2_MATRIX_SRTSR0_SRTOP6_SRTSR0(x)\
	(((x) << 24U) & GENMASK(27U, 24U))
#define HMATRIX2_MATRIX_SRTSR0_SRTOP6_SRTSR0_M GENMASK(27U, 24U)
#define HMATRIX2_MATRIX_SRTSR0_SRTOP6_SRTSR0_X(x)\
	(((x) & GENMASK(27U, 24U)) >> 24U)

#define HMATRIX2_MATRIX_SRTSR0_SRTOP5_SRTSR0(x)\
	(((x) << 20U) & GENMASK(23U, 20U))
#define HMATRIX2_MATRIX_SRTSR0_SRTOP5_SRTSR0_M GENMASK(23U, 20U)
#define HMATRIX2_MATRIX_SRTSR0_SRTOP5_SRTSR0_X(x)\
	(((x) & GENMASK(23U, 20U)) >> 20U)

#define HMATRIX2_MATRIX_SRTSR0_SRTOP4_SRTSR0(x)\
	(((x) << 16U) & GENMASK(19U, 16U))
#define HMATRIX2_MATRIX_SRTSR0_SRTOP4_SRTSR0_M GENMASK(19U, 16U)
#define HMATRIX2_MATRIX_SRTSR0_SRTOP4_SRTSR0_X(x)\
	(((x) & GENMASK(19U, 16U)) >> 16U)

#define HMATRIX2_MATRIX_SRTSR0_SRTOP3_SRTSR0(x)\
	(((x) << 12U) & GENMASK(15U, 12U))
#define HMATRIX2_MATRIX_SRTSR0_SRTOP3_SRTSR0_M GENMASK(15U, 12U)
#define HMATRIX2_MATRIX_SRTSR0_SRTOP3_SRTSR0_X(x)\
	(((x) & GENMASK(15U, 12U)) >> 12U)

#define HMATRIX2_MATRIX_SRTSR0_SRTOP2_SRTSR0(x) (((x) << 8U) & GENMASK(11U, 8U))
#define HMATRIX2_MATRIX_SRTSR0_SRTOP2_SRTSR0_M GENMASK(11U, 8U)
#define HMATRIX2_MATRIX_SRTSR0_SRTOP2_SRTSR0_X(x)\
	(((x) & GENMASK(11U, 8U)) >> 8U)

#define HMATRIX2_MATRIX_SRTSR0_SRTOP1_SRTSR0(x) (((x) << 4U) & GENMASK(7U, 4U))
#define HMATRIX2_MATRIX_SRTSR0_SRTOP1_SRTSR0_M GENMASK(7U, 4U)
#define HMATRIX2_MATRIX_SRTSR0_SRTOP1_SRTSR0_X(x)\
	(((x) & GENMASK(7U, 4U)) >> 4U)

#define HMATRIX2_MATRIX_SRTSR0_SRTOP0_SRTSR0(x) ((x) & GENMASK(3U, 0U))
#define HMATRIX2_MATRIX_SRTSR0_SRTOP0_SRTSR0_M GENMASK(3U, 0U)
#define HMATRIX2_MATRIX_SRTSR0_SRTOP0_SRTSR0_X(x) ((x) & GENMASK(3U, 0U))

/*      OTP:OTP_REGS:OTP_PWR_DN */
#define OTP_OTP_PWR_DN(t)         ((t) + 0x00U)

#define OTP_OTP_PWR_DN_OTP_PWRDN_N(x)       ((x) & GENMASK(0U, 0U))
#define OTP_OTP_PWR_DN_OTP_PWRDN_N_M        GENMASK(0U, 0U)
#define OTP_OTP_PWR_DN_OTP_PWRDN_N_X(x)     ((x) & GENMASK(0U, 0U))

/*      OTP:OTP_REGS:OTP_ADDR_HI */
#define OTP_OTP_ADDR_HI(t)        ((t) + 0x04U)

#define OTP_OTP_ADDR_HI_OTP_ADDR_16_11(x)   ((x) & GENMASK(5U, 0U))
#define OTP_OTP_ADDR_HI_OTP_ADDR_16_11_M    GENMASK(5U, 0U)
#define OTP_OTP_ADDR_HI_OTP_ADDR_16_11_X(x) ((x) & GENMASK(5U, 0U))

/*      OTP:OTP_REGS:OTP_ADDR_LO */
#define OTP_OTP_ADDR_LO(t)        ((t) + 0x08U)

#define OTP_OTP_ADDR_LO_OTP_ADDR_10_3(x)    ((x) & GENMASK(7U, 0U))
#define OTP_OTP_ADDR_LO_OTP_ADDR_10_3_M     GENMASK(7U, 0U)
#define OTP_OTP_ADDR_LO_OTP_ADDR_10_3_X(x)  ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_ADDR_BITS */
#define OTP_OTP_ADDR_BITS(t)      ((t) + 0x0cU)

#define OTP_OTP_ADDR_BITS_OTP_ADDR_2_0(x)   ((x) & GENMASK(2U, 0U))
#define OTP_OTP_ADDR_BITS_OTP_ADDR_2_0_M    GENMASK(2U, 0U)
#define OTP_OTP_ADDR_BITS_OTP_ADDR_2_0_X(x) ((x) & GENMASK(2U, 0U))

/*      OTP:OTP_REGS:OTP_PRGM_DATA */
#define OTP_OTP_PRGM_DATA(t)      ((t) + 0x10U)

#define OTP_OTP_PRGM_DATA_OTP_WR_DATA(x)    ((x) & GENMASK(7U, 0U))
#define OTP_OTP_PRGM_DATA_OTP_WR_DATA_M     GENMASK(7U, 0U)
#define OTP_OTP_PRGM_DATA_OTP_WR_DATA_X(x)  ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_PRGM_MODE */
#define OTP_OTP_PRGM_MODE(t)      ((t) + 0x14U)

#define OTP_OTP_PRGM_MODE_OTP_AUTO_REPAIR_ENA(x) (((x) << 1U) & GENMASK(1U, 1U))
#define OTP_OTP_PRGM_MODE_OTP_AUTO_REPAIR_ENA_M GENMASK(1U, 1U)
#define OTP_OTP_PRGM_MODE_OTP_AUTO_REPAIR_ENA_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

#define OTP_OTP_PRGM_MODE_OTP_PGM_MODE_BYTE(x) ((x) & GENMASK(0U, 0U))
#define OTP_OTP_PRGM_MODE_OTP_PGM_MODE_BYTE_M GENMASK(0U, 0U)
#define OTP_OTP_PRGM_MODE_OTP_PGM_MODE_BYTE_X(x) ((x) & GENMASK(0U, 0U))

/*      OTP:OTP_REGS:OTP_RD_DATA */
#define OTP_OTP_RD_DATA(t)        ((t) + 0x18U)

#define OTP_OTP_RD_DATA_OTP_RD_DATA_FLD(x)  ((x) & GENMASK(7U, 0U))
#define OTP_OTP_RD_DATA_OTP_RD_DATA_FLD_M   GENMASK(7U, 0U)
#define OTP_OTP_RD_DATA_OTP_RD_DATA_FLD_X(x) ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_FUNC_CMD */
#define OTP_OTP_FUNC_CMD(t)       ((t) + 0x20U)

#define OTP_OTP_FUNC_CMD_OTP_FW_SMART_PGM_INIT_ACCESS(x)\
	(((x) << 4U) & GENMASK(4U, 4U))
#define OTP_OTP_FUNC_CMD_OTP_FW_SMART_PGM_INIT_ACCESS_M GENMASK(4U, 4U)
#define OTP_OTP_FUNC_CMD_OTP_FW_SMART_PGM_INIT_ACCESS_X(x)\
	(((x) & GENMASK(4U, 4U)) >> 4U)

#define OTP_OTP_FUNC_CMD_OTP_FW_SMART_PGM_EN(x) (((x) << 3U) & GENMASK(3U, 3U))
#define OTP_OTP_FUNC_CMD_OTP_FW_SMART_PGM_EN_M GENMASK(3U, 3U)
#define OTP_OTP_FUNC_CMD_OTP_FW_SMART_PGM_EN_X(x)\
	(((x) & GENMASK(3U, 3U)) >> 3U)

#define OTP_OTP_FUNC_CMD_OTP_RESET(x)       (((x) << 2U) & GENMASK(2U, 2U))
#define OTP_OTP_FUNC_CMD_OTP_RESET_M        GENMASK(2U, 2U)
#define OTP_OTP_FUNC_CMD_OTP_RESET_X(x)     (((x) & GENMASK(2U, 2U)) >> 2U)

#define OTP_OTP_FUNC_CMD_OTP_PROGRAM(x)     (((x) << 1U) & GENMASK(1U, 1U))
#define OTP_OTP_FUNC_CMD_OTP_PROGRAM_M      GENMASK(1U, 1U)
#define OTP_OTP_FUNC_CMD_OTP_PROGRAM_X(x)   (((x) & GENMASK(1U, 1U)) >> 1U)

#define OTP_OTP_FUNC_CMD_OTP_READ(x)        ((x) & GENMASK(0U, 0U))
#define OTP_OTP_FUNC_CMD_OTP_READ_M         GENMASK(0U, 0U)
#define OTP_OTP_FUNC_CMD_OTP_READ_X(x)      ((x) & GENMASK(0U, 0U))

/*      OTP:OTP_REGS:OTP_TEST_CMD */
#define OTP_OTP_TEST_CMD(t)       ((t) + 0x24U)

#define OTP_OTP_TEST_CMD_OTP_BISR_RD(x)     (((x) << 6U) & GENMASK(6U, 6U))
#define OTP_OTP_TEST_CMD_OTP_BISR_RD_M      GENMASK(6U, 6U)
#define OTP_OTP_TEST_CMD_OTP_BISR_RD_X(x)   (((x) & GENMASK(6U, 6U)) >> 6U)

#define OTP_OTP_TEST_CMD_OTP_BISR_WR(x)     (((x) << 5U) & GENMASK(5U, 5U))
#define OTP_OTP_TEST_CMD_OTP_BISR_WR_M      GENMASK(5U, 5U)
#define OTP_OTP_TEST_CMD_OTP_BISR_WR_X(x)   (((x) & GENMASK(5U, 5U)) >> 5U)

#define OTP_OTP_TEST_CMD_OTP_TEST_DEC_SEL(x) (((x) << 4U) & GENMASK(4U, 4U))
#define OTP_OTP_TEST_CMD_OTP_TEST_DEC_SEL_M GENMASK(4U, 4U)
#define OTP_OTP_TEST_CMD_OTP_TEST_DEC_SEL_X(x) (((x) & GENMASK(4U, 4U)) >> 4U)

#define OTP_OTP_TEST_CMD_OTP_WRTEST(x)      (((x) << 2U) & GENMASK(2U, 2U))
#define OTP_OTP_TEST_CMD_OTP_WRTEST_M       GENMASK(2U, 2U)
#define OTP_OTP_TEST_CMD_OTP_WRTEST_X(x)    (((x) & GENMASK(2U, 2U)) >> 2U)

#define OTP_OTP_TEST_CMD_OTP_TESTDEC(x)     (((x) << 1U) & GENMASK(1U, 1U))
#define OTP_OTP_TEST_CMD_OTP_TESTDEC_M      GENMASK(1U, 1U)
#define OTP_OTP_TEST_CMD_OTP_TESTDEC_X(x)   (((x) & GENMASK(1U, 1U)) >> 1U)

#define OTP_OTP_TEST_CMD_OTP_BLANKCHECK(x)  ((x) & GENMASK(0U, 0U))
#define OTP_OTP_TEST_CMD_OTP_BLANKCHECK_M   GENMASK(0U, 0U)
#define OTP_OTP_TEST_CMD_OTP_BLANKCHECK_X(x) ((x) & GENMASK(0U, 0U))

/*      OTP:OTP_REGS:OTP_CMD_GO */
#define OTP_OTP_CMD_GO(t)         ((t) + 0x28U)

#define OTP_OTP_CMD_GO_OTP_GO(x)            ((x) & GENMASK(0U, 0U))
#define OTP_OTP_CMD_GO_OTP_GO_M             GENMASK(0U, 0U)
#define OTP_OTP_CMD_GO_OTP_GO_X(x)          ((x) & GENMASK(0U, 0U))

/*      OTP:OTP_REGS:OTP_PASS_FAIL */
#define OTP_OTP_PASS_FAIL(t)      ((t) + 0x2cU)

#define OTP_OTP_PASS_FAIL_OTP_AUTO_REPAIR_PASS(x)\
	(((x) << 7U) & GENMASK(7U, 7U))
#define OTP_OTP_PASS_FAIL_OTP_AUTO_REPAIR_PASS_M GENMASK(7U, 7U)
#define OTP_OTP_PASS_FAIL_OTP_AUTO_REPAIR_PASS_X(x)\
	(((x) & GENMASK(7U, 7U)) >> 7U)

#define OTP_OTP_PASS_FAIL_OTP_AUTO_REPAIR_FAIL(x)\
	(((x) << 6U) & GENMASK(6U, 6U))
#define OTP_OTP_PASS_FAIL_OTP_AUTO_REPAIR_FAIL_M GENMASK(6U, 6U)
#define OTP_OTP_PASS_FAIL_OTP_AUTO_REPAIR_FAIL_X(x)\
	(((x) & GENMASK(6U, 6U)) >> 6U)

#define OTP_OTP_PASS_FAIL_OTP_READ_POLICY_FAIL(x)\
	(((x) << 5U) & GENMASK(5U, 5U))
#define OTP_OTP_PASS_FAIL_OTP_READ_POLICY_FAIL_M GENMASK(5U, 5U)
#define OTP_OTP_PASS_FAIL_OTP_READ_POLICY_FAIL_X(x)\
	(((x) & GENMASK(5U, 5U)) >> 5U)

#define OTP_OTP_PASS_FAIL_OTP_WRITE_POLICY_FAIL(x)\
	(((x) << 4U) & GENMASK(4U, 4U))
#define OTP_OTP_PASS_FAIL_OTP_WRITE_POLICY_FAIL_M GENMASK(4U, 4U)
#define OTP_OTP_PASS_FAIL_OTP_WRITE_POLICY_FAIL_X(x)\
	(((x) & GENMASK(4U, 4U)) >> 4U)

#define OTP_OTP_PASS_FAIL_OTP_READ_PROHIBITED(x) (((x) << 3U) & GENMASK(3U, 3U))
#define OTP_OTP_PASS_FAIL_OTP_READ_PROHIBITED_M GENMASK(3U, 3U)
#define OTP_OTP_PASS_FAIL_OTP_READ_PROHIBITED_X(x)\
	(((x) & GENMASK(3U, 3U)) >> 3U)

#define OTP_OTP_PASS_FAIL_OTP_WRITE_PROHIBITED(x)\
	(((x) << 2U) & GENMASK(2U, 2U))
#define OTP_OTP_PASS_FAIL_OTP_WRITE_PROHIBITED_M GENMASK(2U, 2U)
#define OTP_OTP_PASS_FAIL_OTP_WRITE_PROHIBITED_X(x)\
	(((x) & GENMASK(2U, 2U)) >> 2U)

#define OTP_OTP_PASS_FAIL_OTP_PASS(x)       (((x) << 1U) & GENMASK(1U, 1U))
#define OTP_OTP_PASS_FAIL_OTP_PASS_M        GENMASK(1U, 1U)
#define OTP_OTP_PASS_FAIL_OTP_PASS_X(x)     (((x) & GENMASK(1U, 1U)) >> 1U)

#define OTP_OTP_PASS_FAIL_OTP_FAIL(x)       ((x) & GENMASK(0U, 0U))
#define OTP_OTP_PASS_FAIL_OTP_FAIL_M        GENMASK(0U, 0U)
#define OTP_OTP_PASS_FAIL_OTP_FAIL_X(x)     ((x) & GENMASK(0U, 0U))

/*      OTP:OTP_REGS:OTP_STATUS */
#define OTP_OTP_STATUS(t)         ((t) + 0x30U)

#define OTP_OTP_STATUS_OTP_LOADED(x)        (((x) << 7U) & GENMASK(7U, 7U))
#define OTP_OTP_STATUS_OTP_LOADED_M         GENMASK(7U, 7U)
#define OTP_OTP_STATUS_OTP_LOADED_X(x)      (((x) & GENMASK(7U, 7U)) >> 7U)

#define OTP_OTP_STATUS_OTP_LOCK(x)          (((x) << 4U) & GENMASK(4U, 4U))
#define OTP_OTP_STATUS_OTP_LOCK_M           GENMASK(4U, 4U)
#define OTP_OTP_STATUS_OTP_LOCK_X(x)        (((x) & GENMASK(4U, 4U)) >> 4U)

#define OTP_OTP_STATUS_OTP_WEB(x)           (((x) << 3U) & GENMASK(3U, 3U))
#define OTP_OTP_STATUS_OTP_WEB_M            GENMASK(3U, 3U)
#define OTP_OTP_STATUS_OTP_WEB_X(x)         (((x) & GENMASK(3U, 3U)) >> 3U)

#define OTP_OTP_STATUS_OTP_PGMEN(x)         (((x) << 2U) & GENMASK(2U, 2U))
#define OTP_OTP_STATUS_OTP_PGMEN_M          GENMASK(2U, 2U)
#define OTP_OTP_STATUS_OTP_PGMEN_X(x)       (((x) & GENMASK(2U, 2U)) >> 2U)

#define OTP_OTP_STATUS_OTP_CPUMPEN(x)       (((x) << 1U) & GENMASK(1U, 1U))
#define OTP_OTP_STATUS_OTP_CPUMPEN_M        GENMASK(1U, 1U)
#define OTP_OTP_STATUS_OTP_CPUMPEN_X(x)     (((x) & GENMASK(1U, 1U)) >> 1U)

#define OTP_OTP_STATUS_OTP_BUSY(x)          ((x) & GENMASK(0U, 0U))
#define OTP_OTP_STATUS_OTP_BUSY_M           GENMASK(0U, 0U)
#define OTP_OTP_STATUS_OTP_BUSY_X(x)        ((x) & GENMASK(0U, 0U))

/*      OTP:OTP_REGS:OTP_MAX_PRG */
#define OTP_OTP_MAX_PRG(t)        ((t) + 0x34U)

#define OTP_OTP_MAX_PRG_OTP_MAX_PROG(x)     ((x) & GENMASK(4U, 0U))
#define OTP_OTP_MAX_PRG_OTP_MAX_PROG_M      GENMASK(4U, 0U)
#define OTP_OTP_MAX_PRG_OTP_MAX_PROG_X(x)   ((x) & GENMASK(4U, 0U))

/*      OTP:OTP_REGS:OTP_BLANK_FAIL_COUNT */
#define OTP_OTP_BLANK_FAIL_COUNT(t) ((t) + 0x40U)

#define OTP_OTP_BLANK_FAIL_COUNT_OTP_BLANK_FAIL_COUNT(x) ((x) & GENMASK(7U, 0U))
#define OTP_OTP_BLANK_FAIL_COUNT_OTP_BLANK_FAIL_COUNT_M GENMASK(7U, 0U)
#define OTP_OTP_BLANK_FAIL_COUNT_OTP_BLANK_FAIL_COUNT_X(x)\
	((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_BLANK_FAIL_COUNT_ADDR_IDX */
#define OTP_OTP_BLANK_FAIL_COUNT_ADDR_IDX(t) ((t) + 0x44U)

#define OTP_OTP_BLANK_FAIL_COUNT_ADDR_IDX_OTP_BLANK_FAIL_COUNT_ADDR_IDX(x)\
	((x) & GENMASK(2U, 0U))
#define OTP_OTP_BLANK_FAIL_COUNT_ADDR_IDX_OTP_BLANK_FAIL_COUNT_ADDR_IDX_M\
	GENMASK(2U, 0U)
#define OTP_OTP_BLANK_FAIL_COUNT_ADDR_IDX_OTP_BLANK_FAIL_COUNT_ADDR_IDX_X(x)\
	((x) & GENMASK(2U, 0U))

/*      OTP:OTP_REGS:OTP_BLANK_FAIL_ADDR_HI */
#define OTP_OTP_BLANK_FAIL_ADDR_HI(t) ((t) + 0x48U)

#define OTP_OTP_BLANK_FAIL_ADDR_HI_OTP_BLANK_FAIL_ADDR_HI(x)\
	((x) & GENMASK(7U, 0U))
#define OTP_OTP_BLANK_FAIL_ADDR_HI_OTP_BLANK_FAIL_ADDR_HI_M GENMASK(7U, 0U)
#define OTP_OTP_BLANK_FAIL_ADDR_HI_OTP_BLANK_FAIL_ADDR_HI_X(x)\
	((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_BLANK_FAIL_ADDR_LO */
#define OTP_OTP_BLANK_FAIL_ADDR_LO(t) ((t) + 0x4cU)

#define OTP_OTP_BLANK_FAIL_ADDR_LO_OTP_BLANK_FAIL_ADDR_LO(x)\
	((x) & GENMASK(7U, 0U))
#define OTP_OTP_BLANK_FAIL_ADDR_LO_OTP_BLANK_FAIL_ADDR_LO_M GENMASK(7U, 0U)
#define OTP_OTP_BLANK_FAIL_ADDR_LO_OTP_BLANK_FAIL_ADDR_LO_X(x)\
	((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_INTR_STATUS */
#define OTP_OTP_INTR_STATUS(t)    ((t) + 0x38U)

#define OTP_OTP_INTR_STATUS_OTP_READY_INTR_STATUS(x) ((x) & GENMASK(0U, 0U))
#define OTP_OTP_INTR_STATUS_OTP_READY_INTR_STATUS_M GENMASK(0U, 0U)
#define OTP_OTP_INTR_STATUS_OTP_READY_INTR_STATUS_X(x) ((x) & GENMASK(0U, 0U))

/*      OTP:OTP_REGS:OTP_INTR_MASK */
#define OTP_OTP_INTR_MASK(t)      ((t) + 0x3cU)

#define OTP_OTP_INTR_MASK_OTP_READY_INTR_MASK(x) ((x) & GENMASK(0U, 0U))
#define OTP_OTP_INTR_MASK_OTP_READY_INTR_MASK_M GENMASK(0U, 0U)
#define OTP_OTP_INTR_MASK_OTP_READY_INTR_MASK_X(x) ((x) & GENMASK(0U, 0U))

/*      OTP:OTP_REGS:OTP_RSTB_PW_HI */
#define OTP_OTP_RSTB_PW_HI(t)     ((t) + 0x50U)

#define OTP_OTP_RSTB_PW_HI_OTP_RSTW_15_8(x) ((x) & GENMASK(7U, 0U))
#define OTP_OTP_RSTB_PW_HI_OTP_RSTW_15_8_M  GENMASK(7U, 0U)
#define OTP_OTP_RSTB_PW_HI_OTP_RSTW_15_8_X(x) ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_RSTB_PW_LO */
#define OTP_OTP_RSTB_PW_LO(t)     ((t) + 0x54U)

#define OTP_OTP_RSTB_PW_LO_OTP_RSTW_7_0(x)  ((x) & GENMASK(7U, 0U))
#define OTP_OTP_RSTB_PW_LO_OTP_RSTW_7_0_M   GENMASK(7U, 0U)
#define OTP_OTP_RSTB_PW_LO_OTP_RSTW_7_0_X(x) ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_PGM_PW_HI */
#define OTP_OTP_PGM_PW_HI(t)      ((t) + 0x60U)

#define OTP_OTP_PGM_PW_HI_OTP_PPW_HI(x)     ((x) & GENMASK(7U, 0U))
#define OTP_OTP_PGM_PW_HI_OTP_PPW_HI_M      GENMASK(7U, 0U)
#define OTP_OTP_PGM_PW_HI_OTP_PPW_HI_X(x)   ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_PGM_PW_LO */
#define OTP_OTP_PGM_PW_LO(t)      ((t) + 0x64U)

#define OTP_OTP_PGM_PW_LO_OTP_PPW_LO(x)     ((x) & GENMASK(7U, 0U))
#define OTP_OTP_PGM_PW_LO_OTP_PPW_LO_M      GENMASK(7U, 0U)
#define OTP_OTP_PGM_PW_LO_OTP_PPW_LO_X(x)   ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_READ_PW_HI */
#define OTP_OTP_READ_PW_HI(t)     ((t) + 0x70U)

#define OTP_OTP_READ_PW_HI_OTP_RPW_HI(x)    ((x) & GENMASK(7U, 0U))
#define OTP_OTP_READ_PW_HI_OTP_RPW_HI_M     GENMASK(7U, 0U)
#define OTP_OTP_READ_PW_HI_OTP_RPW_HI_X(x)  ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_READ_PW_LO */
#define OTP_OTP_READ_PW_LO(t)     ((t) + 0x74U)

#define OTP_OTP_READ_PW_LO_OTP_RPW_LO(x)    ((x) & GENMASK(7U, 0U))
#define OTP_OTP_READ_PW_LO_OTP_RPW_LO_M     GENMASK(7U, 0U)
#define OTP_OTP_READ_PW_LO_OTP_RPW_LO_X(x)  ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_TCRST_VAL */
#define OTP_OTP_TCRST_VAL(t)      ((t) + 0x80U)

#define OTP_OTP_TCRST_VAL_OTP_TCRST(x)      ((x) & GENMASK(7U, 0U))
#define OTP_OTP_TCRST_VAL_OTP_TCRST_M       GENMASK(7U, 0U)
#define OTP_OTP_TCRST_VAL_OTP_TCRST_X(x)    ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_TRSRD_VAL */
#define OTP_OTP_TRSRD_VAL(t)      ((t) + 0x84U)

#define OTP_OTP_TRSRD_VAL_OTP_TRSRD(x)      ((x) & GENMASK(7U, 0U))
#define OTP_OTP_TRSRD_VAL_OTP_TRSRD_M       GENMASK(7U, 0U)
#define OTP_OTP_TRSRD_VAL_OTP_TRSRD_X(x)    ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_TREADEN_VAL */
#define OTP_OTP_TREADEN_VAL(t)    ((t) + 0x88U)

#define OTP_OTP_TREADEN_VAL_OTP_TREADEN(x)  ((x) & GENMASK(7U, 0U))
#define OTP_OTP_TREADEN_VAL_OTP_TREADEN_M   GENMASK(7U, 0U)
#define OTP_OTP_TREADEN_VAL_OTP_TREADEN_X(x) ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_TDLES_VAL */
#define OTP_OTP_TDLES_VAL(t)      ((t) + 0x8cU)

#define OTP_OTP_TDLES_VAL_OTP_TDLES(x)      ((x) & GENMASK(7U, 0U))
#define OTP_OTP_TDLES_VAL_OTP_TDLES_M       GENMASK(7U, 0U)
#define OTP_OTP_TDLES_VAL_OTP_TDLES_X(x)    ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_TWWL_VAL */
#define OTP_OTP_TWWL_VAL(t)       ((t) + 0x90U)

#define OTP_OTP_TWWL_VAL_OTP_TWWL(x)        ((x) & GENMASK(7U, 0U))
#define OTP_OTP_TWWL_VAL_OTP_TWWL_M         GENMASK(7U, 0U)
#define OTP_OTP_TWWL_VAL_OTP_TWWL_X(x)      ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_TDLEH_VAL */
#define OTP_OTP_TDLEH_VAL(t)      ((t) + 0x94U)

#define OTP_OTP_TDLEH_VAL_OTP_TDLEH(x)      ((x) & GENMASK(7U, 0U))
#define OTP_OTP_TDLEH_VAL_OTP_TDLEH_M       GENMASK(7U, 0U)
#define OTP_OTP_TDLEH_VAL_OTP_TDLEH_X(x)    ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_TWPED_VAL */
#define OTP_OTP_TWPED_VAL(t)      ((t) + 0x98U)

#define OTP_OTP_TWPED_VAL_OTP_TWPED(x)      ((x) & GENMASK(7U, 0U))
#define OTP_OTP_TWPED_VAL_OTP_TWPED_M       GENMASK(7U, 0U)
#define OTP_OTP_TWPED_VAL_OTP_TWPED_X(x)    ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_TPES_VAL */
#define OTP_OTP_TPES_VAL(t)       ((t) + 0x9cU)

#define OTP_OTP_TPES_VAL_OTP_TPES(x)        ((x) & GENMASK(7U, 0U))
#define OTP_OTP_TPES_VAL_OTP_TPES_M         GENMASK(7U, 0U)
#define OTP_OTP_TPES_VAL_OTP_TPES_X(x)      ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_TCPS_VAL */
#define OTP_OTP_TCPS_VAL(t)       ((t) + 0xa0U)

#define OTP_OTP_TCPS_VAL_OTP_TCPS(x)        ((x) & GENMASK(7U, 0U))
#define OTP_OTP_TCPS_VAL_OTP_TCPS_M         GENMASK(7U, 0U)
#define OTP_OTP_TCPS_VAL_OTP_TCPS_X(x)      ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_TCPH_VAL */
#define OTP_OTP_TCPH_VAL(t)       ((t) + 0xa4U)

#define OTP_OTP_TCPH_VAL_OTP_TCPH(x)        ((x) & GENMASK(7U, 0U))
#define OTP_OTP_TCPH_VAL_OTP_TCPH_M         GENMASK(7U, 0U)
#define OTP_OTP_TCPH_VAL_OTP_TCPH_X(x)      ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_TPGMVFY_VAL */
#define OTP_OTP_TPGMVFY_VAL(t)    ((t) + 0xa8U)

#define OTP_OTP_TPGMVFY_VAL_OTP_TPGMVFY(x)  ((x) & GENMASK(7U, 0U))
#define OTP_OTP_TPGMVFY_VAL_OTP_TPGMVFY_M   GENMASK(7U, 0U)
#define OTP_OTP_TPGMVFY_VAL_OTP_TPGMVFY_X(x) ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_TPEH_VAL */
#define OTP_OTP_TPEH_VAL(t)       ((t) + 0xacU)

#define OTP_OTP_TPEH_VAL_OTP_TPEH(x)        ((x) & GENMASK(7U, 0U))
#define OTP_OTP_TPEH_VAL_OTP_TPEH_M         GENMASK(7U, 0U)
#define OTP_OTP_TPEH_VAL_OTP_TPEH_X(x)      ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_TPGRST_VAL */
#define OTP_OTP_TPGRST_VAL(t)     ((t) + 0xb0U)

#define OTP_OTP_TPGRST_VAL_OTP_TPGRST(x)    ((x) & GENMASK(7U, 0U))
#define OTP_OTP_TPGRST_VAL_OTP_TPGRST_M     GENMASK(7U, 0U)
#define OTP_OTP_TPGRST_VAL_OTP_TPGRST_X(x)  ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_TCLES_VAL */
#define OTP_OTP_TCLES_VAL(t)      ((t) + 0xb4U)

#define OTP_OTP_TCLES_VAL_OTP_TCLES(x)      ((x) & GENMASK(7U, 0U))
#define OTP_OTP_TCLES_VAL_OTP_TCLES_M       GENMASK(7U, 0U)
#define OTP_OTP_TCLES_VAL_OTP_TCLES_X(x)    ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_TCLEH_VAL */
#define OTP_OTP_TCLEH_VAL(t)      ((t) + 0xb8U)

#define OTP_OTP_TCLEH_VAL_OTP_TCLEH(x)      ((x) & GENMASK(7U, 0U))
#define OTP_OTP_TCLEH_VAL_OTP_TCLEH_M       GENMASK(7U, 0U)
#define OTP_OTP_TCLEH_VAL_OTP_TCLEH_X(x)    ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_TRDES_VAL */
#define OTP_OTP_TRDES_VAL(t)      ((t) + 0xbcU)

#define OTP_OTP_TRDES_VAL_OTP_TRDES(x)      ((x) & GENMASK(7U, 0U))
#define OTP_OTP_TRDES_VAL_OTP_TRDES_M       GENMASK(7U, 0U)
#define OTP_OTP_TRDES_VAL_OTP_TRDES_X(x)    ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_TBCAAC_VAL */
#define OTP_OTP_TBCAAC_VAL(t)     ((t) + 0xc0U)

#define OTP_OTP_TBCAAC_VAL_OTP_TBCAAC(x)    ((x) & GENMASK(7U, 0U))
#define OTP_OTP_TBCAAC_VAL_OTP_TBCAAC_M     GENMASK(7U, 0U)
#define OTP_OTP_TBCAAC_VAL_OTP_TBCAAC_X(x)  ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_TAAC_VAL */
#define OTP_OTP_TAAC_VAL(t)       ((t) + 0xc4U)

#define OTP_OTP_TAAC_VAL_OTP_TAAC(x)        ((x) & GENMASK(7U, 0U))
#define OTP_OTP_TAAC_VAL_OTP_TAAC_M         GENMASK(7U, 0U)
#define OTP_OTP_TAAC_VAL_OTP_TAAC_X(x)      ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_TACCT_VAL */
#define OTP_OTP_TACCT_VAL(t)      ((t) + 0xc8U)

#define OTP_OTP_TACCT_VAL_OTP_TACCT(x)      ((x) & GENMASK(7U, 0U))
#define OTP_OTP_TACCT_VAL_OTP_TACCT_M       GENMASK(7U, 0U)
#define OTP_OTP_TACCT_VAL_OTP_TACCT_X(x)    ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_TPRYCEB_VAL */
#define OTP_OTP_TPRYCEB_VAL(t)    ((t) + 0xccU)

#define OTP_OTP_TPRYCEB_VAL_OTP_TPRYCEB(x)  ((x) & GENMASK(7U, 0U))
#define OTP_OTP_TPRYCEB_VAL_OTP_TPRYCEB_M   GENMASK(7U, 0U)
#define OTP_OTP_TPRYCEB_VAL_OTP_TPRYCEB_X(x) ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_TCEBPRY_VAL */
#define OTP_OTP_TCEBPRY_VAL(t)    ((t) + 0xd0U)

#define OTP_OTP_TCEBPRY_VAL_OTP_TCEBPRY(x)  ((x) & GENMASK(7U, 0U))
#define OTP_OTP_TCEBPRY_VAL_OTP_TCEBPRY_M   GENMASK(7U, 0U)
#define OTP_OTP_TCEBPRY_VAL_OTP_TCEBPRY_X(x) ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_TPGMAS_VAL */
#define OTP_OTP_TPGMAS_VAL(t)     ((t) + 0xf0U)

#define OTP_OTP_TPGMAS_VAL_OTP_TPGMAS(x)    ((x) & GENMASK(7U, 0U))
#define OTP_OTP_TPGMAS_VAL_OTP_TPGMAS_M     GENMASK(7U, 0U)
#define OTP_OTP_TPGMAS_VAL_OTP_TPGMAS_X(x)  ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_TCPRD_VAL */
#define OTP_OTP_TCPRD_VAL(t)      ((t) + 0x100U)

#define OTP_OTP_TCPRD_VAL_OTP_TCPRD(x)      ((x) & GENMASK(7U, 0U))
#define OTP_OTP_TCPRD_VAL_OTP_TCPRD_M       GENMASK(7U, 0U)
#define OTP_OTP_TCPRD_VAL_OTP_TCPRD_X(x)    ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_TRDCP_VAL */
#define OTP_OTP_TRDCP_VAL(t)      ((t) + 0x104U)

#define OTP_OTP_TRDCP_VAL_OTP_TRDCP(x)      ((x) & GENMASK(7U, 0U))
#define OTP_OTP_TRDCP_VAL_OTP_TRDCP_M       GENMASK(7U, 0U)
#define OTP_OTP_TRDCP_VAL_OTP_TRDCP_X(x)    ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_NP1_VAL */
#define OTP_OTP_NP1_VAL(t)        ((t) + 0x114U)

#define OTP_OTP_NP1_VAL_OTP_NP1(x)          ((x) & GENMASK(3U, 0U))
#define OTP_OTP_NP1_VAL_OTP_NP1_M           GENMASK(3U, 0U)
#define OTP_OTP_NP1_VAL_OTP_NP1_X(x)        ((x) & GENMASK(3U, 0U))

/*      OTP:OTP_REGS:OTP_NP2_VAL */
#define OTP_OTP_NP2_VAL(t)        ((t) + 0x118U)

#define OTP_OTP_NP2_VAL_OTP_NP2(x)          ((x) & GENMASK(3U, 0U))
#define OTP_OTP_NP2_VAL_OTP_NP2_M           GENMASK(3U, 0U)
#define OTP_OTP_NP2_VAL_OTP_NP2_X(x)        ((x) & GENMASK(3U, 0U))

/*      OTP:OTP_REGS:OTP_READ_PROTECT0 */
#define OTP_OTP_READ_PROTECT0(t)  ((t) + 0x200U)

#define OTP_OTP_READ_PROTECT0_OTP_READ_PROTECT_7_0(x) ((x) & GENMASK(7U, 0U))
#define OTP_OTP_READ_PROTECT0_OTP_READ_PROTECT_7_0_M GENMASK(7U, 0U)
#define OTP_OTP_READ_PROTECT0_OTP_READ_PROTECT_7_0_X(x) ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_READ_PROTECT1 */
#define OTP_OTP_READ_PROTECT1(t)  ((t) + 0x204U)

#define OTP_OTP_READ_PROTECT1_OTP_READ_PROTECT_15_8(x) ((x) & GENMASK(7U, 0U))
#define OTP_OTP_READ_PROTECT1_OTP_READ_PROTECT_15_8_M GENMASK(7U, 0U)
#define OTP_OTP_READ_PROTECT1_OTP_READ_PROTECT_15_8_X(x) ((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_READ_PROTECT2 */
#define OTP_OTP_READ_PROTECT2(t)  ((t) + 0x208U)

#define OTP_OTP_READ_PROTECT2_OTP_READ_PROTECT_23_16(x) ((x) & GENMASK(7U, 0U))
#define OTP_OTP_READ_PROTECT2_OTP_READ_PROTECT_23_16_M GENMASK(7U, 0U)
#define OTP_OTP_READ_PROTECT2_OTP_READ_PROTECT_23_16_X(x)\
	((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_READ_PROTECT3 */
#define OTP_OTP_READ_PROTECT3(t)  ((t) + 0x20cU)

#define OTP_OTP_READ_PROTECT3_OTP_READ_PROTECT_31_24(x) ((x) & GENMASK(7U, 0U))
#define OTP_OTP_READ_PROTECT3_OTP_READ_PROTECT_31_24_M GENMASK(7U, 0U)
#define OTP_OTP_READ_PROTECT3_OTP_READ_PROTECT_31_24_X(x)\
	((x) & GENMASK(7U, 0U))

/*      OTP:OTP_REGS:OTP_FPGA_PROM_CTL */
#define OTP_OTP_FPGA_PROM_CTL(t)  ((t) + 0x300U)

#define OTP_OTP_FPGA_PROM_CTL_FPGA_OTP_PROM_BUSY(x)\
	(((x) << 3U) & GENMASK(3U, 3U))
#define OTP_OTP_FPGA_PROM_CTL_FPGA_OTP_PROM_BUSY_M GENMASK(3U, 3U)
#define OTP_OTP_FPGA_PROM_CTL_FPGA_OTP_PROM_BUSY_X(x)\
	(((x) & GENMASK(3U, 3U)) >> 3U)

#define OTP_OTP_FPGA_PROM_CTL_FPGA_OTP_CLR_PROM(x)\
	(((x) << 2U) & GENMASK(2U, 2U))
#define OTP_OTP_FPGA_PROM_CTL_FPGA_OTP_CLR_PROM_M GENMASK(2U, 2U)
#define OTP_OTP_FPGA_PROM_CTL_FPGA_OTP_CLR_PROM_X(x)\
	(((x) & GENMASK(2U, 2U)) >> 2U)

#define OTP_OTP_FPGA_PROM_CTL_FPGA_OTP_PROM_ERR_CTL(x) ((x) & GENMASK(1U, 0U))
#define OTP_OTP_FPGA_PROM_CTL_FPGA_OTP_PROM_ERR_CTL_M GENMASK(1U, 0U)
#define OTP_OTP_FPGA_PROM_CTL_FPGA_OTP_PROM_ERR_CTL_X(x) ((x) & GENMASK(1U, 0U))

/*      PCIE_CFG:PCIE:PCIE_CFG */
#define PCIE_CFG_PCIE_CFG(t)      ((t) + 0x04U)

#define PCIE_CFG_PCIE_CFG_REQ_RETRY_ENA(x)  (((x) << 19U) & GENMASK(19U, 19U))
#define PCIE_CFG_PCIE_CFG_REQ_RETRY_ENA_M   GENMASK(19U, 19U)
#define PCIE_CFG_PCIE_CFG_REQ_RETRY_ENA_X(x) (((x) & GENMASK(19U, 19U)) >> 19U)

#define PCIE_CFG_PCIE_CFG_SRIS_MODE(x)      (((x) << 18U) & GENMASK(18U, 18U))
#define PCIE_CFG_PCIE_CFG_SRIS_MODE_M       GENMASK(18U, 18U)
#define PCIE_CFG_PCIE_CFG_SRIS_MODE_X(x)    (((x) & GENMASK(18U, 18U)) >> 18U)

#define PCIE_CFG_PCIE_CFG_LTSSM_ENA(x)      (((x) << 17U) & GENMASK(17U, 17U))
#define PCIE_CFG_PCIE_CFG_LTSSM_ENA_M       GENMASK(17U, 17U)
#define PCIE_CFG_PCIE_CFG_LTSSM_ENA_X(x)    (((x) & GENMASK(17U, 17U)) >> 17U)

#define PCIE_CFG_PCIE_CFG_DBI_RO_WR_DIS(x)  (((x) << 16U) & GENMASK(16U, 16U))
#define PCIE_CFG_PCIE_CFG_DBI_RO_WR_DIS_M   GENMASK(16U, 16U)
#define PCIE_CFG_PCIE_CFG_DBI_RO_WR_DIS_X(x) (((x) & GENMASK(16U, 16U)) >> 16U)

#define PCIE_CFG_PCIE_CFG_HOLD_PHY_RST(x)   (((x) << 15U) & GENMASK(15U, 15U))
#define PCIE_CFG_PCIE_CFG_HOLD_PHY_RST_M    GENMASK(15U, 15U)
#define PCIE_CFG_PCIE_CFG_HOLD_PHY_RST_X(x) (((x) & GENMASK(15U, 15U)) >> 15U)

#define PCIE_CFG_PCIE_CFG_MEM_RING_CORE_ENA(x)\
	(((x) << 14U) & GENMASK(14U, 14U))
#define PCIE_CFG_PCIE_CFG_MEM_RING_CORE_ENA_M GENMASK(14U, 14U)
#define PCIE_CFG_PCIE_CFG_MEM_RING_CORE_ENA_X(x)\
	(((x) & GENMASK(14U, 14U)) >> 14U)

#define PCIE_CFG_PCIE_CFG_MSTR_XFER_PENDING(x)\
	(((x) << 13U) & GENMASK(13U, 13U))
#define PCIE_CFG_PCIE_CFG_MSTR_XFER_PENDING_M GENMASK(13U, 13U)
#define PCIE_CFG_PCIE_CFG_MSTR_XFER_PENDING_X(x)\
	(((x) & GENMASK(13U, 13U)) >> 13U)

#define PCIE_CFG_PCIE_CFG_WAKE_DIS(x)       (((x) << 12U) & GENMASK(12U, 12U))
#define PCIE_CFG_PCIE_CFG_WAKE_DIS_M        GENMASK(12U, 12U)
#define PCIE_CFG_PCIE_CFG_WAKE_DIS_X(x)     (((x) & GENMASK(12U, 12U)) >> 12U)

#define PCIE_CFG_PCIE_CFG_WAKE_POL(x)       (((x) << 11U) & GENMASK(11U, 11U))
#define PCIE_CFG_PCIE_CFG_WAKE_POL_M        GENMASK(11U, 11U)
#define PCIE_CFG_PCIE_CFG_WAKE_POL_X(x)     (((x) & GENMASK(11U, 11U)) >> 11U)

#define PCIE_CFG_PCIE_CFG_WAKE_OE(x)        (((x) << 10U) & GENMASK(10U, 10U))
#define PCIE_CFG_PCIE_CFG_WAKE_OE_M         GENMASK(10U, 10U)
#define PCIE_CFG_PCIE_CFG_WAKE_OE_X(x)      (((x) & GENMASK(10U, 10U)) >> 10U)

#define PCIE_CFG_PCIE_CFG_DBI_ADDR_31_22(x) ((x) & GENMASK(9U, 0U))
#define PCIE_CFG_PCIE_CFG_DBI_ADDR_31_22_M  GENMASK(9U, 0U)
#define PCIE_CFG_PCIE_CFG_DBI_ADDR_31_22_X(x) ((x) & GENMASK(9U, 0U))

/*      PCIE_CFG:PCIE:PCIE_STAT */
#define PCIE_CFG_PCIE_STAT(t)     ((t) + 0x08U)

#define PCIE_CFG_PCIE_STAT_LTSSM_STATE(x)   (((x) << 6U) & GENMASK(11U, 6U))
#define PCIE_CFG_PCIE_STAT_LTSSM_STATE_M    GENMASK(11U, 6U)
#define PCIE_CFG_PCIE_STAT_LTSSM_STATE_X(x) (((x) & GENMASK(11U, 6U)) >> 6U)

#define PCIE_CFG_PCIE_STAT_LINK_STATE(x)    (((x) << 3U) & GENMASK(5U, 3U))
#define PCIE_CFG_PCIE_STAT_LINK_STATE_M     GENMASK(5U, 3U)
#define PCIE_CFG_PCIE_STAT_LINK_STATE_X(x)  (((x) & GENMASK(5U, 3U)) >> 3U)

#define PCIE_CFG_PCIE_STAT_PM_STATE(x)      ((x) & GENMASK(2U, 0U))
#define PCIE_CFG_PCIE_STAT_PM_STATE_M       GENMASK(2U, 0U)
#define PCIE_CFG_PCIE_STAT_PM_STATE_X(x)    ((x) & GENMASK(2U, 0U))

/*      PCIE_DBI:PF0_TYPE0_HDR:DEVICE_ID_VENDOR_ID_REG */
#define PCIE_DBI_DEVICE_ID_VENDOR_ID_REG(t) ((t) + 0x00U)

#define PCIE_DBI_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID(x)\
	((x) & GENMASK(15U, 0U))
#define PCIE_DBI_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_M GENMASK(15U, 0U)
#define PCIE_DBI_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_X(x)\
	((x) & GENMASK(15U, 0U))

#define PCIE_DBI_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID(x)\
	(((x) << 16U) & GENMASK(31U, 16U))
#define PCIE_DBI_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_M GENMASK(31U, 16U)
#define PCIE_DBI_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_X(x)\
	(((x) & GENMASK(31U, 16U)) >> 16U)

/*      PCIE_DBI:PF0_TYPE0_HDR:CLASS_CODE_REVISION_ID */
#define PCIE_DBI_CLASS_CODE_REVISION_ID(t) ((t) + 0x08U)

#define PCIE_DBI_CLASS_CODE_REVISION_ID_REVISION_ID(x) ((x) & GENMASK(7U, 0U))
#define PCIE_DBI_CLASS_CODE_REVISION_ID_REVISION_ID_M GENMASK(7U, 0U)
#define PCIE_DBI_CLASS_CODE_REVISION_ID_REVISION_ID_X(x) ((x) & GENMASK(7U, 0U))

#define PCIE_DBI_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE(x)\
	(((x) << 8U) & GENMASK(15U, 8U))
#define PCIE_DBI_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_M GENMASK(15U, 8U)
#define PCIE_DBI_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_X(x)\
	(((x) & GENMASK(15U, 8U)) >> 8U)

#define PCIE_DBI_CLASS_CODE_REVISION_ID_SUBCLASS_CODE(x)\
	(((x) << 16U) & GENMASK(23U, 16U))
#define PCIE_DBI_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_M GENMASK(23U, 16U)
#define PCIE_DBI_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_X(x)\
	(((x) & GENMASK(23U, 16U)) >> 16U)

#define PCIE_DBI_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE(x)\
	(((x) << 24U) & GENMASK(31U, 24U))
#define PCIE_DBI_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_M GENMASK(31U, 24U)
#define PCIE_DBI_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_X(x)\
	(((x) & GENMASK(31U, 24U)) >> 24U)

/*      PCIE_DBI:PF0_TYPE0_HDR:BAR0_REG */
#define PCIE_DBI_BAR0_REG(t)      ((t) + 0x10U)

#define PCIE_DBI_BAR0_REG_BAR0_MEM_IO(x)    ((x) & GENMASK(0U, 0U))
#define PCIE_DBI_BAR0_REG_BAR0_MEM_IO_M     GENMASK(0U, 0U)
#define PCIE_DBI_BAR0_REG_BAR0_MEM_IO_X(x)  ((x) & GENMASK(0U, 0U))

#define PCIE_DBI_BAR0_REG_BAR0_TYPE(x)      (((x) << 1U) & GENMASK(2U, 1U))
#define PCIE_DBI_BAR0_REG_BAR0_TYPE_M       GENMASK(2U, 1U)
#define PCIE_DBI_BAR0_REG_BAR0_TYPE_X(x)    (((x) & GENMASK(2U, 1U)) >> 1U)

#define PCIE_DBI_BAR0_REG_BAR0_PREFETCH(x)  (((x) << 3U) & GENMASK(3U, 3U))
#define PCIE_DBI_BAR0_REG_BAR0_PREFETCH_M   GENMASK(3U, 3U)
#define PCIE_DBI_BAR0_REG_BAR0_PREFETCH_X(x) (((x) & GENMASK(3U, 3U)) >> 3U)

#define PCIE_DBI_BAR0_REG_BAR0_START(x)     (((x) << 4U) & GENMASK(31U, 4U))
#define PCIE_DBI_BAR0_REG_BAR0_START_M      GENMASK(31U, 4U)
#define PCIE_DBI_BAR0_REG_BAR0_START_X(x)   (((x) & GENMASK(31U, 4U)) >> 4U)

/*      PCIE_DBI:PF0_TYPE0_HDR:BAR1_REG */
#define PCIE_DBI_BAR1_REG(t)      ((t) + 0x14U)

#define PCIE_DBI_BAR1_REG_BAR1_MEM_IO(x)    ((x) & GENMASK(0U, 0U))
#define PCIE_DBI_BAR1_REG_BAR1_MEM_IO_M     GENMASK(0U, 0U)
#define PCIE_DBI_BAR1_REG_BAR1_MEM_IO_X(x)  ((x) & GENMASK(0U, 0U))

#define PCIE_DBI_BAR1_REG_BAR1_TYPE(x)      (((x) << 1U) & GENMASK(2U, 1U))
#define PCIE_DBI_BAR1_REG_BAR1_TYPE_M       GENMASK(2U, 1U)
#define PCIE_DBI_BAR1_REG_BAR1_TYPE_X(x)    (((x) & GENMASK(2U, 1U)) >> 1U)

#define PCIE_DBI_BAR1_REG_BAR1_PREFETCH(x)  (((x) << 3U) & GENMASK(3U, 3U))
#define PCIE_DBI_BAR1_REG_BAR1_PREFETCH_M   GENMASK(3U, 3U)
#define PCIE_DBI_BAR1_REG_BAR1_PREFETCH_X(x) (((x) & GENMASK(3U, 3U)) >> 3U)

#define PCIE_DBI_BAR1_REG_BAR1_START(x)     (((x) << 4U) & GENMASK(31U, 4U))
#define PCIE_DBI_BAR1_REG_BAR1_START_M      GENMASK(31U, 4U)
#define PCIE_DBI_BAR1_REG_BAR1_START_X(x)   (((x) & GENMASK(31U, 4U)) >> 4U)

/*      PCIE_DBI:PF0_TYPE0_HDR:BAR2_REG */
#define PCIE_DBI_BAR2_REG(t)      ((t) + 0x18U)

#define PCIE_DBI_BAR2_REG_BAR2_MEM_IO(x)    ((x) & GENMASK(0U, 0U))
#define PCIE_DBI_BAR2_REG_BAR2_MEM_IO_M     GENMASK(0U, 0U)
#define PCIE_DBI_BAR2_REG_BAR2_MEM_IO_X(x)  ((x) & GENMASK(0U, 0U))

#define PCIE_DBI_BAR2_REG_BAR2_TYPE(x)      (((x) << 1U) & GENMASK(2U, 1U))
#define PCIE_DBI_BAR2_REG_BAR2_TYPE_M       GENMASK(2U, 1U)
#define PCIE_DBI_BAR2_REG_BAR2_TYPE_X(x)    (((x) & GENMASK(2U, 1U)) >> 1U)

#define PCIE_DBI_BAR2_REG_BAR2_PREFETCH(x)  (((x) << 3U) & GENMASK(3U, 3U))
#define PCIE_DBI_BAR2_REG_BAR2_PREFETCH_M   GENMASK(3U, 3U)
#define PCIE_DBI_BAR2_REG_BAR2_PREFETCH_X(x) (((x) & GENMASK(3U, 3U)) >> 3U)

#define PCIE_DBI_BAR2_REG_BAR2_START(x)     (((x) << 4U) & GENMASK(31U, 4U))
#define PCIE_DBI_BAR2_REG_BAR2_START_M      GENMASK(31U, 4U)
#define PCIE_DBI_BAR2_REG_BAR2_START_X(x)   (((x) & GENMASK(31U, 4U)) >> 4U)

/*      PCIE_DBI:PF0_TYPE0_HDR:BAR3_REG */
#define PCIE_DBI_BAR3_REG(t)      ((t) + 0x1cU)

#define PCIE_DBI_BAR3_REG_BAR3_MEM_IO(x)    ((x) & GENMASK(0U, 0U))
#define PCIE_DBI_BAR3_REG_BAR3_MEM_IO_M     GENMASK(0U, 0U)
#define PCIE_DBI_BAR3_REG_BAR3_MEM_IO_X(x)  ((x) & GENMASK(0U, 0U))

#define PCIE_DBI_BAR3_REG_BAR3_TYPE(x)      (((x) << 1U) & GENMASK(2U, 1U))
#define PCIE_DBI_BAR3_REG_BAR3_TYPE_M       GENMASK(2U, 1U)
#define PCIE_DBI_BAR3_REG_BAR3_TYPE_X(x)    (((x) & GENMASK(2U, 1U)) >> 1U)

#define PCIE_DBI_BAR3_REG_BAR3_PREFETCH(x)  (((x) << 3U) & GENMASK(3U, 3U))
#define PCIE_DBI_BAR3_REG_BAR3_PREFETCH_M   GENMASK(3U, 3U)
#define PCIE_DBI_BAR3_REG_BAR3_PREFETCH_X(x) (((x) & GENMASK(3U, 3U)) >> 3U)

#define PCIE_DBI_BAR3_REG_BAR3_START(x)     (((x) << 4U) & GENMASK(31U, 4U))
#define PCIE_DBI_BAR3_REG_BAR3_START_M      GENMASK(31U, 4U)
#define PCIE_DBI_BAR3_REG_BAR3_START_X(x)   (((x) & GENMASK(31U, 4U)) >> 4U)

/*      PCIE_DBI:PF0_TYPE0_HDR:BAR4_REG */
#define PCIE_DBI_BAR4_REG(t)      ((t) + 0x20U)

#define PCIE_DBI_BAR4_REG_BAR4_MEM_IO(x)    ((x) & GENMASK(0U, 0U))
#define PCIE_DBI_BAR4_REG_BAR4_MEM_IO_M     GENMASK(0U, 0U)
#define PCIE_DBI_BAR4_REG_BAR4_MEM_IO_X(x)  ((x) & GENMASK(0U, 0U))

#define PCIE_DBI_BAR4_REG_BAR4_TYPE(x)      (((x) << 1U) & GENMASK(2U, 1U))
#define PCIE_DBI_BAR4_REG_BAR4_TYPE_M       GENMASK(2U, 1U)
#define PCIE_DBI_BAR4_REG_BAR4_TYPE_X(x)    (((x) & GENMASK(2U, 1U)) >> 1U)

#define PCIE_DBI_BAR4_REG_BAR4_PREFETCH(x)  (((x) << 3U) & GENMASK(3U, 3U))
#define PCIE_DBI_BAR4_REG_BAR4_PREFETCH_M   GENMASK(3U, 3U)
#define PCIE_DBI_BAR4_REG_BAR4_PREFETCH_X(x) (((x) & GENMASK(3U, 3U)) >> 3U)

#define PCIE_DBI_BAR4_REG_BAR4_START(x)     (((x) << 4U) & GENMASK(31U, 4U))
#define PCIE_DBI_BAR4_REG_BAR4_START_M      GENMASK(31U, 4U)
#define PCIE_DBI_BAR4_REG_BAR4_START_X(x)   (((x) & GENMASK(31U, 4U)) >> 4U)

/*      PCIE_DBI:PF0_TYPE0_HDR:BAR5_REG */
#define PCIE_DBI_BAR5_REG(t)      ((t) + 0x24U)

#define PCIE_DBI_BAR5_REG_BAR5_MEM_IO(x)    ((x) & GENMASK(0U, 0U))
#define PCIE_DBI_BAR5_REG_BAR5_MEM_IO_M     GENMASK(0U, 0U)
#define PCIE_DBI_BAR5_REG_BAR5_MEM_IO_X(x)  ((x) & GENMASK(0U, 0U))

#define PCIE_DBI_BAR5_REG_BAR5_TYPE(x)      (((x) << 1U) & GENMASK(2U, 1U))
#define PCIE_DBI_BAR5_REG_BAR5_TYPE_M       GENMASK(2U, 1U)
#define PCIE_DBI_BAR5_REG_BAR5_TYPE_X(x)    (((x) & GENMASK(2U, 1U)) >> 1U)

#define PCIE_DBI_BAR5_REG_BAR5_PREFETCH(x)  (((x) << 3U) & GENMASK(3U, 3U))
#define PCIE_DBI_BAR5_REG_BAR5_PREFETCH_M   GENMASK(3U, 3U)
#define PCIE_DBI_BAR5_REG_BAR5_PREFETCH_X(x) (((x) & GENMASK(3U, 3U)) >> 3U)

#define PCIE_DBI_BAR5_REG_BAR5_START(x)     (((x) << 4U) & GENMASK(31U, 4U))
#define PCIE_DBI_BAR5_REG_BAR5_START_M      GENMASK(31U, 4U)
#define PCIE_DBI_BAR5_REG_BAR5_START_X(x)   (((x) & GENMASK(31U, 4U)) >> 4U)

/*      PCIE_DBI:PF0_TYPE0_HDR:SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG */
#define PCIE_DBI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG(t) ((t) + 0x2cU)

#define PCIE_DBI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID(x)\
	((x) & GENMASK(15U, 0U))
#define PCIE_DBI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_M\
	GENMASK(15U, 0U)
#define PCIE_DBI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_X(x)\
	((x) & GENMASK(15U, 0U))

#define PCIE_DBI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID(x)\
	(((x) << 16U) & GENMASK(31U, 16U))
#define PCIE_DBI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_M\
	GENMASK(31U, 16U)
#define PCIE_DBI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_X(x)\
	(((x) & GENMASK(31U, 16U)) >> 16U)

/*      PCIE_DBI:PF0_TYPE0_HDR_DBI2:BAR0_MASK_REG */
#define PCIE_DBI_BAR0_MASK_REG(t) ((t) + 0x100010U)

#define PCIE_DBI_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED(x) ((x) & GENMASK(0U, 0U))
#define PCIE_DBI_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_M GENMASK(0U, 0U)
#define PCIE_DBI_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_X(x)\
	((x) & GENMASK(0U, 0U))

#define PCIE_DBI_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK(x)\
	(((x) << 1U) & GENMASK(31U, 1U))
#define PCIE_DBI_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_M GENMASK(31U, 1U)
#define PCIE_DBI_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_X(x)\
	(((x) & GENMASK(31U, 1U)) >> 1U)

/*      PCIE_DBI:PF0_TYPE0_HDR_DBI2:BAR1_MASK_REG */
#define PCIE_DBI_BAR1_MASK_REG(t) ((t) + 0x100014U)

#define PCIE_DBI_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED(x) ((x) & GENMASK(0U, 0U))
#define PCIE_DBI_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_M GENMASK(0U, 0U)
#define PCIE_DBI_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_X(x)\
	((x) & GENMASK(0U, 0U))

#define PCIE_DBI_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK(x)\
	(((x) << 1U) & GENMASK(31U, 1U))
#define PCIE_DBI_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_M GENMASK(31U, 1U)
#define PCIE_DBI_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_X(x)\
	(((x) & GENMASK(31U, 1U)) >> 1U)

/*      PCIE_DBI:PF0_TYPE0_HDR_DBI2:BAR2_MASK_REG */
#define PCIE_DBI_BAR2_MASK_REG(t) ((t) + 0x100018U)

#define PCIE_DBI_BAR2_MASK_REG_PCI_TYPE0_BAR2_ENABLED(x) ((x) & GENMASK(0U, 0U))
#define PCIE_DBI_BAR2_MASK_REG_PCI_TYPE0_BAR2_ENABLED_M GENMASK(0U, 0U)
#define PCIE_DBI_BAR2_MASK_REG_PCI_TYPE0_BAR2_ENABLED_X(x)\
	((x) & GENMASK(0U, 0U))

#define PCIE_DBI_BAR2_MASK_REG_PCI_TYPE0_BAR2_MASK(x)\
	(((x) << 1U) & GENMASK(31U, 1U))
#define PCIE_DBI_BAR2_MASK_REG_PCI_TYPE0_BAR2_MASK_M GENMASK(31U, 1U)
#define PCIE_DBI_BAR2_MASK_REG_PCI_TYPE0_BAR2_MASK_X(x)\
	(((x) & GENMASK(31U, 1U)) >> 1U)

/*      PCIE_DBI:PF0_TYPE0_HDR_DBI2:BAR3_MASK_REG */
#define PCIE_DBI_BAR3_MASK_REG(t) ((t) + 0x10001cU)

#define PCIE_DBI_BAR3_MASK_REG_PCI_TYPE0_BAR3_ENABLED(x) ((x) & GENMASK(0U, 0U))
#define PCIE_DBI_BAR3_MASK_REG_PCI_TYPE0_BAR3_ENABLED_M GENMASK(0U, 0U)
#define PCIE_DBI_BAR3_MASK_REG_PCI_TYPE0_BAR3_ENABLED_X(x)\
	((x) & GENMASK(0U, 0U))

#define PCIE_DBI_BAR3_MASK_REG_PCI_TYPE0_BAR3_MASK(x)\
	(((x) << 1U) & GENMASK(31U, 1U))
#define PCIE_DBI_BAR3_MASK_REG_PCI_TYPE0_BAR3_MASK_M GENMASK(31U, 1U)
#define PCIE_DBI_BAR3_MASK_REG_PCI_TYPE0_BAR3_MASK_X(x)\
	(((x) & GENMASK(31U, 1U)) >> 1U)

/*      PCIE_DBI:PF0_TYPE0_HDR_DBI2:BAR4_MASK_REG */
#define PCIE_DBI_BAR4_MASK_REG(t) ((t) + 0x100020U)

#define PCIE_DBI_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED(x) ((x) & GENMASK(0U, 0U))
#define PCIE_DBI_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_M GENMASK(0U, 0U)
#define PCIE_DBI_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_X(x)\
	((x) & GENMASK(0U, 0U))

#define PCIE_DBI_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK(x)\
	(((x) << 1U) & GENMASK(31U, 1U))
#define PCIE_DBI_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_M GENMASK(31U, 1U)
#define PCIE_DBI_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_X(x)\
	(((x) & GENMASK(31U, 1U)) >> 1U)

/*      PCIE_DBI:PF0_TYPE0_HDR_DBI2:BAR5_MASK_REG */
#define PCIE_DBI_BAR5_MASK_REG(t) ((t) + 0x100024U)

#define PCIE_DBI_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED(x) ((x) & GENMASK(0U, 0U))
#define PCIE_DBI_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_M GENMASK(0U, 0U)
#define PCIE_DBI_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_X(x)\
	((x) & GENMASK(0U, 0U))

#define PCIE_DBI_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK(x)\
	(((x) << 1U) & GENMASK(31U, 1U))
#define PCIE_DBI_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_M GENMASK(31U, 1U)
#define PCIE_DBI_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_X(x)\
	(((x) & GENMASK(31U, 1U)) >> 1U)

/*      PCIE_DBI:PF0_PCIE_CAP:DEVICE_CAPABILITIES_REG */
#define PCIE_DBI_DEVICE_CAPABILITIES_REG(t) ((t) + 0x74U)

#define PCIE_DBI_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE(x)\
	((x) & GENMASK(2U, 0U))
#define PCIE_DBI_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_M\
	GENMASK(2U, 0U)
#define PCIE_DBI_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_X(x)\
	((x) & GENMASK(2U, 0U))

#define PCIE_DBI_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT(x)\
	(((x) << 3U) & GENMASK(4U, 3U))
#define PCIE_DBI_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_M\
	GENMASK(4U, 3U)
#define PCIE_DBI_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_X(x)\
	(((x) & GENMASK(4U, 3U)) >> 3U)

#define PCIE_DBI_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP(x)\
	(((x) << 5U) & GENMASK(5U, 5U))
#define PCIE_DBI_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_M GENMASK(5U, 5U)
#define PCIE_DBI_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_X(x)\
	(((x) & GENMASK(5U, 5U)) >> 5U)

#define PCIE_DBI_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY(x)\
	(((x) << 6U) & GENMASK(8U, 6U))
#define PCIE_DBI_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_M\
	GENMASK(8U, 6U)
#define PCIE_DBI_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_X(x)\
	(((x) & GENMASK(8U, 6U)) >> 6U)

#define PCIE_DBI_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY(x)\
	(((x) << 9U) & GENMASK(11U, 9U))
#define PCIE_DBI_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_M\
	GENMASK(11U, 9U)
#define PCIE_DBI_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_X(x)\
	(((x) & GENMASK(11U, 9U)) >> 9U)

#define PCIE_DBI_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT(x)\
	(((x) << 15U) & GENMASK(15U, 15U))
#define PCIE_DBI_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_M\
	GENMASK(15U, 15U)
#define PCIE_DBI_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_X(x)\
	(((x) & GENMASK(15U, 15U)) >> 15U)

#define PCIE_DBI_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE(x)\
	(((x) << 18U) & GENMASK(25U, 18U))
#define PCIE_DBI_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_M\
	GENMASK(25U, 18U)
#define PCIE_DBI_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_X(x)\
	(((x) & GENMASK(25U, 18U)) >> 18U)

#define PCIE_DBI_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE(x)\
	(((x) << 26U) & GENMASK(27U, 26U))
#define PCIE_DBI_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_M\
	GENMASK(27U, 26U)
#define PCIE_DBI_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_X(x)\
	(((x) & GENMASK(27U, 26U)) >> 26U)

#define PCIE_DBI_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP(x)\
	(((x) << 28U) & GENMASK(28U, 28U))
#define PCIE_DBI_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_M GENMASK(28U, 28U)
#define PCIE_DBI_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_X(x)\
	(((x) & GENMASK(28U, 28U)) >> 28U)

/*      PCIE_DBI:PF0_PCIE_CAP:LINK_CAPABILITIES_REG */
#define PCIE_DBI_LINK_CAPABILITIES_REG(t) ((t) + 0x7cU)

#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED(x)\
	((x) & GENMASK(3U, 0U))
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_M GENMASK(3U, 0U)
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_X(x)\
	((x) & GENMASK(3U, 0U))

#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH(x)\
	(((x) << 4U) & GENMASK(9U, 4U))
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_M GENMASK(9U, 4U)
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_X(x)\
	(((x) & GENMASK(9U, 4U)) >> 4U)

#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT(x)\
	(((x) << 10U) & GENMASK(11U, 10U))
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_M\
	GENMASK(11U, 10U)
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_X(x)\
	(((x) & GENMASK(11U, 10U)) >> 10U)

#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY(x)\
	(((x) << 12U) & GENMASK(14U, 12U))
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_M\
	GENMASK(14U, 12U)
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_X(x)\
	(((x) & GENMASK(14U, 12U)) >> 12U)

#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY(x)\
	(((x) << 15U) & GENMASK(17U, 15U))
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_M\
	GENMASK(17U, 15U)
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_X(x)\
	(((x) & GENMASK(17U, 15U)) >> 15U)

#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN(x)\
	(((x) << 18U) & GENMASK(18U, 18U))
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_M\
	GENMASK(18U, 18U)
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_X(x)\
	(((x) & GENMASK(18U, 18U)) >> 18U)

#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP(x)\
	(((x) << 19U) & GENMASK(19U, 19U))
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_M\
	GENMASK(19U, 19U)
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_X(x)\
	(((x) & GENMASK(19U, 19U)) >> 19U)

#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP(x)\
	(((x) << 20U) & GENMASK(20U, 20U))
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_M\
	GENMASK(20U, 20U)
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_X(x)\
	(((x) & GENMASK(20U, 20U)) >> 20U)

#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP(x)\
	(((x) << 21U) & GENMASK(21U, 21U))
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_M\
	GENMASK(21U, 21U)
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_X(x)\
	(((x) & GENMASK(21U, 21U)) >> 21U)

#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE(x)\
	(((x) << 22U) & GENMASK(22U, 22U))
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_M\
	GENMASK(22U, 22U)
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_X(x)\
	(((x) & GENMASK(22U, 22U)) >> 22U)

#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM(x)\
	(((x) << 24U) & GENMASK(31U, 24U))
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_M GENMASK(31U, 24U)
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_X(x)\
	(((x) & GENMASK(31U, 24U)) >> 24U)

/*      PCIE_DBI:PF0_PCIE_CAP:DEVICE_CAPABILITIES2_REG */
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG(t) ((t) + 0x94U)

#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE(x)\
	((x) & GENMASK(3U, 0U))
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_M\
	GENMASK(3U, 0U)
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_X(x)\
	((x) & GENMASK(3U, 0U))

#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT(x)\
	(((x) << 4U) & GENMASK(4U, 4U))
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_M\
	GENMASK(4U, 4U)
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_X(x)\
	(((x) & GENMASK(4U, 4U)) >> 4U)

#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT(x)\
	(((x) << 5U) & GENMASK(5U, 5U))
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_M\
	GENMASK(5U, 5U)
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_X(x)\
	(((x) & GENMASK(5U, 5U)) >> 5U)

#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP(x)\
	(((x) << 6U) & GENMASK(6U, 6U))
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_M\
	GENMASK(6U, 6U)
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_X(x)\
	(((x) & GENMASK(6U, 6U)) >> 6U)

#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP(x)\
	(((x) << 7U) & GENMASK(7U, 7U))
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_M\
	GENMASK(7U, 7U)
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_X(x)\
	(((x) & GENMASK(7U, 7U)) >> 7U)

#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP(x)\
	(((x) << 8U) & GENMASK(8U, 8U))
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_M\
	GENMASK(8U, 8U)
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_X(x)\
	(((x) & GENMASK(8U, 8U)) >> 8U)

#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP(x)\
	(((x) << 9U) & GENMASK(9U, 9U))
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_M\
	GENMASK(9U, 9U)
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_X(x)\
	(((x) & GENMASK(9U, 9U)) >> 9U)

#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR(x)\
	(((x) << 10U) & GENMASK(10U, 10U))
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_M\
	GENMASK(10U, 10U)
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_X(x)\
	(((x) & GENMASK(10U, 10U)) >> 10U)

#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0(x)\
	(((x) << 12U) & GENMASK(12U, 12U))
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_M\
	GENMASK(12U, 12U)
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_X(x)\
	(((x) & GENMASK(12U, 12U)) >> 12U)

#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1(x)\
	(((x) << 13U) & GENMASK(13U, 13U))
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_M\
	GENMASK(13U, 13U)
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_X(x)\
	(((x) & GENMASK(13U, 13U)) >> 13U)

#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS(x)\
	(((x) << 14U) & GENMASK(15U, 14U))
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_M\
	GENMASK(15U, 14U)
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_X(x)\
	(((x) & GENMASK(15U, 14U)) >> 14U)

#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT(x)\
	(((x) << 16U) & GENMASK(16U, 16U))
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_M\
	GENMASK(16U, 16U)
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_X(x)\
	(((x) & GENMASK(16U, 16U)) >> 16U)

#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT(x)\
	(((x) << 17U) & GENMASK(17U, 17U))
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_M\
	GENMASK(17U, 17U)
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_X(x)\
	(((x) & GENMASK(17U, 17U)) >> 17U)

#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_DMWR_CPL_SUPP(x)\
	(((x) << 28U) & GENMASK(28U, 28U))
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_DMWR_CPL_SUPP_M\
	GENMASK(28U, 28U)
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_DMWR_CPL_SUPP_X(x)\
	(((x) & GENMASK(28U, 28U)) >> 28U)

#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_DMWR_LEN_SUPP(x)\
	(((x) << 29U) & GENMASK(30U, 29U))
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_DMWR_LEN_SUPP_M\
	GENMASK(30U, 29U)
#define PCIE_DBI_DEVICE_CAPABILITIES2_REG_PCIE_CAP_DMWR_LEN_SUPP_X(x)\
	(((x) & GENMASK(30U, 29U)) >> 29U)

/*      PCIE_DBI:PF0_ATU_CAP:IATU_REGION_CTRL_2_OFF_INBOUND_0 */
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0(t) ((t) + 0x300104U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE(x)\
	((x) & GENMASK(7U, 0U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_M\
	GENMASK(7U, 0U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_X(x)\
	((x) & GENMASK(7U, 0U))

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM(x)\
	(((x) << 8U) & GENMASK(10U, 8U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_M\
	GENMASK(10U, 8U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_X(x)\
	(((x) & GENMASK(10U, 8U)) >> 8U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE(x)\
	(((x) << 13U) & GENMASK(13U, 13U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_M\
	GENMASK(13U, 13U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_X(x)\
	(((x) & GENMASK(13U, 13U)) >> 13U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN(x)\
	(((x) << 14U) & GENMASK(14U, 14U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_M\
	GENMASK(14U, 14U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_X(x)\
	(((x) & GENMASK(14U, 14U)) >> 14U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN(x)\
	(((x) << 15U) & GENMASK(15U, 15U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_M\
	GENMASK(15U, 15U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_X(x)\
	(((x) & GENMASK(15U, 15U)) >> 15U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN(x)\
	(((x) << 16U) & GENMASK(16U, 16U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_M\
	GENMASK(16U, 16U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_X(x)\
	(((x) & GENMASK(16U, 16U)) >> 16U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN(x)\
	(((x) << 19U) & GENMASK(19U, 19U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_M\
	GENMASK(19U, 19U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_X(x)\
	(((x) & GENMASK(19U, 19U)) >> 19U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN(x)\
	(((x) << 21U) & GENMASK(21U, 21U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_M\
	GENMASK(21U, 21U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_X(x)\
	(((x) & GENMASK(21U, 21U)) >> 21U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN(x)\
	(((x) << 23U) & GENMASK(23U, 23U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_M\
	GENMASK(23U, 23U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_X(x)\
	(((x) & GENMASK(23U, 23U)) >> 23U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE(x)\
	(((x) << 24U) & GENMASK(25U, 24U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_M\
	GENMASK(25U, 24U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_X(x)\
	(((x) & GENMASK(25U, 24U)) >> 24U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE(x)\
	(((x) << 27U) & GENMASK(27U, 27U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_M\
	GENMASK(27U, 27U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_X(x)\
	(((x) & GENMASK(27U, 27U)) >> 27U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE(x)\
	(((x) << 28U) & GENMASK(28U, 28U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_M\
	GENMASK(28U, 28U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_X(x)\
	(((x) & GENMASK(28U, 28U)) >> 28U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE(x)\
	(((x) << 29U) & GENMASK(29U, 29U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_M\
	GENMASK(29U, 29U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_X(x)\
	(((x) & GENMASK(29U, 29U)) >> 29U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE(x)\
	(((x) << 30U) & GENMASK(30U, 30U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_M\
	GENMASK(30U, 30U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_X(x)\
	(((x) & GENMASK(30U, 30U)) >> 30U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN(x)\
	(((x) << 31U) & GENMASK(31U, 31U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_M\
	GENMASK(31U, 31U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_X(x)\
	(((x) & GENMASK(31U, 31U)) >> 31U)

/*      PCIE_DBI:PF0_ATU_CAP:IATU_LWR_TARGET_ADDR_OFF_INBOUND_0 */
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0(t) ((t) + 0x300114U)

#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW(x)\
	((x) & GENMASK(15U, 0U))
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_M\
	GENMASK(15U, 0U)
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_X(x)\
	((x) & GENMASK(15U, 0U))

#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW(x)\
	(((x) << 16U) & GENMASK(31U, 16U))
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_M\
	GENMASK(31U, 16U)
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_X(x)\
	(((x) & GENMASK(31U, 16U)) >> 16U)

/*      PCIE_DBI:PF0_ATU_CAP:IATU_REGION_CTRL_2_OFF_INBOUND_1 */
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1(t) ((t) + 0x300304U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE(x)\
	((x) & GENMASK(7U, 0U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_M\
	GENMASK(7U, 0U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_X(x)\
	((x) & GENMASK(7U, 0U))

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM(x)\
	(((x) << 8U) & GENMASK(10U, 8U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_M\
	GENMASK(10U, 8U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_X(x)\
	(((x) & GENMASK(10U, 8U)) >> 8U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE(x)\
	(((x) << 13U) & GENMASK(13U, 13U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_M\
	GENMASK(13U, 13U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_X(x)\
	(((x) & GENMASK(13U, 13U)) >> 13U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN(x)\
	(((x) << 14U) & GENMASK(14U, 14U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_M\
	GENMASK(14U, 14U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_X(x)\
	(((x) & GENMASK(14U, 14U)) >> 14U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN(x)\
	(((x) << 15U) & GENMASK(15U, 15U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_M\
	GENMASK(15U, 15U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_X(x)\
	(((x) & GENMASK(15U, 15U)) >> 15U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN(x)\
	(((x) << 16U) & GENMASK(16U, 16U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_M\
	GENMASK(16U, 16U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_X(x)\
	(((x) & GENMASK(16U, 16U)) >> 16U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN(x)\
	(((x) << 19U) & GENMASK(19U, 19U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_M\
	GENMASK(19U, 19U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_X(x)\
	(((x) & GENMASK(19U, 19U)) >> 19U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN(x)\
	(((x) << 21U) & GENMASK(21U, 21U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_M\
	GENMASK(21U, 21U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_X(x)\
	(((x) & GENMASK(21U, 21U)) >> 21U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN(x)\
	(((x) << 23U) & GENMASK(23U, 23U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_M\
	GENMASK(23U, 23U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_X(x)\
	(((x) & GENMASK(23U, 23U)) >> 23U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE(x)\
	(((x) << 24U) & GENMASK(25U, 24U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_M\
	GENMASK(25U, 24U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_X(x)\
	(((x) & GENMASK(25U, 24U)) >> 24U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE(x)\
	(((x) << 27U) & GENMASK(27U, 27U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_M\
	GENMASK(27U, 27U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_X(x)\
	(((x) & GENMASK(27U, 27U)) >> 27U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE(x)\
	(((x) << 28U) & GENMASK(28U, 28U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_M\
	GENMASK(28U, 28U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_X(x)\
	(((x) & GENMASK(28U, 28U)) >> 28U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE(x)\
	(((x) << 29U) & GENMASK(29U, 29U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_M\
	GENMASK(29U, 29U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_X(x)\
	(((x) & GENMASK(29U, 29U)) >> 29U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE(x)\
	(((x) << 30U) & GENMASK(30U, 30U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_M\
	GENMASK(30U, 30U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_X(x)\
	(((x) & GENMASK(30U, 30U)) >> 30U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN(x)\
	(((x) << 31U) & GENMASK(31U, 31U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_M\
	GENMASK(31U, 31U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_X(x)\
	(((x) & GENMASK(31U, 31U)) >> 31U)

/*      PCIE_DBI:PF0_ATU_CAP:IATU_LWR_TARGET_ADDR_OFF_INBOUND_1 */
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1(t) ((t) + 0x300314U)

#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW(x)\
	((x) & GENMASK(15U, 0U))
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_M\
	GENMASK(15U, 0U)
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_X(x)\
	((x) & GENMASK(15U, 0U))

#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW(x)\
	(((x) << 16U) & GENMASK(31U, 16U))
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_M\
	GENMASK(31U, 16U)
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_X(x)\
	(((x) & GENMASK(31U, 16U)) >> 16U)

/*      PCIE_DBI:PF0_ATU_CAP:IATU_REGION_CTRL_2_OFF_INBOUND_2 */
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2(t) ((t) + 0x300504U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE(x)\
	((x) & GENMASK(7U, 0U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_M\
	GENMASK(7U, 0U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_X(x)\
	((x) & GENMASK(7U, 0U))

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM(x)\
	(((x) << 8U) & GENMASK(10U, 8U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_M\
	GENMASK(10U, 8U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_X(x)\
	(((x) & GENMASK(10U, 8U)) >> 8U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE(x)\
	(((x) << 13U) & GENMASK(13U, 13U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_M\
	GENMASK(13U, 13U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_X(x)\
	(((x) & GENMASK(13U, 13U)) >> 13U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN(x)\
	(((x) << 14U) & GENMASK(14U, 14U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_M\
	GENMASK(14U, 14U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_X(x)\
	(((x) & GENMASK(14U, 14U)) >> 14U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN(x)\
	(((x) << 15U) & GENMASK(15U, 15U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_M\
	GENMASK(15U, 15U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_X(x)\
	(((x) & GENMASK(15U, 15U)) >> 15U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN(x)\
	(((x) << 16U) & GENMASK(16U, 16U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_M\
	GENMASK(16U, 16U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_X(x)\
	(((x) & GENMASK(16U, 16U)) >> 16U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN(x)\
	(((x) << 19U) & GENMASK(19U, 19U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_M\
	GENMASK(19U, 19U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_X(x)\
	(((x) & GENMASK(19U, 19U)) >> 19U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN(x)\
	(((x) << 21U) & GENMASK(21U, 21U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_M\
	GENMASK(21U, 21U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_X(x)\
	(((x) & GENMASK(21U, 21U)) >> 21U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN(x)\
	(((x) << 23U) & GENMASK(23U, 23U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_M\
	GENMASK(23U, 23U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_X(x)\
	(((x) & GENMASK(23U, 23U)) >> 23U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE(x)\
	(((x) << 24U) & GENMASK(25U, 24U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_M\
	GENMASK(25U, 24U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_X(x)\
	(((x) & GENMASK(25U, 24U)) >> 24U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE(x)\
	(((x) << 27U) & GENMASK(27U, 27U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_M\
	GENMASK(27U, 27U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_X(x)\
	(((x) & GENMASK(27U, 27U)) >> 27U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE(x)\
	(((x) << 28U) & GENMASK(28U, 28U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_M\
	GENMASK(28U, 28U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_X(x)\
	(((x) & GENMASK(28U, 28U)) >> 28U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE(x)\
	(((x) << 29U) & GENMASK(29U, 29U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_M\
	GENMASK(29U, 29U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_X(x)\
	(((x) & GENMASK(29U, 29U)) >> 29U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE(x)\
	(((x) << 30U) & GENMASK(30U, 30U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_M\
	GENMASK(30U, 30U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_X(x)\
	(((x) & GENMASK(30U, 30U)) >> 30U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN(x)\
	(((x) << 31U) & GENMASK(31U, 31U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_M\
	GENMASK(31U, 31U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_X(x)\
	(((x) & GENMASK(31U, 31U)) >> 31U)

/*      PCIE_DBI:PF0_ATU_CAP:IATU_LWR_TARGET_ADDR_OFF_INBOUND_2 */
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2(t) ((t) + 0x300514U)

#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW(x)\
	((x) & GENMASK(15U, 0U))
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_M\
	GENMASK(15U, 0U)
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_X(x)\
	((x) & GENMASK(15U, 0U))

#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW(x)\
	(((x) << 16U) & GENMASK(31U, 16U))
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_M\
	GENMASK(31U, 16U)
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_X(x)\
	(((x) & GENMASK(31U, 16U)) >> 16U)

/*      PCIE_DBI:PF0_ATU_CAP:IATU_REGION_CTRL_2_OFF_INBOUND_3 */
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3(t) ((t) + 0x300704U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE(x)\
	((x) & GENMASK(7U, 0U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_M\
	GENMASK(7U, 0U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_X(x)\
	((x) & GENMASK(7U, 0U))

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM(x)\
	(((x) << 8U) & GENMASK(10U, 8U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_M\
	GENMASK(10U, 8U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_X(x)\
	(((x) & GENMASK(10U, 8U)) >> 8U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE(x)\
	(((x) << 13U) & GENMASK(13U, 13U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_M\
	GENMASK(13U, 13U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_X(x)\
	(((x) & GENMASK(13U, 13U)) >> 13U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN(x)\
	(((x) << 14U) & GENMASK(14U, 14U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_M\
	GENMASK(14U, 14U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_X(x)\
	(((x) & GENMASK(14U, 14U)) >> 14U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN(x)\
	(((x) << 15U) & GENMASK(15U, 15U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_M\
	GENMASK(15U, 15U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_X(x)\
	(((x) & GENMASK(15U, 15U)) >> 15U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN(x)\
	(((x) << 16U) & GENMASK(16U, 16U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_M\
	GENMASK(16U, 16U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_X(x)\
	(((x) & GENMASK(16U, 16U)) >> 16U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN(x)\
	(((x) << 19U) & GENMASK(19U, 19U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_M\
	GENMASK(19U, 19U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_X(x)\
	(((x) & GENMASK(19U, 19U)) >> 19U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN(x)\
	(((x) << 21U) & GENMASK(21U, 21U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_M\
	GENMASK(21U, 21U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_X(x)\
	(((x) & GENMASK(21U, 21U)) >> 21U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN(x)\
	(((x) << 23U) & GENMASK(23U, 23U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_M\
	GENMASK(23U, 23U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_X(x)\
	(((x) & GENMASK(23U, 23U)) >> 23U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE(x)\
	(((x) << 24U) & GENMASK(25U, 24U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_M\
	GENMASK(25U, 24U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_X(x)\
	(((x) & GENMASK(25U, 24U)) >> 24U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE(x)\
	(((x) << 27U) & GENMASK(27U, 27U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_M\
	GENMASK(27U, 27U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_X(x)\
	(((x) & GENMASK(27U, 27U)) >> 27U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE(x)\
	(((x) << 28U) & GENMASK(28U, 28U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_M\
	GENMASK(28U, 28U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_X(x)\
	(((x) & GENMASK(28U, 28U)) >> 28U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE(x)\
	(((x) << 29U) & GENMASK(29U, 29U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_M\
	GENMASK(29U, 29U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_X(x)\
	(((x) & GENMASK(29U, 29U)) >> 29U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE(x)\
	(((x) << 30U) & GENMASK(30U, 30U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_M\
	GENMASK(30U, 30U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_X(x)\
	(((x) & GENMASK(30U, 30U)) >> 30U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN(x)\
	(((x) << 31U) & GENMASK(31U, 31U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_M\
	GENMASK(31U, 31U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_X(x)\
	(((x) & GENMASK(31U, 31U)) >> 31U)

/*      PCIE_DBI:PF0_ATU_CAP:IATU_LWR_TARGET_ADDR_OFF_INBOUND_3 */
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3(t) ((t) + 0x300714U)

#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW(x)\
	((x) & GENMASK(15U, 0U))
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_M\
	GENMASK(15U, 0U)
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_X(x)\
	((x) & GENMASK(15U, 0U))

#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW(x)\
	(((x) << 16U) & GENMASK(31U, 16U))
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_M\
	GENMASK(31U, 16U)
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_X(x)\
	(((x) & GENMASK(31U, 16U)) >> 16U)

/*      PCIE_DBI:PF0_ATU_CAP:IATU_REGION_CTRL_2_OFF_INBOUND_4 */
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4(t) ((t) + 0x300904U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE(x)\
	((x) & GENMASK(7U, 0U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_M\
	GENMASK(7U, 0U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_X(x)\
	((x) & GENMASK(7U, 0U))

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM(x)\
	(((x) << 8U) & GENMASK(10U, 8U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_M\
	GENMASK(10U, 8U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_X(x)\
	(((x) & GENMASK(10U, 8U)) >> 8U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE(x)\
	(((x) << 13U) & GENMASK(13U, 13U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_M\
	GENMASK(13U, 13U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_X(x)\
	(((x) & GENMASK(13U, 13U)) >> 13U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN(x)\
	(((x) << 14U) & GENMASK(14U, 14U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_M\
	GENMASK(14U, 14U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_X(x)\
	(((x) & GENMASK(14U, 14U)) >> 14U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN(x)\
	(((x) << 15U) & GENMASK(15U, 15U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_M\
	GENMASK(15U, 15U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_X(x)\
	(((x) & GENMASK(15U, 15U)) >> 15U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN(x)\
	(((x) << 16U) & GENMASK(16U, 16U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_M\
	GENMASK(16U, 16U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_X(x)\
	(((x) & GENMASK(16U, 16U)) >> 16U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN(x)\
	(((x) << 19U) & GENMASK(19U, 19U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_M\
	GENMASK(19U, 19U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_X(x)\
	(((x) & GENMASK(19U, 19U)) >> 19U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN(x)\
	(((x) << 21U) & GENMASK(21U, 21U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_M\
	GENMASK(21U, 21U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_X(x)\
	(((x) & GENMASK(21U, 21U)) >> 21U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN(x)\
	(((x) << 23U) & GENMASK(23U, 23U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_M\
	GENMASK(23U, 23U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_X(x)\
	(((x) & GENMASK(23U, 23U)) >> 23U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE(x)\
	(((x) << 24U) & GENMASK(25U, 24U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_M\
	GENMASK(25U, 24U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_X(x)\
	(((x) & GENMASK(25U, 24U)) >> 24U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE(x)\
	(((x) << 27U) & GENMASK(27U, 27U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_M\
	GENMASK(27U, 27U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_X(x)\
	(((x) & GENMASK(27U, 27U)) >> 27U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE(x)\
	(((x) << 28U) & GENMASK(28U, 28U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_M\
	GENMASK(28U, 28U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_X(x)\
	(((x) & GENMASK(28U, 28U)) >> 28U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE(x)\
	(((x) << 29U) & GENMASK(29U, 29U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_M\
	GENMASK(29U, 29U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_X(x)\
	(((x) & GENMASK(29U, 29U)) >> 29U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE(x)\
	(((x) << 30U) & GENMASK(30U, 30U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_M\
	GENMASK(30U, 30U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_X(x)\
	(((x) & GENMASK(30U, 30U)) >> 30U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN(x)\
	(((x) << 31U) & GENMASK(31U, 31U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_M\
	GENMASK(31U, 31U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_X(x)\
	(((x) & GENMASK(31U, 31U)) >> 31U)

/*      PCIE_DBI:PF0_ATU_CAP:IATU_LWR_TARGET_ADDR_OFF_INBOUND_4 */
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4(t) ((t) + 0x300914U)

#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW(x)\
	((x) & GENMASK(15U, 0U))
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_M\
	GENMASK(15U, 0U)
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_X(x)\
	((x) & GENMASK(15U, 0U))

#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW(x)\
	(((x) << 16U) & GENMASK(31U, 16U))
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_M\
	GENMASK(31U, 16U)
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_X(x)\
	(((x) & GENMASK(31U, 16U)) >> 16U)

/*      PCIE_DBI:PF0_ATU_CAP:IATU_REGION_CTRL_2_OFF_INBOUND_5 */
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5(t) ((t) + 0x300b04U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE(x)\
	((x) & GENMASK(7U, 0U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_M\
	GENMASK(7U, 0U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_X(x)\
	((x) & GENMASK(7U, 0U))

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM(x)\
	(((x) << 8U) & GENMASK(10U, 8U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_M\
	GENMASK(10U, 8U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_X(x)\
	(((x) & GENMASK(10U, 8U)) >> 8U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE(x)\
	(((x) << 13U) & GENMASK(13U, 13U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_M\
	GENMASK(13U, 13U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_X(x)\
	(((x) & GENMASK(13U, 13U)) >> 13U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN(x)\
	(((x) << 14U) & GENMASK(14U, 14U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_M\
	GENMASK(14U, 14U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_X(x)\
	(((x) & GENMASK(14U, 14U)) >> 14U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN(x)\
	(((x) << 15U) & GENMASK(15U, 15U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_M\
	GENMASK(15U, 15U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_X(x)\
	(((x) & GENMASK(15U, 15U)) >> 15U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN(x)\
	(((x) << 16U) & GENMASK(16U, 16U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_M\
	GENMASK(16U, 16U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_X(x)\
	(((x) & GENMASK(16U, 16U)) >> 16U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN(x)\
	(((x) << 19U) & GENMASK(19U, 19U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_M\
	GENMASK(19U, 19U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_X(x)\
	(((x) & GENMASK(19U, 19U)) >> 19U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN(x)\
	(((x) << 21U) & GENMASK(21U, 21U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_M\
	GENMASK(21U, 21U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_X(x)\
	(((x) & GENMASK(21U, 21U)) >> 21U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN(x)\
	(((x) << 23U) & GENMASK(23U, 23U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_M\
	GENMASK(23U, 23U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_X(x)\
	(((x) & GENMASK(23U, 23U)) >> 23U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE(x)\
	(((x) << 24U) & GENMASK(25U, 24U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_M\
	GENMASK(25U, 24U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_X(x)\
	(((x) & GENMASK(25U, 24U)) >> 24U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE(x)\
	(((x) << 27U) & GENMASK(27U, 27U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_M\
	GENMASK(27U, 27U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_X(x)\
	(((x) & GENMASK(27U, 27U)) >> 27U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE(x)\
	(((x) << 28U) & GENMASK(28U, 28U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_M\
	GENMASK(28U, 28U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_X(x)\
	(((x) & GENMASK(28U, 28U)) >> 28U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE(x)\
	(((x) << 29U) & GENMASK(29U, 29U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_M\
	GENMASK(29U, 29U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_X(x)\
	(((x) & GENMASK(29U, 29U)) >> 29U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE(x)\
	(((x) << 30U) & GENMASK(30U, 30U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_M\
	GENMASK(30U, 30U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_X(x)\
	(((x) & GENMASK(30U, 30U)) >> 30U)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN(x)\
	(((x) << 31U) & GENMASK(31U, 31U))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_M\
	GENMASK(31U, 31U)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_X(x)\
	(((x) & GENMASK(31U, 31U)) >> 31U)

/*      PCIE_DBI:PF0_ATU_CAP:IATU_LWR_TARGET_ADDR_OFF_INBOUND_5 */
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5(t) ((t) + 0x300b14U)

#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW(x)\
	((x) & GENMASK(15U, 0U))
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_M\
	GENMASK(15U, 0U)
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_X(x)\
	((x) & GENMASK(15U, 0U))

#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW(x)\
	(((x) << 16U) & GENMASK(31U, 16U))
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_M\
	GENMASK(31U, 16U)
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_X(x)\
	(((x) & GENMASK(31U, 16U)) >> 16U)

/*      PCIE_DBI:PF0_PORT_LOGIC:MISC_CONTROL_1_OFF */
#define PCIE_DBI_MISC_CONTROL_1_OFF(t) ((t) + 0x8bcU)

#define PCIE_DBI_MISC_CONTROL_1_OFF_DBI_RO_WR_EN(x) ((x) & GENMASK(0U, 0U))
#define PCIE_DBI_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_M GENMASK(0U, 0U)
#define PCIE_DBI_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_X(x) ((x) & GENMASK(0U, 0U))

#define PCIE_DBI_MISC_CONTROL_1_OFF_DEFAULT_TARGET(x)\
	(((x) << 1U) & GENMASK(1U, 1U))
#define PCIE_DBI_MISC_CONTROL_1_OFF_DEFAULT_TARGET_M GENMASK(1U, 1U)
#define PCIE_DBI_MISC_CONTROL_1_OFF_DEFAULT_TARGET_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

#define PCIE_DBI_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1(x)\
	(((x) << 2U) & GENMASK(2U, 2U))
#define PCIE_DBI_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_M GENMASK(2U, 2U)
#define PCIE_DBI_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_X(x)\
	(((x) & GENMASK(2U, 2U)) >> 2U)

#define PCIE_DBI_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER(x)\
	(((x) << 3U) & GENMASK(3U, 3U))
#define PCIE_DBI_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_M GENMASK(3U, 3U)
#define PCIE_DBI_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_X(x)\
	(((x) & GENMASK(3U, 3U)) >> 3U)

#define PCIE_DBI_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER(x)\
	(((x) << 5U) & GENMASK(5U, 5U))
#define PCIE_DBI_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_M GENMASK(5U, 5U)
#define PCIE_DBI_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_X(x)\
	(((x) & GENMASK(5U, 5U)) >> 5U)

#define PCIE_DBI_MISC_CONTROL_1_OFF_CPLQ_MNG_EN(x)\
	(((x) << 6U) & GENMASK(6U, 6U))
#define PCIE_DBI_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_M GENMASK(6U, 6U)
#define PCIE_DBI_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_X(x)\
	(((x) & GENMASK(6U, 6U)) >> 6U)

#define PCIE_DBI_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG(x)\
	(((x) << 7U) & GENMASK(7U, 7U))
#define PCIE_DBI_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_M GENMASK(7U, 7U)
#define PCIE_DBI_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_X(x)\
	(((x) & GENMASK(7U, 7U)) >> 7U)

#define PCIE_DBI_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG(x)\
	(((x) << 8U) & GENMASK(17U, 8U))
#define PCIE_DBI_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_M GENMASK(17U, 8U)
#define PCIE_DBI_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_X(x)\
	(((x) & GENMASK(17U, 8U)) >> 8U)

#define PCIE_DBI_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG(x)\
	(((x) << 18U) & GENMASK(19U, 18U))
#define PCIE_DBI_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_M\
	GENMASK(19U, 18U)
#define PCIE_DBI_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_X(x)\
	(((x) & GENMASK(19U, 18U)) >> 18U)

#define PCIE_DBI_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG(x)\
	(((x) << 20U) & GENMASK(20U, 20U))
#define PCIE_DBI_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_M GENMASK(20U, 20U)
#define PCIE_DBI_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_X(x)\
	(((x) & GENMASK(20U, 20U)) >> 20U)

#define PCIE_DBI_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL(x)\
	(((x) << 21U) & GENMASK(21U, 21U))
#define PCIE_DBI_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_M GENMASK(21U, 21U)
#define PCIE_DBI_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_X(x)\
	(((x) & GENMASK(21U, 21U)) >> 21U)

#define PCIE_DBI_MISC_CONTROL_1_OFF_PORT_LOGIC_WR_DISABLE(x)\
	(((x) << 22U) & GENMASK(22U, 22U))
#define PCIE_DBI_MISC_CONTROL_1_OFF_PORT_LOGIC_WR_DISABLE_M GENMASK(22U, 22U)
#define PCIE_DBI_MISC_CONTROL_1_OFF_PORT_LOGIC_WR_DISABLE_X(x)\
	(((x) & GENMASK(22U, 22U)) >> 22U)

/*      PCIE_PHY_PCS:PHY_LINK_GRP_1:PHY_LINK_04 */
#define PCIE_PHY_PCS_PHY_LINK_04(t) ((t) + 0x10U)

#define PCIE_PHY_PCS_PHY_LINK_04_R_EN_PRE_EMPH_G1(x) ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PCS_PHY_LINK_04_R_EN_PRE_EMPH_G1_M GENMASK(0U, 0U)
#define PCIE_PHY_PCS_PHY_LINK_04_R_EN_PRE_EMPH_G1_X(x) ((x) & GENMASK(0U, 0U))

#define PCIE_PHY_PCS_PHY_LINK_04_R_EN_PRE_EMPH_G2(x)\
	(((x) << 16U) & GENMASK(16U, 16U))
#define PCIE_PHY_PCS_PHY_LINK_04_R_EN_PRE_EMPH_G2_M GENMASK(16U, 16U)
#define PCIE_PHY_PCS_PHY_LINK_04_R_EN_PRE_EMPH_G2_X(x)\
	(((x) & GENMASK(16U, 16U)) >> 16U)

/*      PCIE_PHY_PCS:PHY_LINK_GRP_1:PHY_LINK_05 */
#define PCIE_PHY_PCS_PHY_LINK_05(t) ((t) + 0x14U)

#define PCIE_PHY_PCS_PHY_LINK_05_R_EN_PRE_EMPH_G3(x) ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PCS_PHY_LINK_05_R_EN_PRE_EMPH_G3_M GENMASK(0U, 0U)
#define PCIE_PHY_PCS_PHY_LINK_05_R_EN_PRE_EMPH_G3_X(x) ((x) & GENMASK(0U, 0U))

#define PCIE_PHY_PCS_PHY_LINK_05_R_EN_PRE_EMPH_G4(x)\
	(((x) << 16U) & GENMASK(16U, 16U))
#define PCIE_PHY_PCS_PHY_LINK_05_R_EN_PRE_EMPH_G4_M GENMASK(16U, 16U)
#define PCIE_PHY_PCS_PHY_LINK_05_R_EN_PRE_EMPH_G4_X(x)\
	(((x) & GENMASK(16U, 16U)) >> 16U)

/*      PCIE_PHY_PCS:PHY_LINK_GRP_6:PHY_LINK_2C */
#define PCIE_PHY_PCS_PHY_LINK_2C(t) ((t) + 0xb0U)

#define PCIE_PHY_PCS_PHY_LINK_2C_R_TXMARGIN_0_B7_B0(x) ((x) & GENMASK(7U, 0U))
#define PCIE_PHY_PCS_PHY_LINK_2C_R_TXMARGIN_0_B7_B0_M GENMASK(7U, 0U)
#define PCIE_PHY_PCS_PHY_LINK_2C_R_TXMARGIN_0_B7_B0_X(x) ((x) & GENMASK(7U, 0U))

#define PCIE_PHY_PCS_PHY_LINK_2C_R_TXMARGIN_0_B8(x)\
	(((x) << 8U) & GENMASK(8U, 8U))
#define PCIE_PHY_PCS_PHY_LINK_2C_R_TXMARGIN_0_B8_M GENMASK(8U, 8U)
#define PCIE_PHY_PCS_PHY_LINK_2C_R_TXMARGIN_0_B8_X(x)\
	(((x) & GENMASK(8U, 8U)) >> 8U)

#define PCIE_PHY_PCS_PHY_LINK_2C_R_TXMARGIN_1_B7_B0(x)\
	(((x) << 16U) & GENMASK(23U, 16U))
#define PCIE_PHY_PCS_PHY_LINK_2C_R_TXMARGIN_1_B7_B0_M GENMASK(23U, 16U)
#define PCIE_PHY_PCS_PHY_LINK_2C_R_TXMARGIN_1_B7_B0_X(x)\
	(((x) & GENMASK(23U, 16U)) >> 16U)

#define PCIE_PHY_PCS_PHY_LINK_2C_R_TXMARGIN_1_B8(x)\
	(((x) << 24U) & GENMASK(24U, 24U))
#define PCIE_PHY_PCS_PHY_LINK_2C_R_TXMARGIN_1_B8_M GENMASK(24U, 24U)
#define PCIE_PHY_PCS_PHY_LINK_2C_R_TXMARGIN_1_B8_X(x)\
	(((x) & GENMASK(24U, 24U)) >> 24U)

/*      PCIE_PHY_PCS:PHY_LINK_GRP_6:PHY_LINK_2D */
#define PCIE_PHY_PCS_PHY_LINK_2D(t) ((t) + 0xb4U)

#define PCIE_PHY_PCS_PHY_LINK_2D_R_TXMARGIN_2_B7_B0(x) ((x) & GENMASK(7U, 0U))
#define PCIE_PHY_PCS_PHY_LINK_2D_R_TXMARGIN_2_B7_B0_M GENMASK(7U, 0U)
#define PCIE_PHY_PCS_PHY_LINK_2D_R_TXMARGIN_2_B7_B0_X(x) ((x) & GENMASK(7U, 0U))

#define PCIE_PHY_PCS_PHY_LINK_2D_R_TXMARGIN_2_B8(x)\
	(((x) << 8U) & GENMASK(8U, 8U))
#define PCIE_PHY_PCS_PHY_LINK_2D_R_TXMARGIN_2_B8_M GENMASK(8U, 8U)
#define PCIE_PHY_PCS_PHY_LINK_2D_R_TXMARGIN_2_B8_X(x)\
	(((x) & GENMASK(8U, 8U)) >> 8U)

#define PCIE_PHY_PCS_PHY_LINK_2D_R_TXMARGIN_3_B7_B0(x)\
	(((x) << 16U) & GENMASK(23U, 16U))
#define PCIE_PHY_PCS_PHY_LINK_2D_R_TXMARGIN_3_B7_B0_M GENMASK(23U, 16U)
#define PCIE_PHY_PCS_PHY_LINK_2D_R_TXMARGIN_3_B7_B0_X(x)\
	(((x) & GENMASK(23U, 16U)) >> 16U)

#define PCIE_PHY_PCS_PHY_LINK_2D_R_TXMARGIN_3_B8(x)\
	(((x) << 24U) & GENMASK(24U, 24U))
#define PCIE_PHY_PCS_PHY_LINK_2D_R_TXMARGIN_3_B8_M GENMASK(24U, 24U)
#define PCIE_PHY_PCS_PHY_LINK_2D_R_TXMARGIN_3_B8_X(x)\
	(((x) & GENMASK(24U, 24U)) >> 24U)

/*      PCIE_PHY_PCS:PHY_LINK_GRP_6:PHY_LINK_2E */
#define PCIE_PHY_PCS_PHY_LINK_2E(t) ((t) + 0xb8U)

#define PCIE_PHY_PCS_PHY_LINK_2E_R_TXMARGIN_4_B7_B0(x) ((x) & GENMASK(7U, 0U))
#define PCIE_PHY_PCS_PHY_LINK_2E_R_TXMARGIN_4_B7_B0_M GENMASK(7U, 0U)
#define PCIE_PHY_PCS_PHY_LINK_2E_R_TXMARGIN_4_B7_B0_X(x) ((x) & GENMASK(7U, 0U))

#define PCIE_PHY_PCS_PHY_LINK_2E_R_TXMARGIN_4_B8(x)\
	(((x) << 8U) & GENMASK(8U, 8U))
#define PCIE_PHY_PCS_PHY_LINK_2E_R_TXMARGIN_4_B8_M GENMASK(8U, 8U)
#define PCIE_PHY_PCS_PHY_LINK_2E_R_TXMARGIN_4_B8_X(x)\
	(((x) & GENMASK(8U, 8U)) >> 8U)

#define PCIE_PHY_PCS_PHY_LINK_2E_R_TXMARGIN_5_B7_B0(x)\
	(((x) << 16U) & GENMASK(23U, 16U))
#define PCIE_PHY_PCS_PHY_LINK_2E_R_TXMARGIN_5_B7_B0_M GENMASK(23U, 16U)
#define PCIE_PHY_PCS_PHY_LINK_2E_R_TXMARGIN_5_B7_B0_X(x)\
	(((x) & GENMASK(23U, 16U)) >> 16U)

#define PCIE_PHY_PCS_PHY_LINK_2E_R_TXMARGIN_5_B8(x)\
	(((x) << 24U) & GENMASK(24U, 24U))
#define PCIE_PHY_PCS_PHY_LINK_2E_R_TXMARGIN_5_B8_M GENMASK(24U, 24U)
#define PCIE_PHY_PCS_PHY_LINK_2E_R_TXMARGIN_5_B8_X(x)\
	(((x) & GENMASK(24U, 24U)) >> 24U)

/*      PCIE_PHY_PCS:PHY_LINK_GRP_6:PHY_LINK_2F */
#define PCIE_PHY_PCS_PHY_LINK_2F(t) ((t) + 0xbcU)

#define PCIE_PHY_PCS_PHY_LINK_2F_R_TXMARGIN_6_B7_B0(x) ((x) & GENMASK(7U, 0U))
#define PCIE_PHY_PCS_PHY_LINK_2F_R_TXMARGIN_6_B7_B0_M GENMASK(7U, 0U)
#define PCIE_PHY_PCS_PHY_LINK_2F_R_TXMARGIN_6_B7_B0_X(x) ((x) & GENMASK(7U, 0U))

#define PCIE_PHY_PCS_PHY_LINK_2F_R_TXMARGIN_6_B8(x)\
	(((x) << 8U) & GENMASK(8U, 8U))
#define PCIE_PHY_PCS_PHY_LINK_2F_R_TXMARGIN_6_B8_M GENMASK(8U, 8U)
#define PCIE_PHY_PCS_PHY_LINK_2F_R_TXMARGIN_6_B8_X(x)\
	(((x) & GENMASK(8U, 8U)) >> 8U)

#define PCIE_PHY_PCS_PHY_LINK_2F_R_TXMARGIN_7_B7_B0(x)\
	(((x) << 16U) & GENMASK(23U, 16U))
#define PCIE_PHY_PCS_PHY_LINK_2F_R_TXMARGIN_7_B7_B0_M GENMASK(23U, 16U)
#define PCIE_PHY_PCS_PHY_LINK_2F_R_TXMARGIN_7_B7_B0_X(x)\
	(((x) & GENMASK(23U, 16U)) >> 16U)

#define PCIE_PHY_PCS_PHY_LINK_2F_R_TXMARGIN_7_B8(x)\
	(((x) << 24U) & GENMASK(24U, 24U))
#define PCIE_PHY_PCS_PHY_LINK_2F_R_TXMARGIN_7_B8_M GENMASK(24U, 24U)
#define PCIE_PHY_PCS_PHY_LINK_2F_R_TXMARGIN_7_B8_X(x)\
	(((x) & GENMASK(24U, 24U)) >> 24U)

/*      PCIE_PHY_PCS:PHY_LINK_GRP_6:PHY_LINK_32 */
#define PCIE_PHY_PCS_PHY_LINK_32(t) ((t) + 0xc8U)

#define PCIE_PHY_PCS_PHY_LINK_32_R_SSC_EN(x) ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PCS_PHY_LINK_32_R_SSC_EN_M GENMASK(0U, 0U)
#define PCIE_PHY_PCS_PHY_LINK_32_R_SSC_EN_X(x) ((x) & GENMASK(0U, 0U))

#define PCIE_PHY_PCS_PHY_LINK_32_R_SSC_RESETB(x) (((x) << 8U) & GENMASK(8U, 8U))
#define PCIE_PHY_PCS_PHY_LINK_32_R_SSC_RESETB_M GENMASK(8U, 8U)
#define PCIE_PHY_PCS_PHY_LINK_32_R_SSC_RESETB_X(x)\
	(((x) & GENMASK(8U, 8U)) >> 8U)

/*      PCIE_PHY_PCS:PHY_LINK_GRP_6:PHY_LINK_3E */
#define PCIE_PHY_PCS_PHY_LINK_3E(t) ((t) + 0xf8U)

#define PCIE_PHY_PCS_PHY_LINK_3E_R_BIST_EN_ALL(x) ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PCS_PHY_LINK_3E_R_BIST_EN_ALL_M GENMASK(0U, 0U)
#define PCIE_PHY_PCS_PHY_LINK_3E_R_BIST_EN_ALL_X(x) ((x) & GENMASK(0U, 0U))

#define PCIE_PHY_PCS_PHY_LINK_3E_R_BIST_CHK_ALL(x)\
	(((x) << 1U) & GENMASK(1U, 1U))
#define PCIE_PHY_PCS_PHY_LINK_3E_R_BIST_CHK_ALL_M GENMASK(1U, 1U)
#define PCIE_PHY_PCS_PHY_LINK_3E_R_BIST_CHK_ALL_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

#define PCIE_PHY_PCS_PHY_LINK_3E_R_SEP_REFCLK_SSC(x)\
	(((x) << 8U) & GENMASK(8U, 8U))
#define PCIE_PHY_PCS_PHY_LINK_3E_R_SEP_REFCLK_SSC_M GENMASK(8U, 8U)
#define PCIE_PHY_PCS_PHY_LINK_3E_R_SEP_REFCLK_SSC_X(x)\
	(((x) & GENMASK(8U, 8U)) >> 8U)

#define PCIE_PHY_PCS_PHY_LINK_3E_R_LOWER_SKPOS_RECEPTION(x)\
	(((x) << 9U) & GENMASK(9U, 9U))
#define PCIE_PHY_PCS_PHY_LINK_3E_R_LOWER_SKPOS_RECEPTION_M GENMASK(9U, 9U)
#define PCIE_PHY_PCS_PHY_LINK_3E_R_LOWER_SKPOS_RECEPTION_X(x)\
	(((x) & GENMASK(9U, 9U)) >> 9U)

#define PCIE_PHY_PCS_PHY_LINK_3E_R_OBS_PCS_LANE_CTRL(x)\
	(((x) << 16U) & GENMASK(23U, 16U))
#define PCIE_PHY_PCS_PHY_LINK_3E_R_OBS_PCS_LANE_CTRL_M GENMASK(23U, 16U)
#define PCIE_PHY_PCS_PHY_LINK_3E_R_OBS_PCS_LANE_CTRL_X(x)\
	(((x) & GENMASK(23U, 16U)) >> 16U)

#define PCIE_PHY_PCS_PHY_LINK_3E_R_PCS_DEBUG_SEL(x)\
	(((x) << 24U) & GENMASK(31U, 24U))
#define PCIE_PHY_PCS_PHY_LINK_3E_R_PCS_DEBUG_SEL_M GENMASK(31U, 24U)
#define PCIE_PHY_PCS_PHY_LINK_3E_R_PCS_DEBUG_SEL_X(x)\
	(((x) & GENMASK(31U, 24U)) >> 24U)

/*      PCIE_PHY_PCS:PHY_LINK_GRP_7:PHY_LINK_60 */
#define PCIE_PHY_PCS_PHY_LINK_60(t) ((t) + 0x180U)

#define PCIE_PHY_PCS_PHY_LINK_60_R_TXCOEFF_DIV96(x) ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PCS_PHY_LINK_60_R_TXCOEFF_DIV96_M GENMASK(0U, 0U)
#define PCIE_PHY_PCS_PHY_LINK_60_R_TXCOEFF_DIV96_X(x) ((x) & GENMASK(0U, 0U))

#define PCIE_PHY_PCS_PHY_LINK_60_R_TAP_ADV_SAT_THR(x)\
	(((x) << 8U) & GENMASK(13U, 8U))
#define PCIE_PHY_PCS_PHY_LINK_60_R_TAP_ADV_SAT_THR_M GENMASK(13U, 8U)
#define PCIE_PHY_PCS_PHY_LINK_60_R_TAP_ADV_SAT_THR_X(x)\
	(((x) & GENMASK(13U, 8U)) >> 8U)

#define PCIE_PHY_PCS_PHY_LINK_60_R_TXCOEFF_DIVSEL(x)\
	(((x) << 14U) & GENMASK(15U, 14U))
#define PCIE_PHY_PCS_PHY_LINK_60_R_TXCOEFF_DIVSEL_M GENMASK(15U, 14U)
#define PCIE_PHY_PCS_PHY_LINK_60_R_TXCOEFF_DIVSEL_X(x)\
	(((x) & GENMASK(15U, 14U)) >> 14U)

#define PCIE_PHY_PCS_PHY_LINK_60_R_TAP_ADV_ADJ_OFFSET(x)\
	(((x) << 16U) & GENMASK(20U, 16U))
#define PCIE_PHY_PCS_PHY_LINK_60_R_TAP_ADV_ADJ_OFFSET_M GENMASK(20U, 16U)
#define PCIE_PHY_PCS_PHY_LINK_60_R_TAP_ADV_ADJ_OFFSET_X(x)\
	(((x) & GENMASK(20U, 16U)) >> 16U)

#define PCIE_PHY_PCS_PHY_LINK_60_R_TAP_ADV_SAT_EN(x)\
	(((x) << 22U) & GENMASK(22U, 22U))
#define PCIE_PHY_PCS_PHY_LINK_60_R_TAP_ADV_SAT_EN_M GENMASK(22U, 22U)
#define PCIE_PHY_PCS_PHY_LINK_60_R_TAP_ADV_SAT_EN_X(x)\
	(((x) & GENMASK(22U, 22U)) >> 22U)

#define PCIE_PHY_PCS_PHY_LINK_60_R_TAP_ADV_ADJ_EN(x)\
	(((x) << 23U) & GENMASK(23U, 23U))
#define PCIE_PHY_PCS_PHY_LINK_60_R_TAP_ADV_ADJ_EN_M GENMASK(23U, 23U)
#define PCIE_PHY_PCS_PHY_LINK_60_R_TAP_ADV_ADJ_EN_X(x)\
	(((x) & GENMASK(23U, 23U)) >> 23U)

#define PCIE_PHY_PCS_PHY_LINK_60_R_TAP_DLY_ADJ_OFFSET(x)\
	(((x) << 24U) & GENMASK(28U, 24U))
#define PCIE_PHY_PCS_PHY_LINK_60_R_TAP_DLY_ADJ_OFFSET_M GENMASK(28U, 24U)
#define PCIE_PHY_PCS_PHY_LINK_60_R_TAP_DLY_ADJ_OFFSET_X(x)\
	(((x) & GENMASK(28U, 24U)) >> 24U)

#define PCIE_PHY_PCS_PHY_LINK_60_R_TAP_DLY_SAT_EN(x)\
	(((x) << 30U) & GENMASK(30U, 30U))
#define PCIE_PHY_PCS_PHY_LINK_60_R_TAP_DLY_SAT_EN_M GENMASK(30U, 30U)
#define PCIE_PHY_PCS_PHY_LINK_60_R_TAP_DLY_SAT_EN_X(x)\
	(((x) & GENMASK(30U, 30U)) >> 30U)

#define PCIE_PHY_PCS_PHY_LINK_60_R_TAP_DLY_ADJ_EN(x)\
	(((x) << 31U) & GENMASK(31U, 31U))
#define PCIE_PHY_PCS_PHY_LINK_60_R_TAP_DLY_ADJ_EN_M GENMASK(31U, 31U)
#define PCIE_PHY_PCS_PHY_LINK_60_R_TAP_DLY_ADJ_EN_X(x)\
	(((x) & GENMASK(31U, 31U)) >> 31U)

/*      PCIE_PHY_PCS:PHY_LINK_GRP_7:PHY_LINK_61 */
#define PCIE_PHY_PCS_PHY_LINK_61(t) ((t) + 0x184U)

#define PCIE_PHY_PCS_PHY_LINK_61_R_LOCAL_FS(x) ((x) & GENMASK(5U, 0U))
#define PCIE_PHY_PCS_PHY_LINK_61_R_LOCAL_FS_M GENMASK(5U, 0U)
#define PCIE_PHY_PCS_PHY_LINK_61_R_LOCAL_FS_X(x) ((x) & GENMASK(5U, 0U))

#define PCIE_PHY_PCS_PHY_LINK_61_R_LOCAL_LF(x) (((x) << 8U) & GENMASK(13U, 8U))
#define PCIE_PHY_PCS_PHY_LINK_61_R_LOCAL_LF_M GENMASK(13U, 8U)
#define PCIE_PHY_PCS_PHY_LINK_61_R_LOCAL_LF_X(x)\
	(((x) & GENMASK(13U, 8U)) >> 8U)

#define PCIE_PHY_PCS_PHY_LINK_61_R_TAP_MAIN(x)\
	(((x) << 16U) & GENMASK(21U, 16U))
#define PCIE_PHY_PCS_PHY_LINK_61_R_TAP_MAIN_M GENMASK(21U, 16U)
#define PCIE_PHY_PCS_PHY_LINK_61_R_TAP_MAIN_X(x)\
	(((x) & GENMASK(21U, 16U)) >> 16U)

#define PCIE_PHY_PCS_PHY_LINK_61_R_TAP_DLY_SAT_THR(x)\
	(((x) << 24U) & GENMASK(29U, 24U))
#define PCIE_PHY_PCS_PHY_LINK_61_R_TAP_DLY_SAT_THR_M GENMASK(29U, 24U)
#define PCIE_PHY_PCS_PHY_LINK_61_R_TAP_DLY_SAT_THR_X(x)\
	(((x) & GENMASK(29U, 24U)) >> 24U)

#define PCIE_PHY_PCS_PHY_LINK_61_R_TXCOEFF_PRELUT(x)\
	(((x) << 30U) & GENMASK(31U, 30U))
#define PCIE_PHY_PCS_PHY_LINK_61_R_TXCOEFF_PRELUT_M GENMASK(31U, 30U)
#define PCIE_PHY_PCS_PHY_LINK_61_R_TXCOEFF_PRELUT_X(x)\
	(((x) & GENMASK(31U, 30U)) >> 30U)

/*      PCIE_PHY_PMA:PMA_CMU_GRP_0:PMA_CMU_00 */
#define PCIE_PHY_PMA_PMA_CMU_00(t) ((t) + 0x00U)

#define PCIE_PHY_PMA_PMA_CMU_00_R_HWT_SIMULATION_MODE(x) ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PMA_PMA_CMU_00_R_HWT_SIMULATION_MODE_M GENMASK(0U, 0U)
#define PCIE_PHY_PMA_PMA_CMU_00_R_HWT_SIMULATION_MODE_X(x)\
	((x) & GENMASK(0U, 0U))

#define PCIE_PHY_PMA_PMA_CMU_00_CFG_PLL_LOL_SET(x)\
	(((x) << 1U) & GENMASK(1U, 1U))
#define PCIE_PHY_PMA_PMA_CMU_00_CFG_PLL_LOL_SET_M GENMASK(1U, 1U)
#define PCIE_PHY_PMA_PMA_CMU_00_CFG_PLL_LOL_SET_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

#define PCIE_PHY_PMA_PMA_CMU_00_CFG_PLL_LOS_SET(x)\
	(((x) << 2U) & GENMASK(2U, 2U))
#define PCIE_PHY_PMA_PMA_CMU_00_CFG_PLL_LOS_SET_M GENMASK(2U, 2U)
#define PCIE_PHY_PMA_PMA_CMU_00_CFG_PLL_LOS_SET_X(x)\
	(((x) & GENMASK(2U, 2U)) >> 2U)

#define PCIE_PHY_PMA_PMA_CMU_00_CFG_PLL_TP_SEL_1_0(x)\
	(((x) << 4U) & GENMASK(5U, 4U))
#define PCIE_PHY_PMA_PMA_CMU_00_CFG_PLL_TP_SEL_1_0_M GENMASK(5U, 4U)
#define PCIE_PHY_PMA_PMA_CMU_00_CFG_PLL_TP_SEL_1_0_X(x)\
	(((x) & GENMASK(5U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_CMU_GRP_1:PMA_CMU_0B */
#define PCIE_PHY_PMA_PMA_CMU_0B(t) ((t) + 0x2cU)

#define PCIE_PHY_PMA_PMA_CMU_0B_CFG_I_VCO_3_0(x) ((x) & GENMASK(3U, 0U))
#define PCIE_PHY_PMA_PMA_CMU_0B_CFG_I_VCO_3_0_M GENMASK(3U, 0U)
#define PCIE_PHY_PMA_PMA_CMU_0B_CFG_I_VCO_3_0_X(x) ((x) & GENMASK(3U, 0U))

#define PCIE_PHY_PMA_PMA_CMU_0B_CFG_ICP_BASE_SEL_3_0(x)\
	(((x) << 4U) & GENMASK(7U, 4U))
#define PCIE_PHY_PMA_PMA_CMU_0B_CFG_ICP_BASE_SEL_3_0_M GENMASK(7U, 4U)
#define PCIE_PHY_PMA_PMA_CMU_0B_CFG_ICP_BASE_SEL_3_0_X(x)\
	(((x) & GENMASK(7U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_CMU_GRP_1:PMA_CMU_0C */
#define PCIE_PHY_PMA_PMA_CMU_0C(t) ((t) + 0x30U)

#define PCIE_PHY_PMA_PMA_CMU_0C_CFG_ICP_SEL_2_0(x) ((x) & GENMASK(2U, 0U))
#define PCIE_PHY_PMA_PMA_CMU_0C_CFG_ICP_SEL_2_0_M GENMASK(2U, 0U)
#define PCIE_PHY_PMA_PMA_CMU_0C_CFG_ICP_SEL_2_0_X(x) ((x) & GENMASK(2U, 0U))

#define PCIE_PHY_PMA_PMA_CMU_0C_CFG_RSEL_2_0(x) (((x) << 4U) & GENMASK(6U, 4U))
#define PCIE_PHY_PMA_PMA_CMU_0C_CFG_RSEL_2_0_M GENMASK(6U, 4U)
#define PCIE_PHY_PMA_PMA_CMU_0C_CFG_RSEL_2_0_X(x)\
	(((x) & GENMASK(6U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_CMU_GRP_3:PMA_CMU_1B */
#define PCIE_PHY_PMA_PMA_CMU_1B(t) ((t) + 0x6cU)

#define PCIE_PHY_PMA_PMA_CMU_1B_CFG_RESERVE_7_0(x) ((x) & GENMASK(7U, 0U))
#define PCIE_PHY_PMA_PMA_CMU_1B_CFG_RESERVE_7_0_M GENMASK(7U, 0U)
#define PCIE_PHY_PMA_PMA_CMU_1B_CFG_RESERVE_7_0_X(x) ((x) & GENMASK(7U, 0U))

/*      PCIE_PHY_PMA:PMA_CMU_GRP_4:PMA_CMU_1F */
#define PCIE_PHY_PMA_PMA_CMU_1F(t) ((t) + 0x7cU)

#define PCIE_PHY_PMA_PMA_CMU_1F_CFG_BIAS_DN_EN(x) ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PMA_PMA_CMU_1F_CFG_BIAS_DN_EN_M GENMASK(0U, 0U)
#define PCIE_PHY_PMA_PMA_CMU_1F_CFG_BIAS_DN_EN_X(x) ((x) & GENMASK(0U, 0U))

#define PCIE_PHY_PMA_PMA_CMU_1F_CFG_BIAS_UP_EN(x)\
	(((x) << 1U) & GENMASK(1U, 1U))
#define PCIE_PHY_PMA_PMA_CMU_1F_CFG_BIAS_UP_EN_M GENMASK(1U, 1U)
#define PCIE_PHY_PMA_PMA_CMU_1F_CFG_BIAS_UP_EN_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

#define PCIE_PHY_PMA_PMA_CMU_1F_CFG_IC2IP_N(x) (((x) << 2U) & GENMASK(2U, 2U))
#define PCIE_PHY_PMA_PMA_CMU_1F_CFG_IC2IP_N_M GENMASK(2U, 2U)
#define PCIE_PHY_PMA_PMA_CMU_1F_CFG_IC2IP_N_X(x) (((x) & GENMASK(2U, 2U)) >> 2U)

#define PCIE_PHY_PMA_PMA_CMU_1F_CFG_VTUNE_SEL(x) (((x) << 3U) & GENMASK(3U, 3U))
#define PCIE_PHY_PMA_PMA_CMU_1F_CFG_VTUNE_SEL_M GENMASK(3U, 3U)
#define PCIE_PHY_PMA_PMA_CMU_1F_CFG_VTUNE_SEL_X(x)\
	(((x) & GENMASK(3U, 3U)) >> 3U)

/*      PCIE_PHY_PMA:PMA_CMU_GRP_5:PMA_CMU_30 */
#define PCIE_PHY_PMA_PMA_CMU_30(t) ((t) + 0xc0U)

#define PCIE_PHY_PMA_PMA_CMU_30_R_PLL_DLOL_EN(x) ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PMA_PMA_CMU_30_R_PLL_DLOL_EN_M GENMASK(0U, 0U)
#define PCIE_PHY_PMA_PMA_CMU_30_R_PLL_DLOL_EN_X(x) ((x) & GENMASK(0U, 0U))

/*      PCIE_PHY_PMA:PMA_CMU_GRP_6:PMA_CMU_42 */
#define PCIE_PHY_PMA_PMA_CMU_42(t) ((t) + 0x108U)

#define PCIE_PHY_PMA_PMA_CMU_42_R_LOL_RESET(x) ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PMA_PMA_CMU_42_R_LOL_RESET_M GENMASK(0U, 0U)
#define PCIE_PHY_PMA_PMA_CMU_42_R_LOL_RESET_X(x) ((x) & GENMASK(0U, 0U))

#define PCIE_PHY_PMA_PMA_CMU_42_R_EN_PRE_CAL_VCO(x)\
	(((x) << 1U) & GENMASK(1U, 1U))
#define PCIE_PHY_PMA_PMA_CMU_42_R_EN_PRE_CAL_VCO_M GENMASK(1U, 1U)
#define PCIE_PHY_PMA_PMA_CMU_42_R_EN_PRE_CAL_VCO_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

#define PCIE_PHY_PMA_PMA_CMU_42_R_AUTO_PWRCHG_EN(x)\
	(((x) << 2U) & GENMASK(2U, 2U))
#define PCIE_PHY_PMA_PMA_CMU_42_R_AUTO_PWRCHG_EN_M GENMASK(2U, 2U)
#define PCIE_PHY_PMA_PMA_CMU_42_R_AUTO_PWRCHG_EN_X(x)\
	(((x) & GENMASK(2U, 2U)) >> 2U)

#define PCIE_PHY_PMA_PMA_CMU_42_R_MASK_PLL_RSTN(x)\
	(((x) << 3U) & GENMASK(3U, 3U))
#define PCIE_PHY_PMA_PMA_CMU_42_R_MASK_PLL_RSTN_M GENMASK(3U, 3U)
#define PCIE_PHY_PMA_PMA_CMU_42_R_MASK_PLL_RSTN_X(x)\
	(((x) & GENMASK(3U, 3U)) >> 3U)

/*      PCIE_PHY_PMA:PMA_CMU_GRP_6:PMA_CMU_44 */
#define PCIE_PHY_PMA_PMA_CMU_44(t) ((t) + 0x110U)

#define PCIE_PHY_PMA_PMA_CMU_44_R_PLL_RSTN(x) ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PMA_PMA_CMU_44_R_PLL_RSTN_M GENMASK(0U, 0U)
#define PCIE_PHY_PMA_PMA_CMU_44_R_PLL_RSTN_X(x) ((x) & GENMASK(0U, 0U))

#define PCIE_PHY_PMA_PMA_CMU_44_R_CK_RESETB(x) (((x) << 1U) & GENMASK(1U, 1U))
#define PCIE_PHY_PMA_PMA_CMU_44_R_CK_RESETB_M GENMASK(1U, 1U)
#define PCIE_PHY_PMA_PMA_CMU_44_R_CK_RESETB_X(x) (((x) & GENMASK(1U, 1U)) >> 1U)

/*      PCIE_PHY_PMA:PMA_CMU_GRP_6:PMA_CMU_46 */
#define PCIE_PHY_PMA_PMA_CMU_46(t) ((t) + 0x118U)

#define PCIE_PHY_PMA_PMA_CMU_46_R_DBG_SEL_1_0(x) ((x) & GENMASK(1U, 0U))
#define PCIE_PHY_PMA_PMA_CMU_46_R_DBG_SEL_1_0_M GENMASK(1U, 0U)
#define PCIE_PHY_PMA_PMA_CMU_46_R_DBG_SEL_1_0_X(x) ((x) & GENMASK(1U, 0U))

#define PCIE_PHY_PMA_PMA_CMU_46_R_PWR_CTRL_FROM_HWT(x)\
	(((x) << 4U) & GENMASK(4U, 4U))
#define PCIE_PHY_PMA_PMA_CMU_46_R_PWR_CTRL_FROM_HWT_M GENMASK(4U, 4U)
#define PCIE_PHY_PMA_PMA_CMU_46_R_PWR_CTRL_FROM_HWT_X(x)\
	(((x) & GENMASK(4U, 4U)) >> 4U)

#define PCIE_PHY_PMA_PMA_CMU_46_R_EN_RATECHG_CTRL_SEL_DIV(x)\
	(((x) << 5U) & GENMASK(5U, 5U))
#define PCIE_PHY_PMA_PMA_CMU_46_R_EN_RATECHG_CTRL_SEL_DIV_M GENMASK(5U, 5U)
#define PCIE_PHY_PMA_PMA_CMU_46_R_EN_RATECHG_CTRL_SEL_DIV_X(x)\
	(((x) & GENMASK(5U, 5U)) >> 5U)

/*      PCIE_PHY_PMA:PMA_CMU_GRP_6:PMA_CMU_48 */
#define PCIE_PHY_PMA_PMA_CMU_48(t) ((t) + 0x120U)

#define PCIE_PHY_PMA_PMA_CMU_48_R_GEN12_SEL_DIV_5_0(x) ((x) & GENMASK(5U, 0U))
#define PCIE_PHY_PMA_PMA_CMU_48_R_GEN12_SEL_DIV_5_0_M GENMASK(5U, 0U)
#define PCIE_PHY_PMA_PMA_CMU_48_R_GEN12_SEL_DIV_5_0_X(x) ((x) & GENMASK(5U, 0U))

/*      PCIE_PHY_PMA:PMA_CMU_GRP_6:PMA_CMU_49 */
#define PCIE_PHY_PMA_PMA_CMU_49(t) ((t) + 0x124U)

#define PCIE_PHY_PMA_PMA_CMU_49_R_GEN34_SEL_DIV_5_0(x) ((x) & GENMASK(5U, 0U))
#define PCIE_PHY_PMA_PMA_CMU_49_R_GEN34_SEL_DIV_5_0_M GENMASK(5U, 0U)
#define PCIE_PHY_PMA_PMA_CMU_49_R_GEN34_SEL_DIV_5_0_X(x) ((x) & GENMASK(5U, 0U))

/*      PCIE_PHY_PMA:PMA_CMU_GRP_6:PMA_CMU_4A */
#define PCIE_PHY_PMA_PMA_CMU_4A(t) ((t) + 0x128U)

#define PCIE_PHY_PMA_PMA_CMU_4A_R_SW_8G_GEN12(x) ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PMA_PMA_CMU_4A_R_SW_8G_GEN12_M GENMASK(0U, 0U)
#define PCIE_PHY_PMA_PMA_CMU_4A_R_SW_8G_GEN12_X(x) ((x) & GENMASK(0U, 0U))

#define PCIE_PHY_PMA_PMA_CMU_4A_R_SW_10G_GEN12(x)\
	(((x) << 1U) & GENMASK(1U, 1U))
#define PCIE_PHY_PMA_PMA_CMU_4A_R_SW_10G_GEN12_M GENMASK(1U, 1U)
#define PCIE_PHY_PMA_PMA_CMU_4A_R_SW_10G_GEN12_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

#define PCIE_PHY_PMA_PMA_CMU_4A_R_SW_8G_GEN34(x) (((x) << 4U) & GENMASK(4U, 4U))
#define PCIE_PHY_PMA_PMA_CMU_4A_R_SW_8G_GEN34_M GENMASK(4U, 4U)
#define PCIE_PHY_PMA_PMA_CMU_4A_R_SW_8G_GEN34_X(x)\
	(((x) & GENMASK(4U, 4U)) >> 4U)

#define PCIE_PHY_PMA_PMA_CMU_4A_R_SW_10G_GEN34(x)\
	(((x) << 5U) & GENMASK(5U, 5U))
#define PCIE_PHY_PMA_PMA_CMU_4A_R_SW_10G_GEN34_M GENMASK(5U, 5U)
#define PCIE_PHY_PMA_PMA_CMU_4A_R_SW_10G_GEN34_X(x)\
	(((x) & GENMASK(5U, 5U)) >> 5U)

/*      PCIE_PHY_PMA:PMA_CMU_GRP_6:PMA_CMU_4D */
#define PCIE_PHY_PMA_PMA_CMU_4D(t) ((t) + 0x134U)

#define PCIE_PHY_PMA_PMA_CMU_4D_CFG_I_VCO_GEN34_3_0(x) ((x) & GENMASK(3U, 0U))
#define PCIE_PHY_PMA_PMA_CMU_4D_CFG_I_VCO_GEN34_3_0_M GENMASK(3U, 0U)
#define PCIE_PHY_PMA_PMA_CMU_4D_CFG_I_VCO_GEN34_3_0_X(x) ((x) & GENMASK(3U, 0U))

#define PCIE_PHY_PMA_PMA_CMU_4D_CFG_ICP_SEL_GEN34_2_0(x)\
	(((x) << 4U) & GENMASK(6U, 4U))
#define PCIE_PHY_PMA_PMA_CMU_4D_CFG_ICP_SEL_GEN34_2_0_M GENMASK(6U, 4U)
#define PCIE_PHY_PMA_PMA_CMU_4D_CFG_ICP_SEL_GEN34_2_0_X(x)\
	(((x) & GENMASK(6U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_CMU_GRP_6:PMA_CMU_4E */
#define PCIE_PHY_PMA_PMA_CMU_4E(t) ((t) + 0x138U)

#define PCIE_PHY_PMA_PMA_CMU_4E_CFG_ICP_BASE_SEL_GEN34_3_0(x)\
	((x) & GENMASK(3U, 0U))
#define PCIE_PHY_PMA_PMA_CMU_4E_CFG_ICP_BASE_SEL_GEN34_3_0_M GENMASK(3U, 0U)
#define PCIE_PHY_PMA_PMA_CMU_4E_CFG_ICP_BASE_SEL_GEN34_3_0_X(x)\
	((x) & GENMASK(3U, 0U))

#define PCIE_PHY_PMA_PMA_CMU_4E_CFG_RSEL_GEN34_2_0(x)\
	(((x) << 4U) & GENMASK(6U, 4U))
#define PCIE_PHY_PMA_PMA_CMU_4E_CFG_RSEL_GEN34_2_0_M GENMASK(6U, 4U)
#define PCIE_PHY_PMA_PMA_CMU_4E_CFG_RSEL_GEN34_2_0_X(x)\
	(((x) & GENMASK(6U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_CMU_GRP_7:PMA_CMU_E0 */
#define PCIE_PHY_PMA_PMA_CMU_E0(t) ((t) + 0x380U)

#define PCIE_PHY_PMA_PMA_CMU_E0_READ_VCO_CTUNE_3_0(x) ((x) & GENMASK(3U, 0U))
#define PCIE_PHY_PMA_PMA_CMU_E0_READ_VCO_CTUNE_3_0_M GENMASK(3U, 0U)
#define PCIE_PHY_PMA_PMA_CMU_E0_READ_VCO_CTUNE_3_0_X(x) ((x) & GENMASK(3U, 0U))

#define PCIE_PHY_PMA_PMA_CMU_E0_PLL_LOL_UDL(x) (((x) << 4U) & GENMASK(4U, 4U))
#define PCIE_PHY_PMA_PMA_CMU_E0_PLL_LOL_UDL_M GENMASK(4U, 4U)
#define PCIE_PHY_PMA_PMA_CMU_E0_PLL_LOL_UDL_X(x) (((x) & GENMASK(4U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_CMU_GRP_8:PMA_CMU_FF */
#define PCIE_PHY_PMA_PMA_CMU_FF(t) ((t) + 0x3fcU)

#define PCIE_PHY_PMA_PMA_CMU_FF_MSCC_PMA_CMU_LANE_ACCESS(x)\
	((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PMA_PMA_CMU_FF_MSCC_PMA_CMU_LANE_ACCESS_M GENMASK(0U, 0U)
#define PCIE_PHY_PMA_PMA_CMU_FF_MSCC_PMA_CMU_LANE_ACCESS_X(x)\
	((x) & GENMASK(0U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_02 */
#define PCIE_PHY_PMA_PMA_LANE_02(t) ((t) + 0x408U)

#define PCIE_PHY_PMA_PMA_LANE_02_CFG_EN_ADV(x) ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_02_CFG_EN_ADV_M GENMASK(0U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_02_CFG_EN_ADV_X(x) ((x) & GENMASK(0U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_02_CFG_EN_MAIN(x) (((x) << 1U) & GENMASK(1U, 1U))
#define PCIE_PHY_PMA_PMA_LANE_02_CFG_EN_MAIN_M GENMASK(1U, 1U)
#define PCIE_PHY_PMA_PMA_LANE_02_CFG_EN_MAIN_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

#define PCIE_PHY_PMA_PMA_LANE_02_CFG_EN_DLY(x) (((x) << 2U) & GENMASK(2U, 2U))
#define PCIE_PHY_PMA_PMA_LANE_02_CFG_EN_DLY_M GENMASK(2U, 2U)
#define PCIE_PHY_PMA_PMA_LANE_02_CFG_EN_DLY_X(x) (((x) & GENMASK(2U, 2U)) >> 2U)

#define PCIE_PHY_PMA_PMA_LANE_02_CFG_EN_DLY2(x) (((x) << 3U) & GENMASK(3U, 3U))
#define PCIE_PHY_PMA_PMA_LANE_02_CFG_EN_DLY2_M GENMASK(3U, 3U)
#define PCIE_PHY_PMA_PMA_LANE_02_CFG_EN_DLY2_X(x)\
	(((x) & GENMASK(3U, 3U)) >> 3U)

#define PCIE_PHY_PMA_PMA_LANE_02_CFG_TAP_MAIN(x) (((x) << 4U) & GENMASK(4U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_02_CFG_TAP_MAIN_M GENMASK(4U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_02_CFG_TAP_MAIN_X(x)\
	(((x) & GENMASK(4U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_03 */
#define PCIE_PHY_PMA_PMA_LANE_03(t) ((t) + 0x40cU)

#define PCIE_PHY_PMA_PMA_LANE_03_CFG_TAP_ADV_4_0(x) ((x) & GENMASK(4U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_03_CFG_TAP_ADV_4_0_M GENMASK(4U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_03_CFG_TAP_ADV_4_0_X(x) ((x) & GENMASK(4U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_04 */
#define PCIE_PHY_PMA_PMA_LANE_04(t) ((t) + 0x410U)

#define PCIE_PHY_PMA_PMA_LANE_04_CFG_TAP_DLY_4_0(x) ((x) & GENMASK(4U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_04_CFG_TAP_DLY_4_0_M GENMASK(4U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_04_CFG_TAP_DLY_4_0_X(x) ((x) & GENMASK(4U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_05 */
#define PCIE_PHY_PMA_PMA_LANE_05(t) ((t) + 0x414U)

#define PCIE_PHY_PMA_PMA_LANE_05_CFG_TAP_DLY2_3_0(x) ((x) & GENMASK(3U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_05_CFG_TAP_DLY2_3_0_M GENMASK(3U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_05_CFG_TAP_DLY2_3_0_X(x) ((x) & GENMASK(3U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_07 */
#define PCIE_PHY_PMA_PMA_LANE_07(t) ((t) + 0x41cU)

#define PCIE_PHY_PMA_PMA_LANE_07_CFG_RX_REG_BYP(x) ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_07_CFG_RX_REG_BYP_M GENMASK(0U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_07_CFG_RX_REG_BYP_X(x) ((x) & GENMASK(0U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_07_CFG_RX_REG_PU(x)\
	(((x) << 1U) & GENMASK(1U, 1U))
#define PCIE_PHY_PMA_PMA_LANE_07_CFG_RX_REG_PU_M GENMASK(1U, 1U)
#define PCIE_PHY_PMA_PMA_LANE_07_CFG_RX_REG_PU_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

#define PCIE_PHY_PMA_PMA_LANE_07_CFG_RX_REG_VSEL_1_0(x)\
	(((x) << 4U) & GENMASK(5U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_07_CFG_RX_REG_VSEL_1_0_M GENMASK(5U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_07_CFG_RX_REG_VSEL_1_0_X(x)\
	(((x) & GENMASK(5U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_08 */
#define PCIE_PHY_PMA_PMA_LANE_08(t) ((t) + 0x420U)

#define PCIE_PHY_PMA_PMA_LANE_08_CFG_BYP_OC_CLK(x) ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_08_CFG_BYP_OC_CLK_M GENMASK(0U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_08_CFG_BYP_OC_CLK_X(x) ((x) & GENMASK(0U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_08_CFG_CTLE_NEGC(x)\
	(((x) << 4U) & GENMASK(5U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_08_CFG_CTLE_NEGC_M GENMASK(5U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_08_CFG_CTLE_NEGC_X(x)\
	(((x) & GENMASK(5U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_09 */
#define PCIE_PHY_PMA_PMA_LANE_09(t) ((t) + 0x424U)

#define PCIE_PHY_PMA_PMA_LANE_09_CFG_EN_HYS_SQ(x) ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_09_CFG_EN_HYS_SQ_M GENMASK(0U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_09_CFG_EN_HYS_SQ_X(x) ((x) & GENMASK(0U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_09_CFG_IP_RX_LS_SEL_2_0(x)\
	(((x) << 4U) & GENMASK(6U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_09_CFG_IP_RX_LS_SEL_2_0_M GENMASK(6U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_09_CFG_IP_RX_LS_SEL_2_0_X(x)\
	(((x) & GENMASK(6U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_0A */
#define PCIE_PHY_PMA_PMA_LANE_0A(t) ((t) + 0x428U)

#define PCIE_PHY_PMA_PMA_LANE_0A_CFG_LANE_ID_2_0(x) ((x) & GENMASK(2U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_0A_CFG_LANE_ID_2_0_M GENMASK(2U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_0A_CFG_LANE_ID_2_0_X(x) ((x) & GENMASK(2U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_0A_CFG_SUM_SETCM_EN_GEN2(x)\
	(((x) << 4U) & GENMASK(4U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_0A_CFG_SUM_SETCM_EN_GEN2_M GENMASK(4U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_0A_CFG_SUM_SETCM_EN_GEN2_X(x)\
	(((x) & GENMASK(4U, 4U)) >> 4U)

#define PCIE_PHY_PMA_PMA_LANE_0A_CFG_SUM_SETCM_EN_GEN3(x)\
	(((x) << 5U) & GENMASK(5U, 5U))
#define PCIE_PHY_PMA_PMA_LANE_0A_CFG_SUM_SETCM_EN_GEN3_M GENMASK(5U, 5U)
#define PCIE_PHY_PMA_PMA_LANE_0A_CFG_SUM_SETCM_EN_GEN3_X(x)\
	(((x) & GENMASK(5U, 5U)) >> 5U)

#define PCIE_PHY_PMA_PMA_LANE_0A_CFG_SUM_SETCM_EN_GEN4(x)\
	(((x) << 6U) & GENMASK(6U, 6U))
#define PCIE_PHY_PMA_PMA_LANE_0A_CFG_SUM_SETCM_EN_GEN4_M GENMASK(6U, 6U)
#define PCIE_PHY_PMA_PMA_LANE_0A_CFG_SUM_SETCM_EN_GEN4_X(x)\
	(((x) & GENMASK(6U, 6U)) >> 6U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_0B */
#define PCIE_PHY_PMA_PMA_LANE_0B(t) ((t) + 0x42cU)

#define PCIE_PHY_PMA_PMA_LANE_0B_CFG_EQ_RES_3_0(x) ((x) & GENMASK(3U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_0B_CFG_EQ_RES_3_0_M GENMASK(3U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_0B_CFG_EQ_RES_3_0_X(x) ((x) & GENMASK(3U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_0B_CFG_PD_CTLE(x) (((x) << 4U) & GENMASK(4U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_0B_CFG_PD_CTLE_M GENMASK(4U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_0B_CFG_PD_CTLE_X(x)\
	(((x) & GENMASK(4U, 4U)) >> 4U)

#define PCIE_PHY_PMA_PMA_LANE_0B_CFG_CTLE_TP_EN(x)\
	(((x) << 5U) & GENMASK(5U, 5U))
#define PCIE_PHY_PMA_PMA_LANE_0B_CFG_CTLE_TP_EN_M GENMASK(5U, 5U)
#define PCIE_PHY_PMA_PMA_LANE_0B_CFG_CTLE_TP_EN_X(x)\
	(((x) & GENMASK(5U, 5U)) >> 5U)

#define PCIE_PHY_PMA_PMA_LANE_0B_CFG_RESETB_OSCAL_AFE(x)\
	(((x) << 6U) & GENMASK(6U, 6U))
#define PCIE_PHY_PMA_PMA_LANE_0B_CFG_RESETB_OSCAL_AFE_M GENMASK(6U, 6U)
#define PCIE_PHY_PMA_PMA_LANE_0B_CFG_RESETB_OSCAL_AFE_X(x)\
	(((x) & GENMASK(6U, 6U)) >> 6U)

#define PCIE_PHY_PMA_PMA_LANE_0B_CFG_RESETB_OSCAL_SQ(x)\
	(((x) << 7U) & GENMASK(7U, 7U))
#define PCIE_PHY_PMA_PMA_LANE_0B_CFG_RESETB_OSCAL_SQ_M GENMASK(7U, 7U)
#define PCIE_PHY_PMA_PMA_LANE_0B_CFG_RESETB_OSCAL_SQ_X(x)\
	(((x) & GENMASK(7U, 7U)) >> 7U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_0E */
#define PCIE_PHY_PMA_PMA_LANE_0E(t) ((t) + 0x438U)

#define PCIE_PHY_PMA_PMA_LANE_0E_CFG_EQC_FORCE_3_0(x) ((x) & GENMASK(3U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_0E_CFG_EQC_FORCE_3_0_M GENMASK(3U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_0E_CFG_EQC_FORCE_3_0_X(x) ((x) & GENMASK(3U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_0E_CFG_RXLB_EN(x) (((x) << 4U) & GENMASK(4U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_0E_CFG_RXLB_EN_M GENMASK(4U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_0E_CFG_RXLB_EN_X(x)\
	(((x) & GENMASK(4U, 4U)) >> 4U)

#define PCIE_PHY_PMA_PMA_LANE_0E_CFG_TXLB_EN(x) (((x) << 5U) & GENMASK(5U, 5U))
#define PCIE_PHY_PMA_PMA_LANE_0E_CFG_TXLB_EN_M GENMASK(5U, 5U)
#define PCIE_PHY_PMA_PMA_LANE_0E_CFG_TXLB_EN_X(x)\
	(((x) & GENMASK(5U, 5U)) >> 5U)

#define PCIE_PHY_PMA_PMA_LANE_0E_CFG_SUM_SETCM_EN(x)\
	(((x) << 6U) & GENMASK(6U, 6U))
#define PCIE_PHY_PMA_PMA_LANE_0E_CFG_SUM_SETCM_EN_M GENMASK(6U, 6U)
#define PCIE_PHY_PMA_PMA_LANE_0E_CFG_SUM_SETCM_EN_X(x)\
	(((x) & GENMASK(6U, 6U)) >> 6U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_0F */
#define PCIE_PHY_PMA_PMA_LANE_0F(t) ((t) + 0x43cU)

#define PCIE_PHY_PMA_PMA_LANE_0F_R_CDR_M_GEN1_7_0(x) ((x) & GENMASK(7U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_0F_R_CDR_M_GEN1_7_0_M GENMASK(7U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_0F_R_CDR_M_GEN1_7_0_X(x) ((x) & GENMASK(7U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_10 */
#define PCIE_PHY_PMA_PMA_LANE_10(t) ((t) + 0x440U)

#define PCIE_PHY_PMA_PMA_LANE_10_R_CDR_M_GEN2_7_0(x) ((x) & GENMASK(7U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_10_R_CDR_M_GEN2_7_0_M GENMASK(7U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_10_R_CDR_M_GEN2_7_0_X(x) ((x) & GENMASK(7U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_11 */
#define PCIE_PHY_PMA_PMA_LANE_11(t) ((t) + 0x444U)

#define PCIE_PHY_PMA_PMA_LANE_11_R_CDR_M_GEN3_7_0(x) ((x) & GENMASK(7U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_11_R_CDR_M_GEN3_7_0_M GENMASK(7U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_11_R_CDR_M_GEN3_7_0_X(x) ((x) & GENMASK(7U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_12 */
#define PCIE_PHY_PMA_PMA_LANE_12(t) ((t) + 0x448U)

#define PCIE_PHY_PMA_PMA_LANE_12_R_CDR_M_GEN4_7_0(x) ((x) & GENMASK(7U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_12_R_CDR_M_GEN4_7_0_M GENMASK(7U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_12_R_CDR_M_GEN4_7_0_X(x) ((x) & GENMASK(7U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_14 */
#define PCIE_PHY_PMA_PMA_LANE_14(t) ((t) + 0x450U)

#define PCIE_PHY_PMA_PMA_LANE_14_CFG_PI_EXT_DAC_7_0(x) ((x) & GENMASK(7U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_14_CFG_PI_EXT_DAC_7_0_M GENMASK(7U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_14_CFG_PI_EXT_DAC_7_0_X(x) ((x) & GENMASK(7U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_15 */
#define PCIE_PHY_PMA_PMA_LANE_15(t) ((t) + 0x454U)

#define PCIE_PHY_PMA_PMA_LANE_15_CFG_PI_EXT_DAC_15_8(x) ((x) & GENMASK(7U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_15_CFG_PI_EXT_DAC_15_8_M GENMASK(7U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_15_CFG_PI_EXT_DAC_15_8_X(x)\
	((x) & GENMASK(7U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_16 */
#define PCIE_PHY_PMA_PMA_LANE_16(t) ((t) + 0x458U)

#define PCIE_PHY_PMA_PMA_LANE_16_CFG_PI_EXT_DAC_23_16(x) ((x) & GENMASK(7U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_16_CFG_PI_EXT_DAC_23_16_M GENMASK(7U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_16_CFG_PI_EXT_DAC_23_16_X(x)\
	((x) & GENMASK(7U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_17 */
#define PCIE_PHY_PMA_PMA_LANE_17(t) ((t) + 0x45cU)

#define PCIE_PHY_PMA_PMA_LANE_17_CFG_PI_EXT_DAC_30_24(x) ((x) & GENMASK(6U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_17_CFG_PI_EXT_DAC_30_24_M GENMASK(6U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_17_CFG_PI_EXT_DAC_30_24_X(x)\
	((x) & GENMASK(6U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_18 */
#define PCIE_PHY_PMA_PMA_LANE_18(t) ((t) + 0x460U)

#define PCIE_PHY_PMA_PMA_LANE_18_CFG_PI_EXT_OVR(x) ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_18_CFG_PI_EXT_OVR_M GENMASK(0U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_18_CFG_PI_EXT_OVR_X(x) ((x) & GENMASK(0U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_18_CFG_PI_HOLD(x) (((x) << 1U) & GENMASK(1U, 1U))
#define PCIE_PHY_PMA_PMA_LANE_18_CFG_PI_HOLD_M GENMASK(1U, 1U)
#define PCIE_PHY_PMA_PMA_LANE_18_CFG_PI_HOLD_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

#define PCIE_PHY_PMA_PMA_LANE_18_CFG_PI_OFFSET_DIR(x)\
	(((x) << 2U) & GENMASK(2U, 2U))
#define PCIE_PHY_PMA_PMA_LANE_18_CFG_PI_OFFSET_DIR_M GENMASK(2U, 2U)
#define PCIE_PHY_PMA_PMA_LANE_18_CFG_PI_OFFSET_DIR_X(x)\
	(((x) & GENMASK(2U, 2U)) >> 2U)

#define PCIE_PHY_PMA_PMA_LANE_18_CFG_PI_OFFSET_SET(x)\
	(((x) << 3U) & GENMASK(3U, 3U))
#define PCIE_PHY_PMA_PMA_LANE_18_CFG_PI_OFFSET_SET_M GENMASK(3U, 3U)
#define PCIE_PHY_PMA_PMA_LANE_18_CFG_PI_OFFSET_SET_X(x)\
	(((x) & GENMASK(3U, 3U)) >> 3U)

#define PCIE_PHY_PMA_PMA_LANE_18_CFG_PI_EXT_QRT_1_0(x)\
	(((x) << 4U) & GENMASK(5U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_18_CFG_PI_EXT_QRT_1_0_M GENMASK(5U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_18_CFG_PI_EXT_QRT_1_0_X(x)\
	(((x) & GENMASK(5U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_1A */
#define PCIE_PHY_PMA_PMA_LANE_1A(t) ((t) + 0x468U)

#define PCIE_PHY_PMA_PMA_LANE_1A_CFG_PI_R_SCAN_EN(x) ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_1A_CFG_PI_R_SCAN_EN_M GENMASK(0U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_1A_CFG_PI_R_SCAN_EN_X(x) ((x) & GENMASK(0U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_1A_CFG_PI_EN(x) (((x) << 1U) & GENMASK(1U, 1U))
#define PCIE_PHY_PMA_PMA_LANE_1A_CFG_PI_EN_M GENMASK(1U, 1U)
#define PCIE_PHY_PMA_PMA_LANE_1A_CFG_PI_EN_X(x) (((x) & GENMASK(1U, 1U)) >> 1U)

#define PCIE_PHY_PMA_PMA_LANE_1A_CFG_PI_DFE_EN(x)\
	(((x) << 2U) & GENMASK(2U, 2U))
#define PCIE_PHY_PMA_PMA_LANE_1A_CFG_PI_DFE_EN_M GENMASK(2U, 2U)
#define PCIE_PHY_PMA_PMA_LANE_1A_CFG_PI_DFE_EN_X(x)\
	(((x) & GENMASK(2U, 2U)) >> 2U)

#define PCIE_PHY_PMA_PMA_LANE_1A_CFG_PI_STEPS_GEN1(x)\
	(((x) << 3U) & GENMASK(3U, 3U))
#define PCIE_PHY_PMA_PMA_LANE_1A_CFG_PI_STEPS_GEN1_M GENMASK(3U, 3U)
#define PCIE_PHY_PMA_PMA_LANE_1A_CFG_PI_STEPS_GEN1_X(x)\
	(((x) & GENMASK(3U, 3U)) >> 3U)

#define PCIE_PHY_PMA_PMA_LANE_1A_CFG_PI_FLOOP_STEPS_GEN1_1_0(x)\
	(((x) << 4U) & GENMASK(5U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_1A_CFG_PI_FLOOP_STEPS_GEN1_1_0_M GENMASK(5U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_1A_CFG_PI_FLOOP_STEPS_GEN1_1_0_X(x)\
	(((x) & GENMASK(5U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_24 */
#define PCIE_PHY_PMA_PMA_LANE_24(t) ((t) + 0x490U)

#define PCIE_PHY_PMA_PMA_LANE_24_CFG_PI_BW_GEN1_3_0(x) ((x) & GENMASK(3U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_24_CFG_PI_BW_GEN1_3_0_M GENMASK(3U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_24_CFG_PI_BW_GEN1_3_0_X(x) ((x) & GENMASK(3U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_24_CFG_PI_BW_GEN2_3_0(x)\
	(((x) << 4U) & GENMASK(7U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_24_CFG_PI_BW_GEN2_3_0_M GENMASK(7U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_24_CFG_PI_BW_GEN2_3_0_X(x)\
	(((x) & GENMASK(7U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_25 */
#define PCIE_PHY_PMA_PMA_LANE_25(t) ((t) + 0x494U)

#define PCIE_PHY_PMA_PMA_LANE_25_CFG_PI_BW_GEN3_3_0(x) ((x) & GENMASK(3U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_25_CFG_PI_BW_GEN3_3_0_M GENMASK(3U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_25_CFG_PI_BW_GEN3_3_0_X(x) ((x) & GENMASK(3U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_25_CFG_PI_BW_GEN4_3_0(x)\
	(((x) << 4U) & GENMASK(7U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_25_CFG_PI_BW_GEN4_3_0_M GENMASK(7U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_25_CFG_PI_BW_GEN4_3_0_X(x)\
	(((x) & GENMASK(7U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_26 */
#define PCIE_PHY_PMA_PMA_LANE_26(t) ((t) + 0x498U)

#define PCIE_PHY_PMA_PMA_LANE_26_CFG_ISCAN_EXT_DAC_7_0(x)\
	((x) & GENMASK(7U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_26_CFG_ISCAN_EXT_DAC_7_0_M GENMASK(7U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_26_CFG_ISCAN_EXT_DAC_7_0_X(x)\
	((x) & GENMASK(7U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_27 */
#define PCIE_PHY_PMA_PMA_LANE_27(t) ((t) + 0x49cU)

#define PCIE_PHY_PMA_PMA_LANE_27_CFG_ISCAN_EXT_DAC_15_8(x)\
	((x) & GENMASK(7U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_27_CFG_ISCAN_EXT_DAC_15_8_M GENMASK(7U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_27_CFG_ISCAN_EXT_DAC_15_8_X(x)\
	((x) & GENMASK(7U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_28 */
#define PCIE_PHY_PMA_PMA_LANE_28(t) ((t) + 0x4a0U)

#define PCIE_PHY_PMA_PMA_LANE_28_CFG_ISCAN_EXT_DAC_23_16(x)\
	((x) & GENMASK(7U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_28_CFG_ISCAN_EXT_DAC_23_16_M GENMASK(7U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_28_CFG_ISCAN_EXT_DAC_23_16_X(x)\
	((x) & GENMASK(7U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_29 */
#define PCIE_PHY_PMA_PMA_LANE_29(t) ((t) + 0x4a4U)

#define PCIE_PHY_PMA_PMA_LANE_29_CFG_ISCAN_EXT_DAC_30_24(x)\
	((x) & GENMASK(6U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_29_CFG_ISCAN_EXT_DAC_30_24_M GENMASK(6U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_29_CFG_ISCAN_EXT_DAC_30_24_X(x)\
	((x) & GENMASK(6U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_2A */
#define PCIE_PHY_PMA_PMA_LANE_2A(t) ((t) + 0x4a8U)

#define PCIE_PHY_PMA_PMA_LANE_2A_CFG_ISCAN_EXT_OVR(x) ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_2A_CFG_ISCAN_EXT_OVR_M GENMASK(0U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_2A_CFG_ISCAN_EXT_OVR_X(x) ((x) & GENMASK(0U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_2A_CFG_ISCAN_EXT_QRT_1_0(x)\
	(((x) << 4U) & GENMASK(5U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_2A_CFG_ISCAN_EXT_QRT_1_0_M GENMASK(5U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_2A_CFG_ISCAN_EXT_QRT_1_0_X(x)\
	(((x) & GENMASK(5U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_2F */
#define PCIE_PHY_PMA_PMA_LANE_2F(t) ((t) + 0x4bcU)

#define PCIE_PHY_PMA_PMA_LANE_2F_CFG_VGA_CP_2_0(x) ((x) & GENMASK(2U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_2F_CFG_VGA_CP_2_0_M GENMASK(2U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_2F_CFG_VGA_CP_2_0_X(x) ((x) & GENMASK(2U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_2F_CFG_VGA_CTRL_3_0(x)\
	(((x) << 4U) & GENMASK(7U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_2F_CFG_VGA_CTRL_3_0_M GENMASK(7U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_2F_CFG_VGA_CTRL_3_0_X(x)\
	(((x) & GENMASK(7U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_31 */
#define PCIE_PHY_PMA_PMA_LANE_31(t) ((t) + 0x4c4U)

#define PCIE_PHY_PMA_PMA_LANE_31_CFG_PI_RSTN(x) ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_31_CFG_PI_RSTN_M GENMASK(0U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_31_CFG_PI_RSTN_X(x) ((x) & GENMASK(0U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_31_CFG_CDR_RSTN(x) (((x) << 1U) & GENMASK(1U, 1U))
#define PCIE_PHY_PMA_PMA_LANE_31_CFG_CDR_RSTN_M GENMASK(1U, 1U)
#define PCIE_PHY_PMA_PMA_LANE_31_CFG_CDR_RSTN_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

#define PCIE_PHY_PMA_PMA_LANE_31_CFG_RSTN_DFEDIG_GEN1(x)\
	(((x) << 2U) & GENMASK(2U, 2U))
#define PCIE_PHY_PMA_PMA_LANE_31_CFG_RSTN_DFEDIG_GEN1_M GENMASK(2U, 2U)
#define PCIE_PHY_PMA_PMA_LANE_31_CFG_RSTN_DFEDIG_GEN1_X(x)\
	(((x) & GENMASK(2U, 2U)) >> 2U)

#define PCIE_PHY_PMA_PMA_LANE_31_CFG_CTLE_RSTN(x)\
	(((x) << 3U) & GENMASK(3U, 3U))
#define PCIE_PHY_PMA_PMA_LANE_31_CFG_CTLE_RSTN_M GENMASK(3U, 3U)
#define PCIE_PHY_PMA_PMA_LANE_31_CFG_CTLE_RSTN_X(x)\
	(((x) & GENMASK(3U, 3U)) >> 3U)

#define PCIE_PHY_PMA_PMA_LANE_31_CFG_RSTN_DIV5_8(x)\
	(((x) << 4U) & GENMASK(4U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_31_CFG_RSTN_DIV5_8_M GENMASK(4U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_31_CFG_RSTN_DIV5_8_X(x)\
	(((x) & GENMASK(4U, 4U)) >> 4U)

#define PCIE_PHY_PMA_PMA_LANE_31_CFG_R50_EN(x) (((x) << 5U) & GENMASK(5U, 5U))
#define PCIE_PHY_PMA_PMA_LANE_31_CFG_R50_EN_M GENMASK(5U, 5U)
#define PCIE_PHY_PMA_PMA_LANE_31_CFG_R50_EN_X(x) (((x) & GENMASK(5U, 5U)) >> 5U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_33 */
#define PCIE_PHY_PMA_PMA_LANE_33(t) ((t) + 0x4ccU)

#define PCIE_PHY_PMA_PMA_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0(x)\
	((x) & GENMASK(2U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_M GENMASK(2U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_X(x)\
	((x) & GENMASK(2U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0(x)\
	(((x) << 4U) & GENMASK(5U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_M GENMASK(5U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_X(x)\
	(((x) & GENMASK(5U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_34 */
#define PCIE_PHY_PMA_PMA_LANE_34(t) ((t) + 0x4d0U)

#define PCIE_PHY_PMA_PMA_LANE_34_CFG_RXTERM_PD(x) ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_34_CFG_RXTERM_PD_M GENMASK(0U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_34_CFG_RXTERM_PD_X(x) ((x) & GENMASK(0U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_34_CFG_PD_SQ(x) (((x) << 1U) & GENMASK(1U, 1U))
#define PCIE_PHY_PMA_PMA_LANE_34_CFG_PD_SQ_M GENMASK(1U, 1U)
#define PCIE_PHY_PMA_PMA_LANE_34_CFG_PD_SQ_X(x) (((x) & GENMASK(1U, 1U)) >> 1U)

#define PCIE_PHY_PMA_PMA_LANE_34_CFG_DIS_SQ(x) (((x) << 2U) & GENMASK(2U, 2U))
#define PCIE_PHY_PMA_PMA_LANE_34_CFG_DIS_SQ_M GENMASK(2U, 2U)
#define PCIE_PHY_PMA_PMA_LANE_34_CFG_DIS_SQ_X(x) (((x) & GENMASK(2U, 2U)) >> 2U)

#define PCIE_PHY_PMA_PMA_LANE_34_CFG_HIZ(x) (((x) << 3U) & GENMASK(3U, 3U))
#define PCIE_PHY_PMA_PMA_LANE_34_CFG_HIZ_M  GENMASK(3U, 3U)
#define PCIE_PHY_PMA_PMA_LANE_34_CFG_HIZ_X(x) (((x) & GENMASK(3U, 3U)) >> 3U)

#define PCIE_PHY_PMA_PMA_LANE_34_CFG_EN_DFEDIG_GEN2(x)\
	(((x) << 4U) & GENMASK(4U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_34_CFG_EN_DFEDIG_GEN2_M GENMASK(4U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_34_CFG_EN_DFEDIG_GEN2_X(x)\
	(((x) & GENMASK(4U, 4U)) >> 4U)

#define PCIE_PHY_PMA_PMA_LANE_34_CFG_EN_DFEDIG_GEN3(x)\
	(((x) << 5U) & GENMASK(5U, 5U))
#define PCIE_PHY_PMA_PMA_LANE_34_CFG_EN_DFEDIG_GEN3_M GENMASK(5U, 5U)
#define PCIE_PHY_PMA_PMA_LANE_34_CFG_EN_DFEDIG_GEN3_X(x)\
	(((x) & GENMASK(5U, 5U)) >> 5U)

#define PCIE_PHY_PMA_PMA_LANE_34_CFG_EN_DFEDIG_GEN4(x)\
	(((x) << 6U) & GENMASK(6U, 6U))
#define PCIE_PHY_PMA_PMA_LANE_34_CFG_EN_DFEDIG_GEN4_M GENMASK(6U, 6U)
#define PCIE_PHY_PMA_PMA_LANE_34_CFG_EN_DFEDIG_GEN4_X(x)\
	(((x) & GENMASK(6U, 6U)) >> 6U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_36 */
#define PCIE_PHY_PMA_PMA_LANE_36(t) ((t) + 0x4d8U)

#define PCIE_PHY_PMA_PMA_LANE_36_CFG_PREDRV_SLEWRATE_GEN1_1_0(x)\
	((x) & GENMASK(1U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_36_CFG_PREDRV_SLEWRATE_GEN1_1_0_M GENMASK(1U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_36_CFG_PREDRV_SLEWRATE_GEN1_1_0_X(x)\
	((x) & GENMASK(1U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_36_CFG_EID_LP(x) (((x) << 4U) & GENMASK(4U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_36_CFG_EID_LP_M GENMASK(4U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_36_CFG_EID_LP_X(x) (((x) & GENMASK(4U, 4U)) >> 4U)

#define PCIE_PHY_PMA_PMA_LANE_36_CFG_EN_PREDRV_EMPH(x)\
	(((x) << 5U) & GENMASK(5U, 5U))
#define PCIE_PHY_PMA_PMA_LANE_36_CFG_EN_PREDRV_EMPH_M GENMASK(5U, 5U)
#define PCIE_PHY_PMA_PMA_LANE_36_CFG_EN_PREDRV_EMPH_X(x)\
	(((x) & GENMASK(5U, 5U)) >> 5U)

#define PCIE_PHY_PMA_PMA_LANE_36_CFG_PRBS_SEL(x) (((x) << 6U) & GENMASK(6U, 6U))
#define PCIE_PHY_PMA_PMA_LANE_36_CFG_PRBS_SEL_M GENMASK(6U, 6U)
#define PCIE_PHY_PMA_PMA_LANE_36_CFG_PRBS_SEL_X(x)\
	(((x) & GENMASK(6U, 6U)) >> 6U)

#define PCIE_PHY_PMA_PMA_LANE_36_CFG_PRBS_SETB(x)\
	(((x) << 7U) & GENMASK(7U, 7U))
#define PCIE_PHY_PMA_PMA_LANE_36_CFG_PRBS_SETB_M GENMASK(7U, 7U)
#define PCIE_PHY_PMA_PMA_LANE_36_CFG_PRBS_SETB_X(x)\
	(((x) & GENMASK(7U, 7U)) >> 7U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_37 */
#define PCIE_PHY_PMA_PMA_LANE_37(t) ((t) + 0x4dcU)

#define PCIE_PHY_PMA_PMA_LANE_37_CFG_RXDET_COMP_PD(x) ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_37_CFG_RXDET_COMP_PD_M GENMASK(0U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_37_CFG_RXDET_COMP_PD_X(x) ((x) & GENMASK(0U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_37_CFG_PD_RX_CKTREE(x)\
	(((x) << 1U) & GENMASK(1U, 1U))
#define PCIE_PHY_PMA_PMA_LANE_37_CFG_PD_RX_CKTREE_M GENMASK(1U, 1U)
#define PCIE_PHY_PMA_PMA_LANE_37_CFG_PD_RX_CKTREE_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

#define PCIE_PHY_PMA_PMA_LANE_37_CFG_TXSWING_HALF(x)\
	(((x) << 2U) & GENMASK(2U, 2U))
#define PCIE_PHY_PMA_PMA_LANE_37_CFG_TXSWING_HALF_M GENMASK(2U, 2U)
#define PCIE_PHY_PMA_PMA_LANE_37_CFG_TXSWING_HALF_X(x)\
	(((x) & GENMASK(2U, 2U)) >> 2U)

#define PCIE_PHY_PMA_PMA_LANE_37_CFG_IP_PRE_BASE_GEN1_1_0(x)\
	(((x) << 4U) & GENMASK(5U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_37_CFG_IP_PRE_BASE_GEN1_1_0_M GENMASK(5U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_37_CFG_IP_PRE_BASE_GEN1_1_0_X(x)\
	(((x) & GENMASK(5U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_38 */
#define PCIE_PHY_PMA_PMA_LANE_38(t) ((t) + 0x4e0U)

#define PCIE_PHY_PMA_PMA_LANE_38_CFG_TACC_SEL_GEN1_1_0(x)\
	((x) & GENMASK(1U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_38_CFG_TACC_SEL_GEN1_1_0_M GENMASK(1U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_38_CFG_TACC_SEL_GEN1_1_0_X(x)\
	((x) & GENMASK(1U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_38_CFG_RXFILT_Z_GEN1_1_0(x)\
	(((x) << 4U) & GENMASK(5U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_38_CFG_RXFILT_Z_GEN1_1_0_M GENMASK(5U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_38_CFG_RXFILT_Z_GEN1_1_0_X(x)\
	(((x) & GENMASK(5U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_3A */
#define PCIE_PHY_PMA_PMA_LANE_3A(t) ((t) + 0x4e8U)

#define PCIE_PHY_PMA_PMA_LANE_3A_CFG_MP_MIN_3_0(x) ((x) & GENMASK(3U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_3A_CFG_MP_MIN_3_0_M GENMASK(3U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_3A_CFG_MP_MIN_3_0_X(x) ((x) & GENMASK(3U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_3A_CFG_MP_MAX_GEN1_3_0(x)\
	(((x) << 4U) & GENMASK(7U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_3A_CFG_MP_MAX_GEN1_3_0_M GENMASK(7U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_3A_CFG_MP_MAX_GEN1_3_0_X(x)\
	(((x) & GENMASK(7U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_3B */
#define PCIE_PHY_PMA_PMA_LANE_3B(t) ((t) + 0x4ecU)

#define PCIE_PHY_PMA_PMA_LANE_3B_CFG_MF_MIN_3_0(x) ((x) & GENMASK(3U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_3B_CFG_MF_MIN_3_0_M GENMASK(3U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_3B_CFG_MF_MIN_3_0_X(x) ((x) & GENMASK(3U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_3B_CFG_MF_MAX_3_0(x)\
	(((x) << 4U) & GENMASK(7U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_3B_CFG_MF_MAX_3_0_M GENMASK(7U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_3B_CFG_MF_MAX_3_0_X(x)\
	(((x) & GENMASK(7U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_3C */
#define PCIE_PHY_PMA_PMA_LANE_3C(t) ((t) + 0x4f0U)

#define PCIE_PHY_PMA_PMA_LANE_3C_CFG_DIS_ACC(x) ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_3C_CFG_DIS_ACC_M GENMASK(0U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_3C_CFG_DIS_ACC_X(x) ((x) & GENMASK(0U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_3C_CFG_DIS_2NDORDER_GEN1(x)\
	(((x) << 1U) & GENMASK(1U, 1U))
#define PCIE_PHY_PMA_PMA_LANE_3C_CFG_DIS_2NDORDER_GEN1_M GENMASK(1U, 1U)
#define PCIE_PHY_PMA_PMA_LANE_3C_CFG_DIS_2NDORDER_GEN1_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

#define PCIE_PHY_PMA_PMA_LANE_3C_CFG_ISCAN_EXT_DAC_B7_GEN2(x)\
	(((x) << 4U) & GENMASK(4U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_3C_CFG_ISCAN_EXT_DAC_B7_GEN2_M GENMASK(4U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_3C_CFG_ISCAN_EXT_DAC_B7_GEN2_X(x)\
	(((x) & GENMASK(4U, 4U)) >> 4U)

#define PCIE_PHY_PMA_PMA_LANE_3C_CFG_ISCAN_EXT_DAC_B7_GEN3(x)\
	(((x) << 5U) & GENMASK(5U, 5U))
#define PCIE_PHY_PMA_PMA_LANE_3C_CFG_ISCAN_EXT_DAC_B7_GEN3_M GENMASK(5U, 5U)
#define PCIE_PHY_PMA_PMA_LANE_3C_CFG_ISCAN_EXT_DAC_B7_GEN3_X(x)\
	(((x) & GENMASK(5U, 5U)) >> 5U)

#define PCIE_PHY_PMA_PMA_LANE_3C_CFG_ISCAN_EXT_DAC_B7_GEN4(x)\
	(((x) << 6U) & GENMASK(6U, 6U))
#define PCIE_PHY_PMA_PMA_LANE_3C_CFG_ISCAN_EXT_DAC_B7_GEN4_M GENMASK(6U, 6U)
#define PCIE_PHY_PMA_PMA_LANE_3C_CFG_ISCAN_EXT_DAC_B7_GEN4_X(x)\
	(((x) & GENMASK(6U, 6U)) >> 6U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_40 */
#define PCIE_PHY_PMA_PMA_LANE_40(t) ((t) + 0x500U)

#define PCIE_PHY_PMA_PMA_LANE_40_CFG_LANE_RESERVE_7_0(x) ((x) & GENMASK(7U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_40_CFG_LANE_RESERVE_7_0_M GENMASK(7U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_40_CFG_LANE_RESERVE_7_0_X(x)\
	((x) & GENMASK(7U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_41 */
#define PCIE_PHY_PMA_PMA_LANE_41(t) ((t) + 0x504U)

#define PCIE_PHY_PMA_PMA_LANE_41_CFG_LANE_RESERVE_15_8(x)\
	((x) & GENMASK(7U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_41_CFG_LANE_RESERVE_15_8_M GENMASK(7U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_41_CFG_LANE_RESERVE_15_8_X(x)\
	((x) & GENMASK(7U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_42 */
#define PCIE_PHY_PMA_PMA_LANE_42(t) ((t) + 0x508U)

#define PCIE_PHY_PMA_PMA_LANE_42_CFG_CDR_KF_GEN1_2_0(x) ((x) & GENMASK(2U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_42_CFG_CDR_KF_GEN1_2_0_M GENMASK(2U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_42_CFG_CDR_KF_GEN1_2_0_X(x)\
	((x) & GENMASK(2U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_42_CFG_CDR_KF_GEN2_2_0(x)\
	(((x) << 4U) & GENMASK(6U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_42_CFG_CDR_KF_GEN2_2_0_M GENMASK(6U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_42_CFG_CDR_KF_GEN2_2_0_X(x)\
	(((x) & GENMASK(6U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_44 */
#define PCIE_PHY_PMA_PMA_LANE_44(t) ((t) + 0x510U)

#define PCIE_PHY_PMA_PMA_LANE_44_CFG_CTLE_NEGC_GEN2(x) ((x) & GENMASK(1U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_44_CFG_CTLE_NEGC_GEN2_M GENMASK(1U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_44_CFG_CTLE_NEGC_GEN2_X(x) ((x) & GENMASK(1U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_44_CFG_CTLE_NEGC_GEN3(x)\
	(((x) << 2U) & GENMASK(3U, 2U))
#define PCIE_PHY_PMA_PMA_LANE_44_CFG_CTLE_NEGC_GEN3_M GENMASK(3U, 2U)
#define PCIE_PHY_PMA_PMA_LANE_44_CFG_CTLE_NEGC_GEN3_X(x)\
	(((x) & GENMASK(3U, 2U)) >> 2U)

#define PCIE_PHY_PMA_PMA_LANE_44_CFG_CTLE_NEGC_GEN4(x)\
	(((x) << 4U) & GENMASK(5U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_44_CFG_CTLE_NEGC_GEN4_M GENMASK(5U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_44_CFG_CTLE_NEGC_GEN4_X(x)\
	(((x) & GENMASK(5U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_45 */
#define PCIE_PHY_PMA_PMA_LANE_45(t) ((t) + 0x514U)

#define PCIE_PHY_PMA_PMA_LANE_45_CFG_IP_RX_LS_SEL_GEN2(x)\
	((x) & GENMASK(2U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_45_CFG_IP_RX_LS_SEL_GEN2_M GENMASK(2U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_45_CFG_IP_RX_LS_SEL_GEN2_X(x)\
	((x) & GENMASK(2U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_45_CFG_IP_RX_LS_SEL_GEN3(x)\
	(((x) << 4U) & GENMASK(6U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_45_CFG_IP_RX_LS_SEL_GEN3_M GENMASK(6U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_45_CFG_IP_RX_LS_SEL_GEN3_X(x)\
	(((x) & GENMASK(6U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_46 */
#define PCIE_PHY_PMA_PMA_LANE_46(t) ((t) + 0x518U)

#define PCIE_PHY_PMA_PMA_LANE_46_CFG_IP_RX_LS_SEL_GEN4(x)\
	((x) & GENMASK(2U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_46_CFG_IP_RX_LS_SEL_GEN4_M GENMASK(2U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_46_CFG_IP_RX_LS_SEL_GEN4_X(x)\
	((x) & GENMASK(2U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_47 */
#define PCIE_PHY_PMA_PMA_LANE_47(t) ((t) + 0x51cU)

#define PCIE_PHY_PMA_PMA_LANE_47_CFG_PI_EXT_DAC_B23TOB22_GEN2(x)\
	((x) & GENMASK(1U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_47_CFG_PI_EXT_DAC_B23TOB22_GEN2_M GENMASK(1U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_47_CFG_PI_EXT_DAC_B23TOB22_GEN2_X(x)\
	((x) & GENMASK(1U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_47_CFG_PI_EXT_DAC_B23TOB22_GEN3(x)\
	(((x) << 2U) & GENMASK(3U, 2U))
#define PCIE_PHY_PMA_PMA_LANE_47_CFG_PI_EXT_DAC_B23TOB22_GEN3_M GENMASK(3U, 2U)
#define PCIE_PHY_PMA_PMA_LANE_47_CFG_PI_EXT_DAC_B23TOB22_GEN3_X(x)\
	(((x) & GENMASK(3U, 2U)) >> 2U)

#define PCIE_PHY_PMA_PMA_LANE_47_CFG_PI_EXT_DAC_B23TOB22_GEN4(x)\
	(((x) << 4U) & GENMASK(5U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_47_CFG_PI_EXT_DAC_B23TOB22_GEN4_M GENMASK(5U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_47_CFG_PI_EXT_DAC_B23TOB22_GEN4_X(x)\
	(((x) & GENMASK(5U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_4A */
#define PCIE_PHY_PMA_PMA_LANE_4A(t) ((t) + 0x528U)

#define PCIE_PHY_PMA_PMA_LANE_4A_CFG_RX_SP_CTLE_1_0(x) ((x) & GENMASK(1U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_4A_CFG_RX_SP_CTLE_1_0_M GENMASK(1U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_4A_CFG_RX_SP_CTLE_1_0_X(x) ((x) & GENMASK(1U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_4A_CFG_RX_REG_BYP_GEN2(x)\
	(((x) << 4U) & GENMASK(4U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_4A_CFG_RX_REG_BYP_GEN2_M GENMASK(4U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_4A_CFG_RX_REG_BYP_GEN2_X(x)\
	(((x) & GENMASK(4U, 4U)) >> 4U)

#define PCIE_PHY_PMA_PMA_LANE_4A_CFG_RX_REG_BYP_GEN3(x)\
	(((x) << 5U) & GENMASK(5U, 5U))
#define PCIE_PHY_PMA_PMA_LANE_4A_CFG_RX_REG_BYP_GEN3_M GENMASK(5U, 5U)
#define PCIE_PHY_PMA_PMA_LANE_4A_CFG_RX_REG_BYP_GEN3_X(x)\
	(((x) & GENMASK(5U, 5U)) >> 5U)

#define PCIE_PHY_PMA_PMA_LANE_4A_CFG_RX_REG_BYP_GEN4(x)\
	(((x) << 6U) & GENMASK(6U, 6U))
#define PCIE_PHY_PMA_PMA_LANE_4A_CFG_RX_REG_BYP_GEN4_M GENMASK(6U, 6U)
#define PCIE_PHY_PMA_PMA_LANE_4A_CFG_RX_REG_BYP_GEN4_X(x)\
	(((x) & GENMASK(6U, 6U)) >> 6U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_51 */
#define PCIE_PHY_PMA_PMA_LANE_51(t) ((t) + 0x544U)

#define PCIE_PHY_PMA_PMA_LANE_51_CFG_EQC_FORCE_GEN2(x) ((x) & GENMASK(3U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_51_CFG_EQC_FORCE_GEN2_M GENMASK(3U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_51_CFG_EQC_FORCE_GEN2_X(x) ((x) & GENMASK(3U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_51_CFG_EQC_FORCE_GEN3(x)\
	(((x) << 4U) & GENMASK(7U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_51_CFG_EQC_FORCE_GEN3_M GENMASK(7U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_51_CFG_EQC_FORCE_GEN3_X(x)\
	(((x) & GENMASK(7U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_52 */
#define PCIE_PHY_PMA_PMA_LANE_52(t) ((t) + 0x548U)

#define PCIE_PHY_PMA_PMA_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0(x)\
	((x) & GENMASK(5U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_M GENMASK(5U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_X(x)\
	((x) & GENMASK(5U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_55 */
#define PCIE_PHY_PMA_PMA_LANE_55(t) ((t) + 0x554U)

#define PCIE_PHY_PMA_PMA_LANE_55_CFG_EQC_FORCE_GEN4(x) ((x) & GENMASK(3U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_55_CFG_EQC_FORCE_GEN4_M GENMASK(3U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_55_CFG_EQC_FORCE_GEN4_X(x) ((x) & GENMASK(3U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_55_CFG_EN_PREDRV_EMPH_GEN2(x)\
	(((x) << 4U) & GENMASK(4U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_55_CFG_EN_PREDRV_EMPH_GEN2_M GENMASK(4U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_55_CFG_EN_PREDRV_EMPH_GEN2_X(x)\
	(((x) & GENMASK(4U, 4U)) >> 4U)

#define PCIE_PHY_PMA_PMA_LANE_55_CFG_EN_PREDRV_EMPH_GEN3(x)\
	(((x) << 5U) & GENMASK(5U, 5U))
#define PCIE_PHY_PMA_PMA_LANE_55_CFG_EN_PREDRV_EMPH_GEN3_M GENMASK(5U, 5U)
#define PCIE_PHY_PMA_PMA_LANE_55_CFG_EN_PREDRV_EMPH_GEN3_X(x)\
	(((x) & GENMASK(5U, 5U)) >> 5U)

#define PCIE_PHY_PMA_PMA_LANE_55_CFG_EN_PREDRV_EMPH_GEN4(x)\
	(((x) << 6U) & GENMASK(6U, 6U))
#define PCIE_PHY_PMA_PMA_LANE_55_CFG_EN_PREDRV_EMPH_GEN4_M GENMASK(6U, 6U)
#define PCIE_PHY_PMA_PMA_LANE_55_CFG_EN_PREDRV_EMPH_GEN4_X(x)\
	(((x) & GENMASK(6U, 6U)) >> 6U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_56 */
#define PCIE_PHY_PMA_PMA_LANE_56(t) ((t) + 0x558U)

#define PCIE_PHY_PMA_PMA_LANE_56_CFG_VGA_CTRL_GEN2(x) ((x) & GENMASK(3U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_56_CFG_VGA_CTRL_GEN2_M GENMASK(3U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_56_CFG_VGA_CTRL_GEN2_X(x) ((x) & GENMASK(3U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_56_CFG_VGA_CTRL_GEN3(x)\
	(((x) << 4U) & GENMASK(7U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_56_CFG_VGA_CTRL_GEN3_M GENMASK(7U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_56_CFG_VGA_CTRL_GEN3_X(x)\
	(((x) & GENMASK(7U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_57 */
#define PCIE_PHY_PMA_PMA_LANE_57(t) ((t) + 0x55cU)

#define PCIE_PHY_PMA_PMA_LANE_57_CFG_VGA_CTRL_GEN4(x) ((x) & GENMASK(3U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_57_CFG_VGA_CTRL_GEN4_M GENMASK(3U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_57_CFG_VGA_CTRL_GEN4_X(x) ((x) & GENMASK(3U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_6E */
#define PCIE_PHY_PMA_PMA_LANE_6E(t) ((t) + 0x5b8U)

#define PCIE_PHY_PMA_PMA_LANE_6E_CFG_MF_MIN_GEN2(x) ((x) & GENMASK(3U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_6E_CFG_MF_MIN_GEN2_M GENMASK(3U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_6E_CFG_MF_MIN_GEN2_X(x) ((x) & GENMASK(3U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_6E_CFG_MF_MIN_GEN3(x)\
	(((x) << 4U) & GENMASK(7U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_6E_CFG_MF_MIN_GEN3_M GENMASK(7U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_6E_CFG_MF_MIN_GEN3_X(x)\
	(((x) & GENMASK(7U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_6F */
#define PCIE_PHY_PMA_PMA_LANE_6F(t) ((t) + 0x5bcU)

#define PCIE_PHY_PMA_PMA_LANE_6F_CFG_MF_MIN_GEN4(x) ((x) & GENMASK(3U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_6F_CFG_MF_MIN_GEN4_M GENMASK(3U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_6F_CFG_MF_MIN_GEN4_X(x) ((x) & GENMASK(3U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_70 */
#define PCIE_PHY_PMA_PMA_LANE_70(t) ((t) + 0x5c0U)

#define PCIE_PHY_PMA_PMA_LANE_70_CFG_RX_SP_CTLE_GEN2(x) ((x) & GENMASK(1U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_70_CFG_RX_SP_CTLE_GEN2_M GENMASK(1U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_70_CFG_RX_SP_CTLE_GEN2_X(x)\
	((x) & GENMASK(1U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_70_CFG_RX_SP_CTLE_GEN3(x)\
	(((x) << 2U) & GENMASK(3U, 2U))
#define PCIE_PHY_PMA_PMA_LANE_70_CFG_RX_SP_CTLE_GEN3_M GENMASK(3U, 2U)
#define PCIE_PHY_PMA_PMA_LANE_70_CFG_RX_SP_CTLE_GEN3_X(x)\
	(((x) & GENMASK(3U, 2U)) >> 2U)

#define PCIE_PHY_PMA_PMA_LANE_70_CFG_RX_SP_CTLE_GEN4(x)\
	(((x) << 4U) & GENMASK(5U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_70_CFG_RX_SP_CTLE_GEN4_M GENMASK(5U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_70_CFG_RX_SP_CTLE_GEN4_X(x)\
	(((x) & GENMASK(5U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_71 */
#define PCIE_PHY_PMA_PMA_LANE_71(t) ((t) + 0x5c4U)

#define PCIE_PHY_PMA_PMA_LANE_71_CFG_PI_EXT_DAC_B20TOB18_GEN2(x)\
	((x) & GENMASK(2U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_71_CFG_PI_EXT_DAC_B20TOB18_GEN2_M GENMASK(2U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_71_CFG_PI_EXT_DAC_B20TOB18_GEN2_X(x)\
	((x) & GENMASK(2U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_71_CFG_PI_EXT_DAC_B20TOB18_GEN3(x)\
	(((x) << 4U) & GENMASK(6U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_71_CFG_PI_EXT_DAC_B20TOB18_GEN3_M GENMASK(6U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_71_CFG_PI_EXT_DAC_B20TOB18_GEN3_X(x)\
	(((x) & GENMASK(6U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_72 */
#define PCIE_PHY_PMA_PMA_LANE_72(t) ((t) + 0x5c8U)

#define PCIE_PHY_PMA_PMA_LANE_72_CFG_PI_EXT_DAC_B20TOB18_GEN4(x)\
	((x) & GENMASK(2U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_72_CFG_PI_EXT_DAC_B20TOB18_GEN4_M GENMASK(2U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_72_CFG_PI_EXT_DAC_B20TOB18_GEN4_X(x)\
	((x) & GENMASK(2U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_73 */
#define PCIE_PHY_PMA_PMA_LANE_73(t) ((t) + 0x5ccU)

#define PCIE_PHY_PMA_PMA_LANE_73_CFG_ITX_IPDRIVER_BASE_GEN2(x)\
	((x) & GENMASK(2U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_73_CFG_ITX_IPDRIVER_BASE_GEN2_M GENMASK(2U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_73_CFG_ITX_IPDRIVER_BASE_GEN2_X(x)\
	((x) & GENMASK(2U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_73_CFG_ITX_IPDRIVER_BASE_GEN3(x)\
	(((x) << 4U) & GENMASK(6U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_73_CFG_ITX_IPDRIVER_BASE_GEN3_M GENMASK(6U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_73_CFG_ITX_IPDRIVER_BASE_GEN3_X(x)\
	(((x) & GENMASK(6U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_78 */
#define PCIE_PHY_PMA_PMA_LANE_78(t) ((t) + 0x5e0U)

#define PCIE_PHY_PMA_PMA_LANE_78_R_TIME_DEASSERT_7_0(x) ((x) & GENMASK(7U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_78_R_TIME_DEASSERT_7_0_M GENMASK(7U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_78_R_TIME_DEASSERT_7_0_X(x)\
	((x) & GENMASK(7U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_79 */
#define PCIE_PHY_PMA_PMA_LANE_79(t) ((t) + 0x5e4U)

#define PCIE_PHY_PMA_PMA_LANE_79_R_TIME_DEASSERT_15_8(x) ((x) & GENMASK(7U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_79_R_TIME_DEASSERT_15_8_M GENMASK(7U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_79_R_TIME_DEASSERT_15_8_X(x)\
	((x) & GENMASK(7U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_7A */
#define PCIE_PHY_PMA_PMA_LANE_7A(t) ((t) + 0x5e8U)

#define PCIE_PHY_PMA_PMA_LANE_7A_R_TIME_ASSERT_7_0(x) ((x) & GENMASK(7U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_7A_R_TIME_ASSERT_7_0_M GENMASK(7U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_7A_R_TIME_ASSERT_7_0_X(x) ((x) & GENMASK(7U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_7B */
#define PCIE_PHY_PMA_PMA_LANE_7B(t) ((t) + 0x5ecU)

#define PCIE_PHY_PMA_PMA_LANE_7B_R_TIME_ASSERT_15_8(x) ((x) & GENMASK(7U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_7B_R_TIME_ASSERT_15_8_M GENMASK(7U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_7B_R_TIME_ASSERT_15_8_X(x) ((x) & GENMASK(7U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_7D */
#define PCIE_PHY_PMA_PMA_LANE_7D(t) ((t) + 0x5f4U)

#define PCIE_PHY_PMA_PMA_LANE_7D_R_DEASSERT_PPM_7_0(x) ((x) & GENMASK(7U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_7D_R_DEASSERT_PPM_7_0_M GENMASK(7U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_7D_R_DEASSERT_PPM_7_0_X(x) ((x) & GENMASK(7U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_7E */
#define PCIE_PHY_PMA_PMA_LANE_7E(t) ((t) + 0x5f8U)

#define PCIE_PHY_PMA_PMA_LANE_7E_R_DEASSERT_PPM_9_8(x) ((x) & GENMASK(1U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_7E_R_DEASSERT_PPM_9_8_M GENMASK(1U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_7E_R_DEASSERT_PPM_9_8_X(x) ((x) & GENMASK(1U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_7F */
#define PCIE_PHY_PMA_PMA_LANE_7F(t) ((t) + 0x5fcU)

#define PCIE_PHY_PMA_PMA_LANE_7F_R_ASSERT_PPM_7_0(x) ((x) & GENMASK(7U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_7F_R_ASSERT_PPM_7_0_M GENMASK(7U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_7F_R_ASSERT_PPM_7_0_X(x) ((x) & GENMASK(7U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_80 */
#define PCIE_PHY_PMA_PMA_LANE_80(t) ((t) + 0x600U)

#define PCIE_PHY_PMA_PMA_LANE_80_R_ASSERT_PPM_9_8(x) ((x) & GENMASK(1U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_80_R_ASSERT_PPM_9_8_M GENMASK(1U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_80_R_ASSERT_PPM_9_8_X(x) ((x) & GENMASK(1U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_82 */
#define PCIE_PHY_PMA_PMA_LANE_82(t) ((t) + 0x608U)

#define PCIE_PHY_PMA_PMA_LANE_82_R_TIME_LOS_2_0(x) ((x) & GENMASK(2U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_82_R_TIME_LOS_2_0_M GENMASK(2U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_82_R_TIME_LOS_2_0_X(x) ((x) & GENMASK(2U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_82_R_ALOS_EN(x) (((x) << 4U) & GENMASK(4U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_82_R_ALOS_EN_M GENMASK(4U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_82_R_ALOS_EN_X(x) (((x) & GENMASK(4U, 4U)) >> 4U)

#define PCIE_PHY_PMA_PMA_LANE_82_R_LOL_RESET(x) (((x) << 5U) & GENMASK(5U, 5U))
#define PCIE_PHY_PMA_PMA_LANE_82_R_LOL_RESET_M GENMASK(5U, 5U)
#define PCIE_PHY_PMA_PMA_LANE_82_R_LOL_RESET_X(x)\
	(((x) & GENMASK(5U, 5U)) >> 5U)

#define PCIE_PHY_PMA_PMA_LANE_82_R_TX_RSTN(x) (((x) << 6U) & GENMASK(6U, 6U))
#define PCIE_PHY_PMA_PMA_LANE_82_R_TX_RSTN_M GENMASK(6U, 6U)
#define PCIE_PHY_PMA_PMA_LANE_82_R_TX_RSTN_X(x) (((x) & GENMASK(6U, 6U)) >> 6U)

#define PCIE_PHY_PMA_PMA_LANE_82_R_RX_RSTN(x) (((x) << 7U) & GENMASK(7U, 7U))
#define PCIE_PHY_PMA_PMA_LANE_82_R_RX_RSTN_M GENMASK(7U, 7U)
#define PCIE_PHY_PMA_PMA_LANE_82_R_RX_RSTN_X(x) (((x) & GENMASK(7U, 7U)) >> 7U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_83 */
#define PCIE_PHY_PMA_PMA_LANE_83(t) ((t) + 0x60cU)

#define PCIE_PHY_PMA_PMA_LANE_83_R_TX_BIT_REVERSE(x) ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_83_R_TX_BIT_REVERSE_M GENMASK(0U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_83_R_TX_BIT_REVERSE_X(x) ((x) & GENMASK(0U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_83_R_TX_POL_INV(x) (((x) << 1U) & GENMASK(1U, 1U))
#define PCIE_PHY_PMA_PMA_LANE_83_R_TX_POL_INV_M GENMASK(1U, 1U)
#define PCIE_PHY_PMA_PMA_LANE_83_R_TX_POL_INV_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

#define PCIE_PHY_PMA_PMA_LANE_83_R_RX_BIT_REVERSE(x)\
	(((x) << 2U) & GENMASK(2U, 2U))
#define PCIE_PHY_PMA_PMA_LANE_83_R_RX_BIT_REVERSE_M GENMASK(2U, 2U)
#define PCIE_PHY_PMA_PMA_LANE_83_R_RX_BIT_REVERSE_X(x)\
	(((x) & GENMASK(2U, 2U)) >> 2U)

#define PCIE_PHY_PMA_PMA_LANE_83_R_RX_POL_INV(x) (((x) << 3U) & GENMASK(3U, 3U))
#define PCIE_PHY_PMA_PMA_LANE_83_R_RX_POL_INV_M GENMASK(3U, 3U)
#define PCIE_PHY_PMA_PMA_LANE_83_R_RX_POL_INV_X(x)\
	(((x) & GENMASK(3U, 3U)) >> 3U)

#define PCIE_PHY_PMA_PMA_LANE_83_R_DFE_RSTN(x) (((x) << 4U) & GENMASK(4U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_83_R_DFE_RSTN_M GENMASK(4U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_83_R_DFE_RSTN_X(x) (((x) & GENMASK(4U, 4U)) >> 4U)

#define PCIE_PHY_PMA_PMA_LANE_83_R_CDR_RSTN(x) (((x) << 5U) & GENMASK(5U, 5U))
#define PCIE_PHY_PMA_PMA_LANE_83_R_CDR_RSTN_M GENMASK(5U, 5U)
#define PCIE_PHY_PMA_PMA_LANE_83_R_CDR_RSTN_X(x) (((x) & GENMASK(5U, 5U)) >> 5U)

#define PCIE_PHY_PMA_PMA_LANE_83_R_CTLE_RSTN(x) (((x) << 6U) & GENMASK(6U, 6U))
#define PCIE_PHY_PMA_PMA_LANE_83_R_CTLE_RSTN_M GENMASK(6U, 6U)
#define PCIE_PHY_PMA_PMA_LANE_83_R_CTLE_RSTN_X(x)\
	(((x) & GENMASK(6U, 6U)) >> 6U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_84 */
#define PCIE_PHY_PMA_PMA_LANE_84(t) ((t) + 0x610U)

#define PCIE_PHY_PMA_PMA_LANE_84_R_TXEI(x)  ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_84_R_TXEI_M   GENMASK(0U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_84_R_TXEI_X(x) ((x) & GENMASK(0U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_84_R_LOL_CLR(x) (((x) << 1U) & GENMASK(1U, 1U))
#define PCIE_PHY_PMA_PMA_LANE_84_R_LOL_CLR_M GENMASK(1U, 1U)
#define PCIE_PHY_PMA_PMA_LANE_84_R_LOL_CLR_X(x) (((x) & GENMASK(1U, 1U)) >> 1U)

#define PCIE_PHY_PMA_PMA_LANE_84_R_LOGICAL_RXEI_SEL(x)\
	(((x) << 4U) & GENMASK(5U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_84_R_LOGICAL_RXEI_SEL_M GENMASK(5U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_84_R_LOGICAL_RXEI_SEL_X(x)\
	(((x) & GENMASK(5U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_90 */
#define PCIE_PHY_PMA_PMA_LANE_90(t) ((t) + 0x640U)

#define PCIE_PHY_PMA_PMA_LANE_90_R_CLK_OUT_SEL_1_0(x) ((x) & GENMASK(1U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_90_R_CLK_OUT_SEL_1_0_M GENMASK(1U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_90_R_CLK_OUT_SEL_1_0_X(x) ((x) & GENMASK(1U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_90_R_EN_PWRCHG_RST_TIMER(x)\
	(((x) << 4U) & GENMASK(4U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_90_R_EN_PWRCHG_RST_TIMER_M GENMASK(4U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_90_R_EN_PWRCHG_RST_TIMER_X(x)\
	(((x) & GENMASK(4U, 4U)) >> 4U)

#define PCIE_PHY_PMA_PMA_LANE_90_R_OSCAL_REG(x) (((x) << 5U) & GENMASK(5U, 5U))
#define PCIE_PHY_PMA_PMA_LANE_90_R_OSCAL_REG_M GENMASK(5U, 5U)
#define PCIE_PHY_PMA_PMA_LANE_90_R_OSCAL_REG_X(x)\
	(((x) & GENMASK(5U, 5U)) >> 5U)

#define PCIE_PHY_PMA_PMA_LANE_90_R_AUTO_OSCAL_AFE(x)\
	(((x) << 6U) & GENMASK(6U, 6U))
#define PCIE_PHY_PMA_PMA_LANE_90_R_AUTO_OSCAL_AFE_M GENMASK(6U, 6U)
#define PCIE_PHY_PMA_PMA_LANE_90_R_AUTO_OSCAL_AFE_X(x)\
	(((x) & GENMASK(6U, 6U)) >> 6U)

#define PCIE_PHY_PMA_PMA_LANE_90_R_AUTO_OSCAL_SQ(x)\
	(((x) << 7U) & GENMASK(7U, 7U))
#define PCIE_PHY_PMA_PMA_LANE_90_R_AUTO_OSCAL_SQ_M GENMASK(7U, 7U)
#define PCIE_PHY_PMA_PMA_LANE_90_R_AUTO_OSCAL_SQ_X(x)\
	(((x) & GENMASK(7U, 7U)) >> 7U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_93 */
#define PCIE_PHY_PMA_PMA_LANE_93(t) ((t) + 0x64cU)

#define PCIE_PHY_PMA_PMA_LANE_93_R_RXEI_FIFO_RST_EN(x) ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_93_R_RXEI_FIFO_RST_EN_M GENMASK(0U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_93_R_RXEI_FIFO_RST_EN_X(x) ((x) & GENMASK(0U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_93_R_DWIDTHCTRL_FROM_HWT(x)\
	(((x) << 1U) & GENMASK(1U, 1U))
#define PCIE_PHY_PMA_PMA_LANE_93_R_DWIDTHCTRL_FROM_HWT_M GENMASK(1U, 1U)
#define PCIE_PHY_PMA_PMA_LANE_93_R_DWIDTHCTRL_FROM_HWT_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

#define PCIE_PHY_PMA_PMA_LANE_93_R_DIS_RESTORE_DFE(x)\
	(((x) << 2U) & GENMASK(2U, 2U))
#define PCIE_PHY_PMA_PMA_LANE_93_R_DIS_RESTORE_DFE_M GENMASK(2U, 2U)
#define PCIE_PHY_PMA_PMA_LANE_93_R_DIS_RESTORE_DFE_X(x)\
	(((x) & GENMASK(2U, 2U)) >> 2U)

#define PCIE_PHY_PMA_PMA_LANE_93_R_EN_RATECHG_CTRL(x)\
	(((x) << 3U) & GENMASK(3U, 3U))
#define PCIE_PHY_PMA_PMA_LANE_93_R_EN_RATECHG_CTRL_M GENMASK(3U, 3U)
#define PCIE_PHY_PMA_PMA_LANE_93_R_EN_RATECHG_CTRL_X(x)\
	(((x) & GENMASK(3U, 3U)) >> 3U)

#define PCIE_PHY_PMA_PMA_LANE_93_R_REG_MANUAL(x) (((x) << 4U) & GENMASK(4U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_93_R_REG_MANUAL_M GENMASK(4U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_93_R_REG_MANUAL_X(x)\
	(((x) & GENMASK(4U, 4U)) >> 4U)

#define PCIE_PHY_PMA_PMA_LANE_93_R_AUXCKSEL_FROM_HWT(x)\
	(((x) << 5U) & GENMASK(5U, 5U))
#define PCIE_PHY_PMA_PMA_LANE_93_R_AUXCKSEL_FROM_HWT_M GENMASK(5U, 5U)
#define PCIE_PHY_PMA_PMA_LANE_93_R_AUXCKSEL_FROM_HWT_X(x)\
	(((x) & GENMASK(5U, 5U)) >> 5U)

#define PCIE_PHY_PMA_PMA_LANE_93_R_LANE_ID_FROM_HWT(x)\
	(((x) << 6U) & GENMASK(6U, 6U))
#define PCIE_PHY_PMA_PMA_LANE_93_R_LANE_ID_FROM_HWT_M GENMASK(6U, 6U)
#define PCIE_PHY_PMA_PMA_LANE_93_R_LANE_ID_FROM_HWT_X(x)\
	(((x) & GENMASK(6U, 6U)) >> 6U)

#define PCIE_PHY_PMA_PMA_LANE_93_R_RX_PCIE_GEN12_FROM_HWT(x)\
	(((x) << 7U) & GENMASK(7U, 7U))
#define PCIE_PHY_PMA_PMA_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_M GENMASK(7U, 7U)
#define PCIE_PHY_PMA_PMA_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_X(x)\
	(((x) & GENMASK(7U, 7U)) >> 7U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_9F */
#define PCIE_PHY_PMA_PMA_LANE_9F(t) ((t) + 0x67cU)

#define PCIE_PHY_PMA_PMA_LANE_9F_R_ALOS_THR_FROM_HWT(x) ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_9F_R_ALOS_THR_FROM_HWT_M GENMASK(0U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_9F_R_ALOS_THR_FROM_HWT_X(x)\
	((x) & GENMASK(0U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_9F_R_RXDET_REG(x) (((x) << 1U) & GENMASK(1U, 1U))
#define PCIE_PHY_PMA_PMA_LANE_9F_R_RXDET_REG_M GENMASK(1U, 1U)
#define PCIE_PHY_PMA_PMA_LANE_9F_R_RXDET_REG_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

#define PCIE_PHY_PMA_PMA_LANE_9F_R_SWING_RATECHG_REG(x)\
	(((x) << 2U) & GENMASK(2U, 2U))
#define PCIE_PHY_PMA_PMA_LANE_9F_R_SWING_RATECHG_REG_M GENMASK(2U, 2U)
#define PCIE_PHY_PMA_PMA_LANE_9F_R_SWING_RATECHG_REG_X(x)\
	(((x) & GENMASK(2U, 2U)) >> 2U)

#define PCIE_PHY_PMA_PMA_LANE_9F_R_TXEQ_RATECHG_REG(x)\
	(((x) << 3U) & GENMASK(3U, 3U))
#define PCIE_PHY_PMA_PMA_LANE_9F_R_TXEQ_RATECHG_REG_M GENMASK(3U, 3U)
#define PCIE_PHY_PMA_PMA_LANE_9F_R_TXEQ_RATECHG_REG_X(x)\
	(((x) & GENMASK(3U, 3U)) >> 3U)

#define PCIE_PHY_PMA_PMA_LANE_9F_R_RXEQ_RATECHG_REG(x)\
	(((x) << 4U) & GENMASK(4U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_9F_R_RXEQ_RATECHG_REG_M GENMASK(4U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_9F_R_RXEQ_RATECHG_REG_X(x)\
	(((x) & GENMASK(4U, 4U)) >> 4U)

#define PCIE_PHY_PMA_PMA_LANE_9F_R_PI_HOLD_REG(x)\
	(((x) << 5U) & GENMASK(5U, 5U))
#define PCIE_PHY_PMA_PMA_LANE_9F_R_PI_HOLD_REG_M GENMASK(5U, 5U)
#define PCIE_PHY_PMA_PMA_LANE_9F_R_PI_HOLD_REG_X(x)\
	(((x) & GENMASK(5U, 5U)) >> 5U)

#define PCIE_PHY_PMA_PMA_LANE_9F_R_SUM_SETCM_EN_REG(x)\
	(((x) << 6U) & GENMASK(6U, 6U))
#define PCIE_PHY_PMA_PMA_LANE_9F_R_SUM_SETCM_EN_REG_M GENMASK(6U, 6U)
#define PCIE_PHY_PMA_PMA_LANE_9F_R_SUM_SETCM_EN_REG_X(x)\
	(((x) & GENMASK(6U, 6U)) >> 6U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_A1 */
#define PCIE_PHY_PMA_PMA_LANE_A1(t) ((t) + 0x684U)

#define PCIE_PHY_PMA_PMA_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0(x)\
	((x) & GENMASK(1U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_M GENMASK(1U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_X(x)\
	((x) & GENMASK(1U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_A1_R_SSC_FROM_HWT(x)\
	(((x) << 4U) & GENMASK(4U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_A1_R_SSC_FROM_HWT_M GENMASK(4U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_A1_R_SSC_FROM_HWT_X(x)\
	(((x) & GENMASK(4U, 4U)) >> 4U)

#define PCIE_PHY_PMA_PMA_LANE_A1_R_CDR_FROM_HWT(x)\
	(((x) << 5U) & GENMASK(5U, 5U))
#define PCIE_PHY_PMA_PMA_LANE_A1_R_CDR_FROM_HWT_M GENMASK(5U, 5U)
#define PCIE_PHY_PMA_PMA_LANE_A1_R_CDR_FROM_HWT_X(x)\
	(((x) & GENMASK(5U, 5U)) >> 5U)

#define PCIE_PHY_PMA_PMA_LANE_A1_R_PCLK_GATING_FROM_HWT(x)\
	(((x) << 6U) & GENMASK(6U, 6U))
#define PCIE_PHY_PMA_PMA_LANE_A1_R_PCLK_GATING_FROM_HWT_M GENMASK(6U, 6U)
#define PCIE_PHY_PMA_PMA_LANE_A1_R_PCLK_GATING_FROM_HWT_X(x)\
	(((x) & GENMASK(6U, 6U)) >> 6U)

#define PCIE_PHY_PMA_PMA_LANE_A1_R_PCLK_GATING(x)\
	(((x) << 7U) & GENMASK(7U, 7U))
#define PCIE_PHY_PMA_PMA_LANE_A1_R_PCLK_GATING_M GENMASK(7U, 7U)
#define PCIE_PHY_PMA_PMA_LANE_A1_R_PCLK_GATING_X(x)\
	(((x) & GENMASK(7U, 7U)) >> 7U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_A2 */
#define PCIE_PHY_PMA_PMA_LANE_A2(t) ((t) + 0x688U)

#define PCIE_PHY_PMA_PMA_LANE_A2_R_PCS2PMA_PHYMODE_4_0(x)\
	((x) & GENMASK(4U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_A2_R_PCS2PMA_PHYMODE_4_0_M GENMASK(4U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_A2_R_PCS2PMA_PHYMODE_4_0_X(x)\
	((x) & GENMASK(4U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_A7 */
#define PCIE_PHY_PMA_PMA_LANE_A7(t) ((t) + 0x69cU)

#define PCIE_PHY_PMA_PMA_LANE_A7_CFG_PI_FLOOP_STEPS_GEN2_1_0(x)\
	((x) & GENMASK(1U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_A7_CFG_PI_FLOOP_STEPS_GEN2_1_0_M GENMASK(1U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_A7_CFG_PI_FLOOP_STEPS_GEN2_1_0_X(x)\
	((x) & GENMASK(1U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_A7_CFG_PI_FLOOP_STEPS_GEN3_1_0(x)\
	(((x) << 4U) & GENMASK(5U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_A7_CFG_PI_FLOOP_STEPS_GEN3_1_0_M GENMASK(5U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_A7_CFG_PI_FLOOP_STEPS_GEN3_1_0_X(x)\
	(((x) & GENMASK(5U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_A8 */
#define PCIE_PHY_PMA_PMA_LANE_A8(t) ((t) + 0x6a0U)

#define PCIE_PHY_PMA_PMA_LANE_A8_CFG_PI_FLOOP_STEPS_GEN4_1_0(x)\
	((x) & GENMASK(1U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_A8_CFG_PI_FLOOP_STEPS_GEN4_1_0_M GENMASK(1U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_A8_CFG_PI_FLOOP_STEPS_GEN4_1_0_X(x)\
	((x) & GENMASK(1U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_A9 */
#define PCIE_PHY_PMA_PMA_LANE_A9(t) ((t) + 0x6a4U)

#define PCIE_PHY_PMA_PMA_LANE_A9_CFG_ISCAN_EXT_DAC_B12TOB8_GEN2_4_0(x)\
	((x) & GENMASK(4U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_A9_CFG_ISCAN_EXT_DAC_B12TOB8_GEN2_4_0_M\
	GENMASK(4U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_A9_CFG_ISCAN_EXT_DAC_B12TOB8_GEN2_4_0_X(x)\
	((x) & GENMASK(4U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_AA */
#define PCIE_PHY_PMA_PMA_LANE_AA(t) ((t) + 0x6a8U)

#define PCIE_PHY_PMA_PMA_LANE_AA_CFG_ISCAN_EXT_DAC_B12TOB8_GEN3_4_0(x)\
	((x) & GENMASK(4U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_AA_CFG_ISCAN_EXT_DAC_B12TOB8_GEN3_4_0_M\
	GENMASK(4U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_AA_CFG_ISCAN_EXT_DAC_B12TOB8_GEN3_4_0_X(x)\
	((x) & GENMASK(4U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_AB */
#define PCIE_PHY_PMA_PMA_LANE_AB(t) ((t) + 0x6acU)

#define PCIE_PHY_PMA_PMA_LANE_AB_CFG_ISCAN_EXT_DAC_B12TOB8_GEN4_4_0(x)\
	((x) & GENMASK(4U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_AB_CFG_ISCAN_EXT_DAC_B12TOB8_GEN4_4_0_M\
	GENMASK(4U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_AB_CFG_ISCAN_EXT_DAC_B12TOB8_GEN4_4_0_X(x)\
	((x) & GENMASK(4U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_AE */
#define PCIE_PHY_PMA_PMA_LANE_AE(t) ((t) + 0x6b8U)

#define PCIE_PHY_PMA_PMA_LANE_AE_CFG_ITX_IPDRIVER_BASE_GEN4(x)\
	((x) & GENMASK(2U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_AE_CFG_ITX_IPDRIVER_BASE_GEN4_M GENMASK(2U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_AE_CFG_ITX_IPDRIVER_BASE_GEN4_X(x)\
	((x) & GENMASK(2U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_AE_CFG_VGA_CAP_GEN2(x)\
	(((x) << 4U) & GENMASK(6U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_AE_CFG_VGA_CAP_GEN2_M GENMASK(6U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_AE_CFG_VGA_CAP_GEN2_X(x)\
	(((x) & GENMASK(6U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_AF */
#define PCIE_PHY_PMA_PMA_LANE_AF(t) ((t) + 0x6bcU)

#define PCIE_PHY_PMA_PMA_LANE_AF_CFG_VGA_CAP_GEN3(x) ((x) & GENMASK(2U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_AF_CFG_VGA_CAP_GEN3_M GENMASK(2U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_AF_CFG_VGA_CAP_GEN3_X(x) ((x) & GENMASK(2U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_AF_CFG_VGA_CAP_GEN4(x)\
	(((x) << 4U) & GENMASK(6U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_AF_CFG_VGA_CAP_GEN4_M GENMASK(6U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_AF_CFG_VGA_CAP_GEN4_X(x)\
	(((x) & GENMASK(6U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_B0 */
#define PCIE_PHY_PMA_PMA_LANE_B0(t) ((t) + 0x6c0U)

#define PCIE_PHY_PMA_PMA_LANE_B0_CFG_RXFILT_Z_GEN2_1_0(x)\
	((x) & GENMASK(1U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_B0_CFG_RXFILT_Z_GEN2_1_0_M GENMASK(1U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_B0_CFG_RXFILT_Z_GEN2_1_0_X(x)\
	((x) & GENMASK(1U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_B0_CFG_RXFILT_Z_GEN3_1_0(x)\
	(((x) << 4U) & GENMASK(5U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_B0_CFG_RXFILT_Z_GEN3_1_0_M GENMASK(5U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_B0_CFG_RXFILT_Z_GEN3_1_0_X(x)\
	(((x) & GENMASK(5U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_B1 */
#define PCIE_PHY_PMA_PMA_LANE_B1(t) ((t) + 0x6c4U)

#define PCIE_PHY_PMA_PMA_LANE_B1_CFG_RXFILT_Z_GEN4_1_0(x)\
	((x) & GENMASK(1U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_B1_CFG_RXFILT_Z_GEN4_1_0_M GENMASK(1U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_B1_CFG_RXFILT_Z_GEN4_1_0_X(x)\
	((x) & GENMASK(1U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_B1_CFG_DIS_2NDORDER_GEN2(x)\
	(((x) << 4U) & GENMASK(4U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_B1_CFG_DIS_2NDORDER_GEN2_M GENMASK(4U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_B1_CFG_DIS_2NDORDER_GEN2_X(x)\
	(((x) & GENMASK(4U, 4U)) >> 4U)

#define PCIE_PHY_PMA_PMA_LANE_B1_CFG_DIS_2NDORDER_GEN3(x)\
	(((x) << 5U) & GENMASK(5U, 5U))
#define PCIE_PHY_PMA_PMA_LANE_B1_CFG_DIS_2NDORDER_GEN3_M GENMASK(5U, 5U)
#define PCIE_PHY_PMA_PMA_LANE_B1_CFG_DIS_2NDORDER_GEN3_X(x)\
	(((x) & GENMASK(5U, 5U)) >> 5U)

#define PCIE_PHY_PMA_PMA_LANE_B1_CFG_DIS_2NDORDER_GEN4(x)\
	(((x) << 6U) & GENMASK(6U, 6U))
#define PCIE_PHY_PMA_PMA_LANE_B1_CFG_DIS_2NDORDER_GEN4_M GENMASK(6U, 6U)
#define PCIE_PHY_PMA_PMA_LANE_B1_CFG_DIS_2NDORDER_GEN4_X(x)\
	(((x) & GENMASK(6U, 6U)) >> 6U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_B2 */
#define PCIE_PHY_PMA_PMA_LANE_B2(t) ((t) + 0x6c8U)

#define PCIE_PHY_PMA_PMA_LANE_B2_CFG_PI_EXT_DAC_B17TOB14_GEN2_3_0(x)\
	((x) & GENMASK(3U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_B2_CFG_PI_EXT_DAC_B17TOB14_GEN2_3_0_M\
	GENMASK(3U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_B2_CFG_PI_EXT_DAC_B17TOB14_GEN2_3_0_X(x)\
	((x) & GENMASK(3U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_B2_CFG_PI_EXT_DAC_B17TOB14_GEN3_3_0(x)\
	(((x) << 4U) & GENMASK(7U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_B2_CFG_PI_EXT_DAC_B17TOB14_GEN3_3_0_M\
	GENMASK(7U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_B2_CFG_PI_EXT_DAC_B17TOB14_GEN3_3_0_X(x)\
	(((x) & GENMASK(7U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_B3 */
#define PCIE_PHY_PMA_PMA_LANE_B3(t) ((t) + 0x6ccU)

#define PCIE_PHY_PMA_PMA_LANE_B3_CFG_PI_EXT_DAC_B17TOB14_GEN4_3_0(x)\
	((x) & GENMASK(3U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_B3_CFG_PI_EXT_DAC_B17TOB14_GEN4_3_0_M\
	GENMASK(3U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_B3_CFG_PI_EXT_DAC_B17TOB14_GEN4_3_0_X(x)\
	((x) & GENMASK(3U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_B3_CFG_PI_EXT_DAC_B21_GEN2(x)\
	(((x) << 4U) & GENMASK(4U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_B3_CFG_PI_EXT_DAC_B21_GEN2_M GENMASK(4U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_B3_CFG_PI_EXT_DAC_B21_GEN2_X(x)\
	(((x) & GENMASK(4U, 4U)) >> 4U)

#define PCIE_PHY_PMA_PMA_LANE_B3_CFG_PI_EXT_DAC_B21_GEN3(x)\
	(((x) << 5U) & GENMASK(5U, 5U))
#define PCIE_PHY_PMA_PMA_LANE_B3_CFG_PI_EXT_DAC_B21_GEN3_M GENMASK(5U, 5U)
#define PCIE_PHY_PMA_PMA_LANE_B3_CFG_PI_EXT_DAC_B21_GEN3_X(x)\
	(((x) & GENMASK(5U, 5U)) >> 5U)

#define PCIE_PHY_PMA_PMA_LANE_B3_CFG_PI_EXT_DAC_B21_GEN4(x)\
	(((x) << 6U) & GENMASK(6U, 6U))
#define PCIE_PHY_PMA_PMA_LANE_B3_CFG_PI_EXT_DAC_B21_GEN4_M GENMASK(6U, 6U)
#define PCIE_PHY_PMA_PMA_LANE_B3_CFG_PI_EXT_DAC_B21_GEN4_X(x)\
	(((x) & GENMASK(6U, 6U)) >> 6U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_B4 */
#define PCIE_PHY_PMA_PMA_LANE_B4(t) ((t) + 0x6d0U)

#define PCIE_PHY_PMA_PMA_LANE_B4_CFG_RX_SSC_LH_GEN2(x) ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_B4_CFG_RX_SSC_LH_GEN2_M GENMASK(0U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_B4_CFG_RX_SSC_LH_GEN2_X(x) ((x) & GENMASK(0U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_B4_CFG_RX_SSC_LH_GEN3(x)\
	(((x) << 1U) & GENMASK(1U, 1U))
#define PCIE_PHY_PMA_PMA_LANE_B4_CFG_RX_SSC_LH_GEN3_M GENMASK(1U, 1U)
#define PCIE_PHY_PMA_PMA_LANE_B4_CFG_RX_SSC_LH_GEN3_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

#define PCIE_PHY_PMA_PMA_LANE_B4_CFG_RX_SSC_LH_GEN4(x)\
	(((x) << 2U) & GENMASK(2U, 2U))
#define PCIE_PHY_PMA_PMA_LANE_B4_CFG_RX_SSC_LH_GEN4_M GENMASK(2U, 2U)
#define PCIE_PHY_PMA_PMA_LANE_B4_CFG_RX_SSC_LH_GEN4_X(x)\
	(((x) & GENMASK(2U, 2U)) >> 2U)

#define PCIE_PHY_PMA_PMA_LANE_B4_CFG_PI_STEPS_GEN2(x)\
	(((x) << 4U) & GENMASK(4U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_B4_CFG_PI_STEPS_GEN2_M GENMASK(4U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_B4_CFG_PI_STEPS_GEN2_X(x)\
	(((x) & GENMASK(4U, 4U)) >> 4U)

#define PCIE_PHY_PMA_PMA_LANE_B4_CFG_PI_STEPS_GEN3(x)\
	(((x) << 5U) & GENMASK(5U, 5U))
#define PCIE_PHY_PMA_PMA_LANE_B4_CFG_PI_STEPS_GEN3_M GENMASK(5U, 5U)
#define PCIE_PHY_PMA_PMA_LANE_B4_CFG_PI_STEPS_GEN3_X(x)\
	(((x) & GENMASK(5U, 5U)) >> 5U)

#define PCIE_PHY_PMA_PMA_LANE_B4_CFG_PI_STEPS_GEN4(x)\
	(((x) << 6U) & GENMASK(6U, 6U))
#define PCIE_PHY_PMA_PMA_LANE_B4_CFG_PI_STEPS_GEN4_M GENMASK(6U, 6U)
#define PCIE_PHY_PMA_PMA_LANE_B4_CFG_PI_STEPS_GEN4_X(x)\
	(((x) & GENMASK(6U, 6U)) >> 6U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_B6 */
#define PCIE_PHY_PMA_PMA_LANE_B6(t) ((t) + 0x6d8U)

#define PCIE_PHY_PMA_PMA_LANE_B6_CFG_PI_OFFSET_GEN4_3_0(x)\
	((x) & GENMASK(3U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_B6_CFG_PI_OFFSET_GEN4_3_0_M GENMASK(3U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_B6_CFG_PI_OFFSET_GEN4_3_0_X(x)\
	((x) & GENMASK(3U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_B8 */
#define PCIE_PHY_PMA_PMA_LANE_B8(t) ((t) + 0x6e0U)

#define PCIE_PHY_PMA_PMA_LANE_B8_CFG_TACC_SEL_GEN4_1_0(x)\
	((x) & GENMASK(1U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_B8_CFG_TACC_SEL_GEN4_1_0_M GENMASK(1U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_B8_CFG_TACC_SEL_GEN4_1_0_X(x)\
	((x) & GENMASK(1U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_B9 */
#define PCIE_PHY_PMA_PMA_LANE_B9(t) ((t) + 0x6e4U)

#define PCIE_PHY_PMA_PMA_LANE_B9_CFG_PI_EXT_DAC_B3TOB0_GEN2_3_0(x)\
	((x) & GENMASK(3U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_B9_CFG_PI_EXT_DAC_B3TOB0_GEN2_3_0_M\
	GENMASK(3U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_B9_CFG_PI_EXT_DAC_B3TOB0_GEN2_3_0_X(x)\
	((x) & GENMASK(3U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_B9_CFG_PI_EXT_DAC_B3TOB0_GEN3_3_0(x)\
	(((x) << 4U) & GENMASK(7U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_B9_CFG_PI_EXT_DAC_B3TOB0_GEN3_3_0_M\
	GENMASK(7U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_B9_CFG_PI_EXT_DAC_B3TOB0_GEN3_3_0_X(x)\
	(((x) & GENMASK(7U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_BA */
#define PCIE_PHY_PMA_PMA_LANE_BA(t) ((t) + 0x6e8U)

#define PCIE_PHY_PMA_PMA_LANE_BA_CFG_PI_EXT_DAC_B3TOB0_GEN4_3_0(x)\
	((x) & GENMASK(3U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_BA_CFG_PI_EXT_DAC_B3TOB0_GEN4_3_0_M\
	GENMASK(3U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_BA_CFG_PI_EXT_DAC_B3TOB0_GEN4_3_0_X(x)\
	((x) & GENMASK(3U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_BB */
#define PCIE_PHY_PMA_PMA_LANE_BB(t) ((t) + 0x6ecU)

#define PCIE_PHY_PMA_PMA_LANE_BB_CFG_ISCAN_EXT_DAC_B4TOB0_GEN2_4_0(x)\
	((x) & GENMASK(4U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_BB_CFG_ISCAN_EXT_DAC_B4TOB0_GEN2_4_0_M\
	GENMASK(4U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_BB_CFG_ISCAN_EXT_DAC_B4TOB0_GEN2_4_0_X(x)\
	((x) & GENMASK(4U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_BC */
#define PCIE_PHY_PMA_PMA_LANE_BC(t) ((t) + 0x6f0U)

#define PCIE_PHY_PMA_PMA_LANE_BC_CFG_ISCAN_EXT_DAC_B4TOB0_GEN3_4_0(x)\
	((x) & GENMASK(4U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_BC_CFG_ISCAN_EXT_DAC_B4TOB0_GEN3_4_0_M\
	GENMASK(4U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_BC_CFG_ISCAN_EXT_DAC_B4TOB0_GEN3_4_0_X(x)\
	((x) & GENMASK(4U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_BD */
#define PCIE_PHY_PMA_PMA_LANE_BD(t) ((t) + 0x6f4U)

#define PCIE_PHY_PMA_PMA_LANE_BD_CFG_ISCAN_EXT_DAC_B4TOB0_GEN4_4_0(x)\
	((x) & GENMASK(4U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_BD_CFG_ISCAN_EXT_DAC_B4TOB0_GEN4_4_0_M\
	GENMASK(4U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_BD_CFG_ISCAN_EXT_DAC_B4TOB0_GEN4_4_0_X(x)\
	((x) & GENMASK(4U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_BE */
#define PCIE_PHY_PMA_PMA_LANE_BE(t) ((t) + 0x6f8U)

#define PCIE_PHY_PMA_PMA_LANE_BE_CFG_RSTN_DFEDIG_GEN2(x) ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_BE_CFG_RSTN_DFEDIG_GEN2_M GENMASK(0U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_BE_CFG_RSTN_DFEDIG_GEN2_X(x)\
	((x) & GENMASK(0U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_BE_CFG_RSTN_DFEDIG_GEN3(x)\
	(((x) << 1U) & GENMASK(1U, 1U))
#define PCIE_PHY_PMA_PMA_LANE_BE_CFG_RSTN_DFEDIG_GEN3_M GENMASK(1U, 1U)
#define PCIE_PHY_PMA_PMA_LANE_BE_CFG_RSTN_DFEDIG_GEN3_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

#define PCIE_PHY_PMA_PMA_LANE_BE_CFG_RSTN_DFEDIG_GEN4(x)\
	(((x) << 2U) & GENMASK(2U, 2U))
#define PCIE_PHY_PMA_PMA_LANE_BE_CFG_RSTN_DFEDIG_GEN4_M GENMASK(2U, 2U)
#define PCIE_PHY_PMA_PMA_LANE_BE_CFG_RSTN_DFEDIG_GEN4_X(x)\
	(((x) & GENMASK(2U, 2U)) >> 2U)

#define PCIE_PHY_PMA_PMA_LANE_BE_CFG_ISCAN_EXT_DAC_B30_GEN2(x)\
	(((x) << 4U) & GENMASK(4U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_BE_CFG_ISCAN_EXT_DAC_B30_GEN2_M GENMASK(4U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_BE_CFG_ISCAN_EXT_DAC_B30_GEN2_X(x)\
	(((x) & GENMASK(4U, 4U)) >> 4U)

#define PCIE_PHY_PMA_PMA_LANE_BE_CFG_ISCAN_EXT_DAC_B30_GEN3(x)\
	(((x) << 5U) & GENMASK(5U, 5U))
#define PCIE_PHY_PMA_PMA_LANE_BE_CFG_ISCAN_EXT_DAC_B30_GEN3_M GENMASK(5U, 5U)
#define PCIE_PHY_PMA_PMA_LANE_BE_CFG_ISCAN_EXT_DAC_B30_GEN3_X(x)\
	(((x) & GENMASK(5U, 5U)) >> 5U)

#define PCIE_PHY_PMA_PMA_LANE_BE_CFG_ISCAN_EXT_DAC_B30_GEN4(x)\
	(((x) << 6U) & GENMASK(6U, 6U))
#define PCIE_PHY_PMA_PMA_LANE_BE_CFG_ISCAN_EXT_DAC_B30_GEN4_M GENMASK(6U, 6U)
#define PCIE_PHY_PMA_PMA_LANE_BE_CFG_ISCAN_EXT_DAC_B30_GEN4_X(x)\
	(((x) & GENMASK(6U, 6U)) >> 6U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_0:PMA_LANE_DF */
#define PCIE_PHY_PMA_PMA_LANE_DF(t) ((t) + 0x77cU)

#define PCIE_PHY_PMA_PMA_LANE_DF_LOL_UDL(x) ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_DF_LOL_UDL_M  GENMASK(0U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_DF_LOL_UDL_X(x) ((x) & GENMASK(0U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_DF_LOL(x)     (((x) << 1U) & GENMASK(1U, 1U))
#define PCIE_PHY_PMA_PMA_LANE_DF_LOL_M      GENMASK(1U, 1U)
#define PCIE_PHY_PMA_PMA_LANE_DF_LOL_X(x)   (((x) & GENMASK(1U, 1U)) >> 1U)

#define PCIE_PHY_PMA_PMA_LANE_DF_PMA2PCS_RXEI_FILTERED(x)\
	(((x) << 2U) & GENMASK(2U, 2U))
#define PCIE_PHY_PMA_PMA_LANE_DF_PMA2PCS_RXEI_FILTERED_M GENMASK(2U, 2U)
#define PCIE_PHY_PMA_PMA_LANE_DF_PMA2PCS_RXEI_FILTERED_X(x)\
	(((x) & GENMASK(2U, 2U)) >> 2U)

#define PCIE_PHY_PMA_PMA_LANE_DF_SQUELCH(x) (((x) << 3U) & GENMASK(3U, 3U))
#define PCIE_PHY_PMA_PMA_LANE_DF_SQUELCH_M  GENMASK(3U, 3U)
#define PCIE_PHY_PMA_PMA_LANE_DF_SQUELCH_X(x) (((x) & GENMASK(3U, 3U)) >> 3U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_1:PMA_LANE_F0 */
#define PCIE_PHY_PMA_PMA_LANE_F0(t) ((t) + 0x7c0U)

#define PCIE_PHY_PMA_PMA_LANE_F0_CFG_PREDRV_SLEWRATE_GEN2_1_0(x)\
	((x) & GENMASK(1U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_F0_CFG_PREDRV_SLEWRATE_GEN2_1_0_M GENMASK(1U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_F0_CFG_PREDRV_SLEWRATE_GEN2_1_0_X(x)\
	((x) & GENMASK(1U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_F0_CFG_PREDRV_SLEWRATE_GEN3_1_0(x)\
	(((x) << 4U) & GENMASK(5U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_F0_CFG_PREDRV_SLEWRATE_GEN3_1_0_M GENMASK(5U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_F0_CFG_PREDRV_SLEWRATE_GEN3_1_0_X(x)\
	(((x) & GENMASK(5U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_1:PMA_LANE_F2 */
#define PCIE_PHY_PMA_PMA_LANE_F2(t) ((t) + 0x7c8U)

#define PCIE_PHY_PMA_PMA_LANE_F2_CFG_MP_MAX_GEN2_3_0(x) ((x) & GENMASK(3U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_F2_CFG_MP_MAX_GEN2_3_0_M GENMASK(3U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_F2_CFG_MP_MAX_GEN2_3_0_X(x)\
	((x) & GENMASK(3U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_F2_CFG_MP_MAX_GEN3_3_0(x)\
	(((x) << 4U) & GENMASK(7U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_F2_CFG_MP_MAX_GEN3_3_0_M GENMASK(7U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_F2_CFG_MP_MAX_GEN3_3_0_X(x)\
	(((x) & GENMASK(7U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_1:PMA_LANE_F3 */
#define PCIE_PHY_PMA_PMA_LANE_F3(t) ((t) + 0x7ccU)

#define PCIE_PHY_PMA_PMA_LANE_F3_CFG_MP_MAX_GEN4_3_0(x) ((x) & GENMASK(3U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_F3_CFG_MP_MAX_GEN4_3_0_M GENMASK(3U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_F3_CFG_MP_MAX_GEN4_3_0_X(x)\
	((x) & GENMASK(3U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_F3_CFG_ITX_IPCML_BASE_GEN2_1_0(x)\
	(((x) << 4U) & GENMASK(5U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_F3_CFG_ITX_IPCML_BASE_GEN2_1_0_M GENMASK(5U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_F3_CFG_ITX_IPCML_BASE_GEN2_1_0_X(x)\
	(((x) & GENMASK(5U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_1:PMA_LANE_F5 */
#define PCIE_PHY_PMA_PMA_LANE_F5(t) ((t) + 0x7d4U)

#define PCIE_PHY_PMA_PMA_LANE_F5_CFG_IP_PRE_BASE_GEN2_1_0(x)\
	((x) & GENMASK(1U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_F5_CFG_IP_PRE_BASE_GEN2_1_0_M GENMASK(1U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_F5_CFG_IP_PRE_BASE_GEN2_1_0_X(x)\
	((x) & GENMASK(1U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_F5_CFG_IP_PRE_BASE_GEN3_1_0(x)\
	(((x) << 4U) & GENMASK(5U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_F5_CFG_IP_PRE_BASE_GEN3_1_0_M GENMASK(5U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_F5_CFG_IP_PRE_BASE_GEN3_1_0_X(x)\
	(((x) & GENMASK(5U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_1:PMA_LANE_F7 */
#define PCIE_PHY_PMA_PMA_LANE_F7(t) ((t) + 0x7dcU)

#define PCIE_PHY_PMA_PMA_LANE_F7_CFG_TAP_ADV_GEN2(x) ((x) & GENMASK(4U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_F7_CFG_TAP_ADV_GEN2_M GENMASK(4U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_F7_CFG_TAP_ADV_GEN2_X(x) ((x) & GENMASK(4U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_1:PMA_LANE_F8 */
#define PCIE_PHY_PMA_PMA_LANE_F8(t) ((t) + 0x7e0U)

#define PCIE_PHY_PMA_PMA_LANE_F8_CFG_TAP_ADV_GEN3(x) ((x) & GENMASK(4U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_F8_CFG_TAP_ADV_GEN3_M GENMASK(4U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_F8_CFG_TAP_ADV_GEN3_X(x) ((x) & GENMASK(4U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_1:PMA_LANE_F9 */
#define PCIE_PHY_PMA_PMA_LANE_F9(t) ((t) + 0x7e4U)

#define PCIE_PHY_PMA_PMA_LANE_F9_CFG_TAP_ADV_GEN4(x) ((x) & GENMASK(4U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_F9_CFG_TAP_ADV_GEN4_M GENMASK(4U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_F9_CFG_TAP_ADV_GEN4_X(x) ((x) & GENMASK(4U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_1:PMA_LANE_FA */
#define PCIE_PHY_PMA_PMA_LANE_FA(t) ((t) + 0x7e8U)

#define PCIE_PHY_PMA_PMA_LANE_FA_CFG_TAP_DLY_GEN2(x) ((x) & GENMASK(4U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_FA_CFG_TAP_DLY_GEN2_M GENMASK(4U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_FA_CFG_TAP_DLY_GEN2_X(x) ((x) & GENMASK(4U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_1:PMA_LANE_FB */
#define PCIE_PHY_PMA_PMA_LANE_FB(t) ((t) + 0x7ecU)

#define PCIE_PHY_PMA_PMA_LANE_FB_CFG_TAP_DLY_GEN3(x) ((x) & GENMASK(4U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_FB_CFG_TAP_DLY_GEN3_M GENMASK(4U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_FB_CFG_TAP_DLY_GEN3_X(x) ((x) & GENMASK(4U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_1:PMA_LANE_FC */
#define PCIE_PHY_PMA_PMA_LANE_FC(t) ((t) + 0x7f0U)

#define PCIE_PHY_PMA_PMA_LANE_FC_CFG_TAP_DLY_GEN4(x) ((x) & GENMASK(4U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_FC_CFG_TAP_DLY_GEN4_M GENMASK(4U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_FC_CFG_TAP_DLY_GEN4_X(x) ((x) & GENMASK(4U, 0U))

/*      PCIE_PHY_PMA:PMA_LANE_GRP_1:PMA_LANE_FD */
#define PCIE_PHY_PMA_PMA_LANE_FD(t) ((t) + 0x7f4U)

#define PCIE_PHY_PMA_PMA_LANE_FD_CFG_EQ_RES_GEN2(x) ((x) & GENMASK(3U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_FD_CFG_EQ_RES_GEN2_M GENMASK(3U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_FD_CFG_EQ_RES_GEN2_X(x) ((x) & GENMASK(3U, 0U))

#define PCIE_PHY_PMA_PMA_LANE_FD_CFG_EQ_RES_GEN3(x)\
	(((x) << 4U) & GENMASK(7U, 4U))
#define PCIE_PHY_PMA_PMA_LANE_FD_CFG_EQ_RES_GEN3_M GENMASK(7U, 4U)
#define PCIE_PHY_PMA_PMA_LANE_FD_CFG_EQ_RES_GEN3_X(x)\
	(((x) & GENMASK(7U, 4U)) >> 4U)

/*      PCIE_PHY_PMA:PMA_LANE_GRP_1:PMA_LANE_FE */
#define PCIE_PHY_PMA_PMA_LANE_FE(t) ((t) + 0x7f8U)

#define PCIE_PHY_PMA_PMA_LANE_FE_CFG_EQ_RES_GEN4(x) ((x) & GENMASK(3U, 0U))
#define PCIE_PHY_PMA_PMA_LANE_FE_CFG_EQ_RES_GEN4_M GENMASK(3U, 0U)
#define PCIE_PHY_PMA_PMA_LANE_FE_CFG_EQ_RES_GEN4_X(x) ((x) & GENMASK(3U, 0U))

/*      PCIE_PHY_WRAP:PCIE_PHY_CFG:PCIE_PHY_CFG */
#define PCIE_PHY_WRAP_PCIE_PHY_CFG(t) ((t) + 0x00U)

#define PCIE_PHY_WRAP_PCIE_PHY_CFG_PIPE_RST(x) ((x) & GENMASK(0U, 0U))
#define PCIE_PHY_WRAP_PCIE_PHY_CFG_PIPE_RST_M GENMASK(0U, 0U)
#define PCIE_PHY_WRAP_PCIE_PHY_CFG_PIPE_RST_X(x) ((x) & GENMASK(0U, 0U))

#define PCIE_PHY_WRAP_PCIE_PHY_CFG_EXT_CFG_RST(x)\
	(((x) << 1U) & GENMASK(1U, 1U))
#define PCIE_PHY_WRAP_PCIE_PHY_CFG_EXT_CFG_RST_M GENMASK(1U, 1U)
#define PCIE_PHY_WRAP_PCIE_PHY_CFG_EXT_CFG_RST_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

#define PCIE_PHY_WRAP_PCIE_PHY_CFG_APB_IF_RST(x) (((x) << 2U) & GENMASK(2U, 2U))
#define PCIE_PHY_WRAP_PCIE_PHY_CFG_APB_IF_RST_M GENMASK(2U, 2U)
#define PCIE_PHY_WRAP_PCIE_PHY_CFG_APB_IF_RST_X(x)\
	(((x) & GENMASK(2U, 2U)) >> 2U)

#define PCIE_PHY_WRAP_PCIE_PHY_CFG_PCIE_CNTLR_PHY_RST_DIS(x)\
	(((x) << 3U) & GENMASK(3U, 3U))
#define PCIE_PHY_WRAP_PCIE_PHY_CFG_PCIE_CNTLR_PHY_RST_DIS_M GENMASK(3U, 3U)
#define PCIE_PHY_WRAP_PCIE_PHY_CFG_PCIE_CNTLR_PHY_RST_DIS_X(x)\
	(((x) & GENMASK(3U, 3U)) >> 3U)

#define PCIE_PHY_WRAP_PCIE_PHY_CFG_AMBA_APB_RST_DIS(x)\
	(((x) << 4U) & GENMASK(4U, 4U))
#define PCIE_PHY_WRAP_PCIE_PHY_CFG_AMBA_APB_RST_DIS_M GENMASK(4U, 4U)
#define PCIE_PHY_WRAP_PCIE_PHY_CFG_AMBA_APB_RST_DIS_X(x)\
	(((x) & GENMASK(4U, 4U)) >> 4U)

/*      SHA:SHA_REGS:SHA_CR */
#define SHA_SHA_CR(t)             ((t) + 0x00U)

#define SHA_SHA_CR_UNLOCK(x)                (((x) << 24U) & GENMASK(24U, 24U))
#define SHA_SHA_CR_UNLOCK_M                 GENMASK(24U, 24U)
#define SHA_SHA_CR_UNLOCK_X(x)              (((x) & GENMASK(24U, 24U)) >> 24U)

#define SHA_SHA_CR_WUIEHV(x)                (((x) << 13U) & GENMASK(13U, 13U))
#define SHA_SHA_CR_WUIEHV_M                 GENMASK(13U, 13U)
#define SHA_SHA_CR_WUIEHV_X(x)              (((x) & GENMASK(13U, 13U)) >> 13U)

#define SHA_SHA_CR_WUIHV(x)                 (((x) << 12U) & GENMASK(12U, 12U))
#define SHA_SHA_CR_WUIHV_M                  GENMASK(12U, 12U)
#define SHA_SHA_CR_WUIHV_X(x)               (((x) & GENMASK(12U, 12U)) >> 12U)

#define SHA_SHA_CR_SWRST(x)                 (((x) << 8U) & GENMASK(8U, 8U))
#define SHA_SHA_CR_SWRST_M                  GENMASK(8U, 8U)
#define SHA_SHA_CR_SWRST_X(x)               (((x) & GENMASK(8U, 8U)) >> 8U)

#define SHA_SHA_CR_FIRST(x)                 (((x) << 4U) & GENMASK(4U, 4U))
#define SHA_SHA_CR_FIRST_M                  GENMASK(4U, 4U)
#define SHA_SHA_CR_FIRST_X(x)               (((x) & GENMASK(4U, 4U)) >> 4U)

#define SHA_SHA_CR_START(x)                 ((x) & GENMASK(0U, 0U))
#define SHA_SHA_CR_START_M                  GENMASK(0U, 0U)
#define SHA_SHA_CR_START_X(x)               ((x) & GENMASK(0U, 0U))

/*      SHA:SHA_REGS:SHA_MR */
#define SHA_SHA_MR(t)             ((t) + 0x04U)

#define SHA_SHA_MR_CHKCNT(x)                (((x) << 28U) & GENMASK(31U, 28U))
#define SHA_SHA_MR_CHKCNT_M                 GENMASK(31U, 28U)
#define SHA_SHA_MR_CHKCNT_X(x)              (((x) & GENMASK(31U, 28U)) >> 28U)

#define SHA_SHA_MR_CHECK(x)                 (((x) << 24U) & GENMASK(25U, 24U))
#define SHA_SHA_MR_CHECK_M                  GENMASK(25U, 24U)
#define SHA_SHA_MR_CHECK_X(x)               (((x) & GENMASK(25U, 24U)) >> 24U)

#define SHA_SHA_MR_DUALBUFF(x)              (((x) << 16U) & GENMASK(16U, 16U))
#define SHA_SHA_MR_DUALBUFF_M               GENMASK(16U, 16U)
#define SHA_SHA_MR_DUALBUFF_X(x)            (((x) & GENMASK(16U, 16U)) >> 16U)

#define SHA_SHA_MR_TMPLCK(x)                (((x) << 15U) & GENMASK(15U, 15U))
#define SHA_SHA_MR_TMPLCK_M                 GENMASK(15U, 15U)
#define SHA_SHA_MR_TMPLCK_X(x)              (((x) & GENMASK(15U, 15U)) >> 15U)

#define SHA_SHA_MR_ALGO(x)                  (((x) << 8U) & GENMASK(11U, 8U))
#define SHA_SHA_MR_ALGO_M                   GENMASK(11U, 8U)
#define SHA_SHA_MR_ALGO_X(x)                (((x) & GENMASK(11U, 8U)) >> 8U)

#define SHA_SHA_MR_BPE(x)                   (((x) << 7U) & GENMASK(7U, 7U))
#define SHA_SHA_MR_BPE_M                    GENMASK(7U, 7U)
#define SHA_SHA_MR_BPE_X(x)                 (((x) & GENMASK(7U, 7U)) >> 7U)

#define SHA_SHA_MR_UIEHV(x)                 (((x) << 6U) & GENMASK(6U, 6U))
#define SHA_SHA_MR_UIEHV_M                  GENMASK(6U, 6U)
#define SHA_SHA_MR_UIEHV_X(x)               (((x) & GENMASK(6U, 6U)) >> 6U)

#define SHA_SHA_MR_UIHV(x)                  (((x) << 5U) & GENMASK(5U, 5U))
#define SHA_SHA_MR_UIHV_M                   GENMASK(5U, 5U)
#define SHA_SHA_MR_UIHV_X(x)                (((x) & GENMASK(5U, 5U)) >> 5U)

#define SHA_SHA_MR_PROCDLY(x)               (((x) << 4U) & GENMASK(4U, 4U))
#define SHA_SHA_MR_PROCDLY_M                GENMASK(4U, 4U)
#define SHA_SHA_MR_PROCDLY_X(x)             (((x) & GENMASK(4U, 4U)) >> 4U)

#define SHA_SHA_MR_SMOD(x)                  ((x) & GENMASK(1U, 0U))
#define SHA_SHA_MR_SMOD_M                   GENMASK(1U, 0U)
#define SHA_SHA_MR_SMOD_X(x)                ((x) & GENMASK(1U, 0U))

/*      SHA:SHA_REGS:SHA_IER */
#define SHA_SHA_IER(t)            ((t) + 0x10U)

#define SHA_SHA_IER_SECE(x)                 (((x) << 24U) & GENMASK(24U, 24U))
#define SHA_SHA_IER_SECE_M                  GENMASK(24U, 24U)
#define SHA_SHA_IER_SECE_X(x)               (((x) & GENMASK(24U, 24U)) >> 24U)

#define SHA_SHA_IER_CHECKF(x)               (((x) << 16U) & GENMASK(16U, 16U))
#define SHA_SHA_IER_CHECKF_M                GENMASK(16U, 16U)
#define SHA_SHA_IER_CHECKF_X(x)             (((x) & GENMASK(16U, 16U)) >> 16U)

#define SHA_SHA_IER_URAD(x)                 (((x) << 8U) & GENMASK(8U, 8U))
#define SHA_SHA_IER_URAD_M                  GENMASK(8U, 8U)
#define SHA_SHA_IER_URAD_X(x)               (((x) & GENMASK(8U, 8U)) >> 8U)

#define SHA_SHA_IER_DATRDY(x)               ((x) & GENMASK(0U, 0U))
#define SHA_SHA_IER_DATRDY_M                GENMASK(0U, 0U)
#define SHA_SHA_IER_DATRDY_X(x)             ((x) & GENMASK(0U, 0U))

/*      SHA:SHA_REGS:SHA_IDR */
#define SHA_SHA_IDR(t)            ((t) + 0x14U)

#define SHA_SHA_IDR_SECE_IDR(x)             (((x) << 24U) & GENMASK(24U, 24U))
#define SHA_SHA_IDR_SECE_IDR_M              GENMASK(24U, 24U)
#define SHA_SHA_IDR_SECE_IDR_X(x)           (((x) & GENMASK(24U, 24U)) >> 24U)

#define SHA_SHA_IDR_CHECKF_IDR(x)           (((x) << 16U) & GENMASK(16U, 16U))
#define SHA_SHA_IDR_CHECKF_IDR_M            GENMASK(16U, 16U)
#define SHA_SHA_IDR_CHECKF_IDR_X(x)         (((x) & GENMASK(16U, 16U)) >> 16U)

#define SHA_SHA_IDR_URAD_IDR(x)             (((x) << 8U) & GENMASK(8U, 8U))
#define SHA_SHA_IDR_URAD_IDR_M              GENMASK(8U, 8U)
#define SHA_SHA_IDR_URAD_IDR_X(x)           (((x) & GENMASK(8U, 8U)) >> 8U)

#define SHA_SHA_IDR_DATRDY_IDR(x)           ((x) & GENMASK(0U, 0U))
#define SHA_SHA_IDR_DATRDY_IDR_M            GENMASK(0U, 0U)
#define SHA_SHA_IDR_DATRDY_IDR_X(x)         ((x) & GENMASK(0U, 0U))

/*      SHA:SHA_REGS:SHA_IMR */
#define SHA_SHA_IMR(t)            ((t) + 0x18U)

#define SHA_SHA_IMR_SECE_IMR(x)             (((x) << 24U) & GENMASK(24U, 24U))
#define SHA_SHA_IMR_SECE_IMR_M              GENMASK(24U, 24U)
#define SHA_SHA_IMR_SECE_IMR_X(x)           (((x) & GENMASK(24U, 24U)) >> 24U)

#define SHA_SHA_IMR_CHECKF_IMR(x)           (((x) << 16U) & GENMASK(16U, 16U))
#define SHA_SHA_IMR_CHECKF_IMR_M            GENMASK(16U, 16U)
#define SHA_SHA_IMR_CHECKF_IMR_X(x)         (((x) & GENMASK(16U, 16U)) >> 16U)

#define SHA_SHA_IMR_URAD_IMR(x)             (((x) << 8U) & GENMASK(8U, 8U))
#define SHA_SHA_IMR_URAD_IMR_M              GENMASK(8U, 8U)
#define SHA_SHA_IMR_URAD_IMR_X(x)           (((x) & GENMASK(8U, 8U)) >> 8U)

#define SHA_SHA_IMR_DATRDY_IMR(x)           ((x) & GENMASK(0U, 0U))
#define SHA_SHA_IMR_DATRDY_IMR_M            GENMASK(0U, 0U)
#define SHA_SHA_IMR_DATRDY_IMR_X(x)         ((x) & GENMASK(0U, 0U))

/*      SHA:SHA_REGS:SHA_ISR */
#define SHA_SHA_ISR(t)            ((t) + 0x1cU)

#define SHA_SHA_ISR_SECE_ISR(x)             (((x) << 24U) & GENMASK(24U, 24U))
#define SHA_SHA_ISR_SECE_ISR_M              GENMASK(24U, 24U)
#define SHA_SHA_ISR_SECE_ISR_X(x)           (((x) & GENMASK(24U, 24U)) >> 24U)

#define SHA_SHA_ISR_CHKST_ISR(x)            (((x) << 20U) & GENMASK(23U, 20U))
#define SHA_SHA_ISR_CHKST_ISR_M             GENMASK(23U, 20U)
#define SHA_SHA_ISR_CHKST_ISR_X(x)          (((x) & GENMASK(23U, 20U)) >> 20U)

#define SHA_SHA_ISR_CHECKF_ISR(x)           (((x) << 16U) & GENMASK(16U, 16U))
#define SHA_SHA_ISR_CHECKF_ISR_M            GENMASK(16U, 16U)
#define SHA_SHA_ISR_CHECKF_ISR_X(x)         (((x) & GENMASK(16U, 16U)) >> 16U)

#define SHA_SHA_ISR_URAT_ISR(x)             (((x) << 12U) & GENMASK(14U, 12U))
#define SHA_SHA_ISR_URAT_ISR_M              GENMASK(14U, 12U)
#define SHA_SHA_ISR_URAT_ISR_X(x)           (((x) & GENMASK(14U, 12U)) >> 12U)

#define SHA_SHA_ISR_URAD_ISR(x)             (((x) << 8U) & GENMASK(8U, 8U))
#define SHA_SHA_ISR_URAD_ISR_M              GENMASK(8U, 8U)
#define SHA_SHA_ISR_URAD_ISR_X(x)           (((x) & GENMASK(8U, 8U)) >> 8U)

#define SHA_SHA_ISR_WRDY_ISR(x)             (((x) << 4U) & GENMASK(4U, 4U))
#define SHA_SHA_ISR_WRDY_ISR_M              GENMASK(4U, 4U)
#define SHA_SHA_ISR_WRDY_ISR_X(x)           (((x) & GENMASK(4U, 4U)) >> 4U)

#define SHA_SHA_ISR_DATRDY_ISR(x)           ((x) & GENMASK(0U, 0U))
#define SHA_SHA_ISR_DATRDY_ISR_M            GENMASK(0U, 0U)
#define SHA_SHA_ISR_DATRDY_ISR_X(x)         ((x) & GENMASK(0U, 0U))

/*      SHA:SHA_REGS:SHA_MSR */
#define SHA_SHA_MSR(t)            ((t) + 0x20U)

/*      SHA:SHA_REGS:SHA_BCR */
#define SHA_SHA_BCR(t)            ((t) + 0x30U)

/*      SHA:SHA_REGS:SHA_IDATAR0 */
#define SHA_SHA_IDATAR0(t)        ((t) + 0x40U)

/*      SHA:SHA_REGS:SHA_IDATAR1 */
#define SHA_SHA_IDATAR1(t)        ((t) + 0x44U)

/*      SHA:SHA_REGS:SHA_IDATAR2 */
#define SHA_SHA_IDATAR2(t)        ((t) + 0x48U)

/*      SHA:SHA_REGS:SHA_IDATAR3 */
#define SHA_SHA_IDATAR3(t)        ((t) + 0x4cU)

/*      SHA:SHA_REGS:SHA_IDATAR4 */
#define SHA_SHA_IDATAR4(t)        ((t) + 0x50U)

/*      SHA:SHA_REGS:SHA_IDATAR5 */
#define SHA_SHA_IDATAR5(t)        ((t) + 0x54U)

/*      SHA:SHA_REGS:SHA_IDATAR6 */
#define SHA_SHA_IDATAR6(t)        ((t) + 0x58U)

/*      SHA:SHA_REGS:SHA_IDATAR7 */
#define SHA_SHA_IDATAR7(t)        ((t) + 0x5cU)

/*      SHA:SHA_REGS:SHA_IDATAR8 */
#define SHA_SHA_IDATAR8(t)        ((t) + 0x60U)

/*      SHA:SHA_REGS:SHA_IDATAR9 */
#define SHA_SHA_IDATAR9(t)        ((t) + 0x64U)

/*      SHA:SHA_REGS:SHA_IDATAR10 */
#define SHA_SHA_IDATAR10(t)       ((t) + 0x68U)

/*      SHA:SHA_REGS:SHA_IDATAR11 */
#define SHA_SHA_IDATAR11(t)       ((t) + 0x6cU)

/*      SHA:SHA_REGS:SHA_IDATAR12 */
#define SHA_SHA_IDATAR12(t)       ((t) + 0x70U)

/*      SHA:SHA_REGS:SHA_IDATAR13 */
#define SHA_SHA_IDATAR13(t)       ((t) + 0x74U)

/*      SHA:SHA_REGS:SHA_IDATAR14 */
#define SHA_SHA_IDATAR14(t)       ((t) + 0x78U)

/*      SHA:SHA_REGS:SHA_IDATAR15 */
#define SHA_SHA_IDATAR15(t)       ((t) + 0x7cU)

/*      SHA:SHA_REGS:SHA_IODATAR0 */
#define SHA_SHA_IODATAR0(t)       ((t) + 0x80U)

/*      SHA:SHA_REGS:SHA_IODATAR1 */
#define SHA_SHA_IODATAR1(t)       ((t) + 0x84U)

/*      SHA:SHA_REGS:SHA_IODATAR2 */
#define SHA_SHA_IODATAR2(t)       ((t) + 0x88U)

/*      SHA:SHA_REGS:SHA_IODATAR3 */
#define SHA_SHA_IODATAR3(t)       ((t) + 0x8cU)

/*      SHA:SHA_REGS:SHA_IODATAR4 */
#define SHA_SHA_IODATAR4(t)       ((t) + 0x90U)

/*      SHA:SHA_REGS:SHA_IODATAR5 */
#define SHA_SHA_IODATAR5(t)       ((t) + 0x94U)

/*      SHA:SHA_REGS:SHA_IODATAR6 */
#define SHA_SHA_IODATAR6(t)       ((t) + 0x98U)

/*      SHA:SHA_REGS:SHA_IODATAR7 */
#define SHA_SHA_IODATAR7(t)       ((t) + 0x9cU)

/*      SHA:SHA_REGS:SHA_IODATAR8 */
#define SHA_SHA_IODATAR8(t)       ((t) + 0xa0U)

/*      SHA:SHA_REGS:SHA_IODATAR9 */
#define SHA_SHA_IODATAR9(t)       ((t) + 0xa4U)

/*      SHA:SHA_REGS:SHA_IODATAR10 */
#define SHA_SHA_IODATAR10(t)      ((t) + 0xa8U)

/*      SHA:SHA_REGS:SHA_IODATAR11 */
#define SHA_SHA_IODATAR11(t)      ((t) + 0xacU)

/*      SHA:SHA_REGS:SHA_IODATAR12 */
#define SHA_SHA_IODATAR12(t)      ((t) + 0xb0U)

/*      SHA:SHA_REGS:SHA_IODATAR13 */
#define SHA_SHA_IODATAR13(t)      ((t) + 0xb4U)

/*      SHA:SHA_REGS:SHA_IODATAR14 */
#define SHA_SHA_IODATAR14(t)      ((t) + 0xb8U)

/*      SHA:SHA_REGS:SHA_IODATAR15 */
#define SHA_SHA_IODATAR15(t)      ((t) + 0xbcU)

/*      SHA:SHA_REGS:SHA_WPMR */
#define SHA_SHA_WPMR(t)           ((t) + 0xe4U)

#define SHA_SHA_WPMR_WPKEY(x)               (((x) << 8U) & GENMASK(31U, 8U))
#define SHA_SHA_WPMR_WPKEY_M                GENMASK(31U, 8U)
#define SHA_SHA_WPMR_WPKEY_X(x)             (((x) & GENMASK(31U, 8U)) >> 8U)

#define SHA_SHA_WPMR_ACTION(x)              (((x) << 5U) & GENMASK(6U, 5U))
#define SHA_SHA_WPMR_ACTION_M               GENMASK(6U, 5U)
#define SHA_SHA_WPMR_ACTION_X(x)            (((x) & GENMASK(6U, 5U)) >> 5U)

#define SHA_SHA_WPMR_FIRSTE(x)              (((x) << 4U) & GENMASK(4U, 4U))
#define SHA_SHA_WPMR_FIRSTE_M               GENMASK(4U, 4U)
#define SHA_SHA_WPMR_FIRSTE_X(x)            (((x) & GENMASK(4U, 4U)) >> 4U)

#define SHA_SHA_WPMR_WPCREN(x)              (((x) << 2U) & GENMASK(2U, 2U))
#define SHA_SHA_WPMR_WPCREN_M               GENMASK(2U, 2U)
#define SHA_SHA_WPMR_WPCREN_X(x)            (((x) & GENMASK(2U, 2U)) >> 2U)

#define SHA_SHA_WPMR_WPITEN(x)              (((x) << 1U) & GENMASK(1U, 1U))
#define SHA_SHA_WPMR_WPITEN_M               GENMASK(1U, 1U)
#define SHA_SHA_WPMR_WPITEN_X(x)            (((x) & GENMASK(1U, 1U)) >> 1U)

#define SHA_SHA_WPMR_WPEN(x)                ((x) & GENMASK(0U, 0U))
#define SHA_SHA_WPMR_WPEN_M                 GENMASK(0U, 0U)
#define SHA_SHA_WPMR_WPEN_X(x)              ((x) & GENMASK(0U, 0U))

/*      SHA:SHA_REGS:SHA_WPSR */
#define SHA_SHA_WPSR(t)           ((t) + 0xe8U)

#define SHA_SHA_WPSR_ECLASS(x)              (((x) << 31U) & GENMASK(31U, 31U))
#define SHA_SHA_WPSR_ECLASS_M               GENMASK(31U, 31U)
#define SHA_SHA_WPSR_ECLASS_X(x)            (((x) & GENMASK(31U, 31U)) >> 31U)

#define SHA_SHA_WPSR_SWETYP(x)              (((x) << 24U) & GENMASK(27U, 24U))
#define SHA_SHA_WPSR_SWETYP_M               GENMASK(27U, 24U)
#define SHA_SHA_WPSR_SWETYP_X(x)            (((x) & GENMASK(27U, 24U)) >> 24U)

#define SHA_SHA_WPSR_WPVSRC(x)              (((x) << 8U) & GENMASK(15U, 8U))
#define SHA_SHA_WPSR_WPVSRC_M               GENMASK(15U, 8U)
#define SHA_SHA_WPSR_WPVSRC_X(x)            (((x) & GENMASK(15U, 8U)) >> 8U)

#define SHA_SHA_WPSR_SWE(x)                 (((x) << 3U) & GENMASK(3U, 3U))
#define SHA_SHA_WPSR_SWE_M                  GENMASK(3U, 3U)
#define SHA_SHA_WPSR_SWE_X(x)               (((x) & GENMASK(3U, 3U)) >> 3U)

#define SHA_SHA_WPSR_SEQE(x)                (((x) << 2U) & GENMASK(2U, 2U))
#define SHA_SHA_WPSR_SEQE_M                 GENMASK(2U, 2U)
#define SHA_SHA_WPSR_SEQE_X(x)              (((x) & GENMASK(2U, 2U)) >> 2U)

#define SHA_SHA_WPSR_CGD(x)                 (((x) << 1U) & GENMASK(1U, 1U))
#define SHA_SHA_WPSR_CGD_M                  GENMASK(1U, 1U)
#define SHA_SHA_WPSR_CGD_X(x)               (((x) & GENMASK(1U, 1U)) >> 1U)

#define SHA_SHA_WPSR_WPVS(x)                ((x) & GENMASK(0U, 0U))
#define SHA_SHA_WPSR_WPVS_M                 GENMASK(0U, 0U)
#define SHA_SHA_WPSR_WPVS_X(x)              ((x) & GENMASK(0U, 0U))

/*      SJTAG:SJTAG_REGS:CTL */
#define SJTAG_CTL(t)              ((t) + 0x00U)

#define SJTAG_CTL_BLOCK_RESET(x)            (((x) << 31U) & GENMASK(31U, 31U))
#define SJTAG_CTL_BLOCK_RESET_M             GENMASK(31U, 31U)
#define SJTAG_CTL_BLOCK_RESET_X(x)          (((x) & GENMASK(31U, 31U)) >> 31U)

#define SJTAG_CTL_SJTAG_UNLOCK_STS(x)       (((x) << 11U) & GENMASK(11U, 11U))
#define SJTAG_CTL_SJTAG_UNLOCK_STS_M        GENMASK(11U, 11U)
#define SJTAG_CTL_SJTAG_UNLOCK_STS_X(x)     (((x) & GENMASK(11U, 11U)) >> 11U)

#define SJTAG_CTL_SJTAG_MODE_STS(x)         (((x) << 9U) & GENMASK(10U, 9U))
#define SJTAG_CTL_SJTAG_MODE_STS_M          GENMASK(10U, 9U)
#define SJTAG_CTL_SJTAG_MODE_STS_X(x)       (((x) & GENMASK(10U, 9U)) >> 9U)

#define SJTAG_CTL_SJTAG_HC_TO_UNITS_DBG(x)  (((x) << 8U) & GENMASK(8U, 8U))
#define SJTAG_CTL_SJTAG_HC_TO_UNITS_DBG_M   GENMASK(8U, 8U)
#define SJTAG_CTL_SJTAG_HC_TO_UNITS_DBG_X(x) (((x) & GENMASK(8U, 8U)) >> 8U)

#define SJTAG_CTL_SJTAG_HC_TO_EN(x)         (((x) << 7U) & GENMASK(7U, 7U))
#define SJTAG_CTL_SJTAG_HC_TO_EN_M          GENMASK(7U, 7U)
#define SJTAG_CTL_SJTAG_HC_TO_EN_X(x)       (((x) & GENMASK(7U, 7U)) >> 7U)

#define SJTAG_CTL_SJTAG_DIGEST_CMP(x)       (((x) << 6U) & GENMASK(6U, 6U))
#define SJTAG_CTL_SJTAG_DIGEST_CMP_M        GENMASK(6U, 6U)
#define SJTAG_CTL_SJTAG_DIGEST_CMP_X(x)     (((x) & GENMASK(6U, 6U)) >> 6U)

#define SJTAG_CTL_SJTAG_FREEZE(x)           (((x) << 5U) & GENMASK(5U, 5U))
#define SJTAG_CTL_SJTAG_FREEZE_M            GENMASK(5U, 5U)
#define SJTAG_CTL_SJTAG_FREEZE_X(x)         (((x) & GENMASK(5U, 5U)) >> 5U)

#define SJTAG_CTL_SJTAG_MODE(x)             (((x) << 3U) & GENMASK(4U, 3U))
#define SJTAG_CTL_SJTAG_MODE_M              GENMASK(4U, 3U)
#define SJTAG_CTL_SJTAG_MODE_X(x)           (((x) & GENMASK(4U, 3U)) >> 3U)

#define SJTAG_CTL_SJTAG_EN(x)               (((x) << 2U) & GENMASK(2U, 2U))
#define SJTAG_CTL_SJTAG_EN_M                GENMASK(2U, 2U)
#define SJTAG_CTL_SJTAG_EN_X(x)             (((x) & GENMASK(2U, 2U)) >> 2U)

#define SJTAG_CTL_SJTAG_CPU_EN(x)           (((x) << 1U) & GENMASK(1U, 1U))
#define SJTAG_CTL_SJTAG_CPU_EN_M            GENMASK(1U, 1U)
#define SJTAG_CTL_SJTAG_CPU_EN_X(x)         (((x) & GENMASK(1U, 1U)) >> 1U)

#define SJTAG_CTL_SJTAG_TST_EN(x)           ((x) & GENMASK(0U, 0U))
#define SJTAG_CTL_SJTAG_TST_EN_M            GENMASK(0U, 0U)
#define SJTAG_CTL_SJTAG_TST_EN_X(x)         ((x) & GENMASK(0U, 0U))

/*      SJTAG:SJTAG_REGS:INT_STATUS */
#define SJTAG_INT_STATUS(t)       ((t) + 0x04U)

#define SJTAG_INT_STATUS_SJTAG_TO_STS(x)    (((x) << 7U) & GENMASK(7U, 7U))
#define SJTAG_INT_STATUS_SJTAG_TO_STS_M     GENMASK(7U, 7U)
#define SJTAG_INT_STATUS_SJTAG_TO_STS_X(x)  (((x) & GENMASK(7U, 7U)) >> 7U)

#define SJTAG_INT_STATUS_SJTAG_READ_UUID_RX(x) (((x) << 6U) & GENMASK(6U, 6U))
#define SJTAG_INT_STATUS_SJTAG_READ_UUID_RX_M GENMASK(6U, 6U)
#define SJTAG_INT_STATUS_SJTAG_READ_UUID_RX_X(x) (((x) & GENMASK(6U, 6U)) >> 6U)

#define SJTAG_INT_STATUS_SJTAG_READ_MODE_RX(x) (((x) << 5U) & GENMASK(5U, 5U))
#define SJTAG_INT_STATUS_SJTAG_READ_MODE_RX_M GENMASK(5U, 5U)
#define SJTAG_INT_STATUS_SJTAG_READ_MODE_RX_X(x) (((x) & GENMASK(5U, 5U)) >> 5U)

#define SJTAG_INT_STATUS_SJTAG_DIGEST_FAIL(x) (((x) << 4U) & GENMASK(4U, 4U))
#define SJTAG_INT_STATUS_SJTAG_DIGEST_FAIL_M GENMASK(4U, 4U)
#define SJTAG_INT_STATUS_SJTAG_DIGEST_FAIL_X(x) (((x) & GENMASK(4U, 4U)) >> 4U)

#define SJTAG_INT_STATUS_SJTAG_DIGEST_PASS(x) (((x) << 3U) & GENMASK(3U, 3U))
#define SJTAG_INT_STATUS_SJTAG_DIGEST_PASS_M GENMASK(3U, 3U)
#define SJTAG_INT_STATUS_SJTAG_DIGEST_PASS_X(x) (((x) & GENMASK(3U, 3U)) >> 3U)

#define SJTAG_INT_STATUS_SJTAG_READ_NONCE_RX(x) (((x) << 2U) & GENMASK(2U, 2U))
#define SJTAG_INT_STATUS_SJTAG_READ_NONCE_RX_M GENMASK(2U, 2U)
#define SJTAG_INT_STATUS_SJTAG_READ_NONCE_RX_X(x)\
	(((x) & GENMASK(2U, 2U)) >> 2U)

#define SJTAG_INT_STATUS_SJTAG_DIGEST_RX(x) (((x) << 1U) & GENMASK(1U, 1U))
#define SJTAG_INT_STATUS_SJTAG_DIGEST_RX_M  GENMASK(1U, 1U)
#define SJTAG_INT_STATUS_SJTAG_DIGEST_RX_X(x) (((x) & GENMASK(1U, 1U)) >> 1U)

#define SJTAG_INT_STATUS_SJTAG_UNLOCK_RX(x) ((x) & GENMASK(0U, 0U))
#define SJTAG_INT_STATUS_SJTAG_UNLOCK_RX_M  GENMASK(0U, 0U)
#define SJTAG_INT_STATUS_SJTAG_UNLOCK_RX_X(x) ((x) & GENMASK(0U, 0U))

/*      SJTAG:SJTAG_REGS:INT_MASK */
#define SJTAG_INT_MASK(t)         ((t) + 0x08U)

#define SJTAG_INT_MASK_SJTAG_TO_STS_MSK(x)  (((x) << 7U) & GENMASK(7U, 7U))
#define SJTAG_INT_MASK_SJTAG_TO_STS_MSK_M   GENMASK(7U, 7U)
#define SJTAG_INT_MASK_SJTAG_TO_STS_MSK_X(x) (((x) & GENMASK(7U, 7U)) >> 7U)

#define SJTAG_INT_MASK_SJTAG_UUID_RX_MSK(x) (((x) << 6U) & GENMASK(6U, 6U))
#define SJTAG_INT_MASK_SJTAG_UUID_RX_MSK_M  GENMASK(6U, 6U)
#define SJTAG_INT_MASK_SJTAG_UUID_RX_MSK_X(x) (((x) & GENMASK(6U, 6U)) >> 6U)

#define SJTAG_INT_MASK_SJTAG_READ_MODE_RX_MSK(x) (((x) << 5U) & GENMASK(5U, 5U))
#define SJTAG_INT_MASK_SJTAG_READ_MODE_RX_MSK_M GENMASK(5U, 5U)
#define SJTAG_INT_MASK_SJTAG_READ_MODE_RX_MSK_X(x)\
	(((x) & GENMASK(5U, 5U)) >> 5U)

#define SJTAG_INT_MASK_SJTAG_DIGEST_FAIL_MSK(x) (((x) << 4U) & GENMASK(4U, 4U))
#define SJTAG_INT_MASK_SJTAG_DIGEST_FAIL_MSK_M GENMASK(4U, 4U)
#define SJTAG_INT_MASK_SJTAG_DIGEST_FAIL_MSK_X(x)\
	(((x) & GENMASK(4U, 4U)) >> 4U)

#define SJTAG_INT_MASK_SJTAG_DIGEST_PASS_MSK(x) (((x) << 3U) & GENMASK(3U, 3U))
#define SJTAG_INT_MASK_SJTAG_DIGEST_PASS_MSK_M GENMASK(3U, 3U)
#define SJTAG_INT_MASK_SJTAG_DIGEST_PASS_MSK_X(x)\
	(((x) & GENMASK(3U, 3U)) >> 3U)

#define SJTAG_INT_MASK_SJTAG_NONCE_RX_MSK(x) (((x) << 2U) & GENMASK(2U, 2U))
#define SJTAG_INT_MASK_SJTAG_NONCE_RX_MSK_M GENMASK(2U, 2U)
#define SJTAG_INT_MASK_SJTAG_NONCE_RX_MSK_X(x) (((x) & GENMASK(2U, 2U)) >> 2U)

#define SJTAG_INT_MASK_SJTAG_DIGEST_RX_MSK(x) (((x) << 1U) & GENMASK(1U, 1U))
#define SJTAG_INT_MASK_SJTAG_DIGEST_RX_MSK_M GENMASK(1U, 1U)
#define SJTAG_INT_MASK_SJTAG_DIGEST_RX_MSK_X(x) (((x) & GENMASK(1U, 1U)) >> 1U)

#define SJTAG_INT_MASK_SJTAG_UNLOCK_RX_MSK(x) ((x) & GENMASK(0U, 0U))
#define SJTAG_INT_MASK_SJTAG_UNLOCK_RX_MSK_M GENMASK(0U, 0U)
#define SJTAG_INT_MASK_SJTAG_UNLOCK_RX_MSK_X(x) ((x) & GENMASK(0U, 0U))

/*      SJTAG:SJTAG_REGS:NONCE */
#define SJTAG_NONCE(t, r)         ((t) + (0x10U + ((r) * 4U)))

/*      SJTAG:SJTAG_REGS:HOST_DIGEST */
#define SJTAG_HOST_DIGEST(t, r)   ((t) + (0x30U + ((r) * 4U)))

/*      SJTAG:SJTAG_REGS:DEVICE_DIGEST */
#define SJTAG_DEVICE_DIGEST(t, r) ((t) + (0x50U + ((r) * 4U)))

/*      SJTAG:SJTAG_REGS:UUID */
#define SJTAG_UUID(t, r)          ((t) + (0x70U + ((r) * 4U)))

/*      SJTAG:SJTAG_REGS:HC_TO */
#define SJTAG_HC_TO(t)            ((t) + 0x80U)

/*      TRNG:TRNG_REGS:TRNG_CR */
#define TRNG_TRNG_CR(t)           ((t) + 0x00U)

#define TRNG_TRNG_CR_WAKEY(x)               (((x) << 8U) & GENMASK(31U, 8U))
#define TRNG_TRNG_CR_WAKEY_M                GENMASK(31U, 8U)
#define TRNG_TRNG_CR_WAKEY_X(x)             (((x) & GENMASK(31U, 8U)) >> 8U)

#define TRNG_TRNG_CR_ENABLE(x)              ((x) & GENMASK(0U, 0U))
#define TRNG_TRNG_CR_ENABLE_M               GENMASK(0U, 0U)
#define TRNG_TRNG_CR_ENABLE_X(x)            ((x) & GENMASK(0U, 0U))

/*      TRNG:TRNG_REGS:TRNG_MR */
#define TRNG_TRNG_MR(t)           ((t) + 0x04U)

#define TRNG_TRNG_MR_DIFF(x)                (((x) << 7U) & GENMASK(7U, 7U))
#define TRNG_TRNG_MR_DIFF_M                 GENMASK(7U, 7U)
#define TRNG_TRNG_MR_DIFF_X(x)              (((x) & GENMASK(7U, 7U)) >> 7U)

#define TRNG_TRNG_MR_HDSEL(x)               (((x) << 2U) & GENMASK(3U, 2U))
#define TRNG_TRNG_MR_HDSEL_M                GENMASK(3U, 2U)
#define TRNG_TRNG_MR_HDSEL_X(x)             (((x) & GENMASK(3U, 2U)) >> 2U)

#define TRNG_TRNG_MR_HD(x)                  (((x) << 1U) & GENMASK(1U, 1U))
#define TRNG_TRNG_MR_HD_M                   GENMASK(1U, 1U)
#define TRNG_TRNG_MR_HD_X(x)                (((x) & GENMASK(1U, 1U)) >> 1U)

#define TRNG_TRNG_MR_HALFR(x)               ((x) & GENMASK(0U, 0U))
#define TRNG_TRNG_MR_HALFR_M                GENMASK(0U, 0U)
#define TRNG_TRNG_MR_HALFR_X(x)             ((x) & GENMASK(0U, 0U))

/*      TRNG:TRNG_REGS:TRNG_PKBCR */
#define TRNG_TRNG_PKBCR(t)        ((t) + 0x08U)

#define TRNG_TRNG_PKBCR_WAKEY_PKBCR(x)      (((x) << 16U) & GENMASK(31U, 16U))
#define TRNG_TRNG_PKBCR_WAKEY_PKBCR_M       GENMASK(31U, 16U)
#define TRNG_TRNG_PKBCR_WAKEY_PKBCR_X(x)    (((x) & GENMASK(31U, 16U)) >> 16U)

#define TRNG_TRNG_PKBCR_KLENGTH(x)          (((x) << 8U) & GENMASK(15U, 8U))
#define TRNG_TRNG_PKBCR_KLENGTH_M           GENMASK(15U, 8U)
#define TRNG_TRNG_PKBCR_KLENGTH_X(x)        (((x) & GENMASK(15U, 8U)) >> 8U)

#define TRNG_TRNG_PKBCR_KTARGET(x)          (((x) << 4U) & GENMASK(5U, 4U))
#define TRNG_TRNG_PKBCR_KTARGET_M           GENMASK(5U, 4U)
#define TRNG_TRNG_PKBCR_KTARGET_X(x)        (((x) & GENMASK(5U, 4U)) >> 4U)

#define TRNG_TRNG_PKBCR_KID(x)              ((x) & GENMASK(0U, 0U))
#define TRNG_TRNG_PKBCR_KID_M               GENMASK(0U, 0U)
#define TRNG_TRNG_PKBCR_KID_X(x)            ((x) & GENMASK(0U, 0U))

/*      TRNG:TRNG_REGS:TRNG_IER */
#define TRNG_TRNG_IER(t)          ((t) + 0x10U)

#define TRNG_TRNG_IER_APHT(x)               (((x) << 4U) & GENMASK(4U, 4U))
#define TRNG_TRNG_IER_APHT_M                GENMASK(4U, 4U)
#define TRNG_TRNG_IER_APHT_X(x)             (((x) & GENMASK(4U, 4U)) >> 4U)

#define TRNG_TRNG_IER_RCHT(x)               (((x) << 3U) & GENMASK(3U, 3U))
#define TRNG_TRNG_IER_RCHT_M                GENMASK(3U, 3U)
#define TRNG_TRNG_IER_RCHT_X(x)             (((x) & GENMASK(3U, 3U)) >> 3U)

#define TRNG_TRNG_IER_EOTPKB(x)             (((x) << 2U) & GENMASK(2U, 2U))
#define TRNG_TRNG_IER_EOTPKB_M              GENMASK(2U, 2U)
#define TRNG_TRNG_IER_EOTPKB_X(x)           (((x) & GENMASK(2U, 2U)) >> 2U)

#define TRNG_TRNG_IER_SECE(x)               (((x) << 1U) & GENMASK(1U, 1U))
#define TRNG_TRNG_IER_SECE_M                GENMASK(1U, 1U)
#define TRNG_TRNG_IER_SECE_X(x)             (((x) & GENMASK(1U, 1U)) >> 1U)

#define TRNG_TRNG_IER_DATRDY(x)             ((x) & GENMASK(0U, 0U))
#define TRNG_TRNG_IER_DATRDY_M              GENMASK(0U, 0U)
#define TRNG_TRNG_IER_DATRDY_X(x)           ((x) & GENMASK(0U, 0U))

/*      TRNG:TRNG_REGS:TRNG_IDR */
#define TRNG_TRNG_IDR(t)          ((t) + 0x14U)

#define TRNG_TRNG_IDR_APHT_IDR(x)           (((x) << 4U) & GENMASK(4U, 4U))
#define TRNG_TRNG_IDR_APHT_IDR_M            GENMASK(4U, 4U)
#define TRNG_TRNG_IDR_APHT_IDR_X(x)         (((x) & GENMASK(4U, 4U)) >> 4U)

#define TRNG_TRNG_IDR_RCHT_IDR(x)           (((x) << 3U) & GENMASK(3U, 3U))
#define TRNG_TRNG_IDR_RCHT_IDR_M            GENMASK(3U, 3U)
#define TRNG_TRNG_IDR_RCHT_IDR_X(x)         (((x) & GENMASK(3U, 3U)) >> 3U)

#define TRNG_TRNG_IDR_EOTPKB_IDR(x)         (((x) << 2U) & GENMASK(2U, 2U))
#define TRNG_TRNG_IDR_EOTPKB_IDR_M          GENMASK(2U, 2U)
#define TRNG_TRNG_IDR_EOTPKB_IDR_X(x)       (((x) & GENMASK(2U, 2U)) >> 2U)

#define TRNG_TRNG_IDR_SECE_IDR(x)           (((x) << 1U) & GENMASK(1U, 1U))
#define TRNG_TRNG_IDR_SECE_IDR_M            GENMASK(1U, 1U)
#define TRNG_TRNG_IDR_SECE_IDR_X(x)         (((x) & GENMASK(1U, 1U)) >> 1U)

#define TRNG_TRNG_IDR_DATRDY_IDR(x)         ((x) & GENMASK(0U, 0U))
#define TRNG_TRNG_IDR_DATRDY_IDR_M          GENMASK(0U, 0U)
#define TRNG_TRNG_IDR_DATRDY_IDR_X(x)       ((x) & GENMASK(0U, 0U))

/*      TRNG:TRNG_REGS:TRNG_IMR */
#define TRNG_TRNG_IMR(t)          ((t) + 0x18U)

#define TRNG_TRNG_IMR_APHT_IMR(x)           (((x) << 4U) & GENMASK(4U, 4U))
#define TRNG_TRNG_IMR_APHT_IMR_M            GENMASK(4U, 4U)
#define TRNG_TRNG_IMR_APHT_IMR_X(x)         (((x) & GENMASK(4U, 4U)) >> 4U)

#define TRNG_TRNG_IMR_RCHT_IMR(x)           (((x) << 3U) & GENMASK(3U, 3U))
#define TRNG_TRNG_IMR_RCHT_IMR_M            GENMASK(3U, 3U)
#define TRNG_TRNG_IMR_RCHT_IMR_X(x)         (((x) & GENMASK(3U, 3U)) >> 3U)

#define TRNG_TRNG_IMR_EOTPKB_IMR(x)         (((x) << 2U) & GENMASK(2U, 2U))
#define TRNG_TRNG_IMR_EOTPKB_IMR_M          GENMASK(2U, 2U)
#define TRNG_TRNG_IMR_EOTPKB_IMR_X(x)       (((x) & GENMASK(2U, 2U)) >> 2U)

#define TRNG_TRNG_IMR_SECE_IMR(x)           (((x) << 1U) & GENMASK(1U, 1U))
#define TRNG_TRNG_IMR_SECE_IMR_M            GENMASK(1U, 1U)
#define TRNG_TRNG_IMR_SECE_IMR_X(x)         (((x) & GENMASK(1U, 1U)) >> 1U)

#define TRNG_TRNG_IMR_DATRDY_IMR(x)         ((x) & GENMASK(0U, 0U))
#define TRNG_TRNG_IMR_DATRDY_IMR_M          GENMASK(0U, 0U)
#define TRNG_TRNG_IMR_DATRDY_IMR_X(x)       ((x) & GENMASK(0U, 0U))

/*      TRNG:TRNG_REGS:TRNG_ISR */
#define TRNG_TRNG_ISR(t)          ((t) + 0x1cU)

#define TRNG_TRNG_ISR_APHT_ISR(x)           (((x) << 4U) & GENMASK(4U, 4U))
#define TRNG_TRNG_ISR_APHT_ISR_M            GENMASK(4U, 4U)
#define TRNG_TRNG_ISR_APHT_ISR_X(x)         (((x) & GENMASK(4U, 4U)) >> 4U)

#define TRNG_TRNG_ISR_RCHT_ISR(x)           (((x) << 3U) & GENMASK(3U, 3U))
#define TRNG_TRNG_ISR_RCHT_ISR_M            GENMASK(3U, 3U)
#define TRNG_TRNG_ISR_RCHT_ISR_X(x)         (((x) & GENMASK(3U, 3U)) >> 3U)

#define TRNG_TRNG_ISR_EOTPKB_ISR(x)         (((x) << 2U) & GENMASK(2U, 2U))
#define TRNG_TRNG_ISR_EOTPKB_ISR_M          GENMASK(2U, 2U)
#define TRNG_TRNG_ISR_EOTPKB_ISR_X(x)       (((x) & GENMASK(2U, 2U)) >> 2U)

#define TRNG_TRNG_ISR_SECE_ISR(x)           (((x) << 1U) & GENMASK(1U, 1U))
#define TRNG_TRNG_ISR_SECE_ISR_M            GENMASK(1U, 1U)
#define TRNG_TRNG_ISR_SECE_ISR_X(x)         (((x) & GENMASK(1U, 1U)) >> 1U)

#define TRNG_TRNG_ISR_DATRDY_ISR(x)         ((x) & GENMASK(0U, 0U))
#define TRNG_TRNG_ISR_DATRDY_ISR_M          GENMASK(0U, 0U)
#define TRNG_TRNG_ISR_DATRDY_ISR_X(x)       ((x) & GENMASK(0U, 0U))

/*      TRNG:TRNG_REGS:TRNG_HTMR */
#define TRNG_TRNG_HTMR(t)         ((t) + 0x30U)

#define TRNG_TRNG_HTMR_THRESHOLD(x)         (((x) << 16U) & GENMASK(25U, 16U))
#define TRNG_TRNG_HTMR_THRESHOLD_M          GENMASK(25U, 16U)
#define TRNG_TRNG_HTMR_THRESHOLD_X(x)       (((x) & GENMASK(25U, 16U)) >> 16U)

#define TRNG_TRNG_HTMR_APSRCSEL(x)          (((x) << 1U) & GENMASK(1U, 1U))
#define TRNG_TRNG_HTMR_APSRCSEL_M           GENMASK(1U, 1U)
#define TRNG_TRNG_HTMR_APSRCSEL_X(x)        (((x) & GENMASK(1U, 1U)) >> 1U)

#define TRNG_TRNG_HTMR_MPERIOD(x)           ((x) & GENMASK(0U, 0U))
#define TRNG_TRNG_HTMR_MPERIOD_M            GENMASK(0U, 0U)
#define TRNG_TRNG_HTMR_MPERIOD_X(x)         ((x) & GENMASK(0U, 0U))

/*      TRNG:TRNG_REGS:TRNG_FIR */
#define TRNG_TRNG_FIR(t)          ((t) + 0x40U)

#define TRNG_TRNG_FIR_FIKEY(x)              (((x) << 8U) & GENMASK(31U, 8U))
#define TRNG_TRNG_FIR_FIKEY_M               GENMASK(31U, 8U)
#define TRNG_TRNG_FIR_FIKEY_X(x)            (((x) & GENMASK(31U, 8U)) >> 8U)

#define TRNG_TRNG_FIR_NSFHT(x)              (((x) << 7U) & GENMASK(7U, 7U))
#define TRNG_TRNG_FIR_NSFHT_M               GENMASK(7U, 7U)
#define TRNG_TRNG_FIR_NSFHT_X(x)            (((x) & GENMASK(7U, 7U)) >> 7U)

#define TRNG_TRNG_FIR_FSEQE(x)              (((x) << 5U) & GENMASK(5U, 5U))
#define TRNG_TRNG_FIR_FSEQE_M               GENMASK(5U, 5U)
#define TRNG_TRNG_FIR_FSEQE_X(x)            (((x) & GENMASK(5U, 5U)) >> 5U)

#define TRNG_TRNG_FIR_F4(x)                 (((x) << 4U) & GENMASK(4U, 4U))
#define TRNG_TRNG_FIR_F4_M                  GENMASK(4U, 4U)
#define TRNG_TRNG_FIR_F4_X(x)               (((x) & GENMASK(4U, 4U)) >> 4U)

#define TRNG_TRNG_FIR_F3(x)                 (((x) << 3U) & GENMASK(3U, 3U))
#define TRNG_TRNG_FIR_F3_M                  GENMASK(3U, 3U)
#define TRNG_TRNG_FIR_F3_X(x)               (((x) & GENMASK(3U, 3U)) >> 3U)

#define TRNG_TRNG_FIR_F2(x)                 (((x) << 2U) & GENMASK(2U, 2U))
#define TRNG_TRNG_FIR_F2_M                  GENMASK(2U, 2U)
#define TRNG_TRNG_FIR_F2_X(x)               (((x) & GENMASK(2U, 2U)) >> 2U)

#define TRNG_TRNG_FIR_F1(x)                 (((x) << 1U) & GENMASK(1U, 1U))
#define TRNG_TRNG_FIR_F1_M                  GENMASK(1U, 1U)
#define TRNG_TRNG_FIR_F1_X(x)               (((x) & GENMASK(1U, 1U)) >> 1U)

#define TRNG_TRNG_FIR_F0(x)                 ((x) & GENMASK(0U, 0U))
#define TRNG_TRNG_FIR_F0_M                  GENMASK(0U, 0U)
#define TRNG_TRNG_FIR_F0_X(x)               ((x) & GENMASK(0U, 0U))

/*      TRNG:TRNG_REGS:TRNG_ODATA */
#define TRNG_TRNG_ODATA(t)        ((t) + 0x50U)

/*      TRNG:TRNG_REGS:TRNG_WPMR */
#define TRNG_TRNG_WPMR(t)         ((t) + 0xe4U)

#define TRNG_TRNG_WPMR_WPKEY(x)             (((x) << 8U) & GENMASK(31U, 8U))
#define TRNG_TRNG_WPMR_WPKEY_M              GENMASK(31U, 8U)
#define TRNG_TRNG_WPMR_WPKEY_X(x)           (((x) & GENMASK(31U, 8U)) >> 8U)

#define TRNG_TRNG_WPMR_LCKCREN(x)           (((x) << 7U) & GENMASK(7U, 7U))
#define TRNG_TRNG_WPMR_LCKCREN_M            GENMASK(7U, 7U)
#define TRNG_TRNG_WPMR_LCKCREN_X(x)         (((x) & GENMASK(7U, 7U)) >> 7U)

#define TRNG_TRNG_WPMR_LCKITEN(x)           (((x) << 6U) & GENMASK(6U, 6U))
#define TRNG_TRNG_WPMR_LCKITEN_M            GENMASK(6U, 6U)
#define TRNG_TRNG_WPMR_LCKITEN_X(x)         (((x) & GENMASK(6U, 6U)) >> 6U)

#define TRNG_TRNG_WPMR_LCKWPEN(x)           (((x) << 5U) & GENMASK(5U, 5U))
#define TRNG_TRNG_WPMR_LCKWPEN_M            GENMASK(5U, 5U)
#define TRNG_TRNG_WPMR_LCKWPEN_X(x)         (((x) & GENMASK(5U, 5U)) >> 5U)

#define TRNG_TRNG_WPMR_FIRSTE(x)            (((x) << 4U) & GENMASK(4U, 4U))
#define TRNG_TRNG_WPMR_FIRSTE_M             GENMASK(4U, 4U)
#define TRNG_TRNG_WPMR_FIRSTE_X(x)          (((x) & GENMASK(4U, 4U)) >> 4U)

#define TRNG_TRNG_WPMR_WPCREN(x)            (((x) << 2U) & GENMASK(2U, 2U))
#define TRNG_TRNG_WPMR_WPCREN_M             GENMASK(2U, 2U)
#define TRNG_TRNG_WPMR_WPCREN_X(x)          (((x) & GENMASK(2U, 2U)) >> 2U)

#define TRNG_TRNG_WPMR_WPITEN(x)            (((x) << 1U) & GENMASK(1U, 1U))
#define TRNG_TRNG_WPMR_WPITEN_M             GENMASK(1U, 1U)
#define TRNG_TRNG_WPMR_WPITEN_X(x)          (((x) & GENMASK(1U, 1U)) >> 1U)

#define TRNG_TRNG_WPMR_WPEN(x)              ((x) & GENMASK(0U, 0U))
#define TRNG_TRNG_WPMR_WPEN_M               GENMASK(0U, 0U)
#define TRNG_TRNG_WPMR_WPEN_X(x)            ((x) & GENMASK(0U, 0U))

/*      TRNG:TRNG_REGS:TRNG_WPSR */
#define TRNG_TRNG_WPSR(t)         ((t) + 0xe8U)

#define TRNG_TRNG_WPSR_ECLASS(x)            (((x) << 31U) & GENMASK(31U, 31U))
#define TRNG_TRNG_WPSR_ECLASS_M             GENMASK(31U, 31U)
#define TRNG_TRNG_WPSR_ECLASS_X(x)          (((x) & GENMASK(31U, 31U)) >> 31U)

#define TRNG_TRNG_WPSR_SWETYP(x)            (((x) << 24U) & GENMASK(27U, 24U))
#define TRNG_TRNG_WPSR_SWETYP_M             GENMASK(27U, 24U)
#define TRNG_TRNG_WPSR_SWETYP_X(x)          (((x) & GENMASK(27U, 24U)) >> 24U)

#define TRNG_TRNG_WPSR_WPVSRC(x)            (((x) << 8U) & GENMASK(23U, 8U))
#define TRNG_TRNG_WPSR_WPVSRC_M             GENMASK(23U, 8U)
#define TRNG_TRNG_WPSR_WPVSRC_X(x)          (((x) & GENMASK(23U, 8U)) >> 8U)

#define TRNG_TRNG_WPSR_SDEE(x)              (((x) << 4U) & GENMASK(4U, 4U))
#define TRNG_TRNG_WPSR_SDEE_M               GENMASK(4U, 4U)
#define TRNG_TRNG_WPSR_SDEE_X(x)            (((x) & GENMASK(4U, 4U)) >> 4U)

#define TRNG_TRNG_WPSR_SWE(x)               (((x) << 3U) & GENMASK(3U, 3U))
#define TRNG_TRNG_WPSR_SWE_M                GENMASK(3U, 3U)
#define TRNG_TRNG_WPSR_SWE_X(x)             (((x) & GENMASK(3U, 3U)) >> 3U)

#define TRNG_TRNG_WPSR_SEQE(x)              (((x) << 2U) & GENMASK(2U, 2U))
#define TRNG_TRNG_WPSR_SEQE_M               GENMASK(2U, 2U)
#define TRNG_TRNG_WPSR_SEQE_X(x)            (((x) & GENMASK(2U, 2U)) >> 2U)

#define TRNG_TRNG_WPSR_CGD(x)               (((x) << 1U) & GENMASK(1U, 1U))
#define TRNG_TRNG_WPSR_CGD_M                GENMASK(1U, 1U)
#define TRNG_TRNG_WPSR_CGD_X(x)             (((x) & GENMASK(1U, 1U)) >> 1U)

#define TRNG_TRNG_WPSR_WPVS(x)              ((x) & GENMASK(0U, 0U))
#define TRNG_TRNG_WPSR_WPVS_M               GENMASK(0U, 0U)
#define TRNG_TRNG_WPSR_WPVS_X(x)            ((x) & GENMASK(0U, 0U))

/*      TRNG:TRNG_REGS:TRNG_VERSION */
#define TRNG_TRNG_VERSION(t)      ((t) + 0xfcU)

#define TRNG_TRNG_VERSION_MFN(x)            (((x) << 16U) & GENMASK(18U, 16U))
#define TRNG_TRNG_VERSION_MFN_M             GENMASK(18U, 16U)
#define TRNG_TRNG_VERSION_MFN_X(x)          (((x) & GENMASK(18U, 16U)) >> 16U)

#define TRNG_TRNG_VERSION_VERSION(x)        ((x) & GENMASK(11U, 0U))
#define TRNG_TRNG_VERSION_VERSION_M         GENMASK(11U, 0U)
#define TRNG_TRNG_VERSION_VERSION_X(x)      ((x) & GENMASK(11U, 0U))

/*      TZAESBNS:TZAESB_REGS:TZAESB_CR */
#define TZAESBNS_TZAESB_CR(t)     ((t) + 0x00U)

#define TZAESBNS_TZAESB_CR_UNLOCK(x)        (((x) << 24U) & GENMASK(24U, 24U))
#define TZAESBNS_TZAESB_CR_UNLOCK_M         GENMASK(24U, 24U)
#define TZAESBNS_TZAESB_CR_UNLOCK_X(x)      (((x) & GENMASK(24U, 24U)) >> 24U)

#define TZAESBNS_TZAESB_CR_LOADSEED(x)      (((x) << 16U) & GENMASK(16U, 16U))
#define TZAESBNS_TZAESB_CR_LOADSEED_M       GENMASK(16U, 16U)
#define TZAESBNS_TZAESB_CR_LOADSEED_X(x)    (((x) & GENMASK(16U, 16U)) >> 16U)

#define TZAESBNS_TZAESB_CR_SWRST(x)         (((x) << 8U) & GENMASK(8U, 8U))
#define TZAESBNS_TZAESB_CR_SWRST_M          GENMASK(8U, 8U)
#define TZAESBNS_TZAESB_CR_SWRST_X(x)       (((x) & GENMASK(8U, 8U)) >> 8U)

#define TZAESBNS_TZAESB_CR_START(x)         ((x) & GENMASK(0U, 0U))
#define TZAESBNS_TZAESB_CR_START_M          GENMASK(0U, 0U)
#define TZAESBNS_TZAESB_CR_START_X(x)       ((x) & GENMASK(0U, 0U))

/*      TZAESBNS:TZAESB_REGS:TZAESB_MR */
#define TZAESBNS_TZAESB_MR(t)     ((t) + 0x04U)

#define TZAESBNS_TZAESB_MR_TAMPCLR(x)       (((x) << 31U) & GENMASK(31U, 31U))
#define TZAESBNS_TZAESB_MR_TAMPCLR_M        GENMASK(31U, 31U)
#define TZAESBNS_TZAESB_MR_TAMPCLR_X(x)     (((x) & GENMASK(31U, 31U)) >> 31U)

#define TZAESBNS_TZAESB_MR_CMTYP7(x)        (((x) << 30U) & GENMASK(30U, 30U))
#define TZAESBNS_TZAESB_MR_CMTYP7_M         GENMASK(30U, 30U)
#define TZAESBNS_TZAESB_MR_CMTYP7_X(x)      (((x) & GENMASK(30U, 30U)) >> 30U)

#define TZAESBNS_TZAESB_MR_CMTYP6(x)        (((x) << 29U) & GENMASK(29U, 29U))
#define TZAESBNS_TZAESB_MR_CMTYP6_M         GENMASK(29U, 29U)
#define TZAESBNS_TZAESB_MR_CMTYP6_X(x)      (((x) & GENMASK(29U, 29U)) >> 29U)

#define TZAESBNS_TZAESB_MR_CMTYP5(x)        (((x) << 28U) & GENMASK(28U, 28U))
#define TZAESBNS_TZAESB_MR_CMTYP5_M         GENMASK(28U, 28U)
#define TZAESBNS_TZAESB_MR_CMTYP5_X(x)      (((x) & GENMASK(28U, 28U)) >> 28U)

#define TZAESBNS_TZAESB_MR_CMTYP4(x)        (((x) << 27U) & GENMASK(27U, 27U))
#define TZAESBNS_TZAESB_MR_CMTYP4_M         GENMASK(27U, 27U)
#define TZAESBNS_TZAESB_MR_CMTYP4_X(x)      (((x) & GENMASK(27U, 27U)) >> 27U)

#define TZAESBNS_TZAESB_MR_CMTYP3(x)        (((x) << 26U) & GENMASK(26U, 26U))
#define TZAESBNS_TZAESB_MR_CMTYP3_M         GENMASK(26U, 26U)
#define TZAESBNS_TZAESB_MR_CMTYP3_X(x)      (((x) & GENMASK(26U, 26U)) >> 26U)

#define TZAESBNS_TZAESB_MR_CMTYP2(x)        (((x) << 25U) & GENMASK(25U, 25U))
#define TZAESBNS_TZAESB_MR_CMTYP2_M         GENMASK(25U, 25U)
#define TZAESBNS_TZAESB_MR_CMTYP2_X(x)      (((x) & GENMASK(25U, 25U)) >> 25U)

#define TZAESBNS_TZAESB_MR_CMTYP1(x)        (((x) << 24U) & GENMASK(24U, 24U))
#define TZAESBNS_TZAESB_MR_CMTYP1_M         GENMASK(24U, 24U)
#define TZAESBNS_TZAESB_MR_CMTYP1_X(x)      (((x) & GENMASK(24U, 24U)) >> 24U)

#define TZAESBNS_TZAESB_MR_CKEY(x)          (((x) << 20U) & GENMASK(23U, 20U))
#define TZAESBNS_TZAESB_MR_CKEY_M           GENMASK(23U, 20U)
#define TZAESBNS_TZAESB_MR_CKEY_X(x)        (((x) & GENMASK(23U, 20U)) >> 20U)

#define TZAESBNS_TZAESB_MR_OPMOD(x)         (((x) << 12U) & GENMASK(14U, 12U))
#define TZAESBNS_TZAESB_MR_OPMOD_M          GENMASK(14U, 12U)
#define TZAESBNS_TZAESB_MR_OPMOD_X(x)       (((x) & GENMASK(14U, 12U)) >> 12U)

#define TZAESBNS_TZAESB_MR_PROCDLY(x)       (((x) << 4U) & GENMASK(7U, 4U))
#define TZAESBNS_TZAESB_MR_PROCDLY_M        GENMASK(7U, 4U)
#define TZAESBNS_TZAESB_MR_PROCDLY_X(x)     (((x) & GENMASK(7U, 4U)) >> 4U)

#define TZAESBNS_TZAESB_MR_DUALBUFF(x)      (((x) << 3U) & GENMASK(3U, 3U))
#define TZAESBNS_TZAESB_MR_DUALBUFF_M       GENMASK(3U, 3U)
#define TZAESBNS_TZAESB_MR_DUALBUFF_X(x)    (((x) & GENMASK(3U, 3U)) >> 3U)

#define TZAESBNS_TZAESB_MR_AAHB(x)          (((x) << 2U) & GENMASK(2U, 2U))
#define TZAESBNS_TZAESB_MR_AAHB_M           GENMASK(2U, 2U)
#define TZAESBNS_TZAESB_MR_AAHB_X(x)        (((x) & GENMASK(2U, 2U)) >> 2U)

/*      TZAESBNS:TZAESB_REGS:TZAESB_IER */
#define TZAESBNS_TZAESB_IER(t)    ((t) + 0x10U)

#define TZAESBNS_TZAESB_IER_SECE(x)         (((x) << 19U) & GENMASK(19U, 19U))
#define TZAESBNS_TZAESB_IER_SECE_M          GENMASK(19U, 19U)
#define TZAESBNS_TZAESB_IER_SECE_X(x)       (((x) & GENMASK(19U, 19U)) >> 19U)

#define TZAESBNS_TZAESB_IER_URAD(x)         (((x) << 8U) & GENMASK(8U, 8U))
#define TZAESBNS_TZAESB_IER_URAD_M          GENMASK(8U, 8U)
#define TZAESBNS_TZAESB_IER_URAD_X(x)       (((x) & GENMASK(8U, 8U)) >> 8U)

/*      TZAESBNS:TZAESB_REGS:TZAESB_IDR */
#define TZAESBNS_TZAESB_IDR(t)    ((t) + 0x14U)

#define TZAESBNS_TZAESB_IDR_SECE_IDR(x)     (((x) << 19U) & GENMASK(19U, 19U))
#define TZAESBNS_TZAESB_IDR_SECE_IDR_M      GENMASK(19U, 19U)
#define TZAESBNS_TZAESB_IDR_SECE_IDR_X(x)   (((x) & GENMASK(19U, 19U)) >> 19U)

#define TZAESBNS_TZAESB_IDR_URAD_IDR(x)     (((x) << 8U) & GENMASK(8U, 8U))
#define TZAESBNS_TZAESB_IDR_URAD_IDR_M      GENMASK(8U, 8U)
#define TZAESBNS_TZAESB_IDR_URAD_IDR_X(x)   (((x) & GENMASK(8U, 8U)) >> 8U)

/*      TZAESBNS:TZAESB_REGS:TZAESB_IMR */
#define TZAESBNS_TZAESB_IMR(t)    ((t) + 0x18U)

#define TZAESBNS_TZAESB_IMR_SECE_IMR(x)     (((x) << 19U) & GENMASK(19U, 19U))
#define TZAESBNS_TZAESB_IMR_SECE_IMR_M      GENMASK(19U, 19U)
#define TZAESBNS_TZAESB_IMR_SECE_IMR_X(x)   (((x) & GENMASK(19U, 19U)) >> 19U)

#define TZAESBNS_TZAESB_IMR_URAD_IMR(x)     (((x) << 8U) & GENMASK(8U, 8U))
#define TZAESBNS_TZAESB_IMR_URAD_IMR_M      GENMASK(8U, 8U)
#define TZAESBNS_TZAESB_IMR_URAD_IMR_X(x)   (((x) & GENMASK(8U, 8U)) >> 8U)

/*      TZAESBNS:TZAESB_REGS:TZAESB_ISR */
#define TZAESBNS_TZAESB_ISR(t)    ((t) + 0x1cU)

#define TZAESBNS_TZAESB_ISR_SECE_ISR(x)     (((x) << 19U) & GENMASK(19U, 19U))
#define TZAESBNS_TZAESB_ISR_SECE_ISR_M      GENMASK(19U, 19U)
#define TZAESBNS_TZAESB_ISR_SECE_ISR_X(x)   (((x) & GENMASK(19U, 19U)) >> 19U)

#define TZAESBNS_TZAESB_ISR_URAT_ISR(x)     (((x) << 12U) & GENMASK(15U, 12U))
#define TZAESBNS_TZAESB_ISR_URAT_ISR_M      GENMASK(15U, 12U)
#define TZAESBNS_TZAESB_ISR_URAT_ISR_X(x)   (((x) & GENMASK(15U, 12U)) >> 12U)

#define TZAESBNS_TZAESB_ISR_URAD_ISR(x)     (((x) << 8U) & GENMASK(8U, 8U))
#define TZAESBNS_TZAESB_ISR_URAD_ISR_M      GENMASK(8U, 8U)
#define TZAESBNS_TZAESB_ISR_URAD_ISR_X(x)   (((x) & GENMASK(8U, 8U)) >> 8U)

/*      TZAESBNS:TZAESB_REGS:TZAESB_KEYWR0 */
#define TZAESBNS_TZAESB_KEYWR0(t) ((t) + 0x20U)

/*      TZAESBNS:TZAESB_REGS:TZAESB_KEYWR1 */
#define TZAESBNS_TZAESB_KEYWR1(t) ((t) + 0x24U)

/*      TZAESBNS:TZAESB_REGS:TZAESB_KEYWR2 */
#define TZAESBNS_TZAESB_KEYWR2(t) ((t) + 0x28U)

/*      TZAESBNS:TZAESB_REGS:TZAESB_KEYWR3 */
#define TZAESBNS_TZAESB_KEYWR3(t) ((t) + 0x2cU)

/*      TZAESBNS:TZAESB_REGS:TZAESB_IVR0 */
#define TZAESBNS_TZAESB_IVR0(t)   ((t) + 0x60U)

/*      TZAESBNS:TZAESB_REGS:TZAESB_IVR1 */
#define TZAESBNS_TZAESB_IVR1(t)   ((t) + 0x64U)

/*      TZAESBNS:TZAESB_REGS:TZAESB_IVR2 */
#define TZAESBNS_TZAESB_IVR2(t)   ((t) + 0x68U)

/*      TZAESBNS:TZAESB_REGS:TZAESB_IVR3 */
#define TZAESBNS_TZAESB_IVR3(t)   ((t) + 0x6cU)

/*      TZAESBNS:TZAESB_REGS:TZAESB_EMR */
#define TZAESBNS_TZAESB_EMR(t)    ((t) + 0xb0U)

#define TZAESBNS_TZAESB_EMR_PKRS(x)         (((x) << 7U) & GENMASK(7U, 7U))
#define TZAESBNS_TZAESB_EMR_PKRS_M          GENMASK(7U, 7U)
#define TZAESBNS_TZAESB_EMR_PKRS_X(x)       (((x) & GENMASK(7U, 7U)) >> 7U)

#define TZAESBNS_TZAESB_EMR_PKWO(x)         (((x) << 6U) & GENMASK(6U, 6U))
#define TZAESBNS_TZAESB_EMR_PKWO_M          GENMASK(6U, 6U)
#define TZAESBNS_TZAESB_EMR_PKWO_X(x)       (((x) & GENMASK(6U, 6U)) >> 6U)

/*      TZAESBNS:TZAESB_REGS:TZAESB_WPMR */
#define TZAESBNS_TZAESB_WPMR(t)   ((t) + 0xe4U)

#define TZAESBNS_TZAESB_WPMR_WPKEY(x)       (((x) << 8U) & GENMASK(31U, 8U))
#define TZAESBNS_TZAESB_WPMR_WPKEY_M        GENMASK(31U, 8U)
#define TZAESBNS_TZAESB_WPMR_WPKEY_X(x)     (((x) & GENMASK(31U, 8U)) >> 8U)

#define TZAESBNS_TZAESB_WPMR_ACTION(x)      (((x) << 5U) & GENMASK(7U, 5U))
#define TZAESBNS_TZAESB_WPMR_ACTION_M       GENMASK(7U, 5U)
#define TZAESBNS_TZAESB_WPMR_ACTION_X(x)    (((x) & GENMASK(7U, 5U)) >> 5U)

#define TZAESBNS_TZAESB_WPMR_FIRSTE(x)      (((x) << 4U) & GENMASK(4U, 4U))
#define TZAESBNS_TZAESB_WPMR_FIRSTE_M       GENMASK(4U, 4U)
#define TZAESBNS_TZAESB_WPMR_FIRSTE_X(x)    (((x) & GENMASK(4U, 4U)) >> 4U)

#define TZAESBNS_TZAESB_WPMR_WPCREN(x)      (((x) << 2U) & GENMASK(2U, 2U))
#define TZAESBNS_TZAESB_WPMR_WPCREN_M       GENMASK(2U, 2U)
#define TZAESBNS_TZAESB_WPMR_WPCREN_X(x)    (((x) & GENMASK(2U, 2U)) >> 2U)

#define TZAESBNS_TZAESB_WPMR_WPITEN(x)      (((x) << 1U) & GENMASK(1U, 1U))
#define TZAESBNS_TZAESB_WPMR_WPITEN_M       GENMASK(1U, 1U)
#define TZAESBNS_TZAESB_WPMR_WPITEN_X(x)    (((x) & GENMASK(1U, 1U)) >> 1U)

#define TZAESBNS_TZAESB_WPMR_WPEN(x)        ((x) & GENMASK(0U, 0U))
#define TZAESBNS_TZAESB_WPMR_WPEN_M         GENMASK(0U, 0U)
#define TZAESBNS_TZAESB_WPMR_WPEN_X(x)      ((x) & GENMASK(0U, 0U))

/*      TZAESBNS:TZAESB_REGS:TZAESB_WPSR */
#define TZAESBNS_TZAESB_WPSR(t)   ((t) + 0xe8U)

#define TZAESBNS_TZAESB_WPSR_ECLASS(x)      (((x) << 31U) & GENMASK(31U, 31U))
#define TZAESBNS_TZAESB_WPSR_ECLASS_M       GENMASK(31U, 31U)
#define TZAESBNS_TZAESB_WPSR_ECLASS_X(x)    (((x) & GENMASK(31U, 31U)) >> 31U)

#define TZAESBNS_TZAESB_WPSR_SWETYP(x)      (((x) << 24U) & GENMASK(27U, 24U))
#define TZAESBNS_TZAESB_WPSR_SWETYP_M       GENMASK(27U, 24U)
#define TZAESBNS_TZAESB_WPSR_SWETYP_X(x)    (((x) & GENMASK(27U, 24U)) >> 24U)

#define TZAESBNS_TZAESB_WPSR_WPVSRC(x)      (((x) << 8U) & GENMASK(15U, 8U))
#define TZAESBNS_TZAESB_WPSR_WPVSRC_M       GENMASK(15U, 8U)
#define TZAESBNS_TZAESB_WPSR_WPVSRC_X(x)    (((x) & GENMASK(15U, 8U)) >> 8U)

#define TZAESBNS_TZAESB_WPSR_PKRPVS(x)      (((x) << 4U) & GENMASK(4U, 4U))
#define TZAESBNS_TZAESB_WPSR_PKRPVS_M       GENMASK(4U, 4U)
#define TZAESBNS_TZAESB_WPSR_PKRPVS_X(x)    (((x) & GENMASK(4U, 4U)) >> 4U)

#define TZAESBNS_TZAESB_WPSR_SWE(x)         (((x) << 3U) & GENMASK(3U, 3U))
#define TZAESBNS_TZAESB_WPSR_SWE_M          GENMASK(3U, 3U)
#define TZAESBNS_TZAESB_WPSR_SWE_X(x)       (((x) & GENMASK(3U, 3U)) >> 3U)

#define TZAESBNS_TZAESB_WPSR_SEQE(x)        (((x) << 2U) & GENMASK(2U, 2U))
#define TZAESBNS_TZAESB_WPSR_SEQE_M         GENMASK(2U, 2U)
#define TZAESBNS_TZAESB_WPSR_SEQE_X(x)      (((x) & GENMASK(2U, 2U)) >> 2U)

#define TZAESBNS_TZAESB_WPSR_CGD(x)         (((x) << 1U) & GENMASK(1U, 1U))
#define TZAESBNS_TZAESB_WPSR_CGD_M          GENMASK(1U, 1U)
#define TZAESBNS_TZAESB_WPSR_CGD_X(x)       (((x) & GENMASK(1U, 1U)) >> 1U)

#define TZAESBNS_TZAESB_WPSR_WPVS(x)        ((x) & GENMASK(0U, 0U))
#define TZAESBNS_TZAESB_WPSR_WPVS_M         GENMASK(0U, 0U)
#define TZAESBNS_TZAESB_WPSR_WPVS_X(x)      ((x) & GENMASK(0U, 0U))

/*      TZAESBNS:TZAESB_REGS:TZAESB_VERSION */
#define TZAESBNS_TZAESB_VERSION(t) ((t) + 0xfcU)

#define TZAESBNS_TZAESB_VERSION_MFN(x)      (((x) << 16U) & GENMASK(18U, 16U))
#define TZAESBNS_TZAESB_VERSION_MFN_M       GENMASK(18U, 16U)
#define TZAESBNS_TZAESB_VERSION_MFN_X(x)    (((x) & GENMASK(18U, 16U)) >> 16U)

#define TZAESBNS_TZAESB_VERSION_VERSION(x)  ((x) & GENMASK(11U, 0U))
#define TZAESBNS_TZAESB_VERSION_VERSION_M   GENMASK(11U, 0U)
#define TZAESBNS_TZAESB_VERSION_VERSION_X(x) ((x) & GENMASK(11U, 0U))

/*      TZAESBS:TZAESB_REGS:TZAESB_CR */
#define TZAESBS_TZAESB_CR(t)      ((t) + 0x00U)

#define TZAESBS_TZAESB_CR_UNLOCK(x)         (((x) << 24U) & GENMASK(24U, 24U))
#define TZAESBS_TZAESB_CR_UNLOCK_M          GENMASK(24U, 24U)
#define TZAESBS_TZAESB_CR_UNLOCK_X(x)       (((x) & GENMASK(24U, 24U)) >> 24U)

#define TZAESBS_TZAESB_CR_LOADSEED(x)       (((x) << 16U) & GENMASK(16U, 16U))
#define TZAESBS_TZAESB_CR_LOADSEED_M        GENMASK(16U, 16U)
#define TZAESBS_TZAESB_CR_LOADSEED_X(x)     (((x) & GENMASK(16U, 16U)) >> 16U)

#define TZAESBS_TZAESB_CR_SWRST(x)          (((x) << 8U) & GENMASK(8U, 8U))
#define TZAESBS_TZAESB_CR_SWRST_M           GENMASK(8U, 8U)
#define TZAESBS_TZAESB_CR_SWRST_X(x)        (((x) & GENMASK(8U, 8U)) >> 8U)

#define TZAESBS_TZAESB_CR_START(x)          ((x) & GENMASK(0U, 0U))
#define TZAESBS_TZAESB_CR_START_M           GENMASK(0U, 0U)
#define TZAESBS_TZAESB_CR_START_X(x)        ((x) & GENMASK(0U, 0U))

/*      TZAESBS:TZAESB_REGS:TZAESB_MR */
#define TZAESBS_TZAESB_MR(t)      ((t) + 0x04U)

#define TZAESBS_TZAESB_MR_TAMPCLR(x)        (((x) << 31U) & GENMASK(31U, 31U))
#define TZAESBS_TZAESB_MR_TAMPCLR_M         GENMASK(31U, 31U)
#define TZAESBS_TZAESB_MR_TAMPCLR_X(x)      (((x) & GENMASK(31U, 31U)) >> 31U)

#define TZAESBS_TZAESB_MR_CMTYP7(x)         (((x) << 30U) & GENMASK(30U, 30U))
#define TZAESBS_TZAESB_MR_CMTYP7_M          GENMASK(30U, 30U)
#define TZAESBS_TZAESB_MR_CMTYP7_X(x)       (((x) & GENMASK(30U, 30U)) >> 30U)

#define TZAESBS_TZAESB_MR_CMTYP6(x)         (((x) << 29U) & GENMASK(29U, 29U))
#define TZAESBS_TZAESB_MR_CMTYP6_M          GENMASK(29U, 29U)
#define TZAESBS_TZAESB_MR_CMTYP6_X(x)       (((x) & GENMASK(29U, 29U)) >> 29U)

#define TZAESBS_TZAESB_MR_CMTYP5(x)         (((x) << 28U) & GENMASK(28U, 28U))
#define TZAESBS_TZAESB_MR_CMTYP5_M          GENMASK(28U, 28U)
#define TZAESBS_TZAESB_MR_CMTYP5_X(x)       (((x) & GENMASK(28U, 28U)) >> 28U)

#define TZAESBS_TZAESB_MR_CMTYP4(x)         (((x) << 27U) & GENMASK(27U, 27U))
#define TZAESBS_TZAESB_MR_CMTYP4_M          GENMASK(27U, 27U)
#define TZAESBS_TZAESB_MR_CMTYP4_X(x)       (((x) & GENMASK(27U, 27U)) >> 27U)

#define TZAESBS_TZAESB_MR_CMTYP3(x)         (((x) << 26U) & GENMASK(26U, 26U))
#define TZAESBS_TZAESB_MR_CMTYP3_M          GENMASK(26U, 26U)
#define TZAESBS_TZAESB_MR_CMTYP3_X(x)       (((x) & GENMASK(26U, 26U)) >> 26U)

#define TZAESBS_TZAESB_MR_CMTYP2(x)         (((x) << 25U) & GENMASK(25U, 25U))
#define TZAESBS_TZAESB_MR_CMTYP2_M          GENMASK(25U, 25U)
#define TZAESBS_TZAESB_MR_CMTYP2_X(x)       (((x) & GENMASK(25U, 25U)) >> 25U)

#define TZAESBS_TZAESB_MR_CMTYP1(x)         (((x) << 24U) & GENMASK(24U, 24U))
#define TZAESBS_TZAESB_MR_CMTYP1_M          GENMASK(24U, 24U)
#define TZAESBS_TZAESB_MR_CMTYP1_X(x)       (((x) & GENMASK(24U, 24U)) >> 24U)

#define TZAESBS_TZAESB_MR_CKEY(x)           (((x) << 20U) & GENMASK(23U, 20U))
#define TZAESBS_TZAESB_MR_CKEY_M            GENMASK(23U, 20U)
#define TZAESBS_TZAESB_MR_CKEY_X(x)         (((x) & GENMASK(23U, 20U)) >> 20U)

#define TZAESBS_TZAESB_MR_OPMOD(x)          (((x) << 12U) & GENMASK(14U, 12U))
#define TZAESBS_TZAESB_MR_OPMOD_M           GENMASK(14U, 12U)
#define TZAESBS_TZAESB_MR_OPMOD_X(x)        (((x) & GENMASK(14U, 12U)) >> 12U)

#define TZAESBS_TZAESB_MR_PROCDLY(x)        (((x) << 4U) & GENMASK(7U, 4U))
#define TZAESBS_TZAESB_MR_PROCDLY_M         GENMASK(7U, 4U)
#define TZAESBS_TZAESB_MR_PROCDLY_X(x)      (((x) & GENMASK(7U, 4U)) >> 4U)

#define TZAESBS_TZAESB_MR_DUALBUFF(x)       (((x) << 3U) & GENMASK(3U, 3U))
#define TZAESBS_TZAESB_MR_DUALBUFF_M        GENMASK(3U, 3U)
#define TZAESBS_TZAESB_MR_DUALBUFF_X(x)     (((x) & GENMASK(3U, 3U)) >> 3U)

#define TZAESBS_TZAESB_MR_AAHB(x)           (((x) << 2U) & GENMASK(2U, 2U))
#define TZAESBS_TZAESB_MR_AAHB_M            GENMASK(2U, 2U)
#define TZAESBS_TZAESB_MR_AAHB_X(x)         (((x) & GENMASK(2U, 2U)) >> 2U)

/*      TZAESBS:TZAESB_REGS:TZAESB_IER */
#define TZAESBS_TZAESB_IER(t)     ((t) + 0x10U)

#define TZAESBS_TZAESB_IER_SECE(x)          (((x) << 19U) & GENMASK(19U, 19U))
#define TZAESBS_TZAESB_IER_SECE_M           GENMASK(19U, 19U)
#define TZAESBS_TZAESB_IER_SECE_X(x)        (((x) & GENMASK(19U, 19U)) >> 19U)

#define TZAESBS_TZAESB_IER_URAD(x)          (((x) << 8U) & GENMASK(8U, 8U))
#define TZAESBS_TZAESB_IER_URAD_M           GENMASK(8U, 8U)
#define TZAESBS_TZAESB_IER_URAD_X(x)        (((x) & GENMASK(8U, 8U)) >> 8U)

/*      TZAESBS:TZAESB_REGS:TZAESB_IDR */
#define TZAESBS_TZAESB_IDR(t)     ((t) + 0x14U)

#define TZAESBS_TZAESB_IDR_SECE_IDR(x)      (((x) << 19U) & GENMASK(19U, 19U))
#define TZAESBS_TZAESB_IDR_SECE_IDR_M       GENMASK(19U, 19U)
#define TZAESBS_TZAESB_IDR_SECE_IDR_X(x)    (((x) & GENMASK(19U, 19U)) >> 19U)

#define TZAESBS_TZAESB_IDR_URAD_IDR(x)      (((x) << 8U) & GENMASK(8U, 8U))
#define TZAESBS_TZAESB_IDR_URAD_IDR_M       GENMASK(8U, 8U)
#define TZAESBS_TZAESB_IDR_URAD_IDR_X(x)    (((x) & GENMASK(8U, 8U)) >> 8U)

/*      TZAESBS:TZAESB_REGS:TZAESB_IMR */
#define TZAESBS_TZAESB_IMR(t)     ((t) + 0x18U)

#define TZAESBS_TZAESB_IMR_SECE_IMR(x)      (((x) << 19U) & GENMASK(19U, 19U))
#define TZAESBS_TZAESB_IMR_SECE_IMR_M       GENMASK(19U, 19U)
#define TZAESBS_TZAESB_IMR_SECE_IMR_X(x)    (((x) & GENMASK(19U, 19U)) >> 19U)

#define TZAESBS_TZAESB_IMR_URAD_IMR(x)      (((x) << 8U) & GENMASK(8U, 8U))
#define TZAESBS_TZAESB_IMR_URAD_IMR_M       GENMASK(8U, 8U)
#define TZAESBS_TZAESB_IMR_URAD_IMR_X(x)    (((x) & GENMASK(8U, 8U)) >> 8U)

/*      TZAESBS:TZAESB_REGS:TZAESB_ISR */
#define TZAESBS_TZAESB_ISR(t)     ((t) + 0x1cU)

#define TZAESBS_TZAESB_ISR_SECE_ISR(x)      (((x) << 19U) & GENMASK(19U, 19U))
#define TZAESBS_TZAESB_ISR_SECE_ISR_M       GENMASK(19U, 19U)
#define TZAESBS_TZAESB_ISR_SECE_ISR_X(x)    (((x) & GENMASK(19U, 19U)) >> 19U)

#define TZAESBS_TZAESB_ISR_URAT_ISR(x)      (((x) << 12U) & GENMASK(15U, 12U))
#define TZAESBS_TZAESB_ISR_URAT_ISR_M       GENMASK(15U, 12U)
#define TZAESBS_TZAESB_ISR_URAT_ISR_X(x)    (((x) & GENMASK(15U, 12U)) >> 12U)

#define TZAESBS_TZAESB_ISR_URAD_ISR(x)      (((x) << 8U) & GENMASK(8U, 8U))
#define TZAESBS_TZAESB_ISR_URAD_ISR_M       GENMASK(8U, 8U)
#define TZAESBS_TZAESB_ISR_URAD_ISR_X(x)    (((x) & GENMASK(8U, 8U)) >> 8U)

/*      TZAESBS:TZAESB_REGS:TZAESB_KEYWR0 */
#define TZAESBS_TZAESB_KEYWR0(t)  ((t) + 0x20U)

/*      TZAESBS:TZAESB_REGS:TZAESB_KEYWR1 */
#define TZAESBS_TZAESB_KEYWR1(t)  ((t) + 0x24U)

/*      TZAESBS:TZAESB_REGS:TZAESB_KEYWR2 */
#define TZAESBS_TZAESB_KEYWR2(t)  ((t) + 0x28U)

/*      TZAESBS:TZAESB_REGS:TZAESB_KEYWR3 */
#define TZAESBS_TZAESB_KEYWR3(t)  ((t) + 0x2cU)

/*      TZAESBS:TZAESB_REGS:TZAESB_IVR0 */
#define TZAESBS_TZAESB_IVR0(t)    ((t) + 0x60U)

/*      TZAESBS:TZAESB_REGS:TZAESB_IVR1 */
#define TZAESBS_TZAESB_IVR1(t)    ((t) + 0x64U)

/*      TZAESBS:TZAESB_REGS:TZAESB_IVR2 */
#define TZAESBS_TZAESB_IVR2(t)    ((t) + 0x68U)

/*      TZAESBS:TZAESB_REGS:TZAESB_IVR3 */
#define TZAESBS_TZAESB_IVR3(t)    ((t) + 0x6cU)

/*      TZAESBS:TZAESB_REGS:TZAESB_EMR */
#define TZAESBS_TZAESB_EMR(t)     ((t) + 0xb0U)

#define TZAESBS_TZAESB_EMR_PKRS(x)          (((x) << 7U) & GENMASK(7U, 7U))
#define TZAESBS_TZAESB_EMR_PKRS_M           GENMASK(7U, 7U)
#define TZAESBS_TZAESB_EMR_PKRS_X(x)        (((x) & GENMASK(7U, 7U)) >> 7U)

#define TZAESBS_TZAESB_EMR_PKWO(x)          (((x) << 6U) & GENMASK(6U, 6U))
#define TZAESBS_TZAESB_EMR_PKWO_M           GENMASK(6U, 6U)
#define TZAESBS_TZAESB_EMR_PKWO_X(x)        (((x) & GENMASK(6U, 6U)) >> 6U)

/*      TZAESBS:TZAESB_REGS:TZAESB_WPMR */
#define TZAESBS_TZAESB_WPMR(t)    ((t) + 0xe4U)

#define TZAESBS_TZAESB_WPMR_WPKEY(x)        (((x) << 8U) & GENMASK(31U, 8U))
#define TZAESBS_TZAESB_WPMR_WPKEY_M         GENMASK(31U, 8U)
#define TZAESBS_TZAESB_WPMR_WPKEY_X(x)      (((x) & GENMASK(31U, 8U)) >> 8U)

#define TZAESBS_TZAESB_WPMR_ACTION(x)       (((x) << 5U) & GENMASK(7U, 5U))
#define TZAESBS_TZAESB_WPMR_ACTION_M        GENMASK(7U, 5U)
#define TZAESBS_TZAESB_WPMR_ACTION_X(x)     (((x) & GENMASK(7U, 5U)) >> 5U)

#define TZAESBS_TZAESB_WPMR_FIRSTE(x)       (((x) << 4U) & GENMASK(4U, 4U))
#define TZAESBS_TZAESB_WPMR_FIRSTE_M        GENMASK(4U, 4U)
#define TZAESBS_TZAESB_WPMR_FIRSTE_X(x)     (((x) & GENMASK(4U, 4U)) >> 4U)

#define TZAESBS_TZAESB_WPMR_WPCREN(x)       (((x) << 2U) & GENMASK(2U, 2U))
#define TZAESBS_TZAESB_WPMR_WPCREN_M        GENMASK(2U, 2U)
#define TZAESBS_TZAESB_WPMR_WPCREN_X(x)     (((x) & GENMASK(2U, 2U)) >> 2U)

#define TZAESBS_TZAESB_WPMR_WPITEN(x)       (((x) << 1U) & GENMASK(1U, 1U))
#define TZAESBS_TZAESB_WPMR_WPITEN_M        GENMASK(1U, 1U)
#define TZAESBS_TZAESB_WPMR_WPITEN_X(x)     (((x) & GENMASK(1U, 1U)) >> 1U)

#define TZAESBS_TZAESB_WPMR_WPEN(x)         ((x) & GENMASK(0U, 0U))
#define TZAESBS_TZAESB_WPMR_WPEN_M          GENMASK(0U, 0U)
#define TZAESBS_TZAESB_WPMR_WPEN_X(x)       ((x) & GENMASK(0U, 0U))

/*      TZAESBS:TZAESB_REGS:TZAESB_WPSR */
#define TZAESBS_TZAESB_WPSR(t)    ((t) + 0xe8U)

#define TZAESBS_TZAESB_WPSR_ECLASS(x)       (((x) << 31U) & GENMASK(31U, 31U))
#define TZAESBS_TZAESB_WPSR_ECLASS_M        GENMASK(31U, 31U)
#define TZAESBS_TZAESB_WPSR_ECLASS_X(x)     (((x) & GENMASK(31U, 31U)) >> 31U)

#define TZAESBS_TZAESB_WPSR_SWETYP(x)       (((x) << 24U) & GENMASK(27U, 24U))
#define TZAESBS_TZAESB_WPSR_SWETYP_M        GENMASK(27U, 24U)
#define TZAESBS_TZAESB_WPSR_SWETYP_X(x)     (((x) & GENMASK(27U, 24U)) >> 24U)

#define TZAESBS_TZAESB_WPSR_WPVSRC(x)       (((x) << 8U) & GENMASK(15U, 8U))
#define TZAESBS_TZAESB_WPSR_WPVSRC_M        GENMASK(15U, 8U)
#define TZAESBS_TZAESB_WPSR_WPVSRC_X(x)     (((x) & GENMASK(15U, 8U)) >> 8U)

#define TZAESBS_TZAESB_WPSR_PKRPVS(x)       (((x) << 4U) & GENMASK(4U, 4U))
#define TZAESBS_TZAESB_WPSR_PKRPVS_M        GENMASK(4U, 4U)
#define TZAESBS_TZAESB_WPSR_PKRPVS_X(x)     (((x) & GENMASK(4U, 4U)) >> 4U)

#define TZAESBS_TZAESB_WPSR_SWE(x)          (((x) << 3U) & GENMASK(3U, 3U))
#define TZAESBS_TZAESB_WPSR_SWE_M           GENMASK(3U, 3U)
#define TZAESBS_TZAESB_WPSR_SWE_X(x)        (((x) & GENMASK(3U, 3U)) >> 3U)

#define TZAESBS_TZAESB_WPSR_SEQE(x)         (((x) << 2U) & GENMASK(2U, 2U))
#define TZAESBS_TZAESB_WPSR_SEQE_M          GENMASK(2U, 2U)
#define TZAESBS_TZAESB_WPSR_SEQE_X(x)       (((x) & GENMASK(2U, 2U)) >> 2U)

#define TZAESBS_TZAESB_WPSR_CGD(x)          (((x) << 1U) & GENMASK(1U, 1U))
#define TZAESBS_TZAESB_WPSR_CGD_M           GENMASK(1U, 1U)
#define TZAESBS_TZAESB_WPSR_CGD_X(x)        (((x) & GENMASK(1U, 1U)) >> 1U)

#define TZAESBS_TZAESB_WPSR_WPVS(x)         ((x) & GENMASK(0U, 0U))
#define TZAESBS_TZAESB_WPSR_WPVS_M          GENMASK(0U, 0U)
#define TZAESBS_TZAESB_WPSR_WPVS_X(x)       ((x) & GENMASK(0U, 0U))

/*      TZAESBS:TZAESB_REGS:TZAESB_VERSION */
#define TZAESBS_TZAESB_VERSION(t) ((t) + 0xfcU)

#define TZAESBS_TZAESB_VERSION_MFN(x)       (((x) << 16U) & GENMASK(18U, 16U))
#define TZAESBS_TZAESB_VERSION_MFN_M        GENMASK(18U, 16U)
#define TZAESBS_TZAESB_VERSION_MFN_X(x)     (((x) & GENMASK(18U, 16U)) >> 16U)

#define TZAESBS_TZAESB_VERSION_VERSION(x)   ((x) & GENMASK(11U, 0U))
#define TZAESBS_TZAESB_VERSION_VERSION_M    GENMASK(11U, 0U)
#define TZAESBS_TZAESB_VERSION_VERSION_X(x) ((x) & GENMASK(11U, 0U))

/*      TZC_CSS:APB:BUILD_CONFIG */
#define TZC_CSS_BUILD_CONFIG(t)   ((t) + 0x00U)

#define TZC_CSS_BUILD_CONFIG_NO_OF_REGIONS(x) ((x) & GENMASK(4U, 0U))
#define TZC_CSS_BUILD_CONFIG_NO_OF_REGIONS_M GENMASK(4U, 0U)
#define TZC_CSS_BUILD_CONFIG_NO_OF_REGIONS_X(x) ((x) & GENMASK(4U, 0U))

#define TZC_CSS_BUILD_CONFIG_ADDRESS_WIDTH(x) (((x) << 8U) & GENMASK(13U, 8U))
#define TZC_CSS_BUILD_CONFIG_ADDRESS_WIDTH_M GENMASK(13U, 8U)
#define TZC_CSS_BUILD_CONFIG_ADDRESS_WIDTH_X(x) (((x) & GENMASK(13U, 8U)) >> 8U)

#define TZC_CSS_BUILD_CONFIG_NO_OF_FILTERS(x) (((x) << 24U) & GENMASK(25U, 24U))
#define TZC_CSS_BUILD_CONFIG_NO_OF_FILTERS_M GENMASK(25U, 24U)
#define TZC_CSS_BUILD_CONFIG_NO_OF_FILTERS_X(x)\
	(((x) & GENMASK(25U, 24U)) >> 24U)

/*      TZC_CSS:APB:ACTION */
#define TZC_CSS_ACTION(t)         ((t) + 0x04U)

#define TZC_CSS_ACTION_REACTION_VALUE(x)    ((x) & GENMASK(1U, 0U))
#define TZC_CSS_ACTION_REACTION_VALUE_M     GENMASK(1U, 0U)
#define TZC_CSS_ACTION_REACTION_VALUE_X(x)  ((x) & GENMASK(1U, 0U))

/*      TZC_CSS:APB:GATE_KEEPER */
#define TZC_CSS_GATE_KEEPER(t)    ((t) + 0x08U)

#define TZC_CSS_GATE_KEEPER_OPEN_REQUEST(x) ((x) & GENMASK(0U, 0U))
#define TZC_CSS_GATE_KEEPER_OPEN_REQUEST_M  GENMASK(0U, 0U)
#define TZC_CSS_GATE_KEEPER_OPEN_REQUEST_X(x) ((x) & GENMASK(0U, 0U))

#define TZC_CSS_GATE_KEEPER_OPEN_STATUS(x)  (((x) << 16U) & GENMASK(16U, 16U))
#define TZC_CSS_GATE_KEEPER_OPEN_STATUS_M   GENMASK(16U, 16U)
#define TZC_CSS_GATE_KEEPER_OPEN_STATUS_X(x) (((x) & GENMASK(16U, 16U)) >> 16U)

/*      TZC_CSS:APB:SPECULATION_CTRL */
#define TZC_CSS_SPECULATION_CTRL(t) ((t) + 0x0cU)

#define TZC_CSS_SPECULATION_CTRL_READ_SPEC_DISABLE(x) ((x) & GENMASK(0U, 0U))
#define TZC_CSS_SPECULATION_CTRL_READ_SPEC_DISABLE_M GENMASK(0U, 0U)
#define TZC_CSS_SPECULATION_CTRL_READ_SPEC_DISABLE_X(x) ((x) & GENMASK(0U, 0U))

#define TZC_CSS_SPECULATION_CTRL_WRITE_SPEC_DISABLE(x)\
	(((x) << 1U) & GENMASK(1U, 1U))
#define TZC_CSS_SPECULATION_CTRL_WRITE_SPEC_DISABLE_M GENMASK(1U, 1U)
#define TZC_CSS_SPECULATION_CTRL_WRITE_SPEC_DISABLE_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

/*      TZC_CSS:APB:INT_STATUS */
#define TZC_CSS_INT_STATUS(t)     ((t) + 0x10U)

#define TZC_CSS_INT_STATUS_STATUS(x)        ((x) & GENMASK(0U, 0U))
#define TZC_CSS_INT_STATUS_STATUS_M         GENMASK(0U, 0U)
#define TZC_CSS_INT_STATUS_STATUS_X(x)      ((x) & GENMASK(0U, 0U))

#define TZC_CSS_INT_STATUS_OVERRUN(x)       (((x) << 8U) & GENMASK(8U, 8U))
#define TZC_CSS_INT_STATUS_OVERRUN_M        GENMASK(8U, 8U)
#define TZC_CSS_INT_STATUS_OVERRUN_X(x)     (((x) & GENMASK(8U, 8U)) >> 8U)

#define TZC_CSS_INT_STATUS_OVERLAP(x)       (((x) << 16U) & GENMASK(16U, 16U))
#define TZC_CSS_INT_STATUS_OVERLAP_M        GENMASK(16U, 16U)
#define TZC_CSS_INT_STATUS_OVERLAP_X(x)     (((x) & GENMASK(16U, 16U)) >> 16U)

/*      TZC_CSS:APB:INT_CLEAR */
#define TZC_CSS_INT_CLEAR(t)      ((t) + 0x14U)

#define TZC_CSS_INT_CLEAR_CLEAR(x)          ((x) & GENMASK(0U, 0U))
#define TZC_CSS_INT_CLEAR_CLEAR_M           GENMASK(0U, 0U)
#define TZC_CSS_INT_CLEAR_CLEAR_X(x)        ((x) & GENMASK(0U, 0U))

/*      TZC_CSS:APB:FAIL_ADDRESS_LOW_0 */
#define TZC_CSS_FAIL_ADDRESS_LOW_0(t) ((t) + 0x20U)

/*      TZC_CSS:APB:FAIL_ADDRESS_HIGH_0 */
#define TZC_CSS_FAIL_ADDRESS_HIGH_0(t) ((t) + 0x24U)

/*      TZC_CSS:APB:FAIL_CONTROL_0 */
#define TZC_CSS_FAIL_CONTROL_0(t) ((t) + 0x28U)

#define TZC_CSS_FAIL_CONTROL_0_PRIVILEGED(x) (((x) << 20U) & GENMASK(20U, 20U))
#define TZC_CSS_FAIL_CONTROL_0_PRIVILEGED_M GENMASK(20U, 20U)
#define TZC_CSS_FAIL_CONTROL_0_PRIVILEGED_X(x)\
	(((x) & GENMASK(20U, 20U)) >> 20U)

#define TZC_CSS_FAIL_CONTROL_0_NONSECURE(x) (((x) << 21U) & GENMASK(21U, 21U))
#define TZC_CSS_FAIL_CONTROL_0_NONSECURE_M  GENMASK(21U, 21U)
#define TZC_CSS_FAIL_CONTROL_0_NONSECURE_X(x) (((x) & GENMASK(21U, 21U)) >> 21U)

#define TZC_CSS_FAIL_CONTROL_0_DIRECTION(x) (((x) << 24U) & GENMASK(24U, 24U))
#define TZC_CSS_FAIL_CONTROL_0_DIRECTION_M  GENMASK(24U, 24U)
#define TZC_CSS_FAIL_CONTROL_0_DIRECTION_X(x) (((x) & GENMASK(24U, 24U)) >> 24U)

/*      TZC_CSS:APB:FAIL_ID_0 */
#define TZC_CSS_FAIL_ID_0(t)      ((t) + 0x2cU)

#define TZC_CSS_FAIL_ID_0_ID(x)             ((x) & GENMASK(8U, 0U))
#define TZC_CSS_FAIL_ID_0_ID_M              GENMASK(8U, 0U)
#define TZC_CSS_FAIL_ID_0_ID_X(x)           ((x) & GENMASK(8U, 0U))

#define TZC_CSS_FAIL_ID_0_VNET(x)           (((x) << 24U) & GENMASK(27U, 24U))
#define TZC_CSS_FAIL_ID_0_VNET_M            GENMASK(27U, 24U)
#define TZC_CSS_FAIL_ID_0_VNET_X(x)         (((x) & GENMASK(27U, 24U)) >> 24U)

/*      TZC_CSS:APB:REGION_BASE_LOW_0 */
#define TZC_CSS_REGION_BASE_LOW_0(t) ((t) + 0x100U)

#define TZC_CSS_REGION_BASE_LOW_0_BASE_ADDRESS_LOW_0(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_CSS_REGION_BASE_LOW_0_BASE_ADDRESS_LOW_0_M GENMASK(31U, 12U)
#define TZC_CSS_REGION_BASE_LOW_0_BASE_ADDRESS_LOW_0_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_CSS:APB:REGION_BASE_HIGH_0 */
#define TZC_CSS_REGION_BASE_HIGH_0(t) ((t) + 0x104U)

/*      TZC_CSS:APB:REGION_TOP_LOW_0 */
#define TZC_CSS_REGION_TOP_LOW_0(t) ((t) + 0x108U)

#define TZC_CSS_REGION_TOP_LOW_0_TOP_ADDRESS_LOW_0(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_CSS_REGION_TOP_LOW_0_TOP_ADDRESS_LOW_0_M GENMASK(31U, 12U)
#define TZC_CSS_REGION_TOP_LOW_0_TOP_ADDRESS_LOW_0_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_CSS:APB:REGION_TOP_HIGH_0 */
#define TZC_CSS_REGION_TOP_HIGH_0(t) ((t) + 0x10cU)

/*      TZC_CSS:APB:REGION_ATTRIBUTES_0 */
#define TZC_CSS_REGION_ATTRIBUTES_0(t) ((t) + 0x110U)

#define TZC_CSS_REGION_ATTRIBUTES_0_REGION_ATTRIBUTES_0_FILTER_EN(x)\
	((x) & GENMASK(0U, 0U))
#define TZC_CSS_REGION_ATTRIBUTES_0_REGION_ATTRIBUTES_0_FILTER_EN_M\
	GENMASK(0U, 0U)
#define TZC_CSS_REGION_ATTRIBUTES_0_REGION_ATTRIBUTES_0_FILTER_EN_X(x)\
	((x) & GENMASK(0U, 0U))

#define TZC_CSS_REGION_ATTRIBUTES_0_REGION_ATTRIBUTES_0_S_RD_EN(x)\
	(((x) << 30U) & GENMASK(30U, 30U))
#define TZC_CSS_REGION_ATTRIBUTES_0_REGION_ATTRIBUTES_0_S_RD_EN_M\
	GENMASK(30U, 30U)
#define TZC_CSS_REGION_ATTRIBUTES_0_REGION_ATTRIBUTES_0_S_RD_EN_X(x)\
	(((x) & GENMASK(30U, 30U)) >> 30U)

#define TZC_CSS_REGION_ATTRIBUTES_0_REGION_ATTRIBUTES_0_S_WR_EN(x)\
	(((x) << 31U) & GENMASK(31U, 31U))
#define TZC_CSS_REGION_ATTRIBUTES_0_REGION_ATTRIBUTES_0_S_WR_EN_M\
	GENMASK(31U, 31U)
#define TZC_CSS_REGION_ATTRIBUTES_0_REGION_ATTRIBUTES_0_S_WR_EN_X(x)\
	(((x) & GENMASK(31U, 31U)) >> 31U)

/*      TZC_CSS:APB:REGION_ID_ACCESS_0 */
#define TZC_CSS_REGION_ID_ACCESS_0(t) ((t) + 0x114U)

#define TZC_CSS_REGION_ID_ACCESS_0_REGION_ID_ACCESS_0_NSAID_RD_EN(x)\
	((x) & GENMASK(15U, 0U))
#define TZC_CSS_REGION_ID_ACCESS_0_REGION_ID_ACCESS_0_NSAID_RD_EN_M\
	GENMASK(15U, 0U)
#define TZC_CSS_REGION_ID_ACCESS_0_REGION_ID_ACCESS_0_NSAID_RD_EN_X(x)\
	((x) & GENMASK(15U, 0U))

#define TZC_CSS_REGION_ID_ACCESS_0_REGION_ID_ACCESS_0_NSAID_WR_EN(x)\
	(((x) << 16U) & GENMASK(31U, 16U))
#define TZC_CSS_REGION_ID_ACCESS_0_REGION_ID_ACCESS_0_NSAID_WR_EN_M\
	GENMASK(31U, 16U)
#define TZC_CSS_REGION_ID_ACCESS_0_REGION_ID_ACCESS_0_NSAID_WR_EN_X(x)\
	(((x) & GENMASK(31U, 16U)) >> 16U)

/*      TZC_CSS:APB:REGION_BASE_LOW_1 */
#define TZC_CSS_REGION_BASE_LOW_1(t) ((t) + 0x120U)

#define TZC_CSS_REGION_BASE_LOW_1_BASE_ADDRESS_LOW_1(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_CSS_REGION_BASE_LOW_1_BASE_ADDRESS_LOW_1_M GENMASK(31U, 12U)
#define TZC_CSS_REGION_BASE_LOW_1_BASE_ADDRESS_LOW_1_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_CSS:APB:REGION_BASE_HIGH_1 */
#define TZC_CSS_REGION_BASE_HIGH_1(t) ((t) + 0x124U)

/*      TZC_CSS:APB:REGION_TOP_LOW_1 */
#define TZC_CSS_REGION_TOP_LOW_1(t) ((t) + 0x128U)

#define TZC_CSS_REGION_TOP_LOW_1_TOP_ADDRESS_LOW_1(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_CSS_REGION_TOP_LOW_1_TOP_ADDRESS_LOW_1_M GENMASK(31U, 12U)
#define TZC_CSS_REGION_TOP_LOW_1_TOP_ADDRESS_LOW_1_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_CSS:APB:REGION_TOP_HIGH_1 */
#define TZC_CSS_REGION_TOP_HIGH_1(t) ((t) + 0x12cU)

/*      TZC_CSS:APB:REGION_ATTRIBUTES_1 */
#define TZC_CSS_REGION_ATTRIBUTES_1(t) ((t) + 0x130U)

#define TZC_CSS_REGION_ATTRIBUTES_1_REGION_ATTRIBUTES_1_FILTER_EN(x)\
	((x) & GENMASK(0U, 0U))
#define TZC_CSS_REGION_ATTRIBUTES_1_REGION_ATTRIBUTES_1_FILTER_EN_M\
	GENMASK(0U, 0U)
#define TZC_CSS_REGION_ATTRIBUTES_1_REGION_ATTRIBUTES_1_FILTER_EN_X(x)\
	((x) & GENMASK(0U, 0U))

#define TZC_CSS_REGION_ATTRIBUTES_1_REGION_ATTRIBUTES_1_S_RD_EN(x)\
	(((x) << 30U) & GENMASK(30U, 30U))
#define TZC_CSS_REGION_ATTRIBUTES_1_REGION_ATTRIBUTES_1_S_RD_EN_M\
	GENMASK(30U, 30U)
#define TZC_CSS_REGION_ATTRIBUTES_1_REGION_ATTRIBUTES_1_S_RD_EN_X(x)\
	(((x) & GENMASK(30U, 30U)) >> 30U)

#define TZC_CSS_REGION_ATTRIBUTES_1_REGION_ATTRIBUTES_1_S_WR_EN(x)\
	(((x) << 31U) & GENMASK(31U, 31U))
#define TZC_CSS_REGION_ATTRIBUTES_1_REGION_ATTRIBUTES_1_S_WR_EN_M\
	GENMASK(31U, 31U)
#define TZC_CSS_REGION_ATTRIBUTES_1_REGION_ATTRIBUTES_1_S_WR_EN_X(x)\
	(((x) & GENMASK(31U, 31U)) >> 31U)

/*      TZC_CSS:APB:REGION_ID_ACCESS_1 */
#define TZC_CSS_REGION_ID_ACCESS_1(t) ((t) + 0x134U)

#define TZC_CSS_REGION_ID_ACCESS_1_REGION_ID_ACCESS_1_NSAID_RD_EN(x)\
	((x) & GENMASK(15U, 0U))
#define TZC_CSS_REGION_ID_ACCESS_1_REGION_ID_ACCESS_1_NSAID_RD_EN_M\
	GENMASK(15U, 0U)
#define TZC_CSS_REGION_ID_ACCESS_1_REGION_ID_ACCESS_1_NSAID_RD_EN_X(x)\
	((x) & GENMASK(15U, 0U))

#define TZC_CSS_REGION_ID_ACCESS_1_REGION_ID_ACCESS_1_NSAID_WR_EN(x)\
	(((x) << 16U) & GENMASK(31U, 16U))
#define TZC_CSS_REGION_ID_ACCESS_1_REGION_ID_ACCESS_1_NSAID_WR_EN_M\
	GENMASK(31U, 16U)
#define TZC_CSS_REGION_ID_ACCESS_1_REGION_ID_ACCESS_1_NSAID_WR_EN_X(x)\
	(((x) & GENMASK(31U, 16U)) >> 16U)

/*      TZC_CSS:APB:REGION_BASE_LOW_2 */
#define TZC_CSS_REGION_BASE_LOW_2(t) ((t) + 0x140U)

#define TZC_CSS_REGION_BASE_LOW_2_BASE_ADDRESS_LOW_2(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_CSS_REGION_BASE_LOW_2_BASE_ADDRESS_LOW_2_M GENMASK(31U, 12U)
#define TZC_CSS_REGION_BASE_LOW_2_BASE_ADDRESS_LOW_2_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_CSS:APB:REGION_BASE_HIGH_2 */
#define TZC_CSS_REGION_BASE_HIGH_2(t) ((t) + 0x144U)

/*      TZC_CSS:APB:REGION_TOP_LOW_2 */
#define TZC_CSS_REGION_TOP_LOW_2(t) ((t) + 0x148U)

#define TZC_CSS_REGION_TOP_LOW_2_TOP_ADDRESS_LOW_2(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_CSS_REGION_TOP_LOW_2_TOP_ADDRESS_LOW_2_M GENMASK(31U, 12U)
#define TZC_CSS_REGION_TOP_LOW_2_TOP_ADDRESS_LOW_2_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_CSS:APB:REGION_TOP_HIGH_2 */
#define TZC_CSS_REGION_TOP_HIGH_2(t) ((t) + 0x14cU)

/*      TZC_CSS:APB:REGION_ATTRIBUTES_2 */
#define TZC_CSS_REGION_ATTRIBUTES_2(t) ((t) + 0x150U)

#define TZC_CSS_REGION_ATTRIBUTES_2_REGION_ATTRIBUTES_2_FILTER_EN(x)\
	((x) & GENMASK(0U, 0U))
#define TZC_CSS_REGION_ATTRIBUTES_2_REGION_ATTRIBUTES_2_FILTER_EN_M\
	GENMASK(0U, 0U)
#define TZC_CSS_REGION_ATTRIBUTES_2_REGION_ATTRIBUTES_2_FILTER_EN_X(x)\
	((x) & GENMASK(0U, 0U))

#define TZC_CSS_REGION_ATTRIBUTES_2_REGION_ATTRIBUTES_2_S_RD_EN(x)\
	(((x) << 30U) & GENMASK(30U, 30U))
#define TZC_CSS_REGION_ATTRIBUTES_2_REGION_ATTRIBUTES_2_S_RD_EN_M\
	GENMASK(30U, 30U)
#define TZC_CSS_REGION_ATTRIBUTES_2_REGION_ATTRIBUTES_2_S_RD_EN_X(x)\
	(((x) & GENMASK(30U, 30U)) >> 30U)

#define TZC_CSS_REGION_ATTRIBUTES_2_REGION_ATTRIBUTES_2_S_WR_EN(x)\
	(((x) << 31U) & GENMASK(31U, 31U))
#define TZC_CSS_REGION_ATTRIBUTES_2_REGION_ATTRIBUTES_2_S_WR_EN_M\
	GENMASK(31U, 31U)
#define TZC_CSS_REGION_ATTRIBUTES_2_REGION_ATTRIBUTES_2_S_WR_EN_X(x)\
	(((x) & GENMASK(31U, 31U)) >> 31U)

/*      TZC_CSS:APB:REGION_ID_ACCESS_2 */
#define TZC_CSS_REGION_ID_ACCESS_2(t) ((t) + 0x154U)

#define TZC_CSS_REGION_ID_ACCESS_2_REGION_ID_ACCESS_2_NSAID_RD_EN(x)\
	((x) & GENMASK(15U, 0U))
#define TZC_CSS_REGION_ID_ACCESS_2_REGION_ID_ACCESS_2_NSAID_RD_EN_M\
	GENMASK(15U, 0U)
#define TZC_CSS_REGION_ID_ACCESS_2_REGION_ID_ACCESS_2_NSAID_RD_EN_X(x)\
	((x) & GENMASK(15U, 0U))

#define TZC_CSS_REGION_ID_ACCESS_2_REGION_ID_ACCESS_2_NSAID_WR_EN(x)\
	(((x) << 16U) & GENMASK(31U, 16U))
#define TZC_CSS_REGION_ID_ACCESS_2_REGION_ID_ACCESS_2_NSAID_WR_EN_M\
	GENMASK(31U, 16U)
#define TZC_CSS_REGION_ID_ACCESS_2_REGION_ID_ACCESS_2_NSAID_WR_EN_X(x)\
	(((x) & GENMASK(31U, 16U)) >> 16U)

/*      TZC_CSS:APB:REGION_BASE_LOW_3 */
#define TZC_CSS_REGION_BASE_LOW_3(t) ((t) + 0x160U)

#define TZC_CSS_REGION_BASE_LOW_3_BASE_ADDRESS_LOW_3(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_CSS_REGION_BASE_LOW_3_BASE_ADDRESS_LOW_3_M GENMASK(31U, 12U)
#define TZC_CSS_REGION_BASE_LOW_3_BASE_ADDRESS_LOW_3_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_CSS:APB:REGION_BASE_HIGH_3 */
#define TZC_CSS_REGION_BASE_HIGH_3(t) ((t) + 0x164U)

/*      TZC_CSS:APB:REGION_TOP_LOW_3 */
#define TZC_CSS_REGION_TOP_LOW_3(t) ((t) + 0x168U)

#define TZC_CSS_REGION_TOP_LOW_3_TOP_ADDRESS_LOW_3(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_CSS_REGION_TOP_LOW_3_TOP_ADDRESS_LOW_3_M GENMASK(31U, 12U)
#define TZC_CSS_REGION_TOP_LOW_3_TOP_ADDRESS_LOW_3_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_CSS:APB:REGION_TOP_HIGH_3 */
#define TZC_CSS_REGION_TOP_HIGH_3(t) ((t) + 0x16cU)

/*      TZC_CSS:APB:REGION_ATTRIBUTES_3 */
#define TZC_CSS_REGION_ATTRIBUTES_3(t) ((t) + 0x170U)

#define TZC_CSS_REGION_ATTRIBUTES_3_REGION_ATTRIBUTES_3_FILTER_EN(x)\
	((x) & GENMASK(0U, 0U))
#define TZC_CSS_REGION_ATTRIBUTES_3_REGION_ATTRIBUTES_3_FILTER_EN_M\
	GENMASK(0U, 0U)
#define TZC_CSS_REGION_ATTRIBUTES_3_REGION_ATTRIBUTES_3_FILTER_EN_X(x)\
	((x) & GENMASK(0U, 0U))

#define TZC_CSS_REGION_ATTRIBUTES_3_REGION_ATTRIBUTES_3_S_RD_EN(x)\
	(((x) << 30U) & GENMASK(30U, 30U))
#define TZC_CSS_REGION_ATTRIBUTES_3_REGION_ATTRIBUTES_3_S_RD_EN_M\
	GENMASK(30U, 30U)
#define TZC_CSS_REGION_ATTRIBUTES_3_REGION_ATTRIBUTES_3_S_RD_EN_X(x)\
	(((x) & GENMASK(30U, 30U)) >> 30U)

#define TZC_CSS_REGION_ATTRIBUTES_3_REGION_ATTRIBUTES_3_S_WR_EN(x)\
	(((x) << 31U) & GENMASK(31U, 31U))
#define TZC_CSS_REGION_ATTRIBUTES_3_REGION_ATTRIBUTES_3_S_WR_EN_M\
	GENMASK(31U, 31U)
#define TZC_CSS_REGION_ATTRIBUTES_3_REGION_ATTRIBUTES_3_S_WR_EN_X(x)\
	(((x) & GENMASK(31U, 31U)) >> 31U)

/*      TZC_CSS:APB:REGION_ID_ACCESS_3 */
#define TZC_CSS_REGION_ID_ACCESS_3(t) ((t) + 0x174U)

#define TZC_CSS_REGION_ID_ACCESS_3_REGION_ID_ACCESS_3_NSAID_RD_EN(x)\
	((x) & GENMASK(15U, 0U))
#define TZC_CSS_REGION_ID_ACCESS_3_REGION_ID_ACCESS_3_NSAID_RD_EN_M\
	GENMASK(15U, 0U)
#define TZC_CSS_REGION_ID_ACCESS_3_REGION_ID_ACCESS_3_NSAID_RD_EN_X(x)\
	((x) & GENMASK(15U, 0U))

#define TZC_CSS_REGION_ID_ACCESS_3_REGION_ID_ACCESS_3_NSAID_WR_EN(x)\
	(((x) << 16U) & GENMASK(31U, 16U))
#define TZC_CSS_REGION_ID_ACCESS_3_REGION_ID_ACCESS_3_NSAID_WR_EN_M\
	GENMASK(31U, 16U)
#define TZC_CSS_REGION_ID_ACCESS_3_REGION_ID_ACCESS_3_NSAID_WR_EN_X(x)\
	(((x) & GENMASK(31U, 16U)) >> 16U)

/*      TZC_CSS:APB:REGION_BASE_LOW_4 */
#define TZC_CSS_REGION_BASE_LOW_4(t) ((t) + 0x180U)

#define TZC_CSS_REGION_BASE_LOW_4_BASE_ADDRESS_LOW_4(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_CSS_REGION_BASE_LOW_4_BASE_ADDRESS_LOW_4_M GENMASK(31U, 12U)
#define TZC_CSS_REGION_BASE_LOW_4_BASE_ADDRESS_LOW_4_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_CSS:APB:REGION_BASE_HIGH_4 */
#define TZC_CSS_REGION_BASE_HIGH_4(t) ((t) + 0x184U)

/*      TZC_CSS:APB:REGION_TOP_LOW_4 */
#define TZC_CSS_REGION_TOP_LOW_4(t) ((t) + 0x188U)

#define TZC_CSS_REGION_TOP_LOW_4_TOP_ADDRESS_LOW_4(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_CSS_REGION_TOP_LOW_4_TOP_ADDRESS_LOW_4_M GENMASK(31U, 12U)
#define TZC_CSS_REGION_TOP_LOW_4_TOP_ADDRESS_LOW_4_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_CSS:APB:REGION_TOP_HIGH_4 */
#define TZC_CSS_REGION_TOP_HIGH_4(t) ((t) + 0x18cU)

/*      TZC_CSS:APB:REGION_ATTRIBUTES_4 */
#define TZC_CSS_REGION_ATTRIBUTES_4(t) ((t) + 0x190U)

#define TZC_CSS_REGION_ATTRIBUTES_4_REGION_ATTRIBUTES_4_FILTER_EN(x)\
	((x) & GENMASK(0U, 0U))
#define TZC_CSS_REGION_ATTRIBUTES_4_REGION_ATTRIBUTES_4_FILTER_EN_M\
	GENMASK(0U, 0U)
#define TZC_CSS_REGION_ATTRIBUTES_4_REGION_ATTRIBUTES_4_FILTER_EN_X(x)\
	((x) & GENMASK(0U, 0U))

#define TZC_CSS_REGION_ATTRIBUTES_4_REGION_ATTRIBUTES_4_S_RD_EN(x)\
	(((x) << 30U) & GENMASK(30U, 30U))
#define TZC_CSS_REGION_ATTRIBUTES_4_REGION_ATTRIBUTES_4_S_RD_EN_M\
	GENMASK(30U, 30U)
#define TZC_CSS_REGION_ATTRIBUTES_4_REGION_ATTRIBUTES_4_S_RD_EN_X(x)\
	(((x) & GENMASK(30U, 30U)) >> 30U)

#define TZC_CSS_REGION_ATTRIBUTES_4_REGION_ATTRIBUTES_4_S_WR_EN(x)\
	(((x) << 31U) & GENMASK(31U, 31U))
#define TZC_CSS_REGION_ATTRIBUTES_4_REGION_ATTRIBUTES_4_S_WR_EN_M\
	GENMASK(31U, 31U)
#define TZC_CSS_REGION_ATTRIBUTES_4_REGION_ATTRIBUTES_4_S_WR_EN_X(x)\
	(((x) & GENMASK(31U, 31U)) >> 31U)

/*      TZC_CSS:APB:REGION_ID_ACCESS_4 */
#define TZC_CSS_REGION_ID_ACCESS_4(t) ((t) + 0x194U)

#define TZC_CSS_REGION_ID_ACCESS_4_REGION_ID_ACCESS_4_NSAID_RD_EN(x)\
	((x) & GENMASK(15U, 0U))
#define TZC_CSS_REGION_ID_ACCESS_4_REGION_ID_ACCESS_4_NSAID_RD_EN_M\
	GENMASK(15U, 0U)
#define TZC_CSS_REGION_ID_ACCESS_4_REGION_ID_ACCESS_4_NSAID_RD_EN_X(x)\
	((x) & GENMASK(15U, 0U))

#define TZC_CSS_REGION_ID_ACCESS_4_REGION_ID_ACCESS_4_NSAID_WR_EN(x)\
	(((x) << 16U) & GENMASK(31U, 16U))
#define TZC_CSS_REGION_ID_ACCESS_4_REGION_ID_ACCESS_4_NSAID_WR_EN_M\
	GENMASK(31U, 16U)
#define TZC_CSS_REGION_ID_ACCESS_4_REGION_ID_ACCESS_4_NSAID_WR_EN_X(x)\
	(((x) & GENMASK(31U, 16U)) >> 16U)

/*      TZC_CSS:APB:REGION_BASE_LOW_5 */
#define TZC_CSS_REGION_BASE_LOW_5(t) ((t) + 0x1a0U)

#define TZC_CSS_REGION_BASE_LOW_5_BASE_ADDRESS_LOW_5(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_CSS_REGION_BASE_LOW_5_BASE_ADDRESS_LOW_5_M GENMASK(31U, 12U)
#define TZC_CSS_REGION_BASE_LOW_5_BASE_ADDRESS_LOW_5_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_CSS:APB:REGION_BASE_HIGH_5 */
#define TZC_CSS_REGION_BASE_HIGH_5(t) ((t) + 0x1a4U)

/*      TZC_CSS:APB:REGION_TOP_LOW_5 */
#define TZC_CSS_REGION_TOP_LOW_5(t) ((t) + 0x1a8U)

#define TZC_CSS_REGION_TOP_LOW_5_TOP_ADDRESS_LOW_5(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_CSS_REGION_TOP_LOW_5_TOP_ADDRESS_LOW_5_M GENMASK(31U, 12U)
#define TZC_CSS_REGION_TOP_LOW_5_TOP_ADDRESS_LOW_5_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_CSS:APB:REGION_TOP_HIGH_5 */
#define TZC_CSS_REGION_TOP_HIGH_5(t) ((t) + 0x1acU)

/*      TZC_CSS:APB:REGION_ATTRIBUTES_5 */
#define TZC_CSS_REGION_ATTRIBUTES_5(t) ((t) + 0x1b0U)

#define TZC_CSS_REGION_ATTRIBUTES_5_REGION_ATTRIBUTES_5_FILTER_EN(x)\
	((x) & GENMASK(0U, 0U))
#define TZC_CSS_REGION_ATTRIBUTES_5_REGION_ATTRIBUTES_5_FILTER_EN_M\
	GENMASK(0U, 0U)
#define TZC_CSS_REGION_ATTRIBUTES_5_REGION_ATTRIBUTES_5_FILTER_EN_X(x)\
	((x) & GENMASK(0U, 0U))

#define TZC_CSS_REGION_ATTRIBUTES_5_REGION_ATTRIBUTES_5_S_RD_EN(x)\
	(((x) << 30U) & GENMASK(30U, 30U))
#define TZC_CSS_REGION_ATTRIBUTES_5_REGION_ATTRIBUTES_5_S_RD_EN_M\
	GENMASK(30U, 30U)
#define TZC_CSS_REGION_ATTRIBUTES_5_REGION_ATTRIBUTES_5_S_RD_EN_X(x)\
	(((x) & GENMASK(30U, 30U)) >> 30U)

#define TZC_CSS_REGION_ATTRIBUTES_5_REGION_ATTRIBUTES_5_S_WR_EN(x)\
	(((x) << 31U) & GENMASK(31U, 31U))
#define TZC_CSS_REGION_ATTRIBUTES_5_REGION_ATTRIBUTES_5_S_WR_EN_M\
	GENMASK(31U, 31U)
#define TZC_CSS_REGION_ATTRIBUTES_5_REGION_ATTRIBUTES_5_S_WR_EN_X(x)\
	(((x) & GENMASK(31U, 31U)) >> 31U)

/*      TZC_CSS:APB:REGION_ID_ACCESS_5 */
#define TZC_CSS_REGION_ID_ACCESS_5(t) ((t) + 0x1b4U)

#define TZC_CSS_REGION_ID_ACCESS_5_REGION_ID_ACCESS_5_NSAID_RD_EN(x)\
	((x) & GENMASK(15U, 0U))
#define TZC_CSS_REGION_ID_ACCESS_5_REGION_ID_ACCESS_5_NSAID_RD_EN_M\
	GENMASK(15U, 0U)
#define TZC_CSS_REGION_ID_ACCESS_5_REGION_ID_ACCESS_5_NSAID_RD_EN_X(x)\
	((x) & GENMASK(15U, 0U))

#define TZC_CSS_REGION_ID_ACCESS_5_REGION_ID_ACCESS_5_NSAID_WR_EN(x)\
	(((x) << 16U) & GENMASK(31U, 16U))
#define TZC_CSS_REGION_ID_ACCESS_5_REGION_ID_ACCESS_5_NSAID_WR_EN_M\
	GENMASK(31U, 16U)
#define TZC_CSS_REGION_ID_ACCESS_5_REGION_ID_ACCESS_5_NSAID_WR_EN_X(x)\
	(((x) & GENMASK(31U, 16U)) >> 16U)

/*      TZC_CSS:APB:REGION_BASE_LOW_6 */
#define TZC_CSS_REGION_BASE_LOW_6(t) ((t) + 0x1c0U)

#define TZC_CSS_REGION_BASE_LOW_6_BASE_ADDRESS_LOW_6(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_CSS_REGION_BASE_LOW_6_BASE_ADDRESS_LOW_6_M GENMASK(31U, 12U)
#define TZC_CSS_REGION_BASE_LOW_6_BASE_ADDRESS_LOW_6_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_CSS:APB:REGION_BASE_HIGH_6 */
#define TZC_CSS_REGION_BASE_HIGH_6(t) ((t) + 0x1c4U)

/*      TZC_CSS:APB:REGION_TOP_LOW_6 */
#define TZC_CSS_REGION_TOP_LOW_6(t) ((t) + 0x1c8U)

#define TZC_CSS_REGION_TOP_LOW_6_TOP_ADDRESS_LOW_6(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_CSS_REGION_TOP_LOW_6_TOP_ADDRESS_LOW_6_M GENMASK(31U, 12U)
#define TZC_CSS_REGION_TOP_LOW_6_TOP_ADDRESS_LOW_6_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_CSS:APB:REGION_TOP_HIGH_6 */
#define TZC_CSS_REGION_TOP_HIGH_6(t) ((t) + 0x1ccU)

/*      TZC_CSS:APB:REGION_ATTRIBUTES_6 */
#define TZC_CSS_REGION_ATTRIBUTES_6(t) ((t) + 0x1d0U)

#define TZC_CSS_REGION_ATTRIBUTES_6_REGION_ATTRIBUTES_6_FILTER_EN(x)\
	((x) & GENMASK(0U, 0U))
#define TZC_CSS_REGION_ATTRIBUTES_6_REGION_ATTRIBUTES_6_FILTER_EN_M\
	GENMASK(0U, 0U)
#define TZC_CSS_REGION_ATTRIBUTES_6_REGION_ATTRIBUTES_6_FILTER_EN_X(x)\
	((x) & GENMASK(0U, 0U))

#define TZC_CSS_REGION_ATTRIBUTES_6_REGION_ATTRIBUTES_6_S_RD_EN(x)\
	(((x) << 30U) & GENMASK(30U, 30U))
#define TZC_CSS_REGION_ATTRIBUTES_6_REGION_ATTRIBUTES_6_S_RD_EN_M\
	GENMASK(30U, 30U)
#define TZC_CSS_REGION_ATTRIBUTES_6_REGION_ATTRIBUTES_6_S_RD_EN_X(x)\
	(((x) & GENMASK(30U, 30U)) >> 30U)

#define TZC_CSS_REGION_ATTRIBUTES_6_REGION_ATTRIBUTES_6_S_WR_EN(x)\
	(((x) << 31U) & GENMASK(31U, 31U))
#define TZC_CSS_REGION_ATTRIBUTES_6_REGION_ATTRIBUTES_6_S_WR_EN_M\
	GENMASK(31U, 31U)
#define TZC_CSS_REGION_ATTRIBUTES_6_REGION_ATTRIBUTES_6_S_WR_EN_X(x)\
	(((x) & GENMASK(31U, 31U)) >> 31U)

/*      TZC_CSS:APB:REGION_ID_ACCESS_6 */
#define TZC_CSS_REGION_ID_ACCESS_6(t) ((t) + 0x1d4U)

#define TZC_CSS_REGION_ID_ACCESS_6_REGION_ID_ACCESS_6_NSAID_RD_EN(x)\
	((x) & GENMASK(15U, 0U))
#define TZC_CSS_REGION_ID_ACCESS_6_REGION_ID_ACCESS_6_NSAID_RD_EN_M\
	GENMASK(15U, 0U)
#define TZC_CSS_REGION_ID_ACCESS_6_REGION_ID_ACCESS_6_NSAID_RD_EN_X(x)\
	((x) & GENMASK(15U, 0U))

#define TZC_CSS_REGION_ID_ACCESS_6_REGION_ID_ACCESS_6_NSAID_WR_EN(x)\
	(((x) << 16U) & GENMASK(31U, 16U))
#define TZC_CSS_REGION_ID_ACCESS_6_REGION_ID_ACCESS_6_NSAID_WR_EN_M\
	GENMASK(31U, 16U)
#define TZC_CSS_REGION_ID_ACCESS_6_REGION_ID_ACCESS_6_NSAID_WR_EN_X(x)\
	(((x) & GENMASK(31U, 16U)) >> 16U)

/*      TZC_CSS:APB:REGION_BASE_LOW_7 */
#define TZC_CSS_REGION_BASE_LOW_7(t) ((t) + 0x1e0U)

#define TZC_CSS_REGION_BASE_LOW_7_BASE_ADDRESS_LOW_7(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_CSS_REGION_BASE_LOW_7_BASE_ADDRESS_LOW_7_M GENMASK(31U, 12U)
#define TZC_CSS_REGION_BASE_LOW_7_BASE_ADDRESS_LOW_7_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_CSS:APB:REGION_BASE_HIGH_7 */
#define TZC_CSS_REGION_BASE_HIGH_7(t) ((t) + 0x1e4U)

/*      TZC_CSS:APB:REGION_TOP_LOW_7 */
#define TZC_CSS_REGION_TOP_LOW_7(t) ((t) + 0x1e8U)

#define TZC_CSS_REGION_TOP_LOW_7_TOP_ADDRESS_LOW_7(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_CSS_REGION_TOP_LOW_7_TOP_ADDRESS_LOW_7_M GENMASK(31U, 12U)
#define TZC_CSS_REGION_TOP_LOW_7_TOP_ADDRESS_LOW_7_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_CSS:APB:REGION_TOP_HIGH_7 */
#define TZC_CSS_REGION_TOP_HIGH_7(t) ((t) + 0x1ecU)

/*      TZC_CSS:APB:REGION_ATTRIBUTES_7 */
#define TZC_CSS_REGION_ATTRIBUTES_7(t) ((t) + 0x1f0U)

#define TZC_CSS_REGION_ATTRIBUTES_7_REGION_ATTRIBUTES_7_FILTER_EN(x)\
	((x) & GENMASK(0U, 0U))
#define TZC_CSS_REGION_ATTRIBUTES_7_REGION_ATTRIBUTES_7_FILTER_EN_M\
	GENMASK(0U, 0U)
#define TZC_CSS_REGION_ATTRIBUTES_7_REGION_ATTRIBUTES_7_FILTER_EN_X(x)\
	((x) & GENMASK(0U, 0U))

#define TZC_CSS_REGION_ATTRIBUTES_7_REGION_ATTRIBUTES_7_S_RD_EN(x)\
	(((x) << 30U) & GENMASK(30U, 30U))
#define TZC_CSS_REGION_ATTRIBUTES_7_REGION_ATTRIBUTES_7_S_RD_EN_M\
	GENMASK(30U, 30U)
#define TZC_CSS_REGION_ATTRIBUTES_7_REGION_ATTRIBUTES_7_S_RD_EN_X(x)\
	(((x) & GENMASK(30U, 30U)) >> 30U)

#define TZC_CSS_REGION_ATTRIBUTES_7_REGION_ATTRIBUTES_7_S_WR_EN(x)\
	(((x) << 31U) & GENMASK(31U, 31U))
#define TZC_CSS_REGION_ATTRIBUTES_7_REGION_ATTRIBUTES_7_S_WR_EN_M\
	GENMASK(31U, 31U)
#define TZC_CSS_REGION_ATTRIBUTES_7_REGION_ATTRIBUTES_7_S_WR_EN_X(x)\
	(((x) & GENMASK(31U, 31U)) >> 31U)

/*      TZC_CSS:APB:REGION_ID_ACCESS_7 */
#define TZC_CSS_REGION_ID_ACCESS_7(t) ((t) + 0x1f4U)

#define TZC_CSS_REGION_ID_ACCESS_7_REGION_ID_ACCESS_7_NSAID_RD_EN(x)\
	((x) & GENMASK(15U, 0U))
#define TZC_CSS_REGION_ID_ACCESS_7_REGION_ID_ACCESS_7_NSAID_RD_EN_M\
	GENMASK(15U, 0U)
#define TZC_CSS_REGION_ID_ACCESS_7_REGION_ID_ACCESS_7_NSAID_RD_EN_X(x)\
	((x) & GENMASK(15U, 0U))

#define TZC_CSS_REGION_ID_ACCESS_7_REGION_ID_ACCESS_7_NSAID_WR_EN(x)\
	(((x) << 16U) & GENMASK(31U, 16U))
#define TZC_CSS_REGION_ID_ACCESS_7_REGION_ID_ACCESS_7_NSAID_WR_EN_M\
	GENMASK(31U, 16U)
#define TZC_CSS_REGION_ID_ACCESS_7_REGION_ID_ACCESS_7_NSAID_WR_EN_X(x)\
	(((x) & GENMASK(31U, 16U)) >> 16U)

/*      TZC_CSS:APB:REGION_BASE_LOW_8 */
#define TZC_CSS_REGION_BASE_LOW_8(t) ((t) + 0x200U)

#define TZC_CSS_REGION_BASE_LOW_8_BASE_ADDRESS_LOW_8(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_CSS_REGION_BASE_LOW_8_BASE_ADDRESS_LOW_8_M GENMASK(31U, 12U)
#define TZC_CSS_REGION_BASE_LOW_8_BASE_ADDRESS_LOW_8_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_CSS:APB:REGION_BASE_HIGH_8 */
#define TZC_CSS_REGION_BASE_HIGH_8(t) ((t) + 0x204U)

/*      TZC_CSS:APB:REGION_TOP_LOW_8 */
#define TZC_CSS_REGION_TOP_LOW_8(t) ((t) + 0x208U)

#define TZC_CSS_REGION_TOP_LOW_8_TOP_ADDRESS_LOW_8(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_CSS_REGION_TOP_LOW_8_TOP_ADDRESS_LOW_8_M GENMASK(31U, 12U)
#define TZC_CSS_REGION_TOP_LOW_8_TOP_ADDRESS_LOW_8_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_CSS:APB:REGION_TOP_HIGH_8 */
#define TZC_CSS_REGION_TOP_HIGH_8(t) ((t) + 0x20cU)

/*      TZC_CSS:APB:REGION_ATTRIBUTES_8 */
#define TZC_CSS_REGION_ATTRIBUTES_8(t) ((t) + 0x210U)

#define TZC_CSS_REGION_ATTRIBUTES_8_REGION_ATTRIBUTES_8_FILTER_EN(x)\
	((x) & GENMASK(0U, 0U))
#define TZC_CSS_REGION_ATTRIBUTES_8_REGION_ATTRIBUTES_8_FILTER_EN_M\
	GENMASK(0U, 0U)
#define TZC_CSS_REGION_ATTRIBUTES_8_REGION_ATTRIBUTES_8_FILTER_EN_X(x)\
	((x) & GENMASK(0U, 0U))

#define TZC_CSS_REGION_ATTRIBUTES_8_REGION_ATTRIBUTES_8_S_RD_EN(x)\
	(((x) << 30U) & GENMASK(30U, 30U))
#define TZC_CSS_REGION_ATTRIBUTES_8_REGION_ATTRIBUTES_8_S_RD_EN_M\
	GENMASK(30U, 30U)
#define TZC_CSS_REGION_ATTRIBUTES_8_REGION_ATTRIBUTES_8_S_RD_EN_X(x)\
	(((x) & GENMASK(30U, 30U)) >> 30U)

#define TZC_CSS_REGION_ATTRIBUTES_8_REGION_ATTRIBUTES_8_S_WR_EN(x)\
	(((x) << 31U) & GENMASK(31U, 31U))
#define TZC_CSS_REGION_ATTRIBUTES_8_REGION_ATTRIBUTES_8_S_WR_EN_M\
	GENMASK(31U, 31U)
#define TZC_CSS_REGION_ATTRIBUTES_8_REGION_ATTRIBUTES_8_S_WR_EN_X(x)\
	(((x) & GENMASK(31U, 31U)) >> 31U)

/*      TZC_CSS:APB:REGION_ID_ACCESS_8 */
#define TZC_CSS_REGION_ID_ACCESS_8(t) ((t) + 0x214U)

#define TZC_CSS_REGION_ID_ACCESS_8_REGION_ID_ACCESS_8_NSAID_RD_EN(x)\
	((x) & GENMASK(15U, 0U))
#define TZC_CSS_REGION_ID_ACCESS_8_REGION_ID_ACCESS_8_NSAID_RD_EN_M\
	GENMASK(15U, 0U)
#define TZC_CSS_REGION_ID_ACCESS_8_REGION_ID_ACCESS_8_NSAID_RD_EN_X(x)\
	((x) & GENMASK(15U, 0U))

#define TZC_CSS_REGION_ID_ACCESS_8_REGION_ID_ACCESS_8_NSAID_WR_EN(x)\
	(((x) << 16U) & GENMASK(31U, 16U))
#define TZC_CSS_REGION_ID_ACCESS_8_REGION_ID_ACCESS_8_NSAID_WR_EN_M\
	GENMASK(31U, 16U)
#define TZC_CSS_REGION_ID_ACCESS_8_REGION_ID_ACCESS_8_NSAID_WR_EN_X(x)\
	(((x) & GENMASK(31U, 16U)) >> 16U)

/*      TZC_CSS:APB:PID4 */
#define TZC_CSS_PID4(t)           ((t) + 0xfd0U)

#define TZC_CSS_PID4_JEP106_C_CODE(x)       ((x) & GENMASK(3U, 0U))
#define TZC_CSS_PID4_JEP106_C_CODE_M        GENMASK(3U, 0U)
#define TZC_CSS_PID4_JEP106_C_CODE_X(x)     ((x) & GENMASK(3U, 0U))

#define TZC_CSS_PID4_COUNT_4KB(x)           (((x) << 4U) & GENMASK(7U, 4U))
#define TZC_CSS_PID4_COUNT_4KB_M            GENMASK(7U, 4U)
#define TZC_CSS_PID4_COUNT_4KB_X(x)         (((x) & GENMASK(7U, 4U)) >> 4U)

/*      TZC_CSS:APB:PID5 */
#define TZC_CSS_PID5(t)           ((t) + 0xfd4U)

/*      TZC_CSS:APB:PID6 */
#define TZC_CSS_PID6(t)           ((t) + 0xfd8U)

/*      TZC_CSS:APB:PID7 */
#define TZC_CSS_PID7(t)           ((t) + 0xfdcU)

/*      TZC_CSS:APB:PID0 */
#define TZC_CSS_PID0(t)           ((t) + 0xfe0U)

#define TZC_CSS_PID0_PID0_PART_NUMBER_0(x)  ((x) & GENMASK(7U, 0U))
#define TZC_CSS_PID0_PID0_PART_NUMBER_0_M   GENMASK(7U, 0U)
#define TZC_CSS_PID0_PID0_PART_NUMBER_0_X(x) ((x) & GENMASK(7U, 0U))

/*      TZC_CSS:APB:PID1 */
#define TZC_CSS_PID1(t)           ((t) + 0xfe4U)

#define TZC_CSS_PID1_PID1_PART_NUMBER_0(x)  ((x) & GENMASK(3U, 0U))
#define TZC_CSS_PID1_PID1_PART_NUMBER_0_M   GENMASK(3U, 0U)
#define TZC_CSS_PID1_PID1_PART_NUMBER_0_X(x) ((x) & GENMASK(3U, 0U))

#define TZC_CSS_PID1_JEP106_ID_3_0(x)       (((x) << 4U) & GENMASK(7U, 4U))
#define TZC_CSS_PID1_JEP106_ID_3_0_M        GENMASK(7U, 4U)
#define TZC_CSS_PID1_JEP106_ID_3_0_X(x)     (((x) & GENMASK(7U, 4U)) >> 4U)

/*      TZC_CSS:APB:PID2 */
#define TZC_CSS_PID2(t)           ((t) + 0xfe8U)

#define TZC_CSS_PID2_JEP106_ID_6_4(x)       ((x) & GENMASK(2U, 0U))
#define TZC_CSS_PID2_JEP106_ID_6_4_M        GENMASK(2U, 0U)
#define TZC_CSS_PID2_JEP106_ID_6_4_X(x)     ((x) & GENMASK(2U, 0U))

#define TZC_CSS_PID2_JEDEC_USED(x)          (((x) << 3U) & GENMASK(3U, 3U))
#define TZC_CSS_PID2_JEDEC_USED_M           GENMASK(3U, 3U)
#define TZC_CSS_PID2_JEDEC_USED_X(x)        (((x) & GENMASK(3U, 3U)) >> 3U)

#define TZC_CSS_PID2_REVISION(x)            (((x) << 4U) & GENMASK(7U, 4U))
#define TZC_CSS_PID2_REVISION_M             GENMASK(7U, 4U)
#define TZC_CSS_PID2_REVISION_X(x)          (((x) & GENMASK(7U, 4U)) >> 4U)

/*      TZC_CSS:APB:PID3 */
#define TZC_CSS_PID3(t)           ((t) + 0xfecU)

#define TZC_CSS_PID3_MOD_NUMBER(x)          ((x) & GENMASK(3U, 0U))
#define TZC_CSS_PID3_MOD_NUMBER_M           GENMASK(3U, 0U)
#define TZC_CSS_PID3_MOD_NUMBER_X(x)        ((x) & GENMASK(3U, 0U))

#define TZC_CSS_PID3_REVAND(x)              (((x) << 4U) & GENMASK(7U, 4U))
#define TZC_CSS_PID3_REVAND_M               GENMASK(7U, 4U)
#define TZC_CSS_PID3_REVAND_X(x)            (((x) & GENMASK(7U, 4U)) >> 4U)

/*      TZC_CSS:APB:CID0 */
#define TZC_CSS_CID0(t)           ((t) + 0xff0U)

#define TZC_CSS_CID0_COMP_ID_0(x)           ((x) & GENMASK(7U, 0U))
#define TZC_CSS_CID0_COMP_ID_0_M            GENMASK(7U, 0U)
#define TZC_CSS_CID0_COMP_ID_0_X(x)         ((x) & GENMASK(7U, 0U))

/*      TZC_CSS:APB:CID1 */
#define TZC_CSS_CID1(t)           ((t) + 0xff4U)

#define TZC_CSS_CID1_COMP_ID_1(x)           ((x) & GENMASK(7U, 0U))
#define TZC_CSS_CID1_COMP_ID_1_M            GENMASK(7U, 0U)
#define TZC_CSS_CID1_COMP_ID_1_X(x)         ((x) & GENMASK(7U, 0U))

/*      TZC_CSS:APB:CID2 */
#define TZC_CSS_CID2(t)           ((t) + 0xff8U)

#define TZC_CSS_CID2_COMP_ID_2(x)           ((x) & GENMASK(7U, 0U))
#define TZC_CSS_CID2_COMP_ID_2_M            GENMASK(7U, 0U)
#define TZC_CSS_CID2_COMP_ID_2_X(x)         ((x) & GENMASK(7U, 0U))

/*      TZC_CSS:APB:CID3 */
#define TZC_CSS_CID3(t)           ((t) + 0xffcU)

#define TZC_CSS_CID3_COMP_ID_3(x)           ((x) & GENMASK(7U, 0U))
#define TZC_CSS_CID3_COMP_ID_3_M            GENMASK(7U, 0U)
#define TZC_CSS_CID3_COMP_ID_3_X(x)         ((x) & GENMASK(7U, 0U))

/*      TZC_MAIN_HSS:APB:BUILD_CONFIG */
#define TZC_MAIN_HSS_BUILD_CONFIG(t) ((t) + 0x00U)

#define TZC_MAIN_HSS_BUILD_CONFIG_NO_OF_REGIONS(x) ((x) & GENMASK(4U, 0U))
#define TZC_MAIN_HSS_BUILD_CONFIG_NO_OF_REGIONS_M GENMASK(4U, 0U)
#define TZC_MAIN_HSS_BUILD_CONFIG_NO_OF_REGIONS_X(x) ((x) & GENMASK(4U, 0U))

#define TZC_MAIN_HSS_BUILD_CONFIG_ADDRESS_WIDTH(x)\
	(((x) << 8U) & GENMASK(13U, 8U))
#define TZC_MAIN_HSS_BUILD_CONFIG_ADDRESS_WIDTH_M GENMASK(13U, 8U)
#define TZC_MAIN_HSS_BUILD_CONFIG_ADDRESS_WIDTH_X(x)\
	(((x) & GENMASK(13U, 8U)) >> 8U)

#define TZC_MAIN_HSS_BUILD_CONFIG_NO_OF_FILTERS(x)\
	(((x) << 24U) & GENMASK(25U, 24U))
#define TZC_MAIN_HSS_BUILD_CONFIG_NO_OF_FILTERS_M GENMASK(25U, 24U)
#define TZC_MAIN_HSS_BUILD_CONFIG_NO_OF_FILTERS_X(x)\
	(((x) & GENMASK(25U, 24U)) >> 24U)

/*      TZC_MAIN_HSS:APB:ACTION */
#define TZC_MAIN_HSS_ACTION(t)    ((t) + 0x04U)

#define TZC_MAIN_HSS_ACTION_REACTION_VALUE(x) ((x) & GENMASK(1U, 0U))
#define TZC_MAIN_HSS_ACTION_REACTION_VALUE_M GENMASK(1U, 0U)
#define TZC_MAIN_HSS_ACTION_REACTION_VALUE_X(x) ((x) & GENMASK(1U, 0U))

/*      TZC_MAIN_HSS:APB:GATE_KEEPER */
#define TZC_MAIN_HSS_GATE_KEEPER(t) ((t) + 0x08U)

#define TZC_MAIN_HSS_GATE_KEEPER_OPEN_REQUEST(x) ((x) & GENMASK(3U, 0U))
#define TZC_MAIN_HSS_GATE_KEEPER_OPEN_REQUEST_M GENMASK(3U, 0U)
#define TZC_MAIN_HSS_GATE_KEEPER_OPEN_REQUEST_X(x) ((x) & GENMASK(3U, 0U))

#define TZC_MAIN_HSS_GATE_KEEPER_OPEN_STATUS(x)\
	(((x) << 16U) & GENMASK(19U, 16U))
#define TZC_MAIN_HSS_GATE_KEEPER_OPEN_STATUS_M GENMASK(19U, 16U)
#define TZC_MAIN_HSS_GATE_KEEPER_OPEN_STATUS_X(x)\
	(((x) & GENMASK(19U, 16U)) >> 16U)

/*      TZC_MAIN_HSS:APB:SPECULATION_CTRL */
#define TZC_MAIN_HSS_SPECULATION_CTRL(t) ((t) + 0x0cU)

#define TZC_MAIN_HSS_SPECULATION_CTRL_READ_SPEC_DISABLE(x)\
	((x) & GENMASK(0U, 0U))
#define TZC_MAIN_HSS_SPECULATION_CTRL_READ_SPEC_DISABLE_M GENMASK(0U, 0U)
#define TZC_MAIN_HSS_SPECULATION_CTRL_READ_SPEC_DISABLE_X(x)\
	((x) & GENMASK(0U, 0U))

#define TZC_MAIN_HSS_SPECULATION_CTRL_WRITE_SPEC_DISABLE(x)\
	(((x) << 1U) & GENMASK(1U, 1U))
#define TZC_MAIN_HSS_SPECULATION_CTRL_WRITE_SPEC_DISABLE_M GENMASK(1U, 1U)
#define TZC_MAIN_HSS_SPECULATION_CTRL_WRITE_SPEC_DISABLE_X(x)\
	(((x) & GENMASK(1U, 1U)) >> 1U)

/*      TZC_MAIN_HSS:APB:INT_STATUS */
#define TZC_MAIN_HSS_INT_STATUS(t) ((t) + 0x10U)

#define TZC_MAIN_HSS_INT_STATUS_STATUS(x)   ((x) & GENMASK(3U, 0U))
#define TZC_MAIN_HSS_INT_STATUS_STATUS_M    GENMASK(3U, 0U)
#define TZC_MAIN_HSS_INT_STATUS_STATUS_X(x) ((x) & GENMASK(3U, 0U))

#define TZC_MAIN_HSS_INT_STATUS_OVERRUN(x)  (((x) << 8U) & GENMASK(11U, 8U))
#define TZC_MAIN_HSS_INT_STATUS_OVERRUN_M   GENMASK(11U, 8U)
#define TZC_MAIN_HSS_INT_STATUS_OVERRUN_X(x) (((x) & GENMASK(11U, 8U)) >> 8U)

#define TZC_MAIN_HSS_INT_STATUS_OVERLAP(x)  (((x) << 16U) & GENMASK(19U, 16U))
#define TZC_MAIN_HSS_INT_STATUS_OVERLAP_M   GENMASK(19U, 16U)
#define TZC_MAIN_HSS_INT_STATUS_OVERLAP_X(x) (((x) & GENMASK(19U, 16U)) >> 16U)

/*      TZC_MAIN_HSS:APB:INT_CLEAR */
#define TZC_MAIN_HSS_INT_CLEAR(t) ((t) + 0x14U)

#define TZC_MAIN_HSS_INT_CLEAR_CLEAR(x)     ((x) & GENMASK(3U, 0U))
#define TZC_MAIN_HSS_INT_CLEAR_CLEAR_M      GENMASK(3U, 0U)
#define TZC_MAIN_HSS_INT_CLEAR_CLEAR_X(x)   ((x) & GENMASK(3U, 0U))

/*      TZC_MAIN_HSS:APB:FAIL_ADDRESS_LOW_0 */
#define TZC_MAIN_HSS_FAIL_ADDRESS_LOW_0(t) ((t) + 0x20U)

/*      TZC_MAIN_HSS:APB:FAIL_ADDRESS_HIGH_0 */
#define TZC_MAIN_HSS_FAIL_ADDRESS_HIGH_0(t) ((t) + 0x24U)

/*      TZC_MAIN_HSS:APB:FAIL_CONTROL_0 */
#define TZC_MAIN_HSS_FAIL_CONTROL_0(t) ((t) + 0x28U)

#define TZC_MAIN_HSS_FAIL_CONTROL_0_FAIL_CONTROL_0_PRIVILEGED(x)\
	(((x) << 20U) & GENMASK(20U, 20U))
#define TZC_MAIN_HSS_FAIL_CONTROL_0_FAIL_CONTROL_0_PRIVILEGED_M\
	GENMASK(20U, 20U)
#define TZC_MAIN_HSS_FAIL_CONTROL_0_FAIL_CONTROL_0_PRIVILEGED_X(x)\
	(((x) & GENMASK(20U, 20U)) >> 20U)

#define TZC_MAIN_HSS_FAIL_CONTROL_0_FAIL_CONTROL_0_NONSECURE(x)\
	(((x) << 21U) & GENMASK(21U, 21U))
#define TZC_MAIN_HSS_FAIL_CONTROL_0_FAIL_CONTROL_0_NONSECURE_M GENMASK(21U, 21U)
#define TZC_MAIN_HSS_FAIL_CONTROL_0_FAIL_CONTROL_0_NONSECURE_X(x)\
	(((x) & GENMASK(21U, 21U)) >> 21U)

#define TZC_MAIN_HSS_FAIL_CONTROL_0_FAIL_CONTROL_0_DIRECTION(x)\
	(((x) << 24U) & GENMASK(24U, 24U))
#define TZC_MAIN_HSS_FAIL_CONTROL_0_FAIL_CONTROL_0_DIRECTION_M GENMASK(24U, 24U)
#define TZC_MAIN_HSS_FAIL_CONTROL_0_FAIL_CONTROL_0_DIRECTION_X(x)\
	(((x) & GENMASK(24U, 24U)) >> 24U)

/*      TZC_MAIN_HSS:APB:FAIL_ID_0 */
#define TZC_MAIN_HSS_FAIL_ID_0(t) ((t) + 0x2cU)

#define TZC_MAIN_HSS_FAIL_ID_0_FAIL_ID_0_ID(x) ((x) & GENMASK(8U, 0U))
#define TZC_MAIN_HSS_FAIL_ID_0_FAIL_ID_0_ID_M GENMASK(8U, 0U)
#define TZC_MAIN_HSS_FAIL_ID_0_FAIL_ID_0_ID_X(x) ((x) & GENMASK(8U, 0U))

#define TZC_MAIN_HSS_FAIL_ID_0_FAIL_ID_0_VNET(x)\
	(((x) << 24U) & GENMASK(27U, 24U))
#define TZC_MAIN_HSS_FAIL_ID_0_FAIL_ID_0_VNET_M GENMASK(27U, 24U)
#define TZC_MAIN_HSS_FAIL_ID_0_FAIL_ID_0_VNET_X(x)\
	(((x) & GENMASK(27U, 24U)) >> 24U)

/*      TZC_MAIN_HSS:APB:FAIL_ADDRESS_LOW_1 */
#define TZC_MAIN_HSS_FAIL_ADDRESS_LOW_1(t) ((t) + 0x30U)

/*      TZC_MAIN_HSS:APB:FAIL_ADDRESS_HIGH_1 */
#define TZC_MAIN_HSS_FAIL_ADDRESS_HIGH_1(t) ((t) + 0x34U)

/*      TZC_MAIN_HSS:APB:FAIL_CONTROL_1 */
#define TZC_MAIN_HSS_FAIL_CONTROL_1(t) ((t) + 0x38U)

#define TZC_MAIN_HSS_FAIL_CONTROL_1_FAIL_CONTROL_1_PRIVILEGED(x)\
	(((x) << 20U) & GENMASK(20U, 20U))
#define TZC_MAIN_HSS_FAIL_CONTROL_1_FAIL_CONTROL_1_PRIVILEGED_M\
	GENMASK(20U, 20U)
#define TZC_MAIN_HSS_FAIL_CONTROL_1_FAIL_CONTROL_1_PRIVILEGED_X(x)\
	(((x) & GENMASK(20U, 20U)) >> 20U)

#define TZC_MAIN_HSS_FAIL_CONTROL_1_FAIL_CONTROL_1_NONSECURE(x)\
	(((x) << 21U) & GENMASK(21U, 21U))
#define TZC_MAIN_HSS_FAIL_CONTROL_1_FAIL_CONTROL_1_NONSECURE_M GENMASK(21U, 21U)
#define TZC_MAIN_HSS_FAIL_CONTROL_1_FAIL_CONTROL_1_NONSECURE_X(x)\
	(((x) & GENMASK(21U, 21U)) >> 21U)

#define TZC_MAIN_HSS_FAIL_CONTROL_1_FAIL_CONTROL_1_DIRECTION(x)\
	(((x) << 24U) & GENMASK(24U, 24U))
#define TZC_MAIN_HSS_FAIL_CONTROL_1_FAIL_CONTROL_1_DIRECTION_M GENMASK(24U, 24U)
#define TZC_MAIN_HSS_FAIL_CONTROL_1_FAIL_CONTROL_1_DIRECTION_X(x)\
	(((x) & GENMASK(24U, 24U)) >> 24U)

/*      TZC_MAIN_HSS:APB:FAIL_ID_1 */
#define TZC_MAIN_HSS_FAIL_ID_1(t) ((t) + 0x3cU)

#define TZC_MAIN_HSS_FAIL_ID_1_FAIL_ID_1_ID(x) ((x) & GENMASK(8U, 0U))
#define TZC_MAIN_HSS_FAIL_ID_1_FAIL_ID_1_ID_M GENMASK(8U, 0U)
#define TZC_MAIN_HSS_FAIL_ID_1_FAIL_ID_1_ID_X(x) ((x) & GENMASK(8U, 0U))

#define TZC_MAIN_HSS_FAIL_ID_1_FAIL_ID_1_VNET(x)\
	(((x) << 24U) & GENMASK(27U, 24U))
#define TZC_MAIN_HSS_FAIL_ID_1_FAIL_ID_1_VNET_M GENMASK(27U, 24U)
#define TZC_MAIN_HSS_FAIL_ID_1_FAIL_ID_1_VNET_X(x)\
	(((x) & GENMASK(27U, 24U)) >> 24U)

/*      TZC_MAIN_HSS:APB:FAIL_ADDRESS_LOW_2 */
#define TZC_MAIN_HSS_FAIL_ADDRESS_LOW_2(t) ((t) + 0x40U)

/*      TZC_MAIN_HSS:APB:FAIL_ADDRESS_HIGH_2 */
#define TZC_MAIN_HSS_FAIL_ADDRESS_HIGH_2(t) ((t) + 0x44U)

/*      TZC_MAIN_HSS:APB:FAIL_CONTROL_2 */
#define TZC_MAIN_HSS_FAIL_CONTROL_2(t) ((t) + 0x48U)

#define TZC_MAIN_HSS_FAIL_CONTROL_2_FAIL_CONTROL_2_PRIVILEGED(x)\
	(((x) << 20U) & GENMASK(20U, 20U))
#define TZC_MAIN_HSS_FAIL_CONTROL_2_FAIL_CONTROL_2_PRIVILEGED_M\
	GENMASK(20U, 20U)
#define TZC_MAIN_HSS_FAIL_CONTROL_2_FAIL_CONTROL_2_PRIVILEGED_X(x)\
	(((x) & GENMASK(20U, 20U)) >> 20U)

#define TZC_MAIN_HSS_FAIL_CONTROL_2_FAIL_CONTROL_2_NONSECURE(x)\
	(((x) << 21U) & GENMASK(21U, 21U))
#define TZC_MAIN_HSS_FAIL_CONTROL_2_FAIL_CONTROL_2_NONSECURE_M GENMASK(21U, 21U)
#define TZC_MAIN_HSS_FAIL_CONTROL_2_FAIL_CONTROL_2_NONSECURE_X(x)\
	(((x) & GENMASK(21U, 21U)) >> 21U)

#define TZC_MAIN_HSS_FAIL_CONTROL_2_FAIL_CONTROL_2_DIRECTION(x)\
	(((x) << 24U) & GENMASK(24U, 24U))
#define TZC_MAIN_HSS_FAIL_CONTROL_2_FAIL_CONTROL_2_DIRECTION_M GENMASK(24U, 24U)
#define TZC_MAIN_HSS_FAIL_CONTROL_2_FAIL_CONTROL_2_DIRECTION_X(x)\
	(((x) & GENMASK(24U, 24U)) >> 24U)

/*      TZC_MAIN_HSS:APB:FAIL_ID_2 */
#define TZC_MAIN_HSS_FAIL_ID_2(t) ((t) + 0x4cU)

#define TZC_MAIN_HSS_FAIL_ID_2_FAIL_ID_2_ID(x) ((x) & GENMASK(8U, 0U))
#define TZC_MAIN_HSS_FAIL_ID_2_FAIL_ID_2_ID_M GENMASK(8U, 0U)
#define TZC_MAIN_HSS_FAIL_ID_2_FAIL_ID_2_ID_X(x) ((x) & GENMASK(8U, 0U))

#define TZC_MAIN_HSS_FAIL_ID_2_FAIL_ID_2_VNET(x)\
	(((x) << 24U) & GENMASK(27U, 24U))
#define TZC_MAIN_HSS_FAIL_ID_2_FAIL_ID_2_VNET_M GENMASK(27U, 24U)
#define TZC_MAIN_HSS_FAIL_ID_2_FAIL_ID_2_VNET_X(x)\
	(((x) & GENMASK(27U, 24U)) >> 24U)

/*      TZC_MAIN_HSS:APB:FAIL_ADDRESS_LOW_3 */
#define TZC_MAIN_HSS_FAIL_ADDRESS_LOW_3(t) ((t) + 0x50U)

/*      TZC_MAIN_HSS:APB:FAIL_ADDRESS_HIGH_3 */
#define TZC_MAIN_HSS_FAIL_ADDRESS_HIGH_3(t) ((t) + 0x54U)

/*      TZC_MAIN_HSS:APB:FAIL_CONTROL_3 */
#define TZC_MAIN_HSS_FAIL_CONTROL_3(t) ((t) + 0x58U)

#define TZC_MAIN_HSS_FAIL_CONTROL_3_FAIL_CONTROL_3_PRIVILEGED(x)\
	(((x) << 20U) & GENMASK(20U, 20U))
#define TZC_MAIN_HSS_FAIL_CONTROL_3_FAIL_CONTROL_3_PRIVILEGED_M\
	GENMASK(20U, 20U)
#define TZC_MAIN_HSS_FAIL_CONTROL_3_FAIL_CONTROL_3_PRIVILEGED_X(x)\
	(((x) & GENMASK(20U, 20U)) >> 20U)

#define TZC_MAIN_HSS_FAIL_CONTROL_3_FAIL_CONTROL_3_NONSECURE(x)\
	(((x) << 21U) & GENMASK(21U, 21U))
#define TZC_MAIN_HSS_FAIL_CONTROL_3_FAIL_CONTROL_3_NONSECURE_M GENMASK(21U, 21U)
#define TZC_MAIN_HSS_FAIL_CONTROL_3_FAIL_CONTROL_3_NONSECURE_X(x)\
	(((x) & GENMASK(21U, 21U)) >> 21U)

#define TZC_MAIN_HSS_FAIL_CONTROL_3_FAIL_CONTROL_3_DIRECTION(x)\
	(((x) << 24U) & GENMASK(24U, 24U))
#define TZC_MAIN_HSS_FAIL_CONTROL_3_FAIL_CONTROL_3_DIRECTION_M GENMASK(24U, 24U)
#define TZC_MAIN_HSS_FAIL_CONTROL_3_FAIL_CONTROL_3_DIRECTION_X(x)\
	(((x) & GENMASK(24U, 24U)) >> 24U)

/*      TZC_MAIN_HSS:APB:FAIL_ID_3 */
#define TZC_MAIN_HSS_FAIL_ID_3(t) ((t) + 0x5cU)

#define TZC_MAIN_HSS_FAIL_ID_3_FAIL_ID_3_ID(x) ((x) & GENMASK(8U, 0U))
#define TZC_MAIN_HSS_FAIL_ID_3_FAIL_ID_3_ID_M GENMASK(8U, 0U)
#define TZC_MAIN_HSS_FAIL_ID_3_FAIL_ID_3_ID_X(x) ((x) & GENMASK(8U, 0U))

#define TZC_MAIN_HSS_FAIL_ID_3_FAIL_ID_3_VNET(x)\
	(((x) << 24U) & GENMASK(27U, 24U))
#define TZC_MAIN_HSS_FAIL_ID_3_FAIL_ID_3_VNET_M GENMASK(27U, 24U)
#define TZC_MAIN_HSS_FAIL_ID_3_FAIL_ID_3_VNET_X(x)\
	(((x) & GENMASK(27U, 24U)) >> 24U)

/*      TZC_MAIN_HSS:APB:REGION_BASE_LOW_0 */
#define TZC_MAIN_HSS_REGION_BASE_LOW_0(t) ((t) + 0x100U)

#define TZC_MAIN_HSS_REGION_BASE_LOW_0_BASE_ADDRESS_LOW_0(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_MAIN_HSS_REGION_BASE_LOW_0_BASE_ADDRESS_LOW_0_M GENMASK(31U, 12U)
#define TZC_MAIN_HSS_REGION_BASE_LOW_0_BASE_ADDRESS_LOW_0_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_MAIN_HSS:APB:REGION_BASE_HIGH_0 */
#define TZC_MAIN_HSS_REGION_BASE_HIGH_0(t) ((t) + 0x104U)

/*      TZC_MAIN_HSS:APB:REGION_TOP_LOW_0 */
#define TZC_MAIN_HSS_REGION_TOP_LOW_0(t) ((t) + 0x108U)

#define TZC_MAIN_HSS_REGION_TOP_LOW_0_TOP_ADDRESS_LOW_0(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_MAIN_HSS_REGION_TOP_LOW_0_TOP_ADDRESS_LOW_0_M GENMASK(31U, 12U)
#define TZC_MAIN_HSS_REGION_TOP_LOW_0_TOP_ADDRESS_LOW_0_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_MAIN_HSS:APB:REGION_TOP_HIGH_0 */
#define TZC_MAIN_HSS_REGION_TOP_HIGH_0(t) ((t) + 0x10cU)

/*      TZC_MAIN_HSS:APB:REGION_ATTRIBUTES_0 */
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_0(t) ((t) + 0x110U)

#define TZC_MAIN_HSS_REGION_ATTRIBUTES_0_REGION_ATTRIBUTES_0_FILTER_EN(x)\
	((x) & GENMASK(3U, 0U))
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_0_REGION_ATTRIBUTES_0_FILTER_EN_M\
	GENMASK(3U, 0U)
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_0_REGION_ATTRIBUTES_0_FILTER_EN_X(x)\
	((x) & GENMASK(3U, 0U))

#define TZC_MAIN_HSS_REGION_ATTRIBUTES_0_REGION_ATTRIBUTES_0_S_RD_EN(x)\
	(((x) << 30U) & GENMASK(30U, 30U))
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_0_REGION_ATTRIBUTES_0_S_RD_EN_M\
	GENMASK(30U, 30U)
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_0_REGION_ATTRIBUTES_0_S_RD_EN_X(x)\
	(((x) & GENMASK(30U, 30U)) >> 30U)

#define TZC_MAIN_HSS_REGION_ATTRIBUTES_0_REGION_ATTRIBUTES_0_S_WR_EN(x)\
	(((x) << 31U) & GENMASK(31U, 31U))
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_0_REGION_ATTRIBUTES_0_S_WR_EN_M\
	GENMASK(31U, 31U)
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_0_REGION_ATTRIBUTES_0_S_WR_EN_X(x)\
	(((x) & GENMASK(31U, 31U)) >> 31U)

/*      TZC_MAIN_HSS:APB:REGION_ID_ACCESS_0 */
#define TZC_MAIN_HSS_REGION_ID_ACCESS_0(t) ((t) + 0x114U)

#define TZC_MAIN_HSS_REGION_ID_ACCESS_0_REGION_ID_ACCESS_0_NSAID_RD_EN(x)\
	((x) & GENMASK(15U, 0U))
#define TZC_MAIN_HSS_REGION_ID_ACCESS_0_REGION_ID_ACCESS_0_NSAID_RD_EN_M\
	GENMASK(15U, 0U)
#define TZC_MAIN_HSS_REGION_ID_ACCESS_0_REGION_ID_ACCESS_0_NSAID_RD_EN_X(x)\
	((x) & GENMASK(15U, 0U))

#define TZC_MAIN_HSS_REGION_ID_ACCESS_0_REGION_ID_ACCESS_0_NSAID_WR_EN(x)\
	(((x) << 16U) & GENMASK(31U, 16U))
#define TZC_MAIN_HSS_REGION_ID_ACCESS_0_REGION_ID_ACCESS_0_NSAID_WR_EN_M\
	GENMASK(31U, 16U)
#define TZC_MAIN_HSS_REGION_ID_ACCESS_0_REGION_ID_ACCESS_0_NSAID_WR_EN_X(x)\
	(((x) & GENMASK(31U, 16U)) >> 16U)

/*      TZC_MAIN_HSS:APB:REGION_BASE_LOW_1 */
#define TZC_MAIN_HSS_REGION_BASE_LOW_1(t) ((t) + 0x120U)

#define TZC_MAIN_HSS_REGION_BASE_LOW_1_BASE_ADDRESS_LOW_1(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_MAIN_HSS_REGION_BASE_LOW_1_BASE_ADDRESS_LOW_1_M GENMASK(31U, 12U)
#define TZC_MAIN_HSS_REGION_BASE_LOW_1_BASE_ADDRESS_LOW_1_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_MAIN_HSS:APB:REGION_BASE_HIGH_1 */
#define TZC_MAIN_HSS_REGION_BASE_HIGH_1(t) ((t) + 0x124U)

/*      TZC_MAIN_HSS:APB:REGION_TOP_LOW_1 */
#define TZC_MAIN_HSS_REGION_TOP_LOW_1(t) ((t) + 0x128U)

#define TZC_MAIN_HSS_REGION_TOP_LOW_1_TOP_ADDRESS_LOW_1(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_MAIN_HSS_REGION_TOP_LOW_1_TOP_ADDRESS_LOW_1_M GENMASK(31U, 12U)
#define TZC_MAIN_HSS_REGION_TOP_LOW_1_TOP_ADDRESS_LOW_1_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_MAIN_HSS:APB:REGION_TOP_HIGH_1 */
#define TZC_MAIN_HSS_REGION_TOP_HIGH_1(t) ((t) + 0x12cU)

/*      TZC_MAIN_HSS:APB:REGION_ATTRIBUTES_1 */
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_1(t) ((t) + 0x130U)

#define TZC_MAIN_HSS_REGION_ATTRIBUTES_1_REGION_ATTRIBUTES_1_FILTER_EN(x)\
	((x) & GENMASK(3U, 0U))
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_1_REGION_ATTRIBUTES_1_FILTER_EN_M\
	GENMASK(3U, 0U)
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_1_REGION_ATTRIBUTES_1_FILTER_EN_X(x)\
	((x) & GENMASK(3U, 0U))

#define TZC_MAIN_HSS_REGION_ATTRIBUTES_1_REGION_ATTRIBUTES_1_S_RD_EN(x)\
	(((x) << 30U) & GENMASK(30U, 30U))
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_1_REGION_ATTRIBUTES_1_S_RD_EN_M\
	GENMASK(30U, 30U)
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_1_REGION_ATTRIBUTES_1_S_RD_EN_X(x)\
	(((x) & GENMASK(30U, 30U)) >> 30U)

#define TZC_MAIN_HSS_REGION_ATTRIBUTES_1_REGION_ATTRIBUTES_1_S_WR_EN(x)\
	(((x) << 31U) & GENMASK(31U, 31U))
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_1_REGION_ATTRIBUTES_1_S_WR_EN_M\
	GENMASK(31U, 31U)
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_1_REGION_ATTRIBUTES_1_S_WR_EN_X(x)\
	(((x) & GENMASK(31U, 31U)) >> 31U)

/*      TZC_MAIN_HSS:APB:REGION_ID_ACCESS_1 */
#define TZC_MAIN_HSS_REGION_ID_ACCESS_1(t) ((t) + 0x134U)

#define TZC_MAIN_HSS_REGION_ID_ACCESS_1_REGION_ID_ACCESS_1_NSAID_RD_EN(x)\
	((x) & GENMASK(15U, 0U))
#define TZC_MAIN_HSS_REGION_ID_ACCESS_1_REGION_ID_ACCESS_1_NSAID_RD_EN_M\
	GENMASK(15U, 0U)
#define TZC_MAIN_HSS_REGION_ID_ACCESS_1_REGION_ID_ACCESS_1_NSAID_RD_EN_X(x)\
	((x) & GENMASK(15U, 0U))

#define TZC_MAIN_HSS_REGION_ID_ACCESS_1_REGION_ID_ACCESS_1_NSAID_WR_EN(x)\
	(((x) << 16U) & GENMASK(31U, 16U))
#define TZC_MAIN_HSS_REGION_ID_ACCESS_1_REGION_ID_ACCESS_1_NSAID_WR_EN_M\
	GENMASK(31U, 16U)
#define TZC_MAIN_HSS_REGION_ID_ACCESS_1_REGION_ID_ACCESS_1_NSAID_WR_EN_X(x)\
	(((x) & GENMASK(31U, 16U)) >> 16U)

/*      TZC_MAIN_HSS:APB:REGION_BASE_LOW_2 */
#define TZC_MAIN_HSS_REGION_BASE_LOW_2(t) ((t) + 0x140U)

#define TZC_MAIN_HSS_REGION_BASE_LOW_2_BASE_ADDRESS_LOW_2(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_MAIN_HSS_REGION_BASE_LOW_2_BASE_ADDRESS_LOW_2_M GENMASK(31U, 12U)
#define TZC_MAIN_HSS_REGION_BASE_LOW_2_BASE_ADDRESS_LOW_2_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_MAIN_HSS:APB:REGION_BASE_HIGH_2 */
#define TZC_MAIN_HSS_REGION_BASE_HIGH_2(t) ((t) + 0x144U)

/*      TZC_MAIN_HSS:APB:REGION_TOP_LOW_2 */
#define TZC_MAIN_HSS_REGION_TOP_LOW_2(t) ((t) + 0x148U)

#define TZC_MAIN_HSS_REGION_TOP_LOW_2_TOP_ADDRESS_LOW_2(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_MAIN_HSS_REGION_TOP_LOW_2_TOP_ADDRESS_LOW_2_M GENMASK(31U, 12U)
#define TZC_MAIN_HSS_REGION_TOP_LOW_2_TOP_ADDRESS_LOW_2_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_MAIN_HSS:APB:REGION_TOP_HIGH_2 */
#define TZC_MAIN_HSS_REGION_TOP_HIGH_2(t) ((t) + 0x14cU)

/*      TZC_MAIN_HSS:APB:REGION_ATTRIBUTES_2 */
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_2(t) ((t) + 0x150U)

#define TZC_MAIN_HSS_REGION_ATTRIBUTES_2_REGION_ATTRIBUTES_2_FILTER_EN(x)\
	((x) & GENMASK(3U, 0U))
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_2_REGION_ATTRIBUTES_2_FILTER_EN_M\
	GENMASK(3U, 0U)
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_2_REGION_ATTRIBUTES_2_FILTER_EN_X(x)\
	((x) & GENMASK(3U, 0U))

#define TZC_MAIN_HSS_REGION_ATTRIBUTES_2_REGION_ATTRIBUTES_2_S_RD_EN(x)\
	(((x) << 30U) & GENMASK(30U, 30U))
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_2_REGION_ATTRIBUTES_2_S_RD_EN_M\
	GENMASK(30U, 30U)
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_2_REGION_ATTRIBUTES_2_S_RD_EN_X(x)\
	(((x) & GENMASK(30U, 30U)) >> 30U)

#define TZC_MAIN_HSS_REGION_ATTRIBUTES_2_REGION_ATTRIBUTES_2_S_WR_EN(x)\
	(((x) << 31U) & GENMASK(31U, 31U))
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_2_REGION_ATTRIBUTES_2_S_WR_EN_M\
	GENMASK(31U, 31U)
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_2_REGION_ATTRIBUTES_2_S_WR_EN_X(x)\
	(((x) & GENMASK(31U, 31U)) >> 31U)

/*      TZC_MAIN_HSS:APB:REGION_ID_ACCESS_2 */
#define TZC_MAIN_HSS_REGION_ID_ACCESS_2(t) ((t) + 0x154U)

#define TZC_MAIN_HSS_REGION_ID_ACCESS_2_REGION_ID_ACCESS_2_NSAID_RD_EN(x)\
	((x) & GENMASK(15U, 0U))
#define TZC_MAIN_HSS_REGION_ID_ACCESS_2_REGION_ID_ACCESS_2_NSAID_RD_EN_M\
	GENMASK(15U, 0U)
#define TZC_MAIN_HSS_REGION_ID_ACCESS_2_REGION_ID_ACCESS_2_NSAID_RD_EN_X(x)\
	((x) & GENMASK(15U, 0U))

#define TZC_MAIN_HSS_REGION_ID_ACCESS_2_REGION_ID_ACCESS_2_NSAID_WR_EN(x)\
	(((x) << 16U) & GENMASK(31U, 16U))
#define TZC_MAIN_HSS_REGION_ID_ACCESS_2_REGION_ID_ACCESS_2_NSAID_WR_EN_M\
	GENMASK(31U, 16U)
#define TZC_MAIN_HSS_REGION_ID_ACCESS_2_REGION_ID_ACCESS_2_NSAID_WR_EN_X(x)\
	(((x) & GENMASK(31U, 16U)) >> 16U)

/*      TZC_MAIN_HSS:APB:REGION_BASE_LOW_3 */
#define TZC_MAIN_HSS_REGION_BASE_LOW_3(t) ((t) + 0x160U)

#define TZC_MAIN_HSS_REGION_BASE_LOW_3_BASE_ADDRESS_LOW_3(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_MAIN_HSS_REGION_BASE_LOW_3_BASE_ADDRESS_LOW_3_M GENMASK(31U, 12U)
#define TZC_MAIN_HSS_REGION_BASE_LOW_3_BASE_ADDRESS_LOW_3_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_MAIN_HSS:APB:REGION_BASE_HIGH_3 */
#define TZC_MAIN_HSS_REGION_BASE_HIGH_3(t) ((t) + 0x164U)

/*      TZC_MAIN_HSS:APB:REGION_TOP_LOW_3 */
#define TZC_MAIN_HSS_REGION_TOP_LOW_3(t) ((t) + 0x168U)

#define TZC_MAIN_HSS_REGION_TOP_LOW_3_TOP_ADDRESS_LOW_3(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_MAIN_HSS_REGION_TOP_LOW_3_TOP_ADDRESS_LOW_3_M GENMASK(31U, 12U)
#define TZC_MAIN_HSS_REGION_TOP_LOW_3_TOP_ADDRESS_LOW_3_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_MAIN_HSS:APB:REGION_TOP_HIGH_3 */
#define TZC_MAIN_HSS_REGION_TOP_HIGH_3(t) ((t) + 0x16cU)

/*      TZC_MAIN_HSS:APB:REGION_ATTRIBUTES_3 */
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_3(t) ((t) + 0x170U)

#define TZC_MAIN_HSS_REGION_ATTRIBUTES_3_REGION_ATTRIBUTES_3_FILTER_EN(x)\
	((x) & GENMASK(3U, 0U))
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_3_REGION_ATTRIBUTES_3_FILTER_EN_M\
	GENMASK(3U, 0U)
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_3_REGION_ATTRIBUTES_3_FILTER_EN_X(x)\
	((x) & GENMASK(3U, 0U))

#define TZC_MAIN_HSS_REGION_ATTRIBUTES_3_REGION_ATTRIBUTES_3_S_RD_EN(x)\
	(((x) << 30U) & GENMASK(30U, 30U))
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_3_REGION_ATTRIBUTES_3_S_RD_EN_M\
	GENMASK(30U, 30U)
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_3_REGION_ATTRIBUTES_3_S_RD_EN_X(x)\
	(((x) & GENMASK(30U, 30U)) >> 30U)

#define TZC_MAIN_HSS_REGION_ATTRIBUTES_3_REGION_ATTRIBUTES_3_S_WR_EN(x)\
	(((x) << 31U) & GENMASK(31U, 31U))
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_3_REGION_ATTRIBUTES_3_S_WR_EN_M\
	GENMASK(31U, 31U)
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_3_REGION_ATTRIBUTES_3_S_WR_EN_X(x)\
	(((x) & GENMASK(31U, 31U)) >> 31U)

/*      TZC_MAIN_HSS:APB:REGION_ID_ACCESS_3 */
#define TZC_MAIN_HSS_REGION_ID_ACCESS_3(t) ((t) + 0x174U)

#define TZC_MAIN_HSS_REGION_ID_ACCESS_3_REGION_ID_ACCESS_3_NSAID_RD_EN(x)\
	((x) & GENMASK(15U, 0U))
#define TZC_MAIN_HSS_REGION_ID_ACCESS_3_REGION_ID_ACCESS_3_NSAID_RD_EN_M\
	GENMASK(15U, 0U)
#define TZC_MAIN_HSS_REGION_ID_ACCESS_3_REGION_ID_ACCESS_3_NSAID_RD_EN_X(x)\
	((x) & GENMASK(15U, 0U))

#define TZC_MAIN_HSS_REGION_ID_ACCESS_3_REGION_ID_ACCESS_3_NSAID_WR_EN(x)\
	(((x) << 16U) & GENMASK(31U, 16U))
#define TZC_MAIN_HSS_REGION_ID_ACCESS_3_REGION_ID_ACCESS_3_NSAID_WR_EN_M\
	GENMASK(31U, 16U)
#define TZC_MAIN_HSS_REGION_ID_ACCESS_3_REGION_ID_ACCESS_3_NSAID_WR_EN_X(x)\
	(((x) & GENMASK(31U, 16U)) >> 16U)

/*      TZC_MAIN_HSS:APB:REGION_BASE_LOW_4 */
#define TZC_MAIN_HSS_REGION_BASE_LOW_4(t) ((t) + 0x180U)

#define TZC_MAIN_HSS_REGION_BASE_LOW_4_BASE_ADDRESS_LOW_4(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_MAIN_HSS_REGION_BASE_LOW_4_BASE_ADDRESS_LOW_4_M GENMASK(31U, 12U)
#define TZC_MAIN_HSS_REGION_BASE_LOW_4_BASE_ADDRESS_LOW_4_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_MAIN_HSS:APB:REGION_BASE_HIGH_4 */
#define TZC_MAIN_HSS_REGION_BASE_HIGH_4(t) ((t) + 0x184U)

/*      TZC_MAIN_HSS:APB:REGION_TOP_LOW_4 */
#define TZC_MAIN_HSS_REGION_TOP_LOW_4(t) ((t) + 0x188U)

#define TZC_MAIN_HSS_REGION_TOP_LOW_4_TOP_ADDRESS_LOW_4(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_MAIN_HSS_REGION_TOP_LOW_4_TOP_ADDRESS_LOW_4_M GENMASK(31U, 12U)
#define TZC_MAIN_HSS_REGION_TOP_LOW_4_TOP_ADDRESS_LOW_4_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_MAIN_HSS:APB:REGION_TOP_HIGH_4 */
#define TZC_MAIN_HSS_REGION_TOP_HIGH_4(t) ((t) + 0x18cU)

/*      TZC_MAIN_HSS:APB:REGION_ATTRIBUTES_4 */
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_4(t) ((t) + 0x190U)

#define TZC_MAIN_HSS_REGION_ATTRIBUTES_4_REGION_ATTRIBUTES_4_FILTER_EN(x)\
	((x) & GENMASK(3U, 0U))
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_4_REGION_ATTRIBUTES_4_FILTER_EN_M\
	GENMASK(3U, 0U)
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_4_REGION_ATTRIBUTES_4_FILTER_EN_X(x)\
	((x) & GENMASK(3U, 0U))

#define TZC_MAIN_HSS_REGION_ATTRIBUTES_4_REGION_ATTRIBUTES_4_S_RD_EN(x)\
	(((x) << 30U) & GENMASK(30U, 30U))
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_4_REGION_ATTRIBUTES_4_S_RD_EN_M\
	GENMASK(30U, 30U)
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_4_REGION_ATTRIBUTES_4_S_RD_EN_X(x)\
	(((x) & GENMASK(30U, 30U)) >> 30U)

#define TZC_MAIN_HSS_REGION_ATTRIBUTES_4_REGION_ATTRIBUTES_4_S_WR_EN(x)\
	(((x) << 31U) & GENMASK(31U, 31U))
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_4_REGION_ATTRIBUTES_4_S_WR_EN_M\
	GENMASK(31U, 31U)
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_4_REGION_ATTRIBUTES_4_S_WR_EN_X(x)\
	(((x) & GENMASK(31U, 31U)) >> 31U)

/*      TZC_MAIN_HSS:APB:REGION_ID_ACCESS_4 */
#define TZC_MAIN_HSS_REGION_ID_ACCESS_4(t) ((t) + 0x194U)

#define TZC_MAIN_HSS_REGION_ID_ACCESS_4_REGION_ID_ACCESS_4_NSAID_RD_EN(x)\
	((x) & GENMASK(15U, 0U))
#define TZC_MAIN_HSS_REGION_ID_ACCESS_4_REGION_ID_ACCESS_4_NSAID_RD_EN_M\
	GENMASK(15U, 0U)
#define TZC_MAIN_HSS_REGION_ID_ACCESS_4_REGION_ID_ACCESS_4_NSAID_RD_EN_X(x)\
	((x) & GENMASK(15U, 0U))

#define TZC_MAIN_HSS_REGION_ID_ACCESS_4_REGION_ID_ACCESS_4_NSAID_WR_EN(x)\
	(((x) << 16U) & GENMASK(31U, 16U))
#define TZC_MAIN_HSS_REGION_ID_ACCESS_4_REGION_ID_ACCESS_4_NSAID_WR_EN_M\
	GENMASK(31U, 16U)
#define TZC_MAIN_HSS_REGION_ID_ACCESS_4_REGION_ID_ACCESS_4_NSAID_WR_EN_X(x)\
	(((x) & GENMASK(31U, 16U)) >> 16U)

/*      TZC_MAIN_HSS:APB:REGION_BASE_LOW_5 */
#define TZC_MAIN_HSS_REGION_BASE_LOW_5(t) ((t) + 0x1a0U)

#define TZC_MAIN_HSS_REGION_BASE_LOW_5_BASE_ADDRESS_LOW_5(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_MAIN_HSS_REGION_BASE_LOW_5_BASE_ADDRESS_LOW_5_M GENMASK(31U, 12U)
#define TZC_MAIN_HSS_REGION_BASE_LOW_5_BASE_ADDRESS_LOW_5_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_MAIN_HSS:APB:REGION_BASE_HIGH_5 */
#define TZC_MAIN_HSS_REGION_BASE_HIGH_5(t) ((t) + 0x1a4U)

/*      TZC_MAIN_HSS:APB:REGION_TOP_LOW_5 */
#define TZC_MAIN_HSS_REGION_TOP_LOW_5(t) ((t) + 0x1a8U)

#define TZC_MAIN_HSS_REGION_TOP_LOW_5_TOP_ADDRESS_LOW_5(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_MAIN_HSS_REGION_TOP_LOW_5_TOP_ADDRESS_LOW_5_M GENMASK(31U, 12U)
#define TZC_MAIN_HSS_REGION_TOP_LOW_5_TOP_ADDRESS_LOW_5_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_MAIN_HSS:APB:REGION_TOP_HIGH_5 */
#define TZC_MAIN_HSS_REGION_TOP_HIGH_5(t) ((t) + 0x1acU)

/*      TZC_MAIN_HSS:APB:REGION_ATTRIBUTES_5 */
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_5(t) ((t) + 0x1b0U)

#define TZC_MAIN_HSS_REGION_ATTRIBUTES_5_REGION_ATTRIBUTES_5_FILTER_EN(x)\
	((x) & GENMASK(3U, 0U))
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_5_REGION_ATTRIBUTES_5_FILTER_EN_M\
	GENMASK(3U, 0U)
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_5_REGION_ATTRIBUTES_5_FILTER_EN_X(x)\
	((x) & GENMASK(3U, 0U))

#define TZC_MAIN_HSS_REGION_ATTRIBUTES_5_REGION_ATTRIBUTES_5_S_RD_EN(x)\
	(((x) << 30U) & GENMASK(30U, 30U))
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_5_REGION_ATTRIBUTES_5_S_RD_EN_M\
	GENMASK(30U, 30U)
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_5_REGION_ATTRIBUTES_5_S_RD_EN_X(x)\
	(((x) & GENMASK(30U, 30U)) >> 30U)

#define TZC_MAIN_HSS_REGION_ATTRIBUTES_5_REGION_ATTRIBUTES_5_S_WR_EN(x)\
	(((x) << 31U) & GENMASK(31U, 31U))
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_5_REGION_ATTRIBUTES_5_S_WR_EN_M\
	GENMASK(31U, 31U)
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_5_REGION_ATTRIBUTES_5_S_WR_EN_X(x)\
	(((x) & GENMASK(31U, 31U)) >> 31U)

/*      TZC_MAIN_HSS:APB:REGION_ID_ACCESS_5 */
#define TZC_MAIN_HSS_REGION_ID_ACCESS_5(t) ((t) + 0x1b4U)

#define TZC_MAIN_HSS_REGION_ID_ACCESS_5_REGION_ID_ACCESS_5_NSAID_RD_EN(x)\
	((x) & GENMASK(15U, 0U))
#define TZC_MAIN_HSS_REGION_ID_ACCESS_5_REGION_ID_ACCESS_5_NSAID_RD_EN_M\
	GENMASK(15U, 0U)
#define TZC_MAIN_HSS_REGION_ID_ACCESS_5_REGION_ID_ACCESS_5_NSAID_RD_EN_X(x)\
	((x) & GENMASK(15U, 0U))

#define TZC_MAIN_HSS_REGION_ID_ACCESS_5_REGION_ID_ACCESS_5_NSAID_WR_EN(x)\
	(((x) << 16U) & GENMASK(31U, 16U))
#define TZC_MAIN_HSS_REGION_ID_ACCESS_5_REGION_ID_ACCESS_5_NSAID_WR_EN_M\
	GENMASK(31U, 16U)
#define TZC_MAIN_HSS_REGION_ID_ACCESS_5_REGION_ID_ACCESS_5_NSAID_WR_EN_X(x)\
	(((x) & GENMASK(31U, 16U)) >> 16U)

/*      TZC_MAIN_HSS:APB:REGION_BASE_LOW_6 */
#define TZC_MAIN_HSS_REGION_BASE_LOW_6(t) ((t) + 0x1c0U)

#define TZC_MAIN_HSS_REGION_BASE_LOW_6_BASE_ADDRESS_LOW_6(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_MAIN_HSS_REGION_BASE_LOW_6_BASE_ADDRESS_LOW_6_M GENMASK(31U, 12U)
#define TZC_MAIN_HSS_REGION_BASE_LOW_6_BASE_ADDRESS_LOW_6_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_MAIN_HSS:APB:REGION_BASE_HIGH_6 */
#define TZC_MAIN_HSS_REGION_BASE_HIGH_6(t) ((t) + 0x1c4U)

/*      TZC_MAIN_HSS:APB:REGION_TOP_LOW_6 */
#define TZC_MAIN_HSS_REGION_TOP_LOW_6(t) ((t) + 0x1c8U)

#define TZC_MAIN_HSS_REGION_TOP_LOW_6_TOP_ADDRESS_LOW_6(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_MAIN_HSS_REGION_TOP_LOW_6_TOP_ADDRESS_LOW_6_M GENMASK(31U, 12U)
#define TZC_MAIN_HSS_REGION_TOP_LOW_6_TOP_ADDRESS_LOW_6_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_MAIN_HSS:APB:REGION_TOP_HIGH_6 */
#define TZC_MAIN_HSS_REGION_TOP_HIGH_6(t) ((t) + 0x1ccU)

/*      TZC_MAIN_HSS:APB:REGION_ATTRIBUTES_6 */
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_6(t) ((t) + 0x1d0U)

#define TZC_MAIN_HSS_REGION_ATTRIBUTES_6_REGION_ATTRIBUTES_6_FILTER_EN(x)\
	((x) & GENMASK(3U, 0U))
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_6_REGION_ATTRIBUTES_6_FILTER_EN_M\
	GENMASK(3U, 0U)
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_6_REGION_ATTRIBUTES_6_FILTER_EN_X(x)\
	((x) & GENMASK(3U, 0U))

#define TZC_MAIN_HSS_REGION_ATTRIBUTES_6_REGION_ATTRIBUTES_6_S_RD_EN(x)\
	(((x) << 30U) & GENMASK(30U, 30U))
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_6_REGION_ATTRIBUTES_6_S_RD_EN_M\
	GENMASK(30U, 30U)
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_6_REGION_ATTRIBUTES_6_S_RD_EN_X(x)\
	(((x) & GENMASK(30U, 30U)) >> 30U)

#define TZC_MAIN_HSS_REGION_ATTRIBUTES_6_REGION_ATTRIBUTES_6_S_WR_EN(x)\
	(((x) << 31U) & GENMASK(31U, 31U))
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_6_REGION_ATTRIBUTES_6_S_WR_EN_M\
	GENMASK(31U, 31U)
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_6_REGION_ATTRIBUTES_6_S_WR_EN_X(x)\
	(((x) & GENMASK(31U, 31U)) >> 31U)

/*      TZC_MAIN_HSS:APB:REGION_ID_ACCESS_6 */
#define TZC_MAIN_HSS_REGION_ID_ACCESS_6(t) ((t) + 0x1d4U)

#define TZC_MAIN_HSS_REGION_ID_ACCESS_6_REGION_ID_ACCESS_6_NSAID_RD_EN(x)\
	((x) & GENMASK(15U, 0U))
#define TZC_MAIN_HSS_REGION_ID_ACCESS_6_REGION_ID_ACCESS_6_NSAID_RD_EN_M\
	GENMASK(15U, 0U)
#define TZC_MAIN_HSS_REGION_ID_ACCESS_6_REGION_ID_ACCESS_6_NSAID_RD_EN_X(x)\
	((x) & GENMASK(15U, 0U))

#define TZC_MAIN_HSS_REGION_ID_ACCESS_6_REGION_ID_ACCESS_6_NSAID_WR_EN(x)\
	(((x) << 16U) & GENMASK(31U, 16U))
#define TZC_MAIN_HSS_REGION_ID_ACCESS_6_REGION_ID_ACCESS_6_NSAID_WR_EN_M\
	GENMASK(31U, 16U)
#define TZC_MAIN_HSS_REGION_ID_ACCESS_6_REGION_ID_ACCESS_6_NSAID_WR_EN_X(x)\
	(((x) & GENMASK(31U, 16U)) >> 16U)

/*      TZC_MAIN_HSS:APB:REGION_BASE_LOW_7 */
#define TZC_MAIN_HSS_REGION_BASE_LOW_7(t) ((t) + 0x1e0U)

#define TZC_MAIN_HSS_REGION_BASE_LOW_7_BASE_ADDRESS_LOW_7(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_MAIN_HSS_REGION_BASE_LOW_7_BASE_ADDRESS_LOW_7_M GENMASK(31U, 12U)
#define TZC_MAIN_HSS_REGION_BASE_LOW_7_BASE_ADDRESS_LOW_7_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_MAIN_HSS:APB:REGION_BASE_HIGH_7 */
#define TZC_MAIN_HSS_REGION_BASE_HIGH_7(t) ((t) + 0x1e4U)

/*      TZC_MAIN_HSS:APB:REGION_TOP_LOW_7 */
#define TZC_MAIN_HSS_REGION_TOP_LOW_7(t) ((t) + 0x1e8U)

#define TZC_MAIN_HSS_REGION_TOP_LOW_7_TOP_ADDRESS_LOW_7(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_MAIN_HSS_REGION_TOP_LOW_7_TOP_ADDRESS_LOW_7_M GENMASK(31U, 12U)
#define TZC_MAIN_HSS_REGION_TOP_LOW_7_TOP_ADDRESS_LOW_7_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_MAIN_HSS:APB:REGION_TOP_HIGH_7 */
#define TZC_MAIN_HSS_REGION_TOP_HIGH_7(t) ((t) + 0x1ecU)

/*      TZC_MAIN_HSS:APB:REGION_ATTRIBUTES_7 */
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_7(t) ((t) + 0x1f0U)

#define TZC_MAIN_HSS_REGION_ATTRIBUTES_7_REGION_ATTRIBUTES_7_FILTER_EN(x)\
	((x) & GENMASK(3U, 0U))
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_7_REGION_ATTRIBUTES_7_FILTER_EN_M\
	GENMASK(3U, 0U)
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_7_REGION_ATTRIBUTES_7_FILTER_EN_X(x)\
	((x) & GENMASK(3U, 0U))

#define TZC_MAIN_HSS_REGION_ATTRIBUTES_7_REGION_ATTRIBUTES_7_S_RD_EN(x)\
	(((x) << 30U) & GENMASK(30U, 30U))
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_7_REGION_ATTRIBUTES_7_S_RD_EN_M\
	GENMASK(30U, 30U)
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_7_REGION_ATTRIBUTES_7_S_RD_EN_X(x)\
	(((x) & GENMASK(30U, 30U)) >> 30U)

#define TZC_MAIN_HSS_REGION_ATTRIBUTES_7_REGION_ATTRIBUTES_7_S_WR_EN(x)\
	(((x) << 31U) & GENMASK(31U, 31U))
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_7_REGION_ATTRIBUTES_7_S_WR_EN_M\
	GENMASK(31U, 31U)
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_7_REGION_ATTRIBUTES_7_S_WR_EN_X(x)\
	(((x) & GENMASK(31U, 31U)) >> 31U)

/*      TZC_MAIN_HSS:APB:REGION_ID_ACCESS_7 */
#define TZC_MAIN_HSS_REGION_ID_ACCESS_7(t) ((t) + 0x1f4U)

#define TZC_MAIN_HSS_REGION_ID_ACCESS_7_REGION_ID_ACCESS_7_NSAID_RD_EN(x)\
	((x) & GENMASK(15U, 0U))
#define TZC_MAIN_HSS_REGION_ID_ACCESS_7_REGION_ID_ACCESS_7_NSAID_RD_EN_M\
	GENMASK(15U, 0U)
#define TZC_MAIN_HSS_REGION_ID_ACCESS_7_REGION_ID_ACCESS_7_NSAID_RD_EN_X(x)\
	((x) & GENMASK(15U, 0U))

#define TZC_MAIN_HSS_REGION_ID_ACCESS_7_REGION_ID_ACCESS_7_NSAID_WR_EN(x)\
	(((x) << 16U) & GENMASK(31U, 16U))
#define TZC_MAIN_HSS_REGION_ID_ACCESS_7_REGION_ID_ACCESS_7_NSAID_WR_EN_M\
	GENMASK(31U, 16U)
#define TZC_MAIN_HSS_REGION_ID_ACCESS_7_REGION_ID_ACCESS_7_NSAID_WR_EN_X(x)\
	(((x) & GENMASK(31U, 16U)) >> 16U)

/*      TZC_MAIN_HSS:APB:REGION_BASE_LOW_8 */
#define TZC_MAIN_HSS_REGION_BASE_LOW_8(t) ((t) + 0x200U)

#define TZC_MAIN_HSS_REGION_BASE_LOW_8_BASE_ADDRESS_LOW_8(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_MAIN_HSS_REGION_BASE_LOW_8_BASE_ADDRESS_LOW_8_M GENMASK(31U, 12U)
#define TZC_MAIN_HSS_REGION_BASE_LOW_8_BASE_ADDRESS_LOW_8_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_MAIN_HSS:APB:REGION_BASE_HIGH_8 */
#define TZC_MAIN_HSS_REGION_BASE_HIGH_8(t) ((t) + 0x204U)

/*      TZC_MAIN_HSS:APB:REGION_TOP_LOW_8 */
#define TZC_MAIN_HSS_REGION_TOP_LOW_8(t) ((t) + 0x208U)

#define TZC_MAIN_HSS_REGION_TOP_LOW_8_TOP_ADDRESS_LOW_8(x)\
	(((x) << 12U) & GENMASK(31U, 12U))
#define TZC_MAIN_HSS_REGION_TOP_LOW_8_TOP_ADDRESS_LOW_8_M GENMASK(31U, 12U)
#define TZC_MAIN_HSS_REGION_TOP_LOW_8_TOP_ADDRESS_LOW_8_X(x)\
	(((x) & GENMASK(31U, 12U)) >> 12U)

/*      TZC_MAIN_HSS:APB:REGION_TOP_HIGH_8 */
#define TZC_MAIN_HSS_REGION_TOP_HIGH_8(t) ((t) + 0x20cU)

/*      TZC_MAIN_HSS:APB:REGION_ATTRIBUTES_8 */
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_8(t) ((t) + 0x210U)

#define TZC_MAIN_HSS_REGION_ATTRIBUTES_8_REGION_ATTRIBUTES_8_FILTER_EN(x)\
	((x) & GENMASK(3U, 0U))
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_8_REGION_ATTRIBUTES_8_FILTER_EN_M\
	GENMASK(3U, 0U)
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_8_REGION_ATTRIBUTES_8_FILTER_EN_X(x)\
	((x) & GENMASK(3U, 0U))

#define TZC_MAIN_HSS_REGION_ATTRIBUTES_8_REGION_ATTRIBUTES_8_S_RD_EN(x)\
	(((x) << 30U) & GENMASK(30U, 30U))
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_8_REGION_ATTRIBUTES_8_S_RD_EN_M\
	GENMASK(30U, 30U)
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_8_REGION_ATTRIBUTES_8_S_RD_EN_X(x)\
	(((x) & GENMASK(30U, 30U)) >> 30U)

#define TZC_MAIN_HSS_REGION_ATTRIBUTES_8_REGION_ATTRIBUTES_8_S_WR_EN(x)\
	(((x) << 31U) & GENMASK(31U, 31U))
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_8_REGION_ATTRIBUTES_8_S_WR_EN_M\
	GENMASK(31U, 31U)
#define TZC_MAIN_HSS_REGION_ATTRIBUTES_8_REGION_ATTRIBUTES_8_S_WR_EN_X(x)\
	(((x) & GENMASK(31U, 31U)) >> 31U)

/*      TZC_MAIN_HSS:APB:REGION_ID_ACCESS_8 */
#define TZC_MAIN_HSS_REGION_ID_ACCESS_8(t) ((t) + 0x214U)

#define TZC_MAIN_HSS_REGION_ID_ACCESS_8_REGION_ID_ACCESS_8_NSAID_RD_EN(x)\
	((x) & GENMASK(15U, 0U))
#define TZC_MAIN_HSS_REGION_ID_ACCESS_8_REGION_ID_ACCESS_8_NSAID_RD_EN_M\
	GENMASK(15U, 0U)
#define TZC_MAIN_HSS_REGION_ID_ACCESS_8_REGION_ID_ACCESS_8_NSAID_RD_EN_X(x)\
	((x) & GENMASK(15U, 0U))

#define TZC_MAIN_HSS_REGION_ID_ACCESS_8_REGION_ID_ACCESS_8_NSAID_WR_EN(x)\
	(((x) << 16U) & GENMASK(31U, 16U))
#define TZC_MAIN_HSS_REGION_ID_ACCESS_8_REGION_ID_ACCESS_8_NSAID_WR_EN_M\
	GENMASK(31U, 16U)
#define TZC_MAIN_HSS_REGION_ID_ACCESS_8_REGION_ID_ACCESS_8_NSAID_WR_EN_X(x)\
	(((x) & GENMASK(31U, 16U)) >> 16U)

/*      TZC_MAIN_HSS:APB:PID4 */
#define TZC_MAIN_HSS_PID4(t)      ((t) + 0xfd0U)

#define TZC_MAIN_HSS_PID4_JEP106_C_CODE(x)  ((x) & GENMASK(3U, 0U))
#define TZC_MAIN_HSS_PID4_JEP106_C_CODE_M   GENMASK(3U, 0U)
#define TZC_MAIN_HSS_PID4_JEP106_C_CODE_X(x) ((x) & GENMASK(3U, 0U))

#define TZC_MAIN_HSS_PID4_COUNT_4KB(x)      (((x) << 4U) & GENMASK(7U, 4U))
#define TZC_MAIN_HSS_PID4_COUNT_4KB_M       GENMASK(7U, 4U)
#define TZC_MAIN_HSS_PID4_COUNT_4KB_X(x)    (((x) & GENMASK(7U, 4U)) >> 4U)

/*      TZC_MAIN_HSS:APB:PID5 */
#define TZC_MAIN_HSS_PID5(t)      ((t) + 0xfd4U)

/*      TZC_MAIN_HSS:APB:PID6 */
#define TZC_MAIN_HSS_PID6(t)      ((t) + 0xfd8U)

/*      TZC_MAIN_HSS:APB:PID7 */
#define TZC_MAIN_HSS_PID7(t)      ((t) + 0xfdcU)

/*      TZC_MAIN_HSS:APB:PID0 */
#define TZC_MAIN_HSS_PID0(t)      ((t) + 0xfe0U)

#define TZC_MAIN_HSS_PID0_PID0_PART_NUMBER_0(x) ((x) & GENMASK(7U, 0U))
#define TZC_MAIN_HSS_PID0_PID0_PART_NUMBER_0_M GENMASK(7U, 0U)
#define TZC_MAIN_HSS_PID0_PID0_PART_NUMBER_0_X(x) ((x) & GENMASK(7U, 0U))

/*      TZC_MAIN_HSS:APB:PID1 */
#define TZC_MAIN_HSS_PID1(t)      ((t) + 0xfe4U)

#define TZC_MAIN_HSS_PID1_PID1_PART_NUMBER_0(x) ((x) & GENMASK(3U, 0U))
#define TZC_MAIN_HSS_PID1_PID1_PART_NUMBER_0_M GENMASK(3U, 0U)
#define TZC_MAIN_HSS_PID1_PID1_PART_NUMBER_0_X(x) ((x) & GENMASK(3U, 0U))

#define TZC_MAIN_HSS_PID1_JEP106_ID_3_0(x)  (((x) << 4U) & GENMASK(7U, 4U))
#define TZC_MAIN_HSS_PID1_JEP106_ID_3_0_M   GENMASK(7U, 4U)
#define TZC_MAIN_HSS_PID1_JEP106_ID_3_0_X(x) (((x) & GENMASK(7U, 4U)) >> 4U)

/*      TZC_MAIN_HSS:APB:PID2 */
#define TZC_MAIN_HSS_PID2(t)      ((t) + 0xfe8U)

#define TZC_MAIN_HSS_PID2_JEP106_ID_6_4(x)  ((x) & GENMASK(2U, 0U))
#define TZC_MAIN_HSS_PID2_JEP106_ID_6_4_M   GENMASK(2U, 0U)
#define TZC_MAIN_HSS_PID2_JEP106_ID_6_4_X(x) ((x) & GENMASK(2U, 0U))

#define TZC_MAIN_HSS_PID2_JEDEC_USED(x)     (((x) << 3U) & GENMASK(3U, 3U))
#define TZC_MAIN_HSS_PID2_JEDEC_USED_M      GENMASK(3U, 3U)
#define TZC_MAIN_HSS_PID2_JEDEC_USED_X(x)   (((x) & GENMASK(3U, 3U)) >> 3U)

#define TZC_MAIN_HSS_PID2_REVISION(x)       (((x) << 4U) & GENMASK(7U, 4U))
#define TZC_MAIN_HSS_PID2_REVISION_M        GENMASK(7U, 4U)
#define TZC_MAIN_HSS_PID2_REVISION_X(x)     (((x) & GENMASK(7U, 4U)) >> 4U)

/*      TZC_MAIN_HSS:APB:PID3 */
#define TZC_MAIN_HSS_PID3(t)      ((t) + 0xfecU)

#define TZC_MAIN_HSS_PID3_MOD_NUMBER(x)     ((x) & GENMASK(3U, 0U))
#define TZC_MAIN_HSS_PID3_MOD_NUMBER_M      GENMASK(3U, 0U)
#define TZC_MAIN_HSS_PID3_MOD_NUMBER_X(x)   ((x) & GENMASK(3U, 0U))

#define TZC_MAIN_HSS_PID3_REVAND(x)         (((x) << 4U) & GENMASK(7U, 4U))
#define TZC_MAIN_HSS_PID3_REVAND_M          GENMASK(7U, 4U)
#define TZC_MAIN_HSS_PID3_REVAND_X(x)       (((x) & GENMASK(7U, 4U)) >> 4U)

/*      TZC_MAIN_HSS:APB:CID0 */
#define TZC_MAIN_HSS_CID0(t)      ((t) + 0xff0U)

#define TZC_MAIN_HSS_CID0_COMP_ID_0(x)      ((x) & GENMASK(7U, 0U))
#define TZC_MAIN_HSS_CID0_COMP_ID_0_M       GENMASK(7U, 0U)
#define TZC_MAIN_HSS_CID0_COMP_ID_0_X(x)    ((x) & GENMASK(7U, 0U))

/*      TZC_MAIN_HSS:APB:CID1 */
#define TZC_MAIN_HSS_CID1(t)      ((t) + 0xff4U)

#define TZC_MAIN_HSS_CID1_COMP_ID_1(x)      ((x) & GENMASK(7U, 0U))
#define TZC_MAIN_HSS_CID1_COMP_ID_1_M       GENMASK(7U, 0U)
#define TZC_MAIN_HSS_CID1_COMP_ID_1_X(x)    ((x) & GENMASK(7U, 0U))

/*      TZC_MAIN_HSS:APB:CID2 */
#define TZC_MAIN_HSS_CID2(t)      ((t) + 0xff8U)

#define TZC_MAIN_HSS_CID2_COMP_ID_2(x)      ((x) & GENMASK(7U, 0U))
#define TZC_MAIN_HSS_CID2_COMP_ID_2_M       GENMASK(7U, 0U)
#define TZC_MAIN_HSS_CID2_COMP_ID_2_X(x)    ((x) & GENMASK(7U, 0U))

/*      TZC_MAIN_HSS:APB:CID3 */
#define TZC_MAIN_HSS_CID3(t)      ((t) + 0xffcU)

#define TZC_MAIN_HSS_CID3_COMP_ID_3(x)      ((x) & GENMASK(7U, 0U))
#define TZC_MAIN_HSS_CID3_COMP_ID_3_M       GENMASK(7U, 0U)
#define TZC_MAIN_HSS_CID3_COMP_ID_3_X(x)    ((x) & GENMASK(7U, 0U))

/*      TZPM:TZPM_REGS:TZPM_EN */
#define TZPM_TZPM_EN(t)           ((t) + 0x00U)

#define TZPM_TZPM_EN_TZPM_EN(x)             ((x) & GENMASK(0U, 0U))
#define TZPM_TZPM_EN_TZPM_EN_M              GENMASK(0U, 0U)
#define TZPM_TZPM_EN_TZPM_EN_X(x)           ((x) & GENMASK(0U, 0U))

/*      TZPM:TZPM_REGS:TZPM_KEY */
#define TZPM_TZPM_KEY(t)          ((t) + 0x04U)

/*      TZPM:TZPM_REGS:TZPCTL0 */
#define TZPM_TZPCTL0(t)           ((t) + 0x08U)

#define TZPM_TZPCTL0_SDMMC1(x)              (((x) << 14U) & GENMASK(14U, 14U))
#define TZPM_TZPCTL0_SDMMC1_M               GENMASK(14U, 14U)
#define TZPM_TZPCTL0_SDMMC1_X(x)            (((x) & GENMASK(14U, 14U)) >> 14U)

#define TZPM_TZPCTL0_QSPI2(x)               (((x) << 13U) & GENMASK(13U, 13U))
#define TZPM_TZPCTL0_QSPI2_M                GENMASK(13U, 13U)
#define TZPM_TZPCTL0_QSPI2_X(x)             (((x) & GENMASK(13U, 13U)) >> 13U)

#define TZPM_TZPCTL0_SDMMC0(x)              (((x) << 12U) & GENMASK(12U, 12U))
#define TZPM_TZPCTL0_SDMMC0_M               GENMASK(12U, 12U)
#define TZPM_TZPCTL0_SDMMC0_X(x)            (((x) & GENMASK(12U, 12U)) >> 12U)

#define TZPM_TZPCTL0_TC1(x)                 (((x) << 9U) & GENMASK(9U, 9U))
#define TZPM_TZPCTL0_TC1_M                  GENMASK(9U, 9U)
#define TZPM_TZPCTL0_TC1_X(x)               (((x) & GENMASK(9U, 9U)) >> 9U)

#define TZPM_TZPCTL0_MCAN1(x)               (((x) << 8U) & GENMASK(8U, 8U))
#define TZPM_TZPCTL0_MCAN1_M                GENMASK(8U, 8U)
#define TZPM_TZPCTL0_MCAN1_X(x)             (((x) & GENMASK(8U, 8U)) >> 8U)

#define TZPM_TZPCTL0_MCAN0(x)               (((x) << 7U) & GENMASK(7U, 7U))
#define TZPM_TZPCTL0_MCAN0_M                GENMASK(7U, 7U)
#define TZPM_TZPCTL0_MCAN0_X(x)             (((x) & GENMASK(7U, 7U)) >> 7U)

#define TZPM_TZPCTL0_TZAESBS(x)             (((x) << 6U) & GENMASK(6U, 6U))
#define TZPM_TZPCTL0_TZAESBS_M              GENMASK(6U, 6U)
#define TZPM_TZPCTL0_TZAESBS_X(x)           (((x) & GENMASK(6U, 6U)) >> 6U)

#define TZPM_TZPCTL0_TZAESBNS(x)            (((x) << 5U) & GENMASK(5U, 5U))
#define TZPM_TZPCTL0_TZAESBNS_M             GENMASK(5U, 5U)
#define TZPM_TZPCTL0_TZAESBNS_X(x)          (((x) & GENMASK(5U, 5U)) >> 5U)

#define TZPM_TZPCTL0_ICM(x)                 (((x) << 4U) & GENMASK(4U, 4U))
#define TZPM_TZPCTL0_ICM_M                  GENMASK(4U, 4U)
#define TZPM_TZPCTL0_ICM_X(x)               (((x) & GENMASK(4U, 4U)) >> 4U)

#define TZPM_TZPCTL0_QSPI0(x)               (((x) << 1U) & GENMASK(1U, 1U))
#define TZPM_TZPCTL0_QSPI0_M                GENMASK(1U, 1U)
#define TZPM_TZPCTL0_QSPI0_X(x)             (((x) & GENMASK(1U, 1U)) >> 1U)

#define TZPM_TZPCTL0_HMATRIX(x)             ((x) & GENMASK(0U, 0U))
#define TZPM_TZPCTL0_HMATRIX_M              GENMASK(0U, 0U)
#define TZPM_TZPCTL0_HMATRIX_X(x)           ((x) & GENMASK(0U, 0U))

/*      TZPM:TZPM_REGS:TZPCTL1 */
#define TZPM_TZPCTL1(t)           ((t) + 0x0cU)

#define TZPM_TZPCTL1_FLEXCOM4(x)            (((x) << 20U) & GENMASK(20U, 20U))
#define TZPM_TZPCTL1_FLEXCOM4_M             GENMASK(20U, 20U)
#define TZPM_TZPCTL1_FLEXCOM4_X(x)          (((x) & GENMASK(20U, 20U)) >> 20U)

#define TZPM_TZPCTL1_SHA(x)                 (((x) << 19U) & GENMASK(19U, 19U))
#define TZPM_TZPCTL1_SHA_M                  GENMASK(19U, 19U)
#define TZPM_TZPCTL1_SHA_X(x)               (((x) & GENMASK(19U, 19U)) >> 19U)

#define TZPM_TZPCTL1_XDMA(x)                (((x) << 18U) & GENMASK(18U, 18U))
#define TZPM_TZPCTL1_XDMA_M                 GENMASK(18U, 18U)
#define TZPM_TZPCTL1_XDMA_X(x)              (((x) & GENMASK(18U, 18U)) >> 18U)

#define TZPM_TZPCTL1_FLEXCOM3(x)            (((x) << 17U) & GENMASK(17U, 17U))
#define TZPM_TZPCTL1_FLEXCOM3_M             GENMASK(17U, 17U)
#define TZPM_TZPCTL1_FLEXCOM3_X(x)          (((x) & GENMASK(17U, 17U)) >> 17U)

#define TZPM_TZPCTL1_FLEXCOM2(x)            (((x) << 16U) & GENMASK(16U, 16U))
#define TZPM_TZPCTL1_FLEXCOM2_M             GENMASK(16U, 16U)
#define TZPM_TZPCTL1_FLEXCOM2_X(x)          (((x) & GENMASK(16U, 16U)) >> 16U)

#define TZPM_TZPCTL1_AESB_ASC(x)            (((x) << 4U) & GENMASK(4U, 4U))
#define TZPM_TZPCTL1_AESB_ASC_M             GENMASK(4U, 4U)
#define TZPM_TZPCTL1_AESB_ASC_X(x)          (((x) & GENMASK(4U, 4U)) >> 4U)

#define TZPM_TZPCTL1_AES(x)                 (((x) << 3U) & GENMASK(3U, 3U))
#define TZPM_TZPCTL1_AES_M                  GENMASK(3U, 3U)
#define TZPM_TZPCTL1_AES_X(x)               (((x) & GENMASK(3U, 3U)) >> 3U)

#define TZPM_TZPCTL1_TRNG(x)                (((x) << 2U) & GENMASK(2U, 2U))
#define TZPM_TZPCTL1_TRNG_M                 GENMASK(2U, 2U)
#define TZPM_TZPCTL1_TRNG_X(x)              (((x) & GENMASK(2U, 2U)) >> 2U)

#define TZPM_TZPCTL1_FLEXCOM1(x)            (((x) << 1U) & GENMASK(1U, 1U))
#define TZPM_TZPCTL1_FLEXCOM1_M             GENMASK(1U, 1U)
#define TZPM_TZPCTL1_FLEXCOM1_X(x)          (((x) & GENMASK(1U, 1U)) >> 1U)

#define TZPM_TZPCTL1_FLEXCOM0(x)            ((x) & GENMASK(0U, 0U))
#define TZPM_TZPCTL1_FLEXCOM0_M             GENMASK(0U, 0U)
#define TZPM_TZPCTL1_FLEXCOM0_X(x)          ((x) & GENMASK(0U, 0U))

/*      TZPM:TZPM_REGS:TZPCTL2 */
#define TZPM_TZPCTL2(t)           ((t) + 0x10U)

#define TZPM_TZPCTL2_TZPM(x)                (((x) << 1U) & GENMASK(1U, 1U))
#define TZPM_TZPCTL2_TZPM_M                 GENMASK(1U, 1U)
#define TZPM_TZPCTL2_TZPM_X(x)              (((x) & GENMASK(1U, 1U)) >> 1U)

#define TZPM_TZPCTL2_PKE(x)                 ((x) & GENMASK(0U, 0U))
#define TZPM_TZPCTL2_PKE_M                  GENMASK(0U, 0U)
#define TZPM_TZPCTL2_PKE_X(x)               ((x) & GENMASK(0U, 0U))

/*      TZPM:TZPM_REGS:TZPCTL3 */
#define TZPM_TZPCTL3(t)           ((t) + 0x14U)

#define TZPM_TZPCTL3_PCIE_IB(x)             (((x) << 27U) & GENMASK(27U, 27U))
#define TZPM_TZPCTL3_PCIE_IB_M              GENMASK(27U, 27U)
#define TZPM_TZPCTL3_PCIE_IB_X(x)           (((x) & GENMASK(27U, 27U)) >> 27U)

#define TZPM_TZPCTL3_FDMA(x)                (((x) << 25U) & GENMASK(25U, 25U))
#define TZPM_TZPCTL3_FDMA_M                 GENMASK(25U, 25U)
#define TZPM_TZPCTL3_FDMA_X(x)              (((x) & GENMASK(25U, 25U)) >> 25U)

#define TZPM_TZPCTL3_EXT_INITIATOR(x)       (((x) << 24U) & GENMASK(24U, 24U))
#define TZPM_TZPCTL3_EXT_INITIATOR_M        GENMASK(24U, 24U)
#define TZPM_TZPCTL3_EXT_INITIATOR_X(x)     (((x) & GENMASK(24U, 24U)) >> 24U)

/*      TZPM:TZPM_REGS:TZPM_SFR */
#define TZPM_TZPM_SFR(t)          ((t) + 0x18U)

#define TZPM_TZPM_SFR_GIC400_CFGSDISABLE(x) ((x) & GENMASK(0U, 0U))
#define TZPM_TZPM_SFR_GIC400_CFGSDISABLE_M  GENMASK(0U, 0U)
#define TZPM_TZPM_SFR_GIC400_CFGSDISABLE_X(x) ((x) & GENMASK(0U, 0U))

/*      UVOV:UVOV_REGS:UVOV_CTL */
#define UVOV_UVOV_CTL(t)          ((t) + 0x00U)

#define UVOV_UVOV_CTL_MST_OVR_DET_EN(x)     (((x) << 1U) & GENMASK(1U, 1U))
#define UVOV_UVOV_CTL_MST_OVR_DET_EN_M      GENMASK(1U, 1U)
#define UVOV_UVOV_CTL_MST_OVR_DET_EN_X(x)   (((x) & GENMASK(1U, 1U)) >> 1U)

#define UVOV_UVOV_CTL_MST_UVR_DET_EN(x)     ((x) & GENMASK(0U, 0U))
#define UVOV_UVOV_CTL_MST_UVR_DET_EN_M      GENMASK(0U, 0U)
#define UVOV_UVOV_CTL_MST_UVR_DET_EN_X(x)   ((x) & GENMASK(0U, 0U))

/*      UVOV:UVOV_REGS:UVOV_INT_STS */
#define UVOV_UVOV_INT_STS(t)      ((t) + 0x04U)

#define UVOV_UVOV_INT_STS_TRIM_INT_STS(x)   (((x) << 24U) & GENMASK(24U, 24U))
#define UVOV_UVOV_INT_STS_TRIM_INT_STS_M    GENMASK(24U, 24U)
#define UVOV_UVOV_INT_STS_TRIM_INT_STS_X(x) (((x) & GENMASK(24U, 24U)) >> 24U)

#define UVOV_UVOV_INT_STS_OVR_INT_STS_V09(x) (((x) << 20U) & GENMASK(20U, 20U))
#define UVOV_UVOV_INT_STS_OVR_INT_STS_V09_M GENMASK(20U, 20U)
#define UVOV_UVOV_INT_STS_OVR_INT_STS_V09_X(x)\
	(((x) & GENMASK(20U, 20U)) >> 20U)

#define UVOV_UVOV_INT_STS_UVR_INT_STS_V09(x) (((x) << 16U) & GENMASK(16U, 16U))
#define UVOV_UVOV_INT_STS_UVR_INT_STS_V09_M GENMASK(16U, 16U)
#define UVOV_UVOV_INT_STS_UVR_INT_STS_V09_X(x)\
	(((x) & GENMASK(16U, 16U)) >> 16U)

#define UVOV_UVOV_INT_STS_OVR_INT_STS_V12(x) (((x) << 12U) & GENMASK(12U, 12U))
#define UVOV_UVOV_INT_STS_OVR_INT_STS_V12_M GENMASK(12U, 12U)
#define UVOV_UVOV_INT_STS_OVR_INT_STS_V12_X(x)\
	(((x) & GENMASK(12U, 12U)) >> 12U)

#define UVOV_UVOV_INT_STS_UVR_INT_STS_V12(x) (((x) << 8U) & GENMASK(8U, 8U))
#define UVOV_UVOV_INT_STS_UVR_INT_STS_V12_M GENMASK(8U, 8U)
#define UVOV_UVOV_INT_STS_UVR_INT_STS_V12_X(x) (((x) & GENMASK(8U, 8U)) >> 8U)

#define UVOV_UVOV_INT_STS_OVR_INT_STS_V18(x) (((x) << 4U) & GENMASK(4U, 4U))
#define UVOV_UVOV_INT_STS_OVR_INT_STS_V18_M GENMASK(4U, 4U)
#define UVOV_UVOV_INT_STS_OVR_INT_STS_V18_X(x) (((x) & GENMASK(4U, 4U)) >> 4U)

#define UVOV_UVOV_INT_STS_UVR_INT_STS_V18(x) ((x) & GENMASK(0U, 0U))
#define UVOV_UVOV_INT_STS_UVR_INT_STS_V18_M GENMASK(0U, 0U)
#define UVOV_UVOV_INT_STS_UVR_INT_STS_V18_X(x) ((x) & GENMASK(0U, 0U))

/*      UVOV:UVOV_REGS:UVOV_INT_EN */
#define UVOV_UVOV_INT_EN(t)       ((t) + 0x08U)

#define UVOV_UVOV_INT_EN_TRIM_INT_EN(x)     (((x) << 24U) & GENMASK(24U, 24U))
#define UVOV_UVOV_INT_EN_TRIM_INT_EN_M      GENMASK(24U, 24U)
#define UVOV_UVOV_INT_EN_TRIM_INT_EN_X(x)   (((x) & GENMASK(24U, 24U)) >> 24U)

#define UVOV_UVOV_INT_EN_OVR_INT_EN_v09(x)  (((x) << 20U) & GENMASK(20U, 20U))
#define UVOV_UVOV_INT_EN_OVR_INT_EN_v09_M   GENMASK(20U, 20U)
#define UVOV_UVOV_INT_EN_OVR_INT_EN_v09_X(x) (((x) & GENMASK(20U, 20U)) >> 20U)

#define UVOV_UVOV_INT_EN_UVR_INT_EN_v09(x)  (((x) << 16U) & GENMASK(16U, 16U))
#define UVOV_UVOV_INT_EN_UVR_INT_EN_v09_M   GENMASK(16U, 16U)
#define UVOV_UVOV_INT_EN_UVR_INT_EN_v09_X(x) (((x) & GENMASK(16U, 16U)) >> 16U)

#define UVOV_UVOV_INT_EN_OVR_INT_EN_v12(x)  (((x) << 12U) & GENMASK(12U, 12U))
#define UVOV_UVOV_INT_EN_OVR_INT_EN_v12_M   GENMASK(12U, 12U)
#define UVOV_UVOV_INT_EN_OVR_INT_EN_v12_X(x) (((x) & GENMASK(12U, 12U)) >> 12U)

#define UVOV_UVOV_INT_EN_UVR_INT_EN_v12(x)  (((x) << 8U) & GENMASK(8U, 8U))
#define UVOV_UVOV_INT_EN_UVR_INT_EN_v12_M   GENMASK(8U, 8U)
#define UVOV_UVOV_INT_EN_UVR_INT_EN_v12_X(x) (((x) & GENMASK(8U, 8U)) >> 8U)

#define UVOV_UVOV_INT_EN_OVR_INT_EN_v18(x)  (((x) << 4U) & GENMASK(4U, 4U))
#define UVOV_UVOV_INT_EN_OVR_INT_EN_v18_M   GENMASK(4U, 4U)
#define UVOV_UVOV_INT_EN_OVR_INT_EN_v18_X(x) (((x) & GENMASK(4U, 4U)) >> 4U)

#define UVOV_UVOV_INT_EN_UVR_INT_EN_v18(x)  ((x) & GENMASK(0U, 0U))
#define UVOV_UVOV_INT_EN_UVR_INT_EN_v18_M   GENMASK(0U, 0U)
#define UVOV_UVOV_INT_EN_UVR_INT_EN_v18_X(x) ((x) & GENMASK(0U, 0U))

/*      UVOV:UVOV_CFG:TUNE */
#define UVOV_TUNE(t)              ((t) + 0x0cU)

#define UVOV_TUNE_TUNE_CDR(x)               (((x) << 24U) & GENMASK(26U, 24U))
#define UVOV_TUNE_TUNE_CDR_M                GENMASK(26U, 24U)
#define UVOV_TUNE_TUNE_CDR_X(x)             (((x) & GENMASK(26U, 24U)) >> 24U)

#define UVOV_TUNE_TUNE_M(x)                 (((x) << 18U) & GENMASK(23U, 18U))
#define UVOV_TUNE_TUNE_M_M                  GENMASK(23U, 18U)
#define UVOV_TUNE_TUNE_M_X(x)               (((x) & GENMASK(23U, 18U)) >> 18U)

#define UVOV_TUNE_TUNE_MAG(x)               (((x) << 12U) & GENMASK(17U, 12U))
#define UVOV_TUNE_TUNE_MAG_M                GENMASK(17U, 12U)
#define UVOV_TUNE_TUNE_MAG_X(x)             (((x) & GENMASK(17U, 12U)) >> 12U)

#define UVOV_TUNE_TRIM_EN(x)                (((x) << 6U) & GENMASK(6U, 6U))
#define UVOV_TUNE_TRIM_EN_M                 GENMASK(6U, 6U)
#define UVOV_TUNE_TRIM_EN_X(x)              (((x) & GENMASK(6U, 6U)) >> 6U)

/*      UVOV:UVOV_CFG:ATP_UVOV */
#define UVOV_ATP_UVOV(t)          ((t) + 0x10U)

#define UVOV_ATP_UVOV_ATP_UVOV_SEL(x)       ((x) & GENMASK(1U, 0U))
#define UVOV_ATP_UVOV_ATP_UVOV_SEL_M        GENMASK(1U, 0U)
#define UVOV_ATP_UVOV_ATP_UVOV_SEL_X(x)     ((x) & GENMASK(1U, 0U))

/*      UVOV:UVOV_CFG:UVOV_CFG0_V09 */
#define UVOV_UVOV_CFG0_V09(t)     ((t) + 0x14U)

#define UVOV_UVOV_CFG0_V09_OV_DEB_EN_V09(x) (((x) << 28U) & GENMASK(28U, 28U))
#define UVOV_UVOV_CFG0_V09_OV_DEB_EN_V09_M  GENMASK(28U, 28U)
#define UVOV_UVOV_CFG0_V09_OV_DEB_EN_V09_X(x) (((x) & GENMASK(28U, 28U)) >> 28U)

#define UVOV_UVOV_CFG0_V09_UV_DEB_EN_V09(x) (((x) << 27U) & GENMASK(27U, 27U))
#define UVOV_UVOV_CFG0_V09_UV_DEB_EN_V09_M  GENMASK(27U, 27U)
#define UVOV_UVOV_CFG0_V09_UV_DEB_EN_V09_X(x) (((x) & GENMASK(27U, 27U)) >> 27U)

#define UVOV_UVOV_CFG0_V09_OV_RST_EN_V09(x) (((x) << 11U) & GENMASK(11U, 11U))
#define UVOV_UVOV_CFG0_V09_OV_RST_EN_V09_M  GENMASK(11U, 11U)
#define UVOV_UVOV_CFG0_V09_OV_RST_EN_V09_X(x) (((x) & GENMASK(11U, 11U)) >> 11U)

#define UVOV_UVOV_CFG0_V09_UV_RST_EN_V09(x) (((x) << 10U) & GENMASK(10U, 10U))
#define UVOV_UVOV_CFG0_V09_UV_RST_EN_V09_M  GENMASK(10U, 10U)
#define UVOV_UVOV_CFG0_V09_UV_RST_EN_V09_X(x) (((x) & GENMASK(10U, 10U)) >> 10U)

#define UVOV_UVOV_CFG0_V09_OVR_RNG_SEL_V09(x) (((x) << 4U) & GENMASK(5U, 4U))
#define UVOV_UVOV_CFG0_V09_OVR_RNG_SEL_V09_M GENMASK(5U, 4U)
#define UVOV_UVOV_CFG0_V09_OVR_RNG_SEL_V09_X(x) (((x) & GENMASK(5U, 4U)) >> 4U)

#define UVOV_UVOV_CFG0_V09_UVR_RNG_SEL_V09(x) (((x) << 2U) & GENMASK(3U, 2U))
#define UVOV_UVOV_CFG0_V09_UVR_RNG_SEL_V09_M GENMASK(3U, 2U)
#define UVOV_UVOV_CFG0_V09_UVR_RNG_SEL_V09_X(x) (((x) & GENMASK(3U, 2U)) >> 2U)

#define UVOV_UVOV_CFG0_V09_OVR_DET_EN_V09(x) (((x) << 1U) & GENMASK(1U, 1U))
#define UVOV_UVOV_CFG0_V09_OVR_DET_EN_V09_M GENMASK(1U, 1U)
#define UVOV_UVOV_CFG0_V09_OVR_DET_EN_V09_X(x) (((x) & GENMASK(1U, 1U)) >> 1U)

#define UVOV_UVOV_CFG0_V09_UVR_DET_EN_V09(x) ((x) & GENMASK(0U, 0U))
#define UVOV_UVOV_CFG0_V09_UVR_DET_EN_V09_M GENMASK(0U, 0U)
#define UVOV_UVOV_CFG0_V09_UVR_DET_EN_V09_X(x) ((x) & GENMASK(0U, 0U))

/*      UVOV:UVOV_CFG:UVOV_CFG1_V09 */
#define UVOV_UVOV_CFG1_V09(t)     ((t) + 0x18U)

#define UVOV_UVOV_CFG1_V09_UVOV_DEB_V09(x)  (((x) << 8U) & GENMASK(31U, 8U))
#define UVOV_UVOV_CFG1_V09_UVOV_DEB_V09_M   GENMASK(31U, 8U)
#define UVOV_UVOV_CFG1_V09_UVOV_DEB_V09_X(x) (((x) & GENMASK(31U, 8U)) >> 8U)

#define UVOV_UVOV_CFG1_V09_OV_STS_V09(x)    (((x) << 1U) & GENMASK(1U, 1U))
#define UVOV_UVOV_CFG1_V09_OV_STS_V09_M     GENMASK(1U, 1U)
#define UVOV_UVOV_CFG1_V09_OV_STS_V09_X(x)  (((x) & GENMASK(1U, 1U)) >> 1U)

#define UVOV_UVOV_CFG1_V09_UV_STS_V09(x)    ((x) & GENMASK(0U, 0U))
#define UVOV_UVOV_CFG1_V09_UV_STS_V09_M     GENMASK(0U, 0U)
#define UVOV_UVOV_CFG1_V09_UV_STS_V09_X(x)  ((x) & GENMASK(0U, 0U))

/*      UVOV:UVOV_CFG:UVOV_CFG0_V12 */
#define UVOV_UVOV_CFG0_V12(t)     ((t) + 0x1cU)

#define UVOV_UVOV_CFG0_V12_OV_DEB_EN_V12(x) (((x) << 28U) & GENMASK(28U, 28U))
#define UVOV_UVOV_CFG0_V12_OV_DEB_EN_V12_M  GENMASK(28U, 28U)
#define UVOV_UVOV_CFG0_V12_OV_DEB_EN_V12_X(x) (((x) & GENMASK(28U, 28U)) >> 28U)

#define UVOV_UVOV_CFG0_V12_UV_DEB_EN_V12(x) (((x) << 27U) & GENMASK(27U, 27U))
#define UVOV_UVOV_CFG0_V12_UV_DEB_EN_V12_M  GENMASK(27U, 27U)
#define UVOV_UVOV_CFG0_V12_UV_DEB_EN_V12_X(x) (((x) & GENMASK(27U, 27U)) >> 27U)

#define UVOV_UVOV_CFG0_V12_OV_RST_EN_V12(x) (((x) << 11U) & GENMASK(11U, 11U))
#define UVOV_UVOV_CFG0_V12_OV_RST_EN_V12_M  GENMASK(11U, 11U)
#define UVOV_UVOV_CFG0_V12_OV_RST_EN_V12_X(x) (((x) & GENMASK(11U, 11U)) >> 11U)

#define UVOV_UVOV_CFG0_V12_UV_RST_EN_V12(x) (((x) << 10U) & GENMASK(10U, 10U))
#define UVOV_UVOV_CFG0_V12_UV_RST_EN_V12_M  GENMASK(10U, 10U)
#define UVOV_UVOV_CFG0_V12_UV_RST_EN_V12_X(x) (((x) & GENMASK(10U, 10U)) >> 10U)

#define UVOV_UVOV_CFG0_V12_OVR_RNG_SEL_V12(x) (((x) << 4U) & GENMASK(5U, 4U))
#define UVOV_UVOV_CFG0_V12_OVR_RNG_SEL_V12_M GENMASK(5U, 4U)
#define UVOV_UVOV_CFG0_V12_OVR_RNG_SEL_V12_X(x) (((x) & GENMASK(5U, 4U)) >> 4U)

#define UVOV_UVOV_CFG0_V12_UVR_RNG_SEL_V12(x) (((x) << 2U) & GENMASK(3U, 2U))
#define UVOV_UVOV_CFG0_V12_UVR_RNG_SEL_V12_M GENMASK(3U, 2U)
#define UVOV_UVOV_CFG0_V12_UVR_RNG_SEL_V12_X(x) (((x) & GENMASK(3U, 2U)) >> 2U)

#define UVOV_UVOV_CFG0_V12_OVR_DET_EN_V12(x) (((x) << 1U) & GENMASK(1U, 1U))
#define UVOV_UVOV_CFG0_V12_OVR_DET_EN_V12_M GENMASK(1U, 1U)
#define UVOV_UVOV_CFG0_V12_OVR_DET_EN_V12_X(x) (((x) & GENMASK(1U, 1U)) >> 1U)

#define UVOV_UVOV_CFG0_V12_UVR_DET_EN_V12(x) ((x) & GENMASK(0U, 0U))
#define UVOV_UVOV_CFG0_V12_UVR_DET_EN_V12_M GENMASK(0U, 0U)
#define UVOV_UVOV_CFG0_V12_UVR_DET_EN_V12_X(x) ((x) & GENMASK(0U, 0U))

/*      UVOV:UVOV_CFG:UVOV_CFG1_V12 */
#define UVOV_UVOV_CFG1_V12(t)     ((t) + 0x20U)

#define UVOV_UVOV_CFG1_V12_UVOV_DEB_V12(x)  (((x) << 8U) & GENMASK(31U, 8U))
#define UVOV_UVOV_CFG1_V12_UVOV_DEB_V12_M   GENMASK(31U, 8U)
#define UVOV_UVOV_CFG1_V12_UVOV_DEB_V12_X(x) (((x) & GENMASK(31U, 8U)) >> 8U)

#define UVOV_UVOV_CFG1_V12_OV_STS_V12(x)    (((x) << 1U) & GENMASK(1U, 1U))
#define UVOV_UVOV_CFG1_V12_OV_STS_V12_M     GENMASK(1U, 1U)
#define UVOV_UVOV_CFG1_V12_OV_STS_V12_X(x)  (((x) & GENMASK(1U, 1U)) >> 1U)

#define UVOV_UVOV_CFG1_V12_UV_STS_V12(x)    ((x) & GENMASK(0U, 0U))
#define UVOV_UVOV_CFG1_V12_UV_STS_V12_M     GENMASK(0U, 0U)
#define UVOV_UVOV_CFG1_V12_UV_STS_V12_X(x)  ((x) & GENMASK(0U, 0U))

/*      UVOV:UVOV_CFG:UVOV_CFG0_V18 */
#define UVOV_UVOV_CFG0_V18(t)     ((t) + 0x24U)

#define UVOV_UVOV_CFG0_V18_OV_DEB_EN_V18(x) (((x) << 28U) & GENMASK(28U, 28U))
#define UVOV_UVOV_CFG0_V18_OV_DEB_EN_V18_M  GENMASK(28U, 28U)
#define UVOV_UVOV_CFG0_V18_OV_DEB_EN_V18_X(x) (((x) & GENMASK(28U, 28U)) >> 28U)

#define UVOV_UVOV_CFG0_V18_UV_DEB_EN_V18(x) (((x) << 27U) & GENMASK(27U, 27U))
#define UVOV_UVOV_CFG0_V18_UV_DEB_EN_V18_M  GENMASK(27U, 27U)
#define UVOV_UVOV_CFG0_V18_UV_DEB_EN_V18_X(x) (((x) & GENMASK(27U, 27U)) >> 27U)

#define UVOV_UVOV_CFG0_V18_OV_RST_EN_V18(x) (((x) << 11U) & GENMASK(11U, 11U))
#define UVOV_UVOV_CFG0_V18_OV_RST_EN_V18_M  GENMASK(11U, 11U)
#define UVOV_UVOV_CFG0_V18_OV_RST_EN_V18_X(x) (((x) & GENMASK(11U, 11U)) >> 11U)

#define UVOV_UVOV_CFG0_V18_UV_RST_EN_V18(x) (((x) << 10U) & GENMASK(10U, 10U))
#define UVOV_UVOV_CFG0_V18_UV_RST_EN_V18_M  GENMASK(10U, 10U)
#define UVOV_UVOV_CFG0_V18_UV_RST_EN_V18_X(x) (((x) & GENMASK(10U, 10U)) >> 10U)

#define UVOV_UVOV_CFG0_V18_OVR_RNG_SEL_V18(x) (((x) << 4U) & GENMASK(5U, 4U))
#define UVOV_UVOV_CFG0_V18_OVR_RNG_SEL_V18_M GENMASK(5U, 4U)
#define UVOV_UVOV_CFG0_V18_OVR_RNG_SEL_V18_X(x) (((x) & GENMASK(5U, 4U)) >> 4U)

#define UVOV_UVOV_CFG0_V18_UVR_RNG_SEL_V18(x) (((x) << 2U) & GENMASK(3U, 2U))
#define UVOV_UVOV_CFG0_V18_UVR_RNG_SEL_V18_M GENMASK(3U, 2U)
#define UVOV_UVOV_CFG0_V18_UVR_RNG_SEL_V18_X(x) (((x) & GENMASK(3U, 2U)) >> 2U)

#define UVOV_UVOV_CFG0_V18_OVR_DET_EN_V18(x) (((x) << 1U) & GENMASK(1U, 1U))
#define UVOV_UVOV_CFG0_V18_OVR_DET_EN_V18_M GENMASK(1U, 1U)
#define UVOV_UVOV_CFG0_V18_OVR_DET_EN_V18_X(x) (((x) & GENMASK(1U, 1U)) >> 1U)

#define UVOV_UVOV_CFG0_V18_UVR_DET_EN_V18(x) ((x) & GENMASK(0U, 0U))
#define UVOV_UVOV_CFG0_V18_UVR_DET_EN_V18_M GENMASK(0U, 0U)
#define UVOV_UVOV_CFG0_V18_UVR_DET_EN_V18_X(x) ((x) & GENMASK(0U, 0U))

/*      UVOV:UVOV_CFG:UVOV_CFG1_V18 */
#define UVOV_UVOV_CFG1_V18(t)     ((t) + 0x28U)

#define UVOV_UVOV_CFG1_V18_UVOV_DEB_V18(x)  (((x) << 8U) & GENMASK(31U, 8U))
#define UVOV_UVOV_CFG1_V18_UVOV_DEB_V18_M   GENMASK(31U, 8U)
#define UVOV_UVOV_CFG1_V18_UVOV_DEB_V18_X(x) (((x) & GENMASK(31U, 8U)) >> 8U)

#define UVOV_UVOV_CFG1_V18_OV_STS_V18(x)    (((x) << 1U) & GENMASK(1U, 1U))
#define UVOV_UVOV_CFG1_V18_OV_STS_V18_M     GENMASK(1U, 1U)
#define UVOV_UVOV_CFG1_V18_OV_STS_V18_X(x)  (((x) & GENMASK(1U, 1U)) >> 1U)

#define UVOV_UVOV_CFG1_V18_UV_STS_V18(x)    ((x) & GENMASK(0U, 0U))
#define UVOV_UVOV_CFG1_V18_UV_STS_V18_M     GENMASK(0U, 0U)
#define UVOV_UVOV_CFG1_V18_UV_STS_V18_X(x)  ((x) & GENMASK(0U, 0U))

/*      XDMAC:XDMAC_REG:XDMAC_GTYPE */
#define XDMAC_XDMAC_GTYPE(t)      ((t) + 0x00U)

#define XDMAC_XDMAC_GTYPE_NB_REQ(x)         (((x) << 16U) & GENMASK(22U, 16U))
#define XDMAC_XDMAC_GTYPE_NB_REQ_M          GENMASK(22U, 16U)
#define XDMAC_XDMAC_GTYPE_NB_REQ_X(x)       (((x) & GENMASK(22U, 16U)) >> 16U)

#define XDMAC_XDMAC_GTYPE_FIFO_SZ(x)        (((x) << 5U) & GENMASK(15U, 5U))
#define XDMAC_XDMAC_GTYPE_FIFO_SZ_M         GENMASK(15U, 5U)
#define XDMAC_XDMAC_GTYPE_FIFO_SZ_X(x)      (((x) & GENMASK(15U, 5U)) >> 5U)

#define XDMAC_XDMAC_GTYPE_NB_CH(x)          ((x) & GENMASK(4U, 0U))
#define XDMAC_XDMAC_GTYPE_NB_CH_M           GENMASK(4U, 0U)
#define XDMAC_XDMAC_GTYPE_NB_CH_X(x)        ((x) & GENMASK(4U, 0U))

/*      XDMAC:XDMAC_REG:XDMAC_GIE */
#define XDMAC_XDMAC_GIE(t)        ((t) + 0x0cU)

#define XDMAC_XDMAC_GIE_IEX(x)              ((x) & GENMASK(15U, 0U))
#define XDMAC_XDMAC_GIE_IEX_M               GENMASK(15U, 0U)
#define XDMAC_XDMAC_GIE_IEX_X(x)            ((x) & GENMASK(15U, 0U))

/*      XDMAC:XDMAC_REG:XDMAC_GE */
#define XDMAC_XDMAC_GE(t)         ((t) + 0x1cU)

#define XDMAC_XDMAC_GE_ENX(x)               ((x) & GENMASK(15U, 0U))
#define XDMAC_XDMAC_GE_ENX_M                GENMASK(15U, 0U)
#define XDMAC_XDMAC_GE_ENX_X(x)             ((x) & GENMASK(15U, 0U))

/*      XDMAC:XDMAC_REG:XDMAC_GD */
#define XDMAC_XDMAC_GD(t)         ((t) + 0x20U)

#define XDMAC_XDMAC_GD_DIX(x)               ((x) & GENMASK(15U, 0U))
#define XDMAC_XDMAC_GD_DIX_M                GENMASK(15U, 0U)
#define XDMAC_XDMAC_GD_DIX_X(x)             ((x) & GENMASK(15U, 0U))

/*      XDMAC:XDMAC_REG:XDMAC_GS */
#define XDMAC_XDMAC_GS(t)         ((t) + 0x24U)

#define XDMAC_XDMAC_GS_STX(x)               ((x) & GENMASK(15U, 0U))
#define XDMAC_XDMAC_GS_STX_M                GENMASK(15U, 0U)
#define XDMAC_XDMAC_GS_STX_X(x)             ((x) & GENMASK(15U, 0U))

/*      XDMAC:XDMAC_REG:XDMAC_CIE_CH0 */
#define XDMAC_XDMAC_CIE_CH0(t)    ((t) + 0x60U)

#define XDMAC_XDMAC_CIE_CH0_TCIE_CH0(x)     (((x) << 7U) & GENMASK(7U, 7U))
#define XDMAC_XDMAC_CIE_CH0_TCIE_CH0_M      GENMASK(7U, 7U)
#define XDMAC_XDMAC_CIE_CH0_TCIE_CH0_X(x)   (((x) & GENMASK(7U, 7U)) >> 7U)

#define XDMAC_XDMAC_CIE_CH0_ROIE_CH0(x)     (((x) << 6U) & GENMASK(6U, 6U))
#define XDMAC_XDMAC_CIE_CH0_ROIE_CH0_M      GENMASK(6U, 6U)
#define XDMAC_XDMAC_CIE_CH0_ROIE_CH0_X(x)   (((x) & GENMASK(6U, 6U)) >> 6U)

#define XDMAC_XDMAC_CIE_CH0_WBIE_CH0(x)     (((x) << 5U) & GENMASK(5U, 5U))
#define XDMAC_XDMAC_CIE_CH0_WBIE_CH0_M      GENMASK(5U, 5U)
#define XDMAC_XDMAC_CIE_CH0_WBIE_CH0_X(x)   (((x) & GENMASK(5U, 5U)) >> 5U)

#define XDMAC_XDMAC_CIE_CH0_RBIE_CH0(x)     (((x) << 4U) & GENMASK(4U, 4U))
#define XDMAC_XDMAC_CIE_CH0_RBIE_CH0_M      GENMASK(4U, 4U)
#define XDMAC_XDMAC_CIE_CH0_RBIE_CH0_X(x)   (((x) & GENMASK(4U, 4U)) >> 4U)

#define XDMAC_XDMAC_CIE_CH0_FIE_CH0(x)      (((x) << 3U) & GENMASK(3U, 3U))
#define XDMAC_XDMAC_CIE_CH0_FIE_CH0_M       GENMASK(3U, 3U)
#define XDMAC_XDMAC_CIE_CH0_FIE_CH0_X(x)    (((x) & GENMASK(3U, 3U)) >> 3U)

#define XDMAC_XDMAC_CIE_CH0_DIE_CH0(x)      (((x) << 2U) & GENMASK(2U, 2U))
#define XDMAC_XDMAC_CIE_CH0_DIE_CH0_M       GENMASK(2U, 2U)
#define XDMAC_XDMAC_CIE_CH0_DIE_CH0_X(x)    (((x) & GENMASK(2U, 2U)) >> 2U)

#define XDMAC_XDMAC_CIE_CH0_LIE_CH0(x)      (((x) << 1U) & GENMASK(1U, 1U))
#define XDMAC_XDMAC_CIE_CH0_LIE_CH0_M       GENMASK(1U, 1U)
#define XDMAC_XDMAC_CIE_CH0_LIE_CH0_X(x)    (((x) & GENMASK(1U, 1U)) >> 1U)

#define XDMAC_XDMAC_CIE_CH0_BIE_CH0(x)      ((x) & GENMASK(0U, 0U))
#define XDMAC_XDMAC_CIE_CH0_BIE_CH0_M       GENMASK(0U, 0U)
#define XDMAC_XDMAC_CIE_CH0_BIE_CH0_X(x)    ((x) & GENMASK(0U, 0U))

/*      XDMAC:XDMAC_REG:XDMAC_CID_CH0 */
#define XDMAC_XDMAC_CID_CH0(t)    ((t) + 0x64U)

#define XDMAC_XDMAC_CID_CH0_TCID_CH0(x)     (((x) << 7U) & GENMASK(7U, 7U))
#define XDMAC_XDMAC_CID_CH0_TCID_CH0_M      GENMASK(7U, 7U)
#define XDMAC_XDMAC_CID_CH0_TCID_CH0_X(x)   (((x) & GENMASK(7U, 7U)) >> 7U)

#define XDMAC_XDMAC_CID_CH0_ROID_CH0(x)     (((x) << 6U) & GENMASK(6U, 6U))
#define XDMAC_XDMAC_CID_CH0_ROID_CH0_M      GENMASK(6U, 6U)
#define XDMAC_XDMAC_CID_CH0_ROID_CH0_X(x)   (((x) & GENMASK(6U, 6U)) >> 6U)

#define XDMAC_XDMAC_CID_CH0_WBEID_CH0(x)    (((x) << 5U) & GENMASK(5U, 5U))
#define XDMAC_XDMAC_CID_CH0_WBEID_CH0_M     GENMASK(5U, 5U)
#define XDMAC_XDMAC_CID_CH0_WBEID_CH0_X(x)  (((x) & GENMASK(5U, 5U)) >> 5U)

#define XDMAC_XDMAC_CID_CH0_RBEID_CH0(x)    (((x) << 4U) & GENMASK(4U, 4U))
#define XDMAC_XDMAC_CID_CH0_RBEID_CH0_M     GENMASK(4U, 4U)
#define XDMAC_XDMAC_CID_CH0_RBEID_CH0_X(x)  (((x) & GENMASK(4U, 4U)) >> 4U)

#define XDMAC_XDMAC_CID_CH0_FID_CH0(x)      (((x) << 3U) & GENMASK(3U, 3U))
#define XDMAC_XDMAC_CID_CH0_FID_CH0_M       GENMASK(3U, 3U)
#define XDMAC_XDMAC_CID_CH0_FID_CH0_X(x)    (((x) & GENMASK(3U, 3U)) >> 3U)

#define XDMAC_XDMAC_CID_CH0_DID_CH0(x)      (((x) << 2U) & GENMASK(2U, 2U))
#define XDMAC_XDMAC_CID_CH0_DID_CH0_M       GENMASK(2U, 2U)
#define XDMAC_XDMAC_CID_CH0_DID_CH0_X(x)    (((x) & GENMASK(2U, 2U)) >> 2U)

#define XDMAC_XDMAC_CID_CH0_LID_CH0(x)      (((x) << 1U) & GENMASK(1U, 1U))
#define XDMAC_XDMAC_CID_CH0_LID_CH0_M       GENMASK(1U, 1U)
#define XDMAC_XDMAC_CID_CH0_LID_CH0_X(x)    (((x) & GENMASK(1U, 1U)) >> 1U)

#define XDMAC_XDMAC_CID_CH0_BID_CH0(x)      ((x) & GENMASK(0U, 0U))
#define XDMAC_XDMAC_CID_CH0_BID_CH0_M       GENMASK(0U, 0U)
#define XDMAC_XDMAC_CID_CH0_BID_CH0_X(x)    ((x) & GENMASK(0U, 0U))

/*      XDMAC:XDMAC_REG:XDMAC_CIM_CH0 */
#define XDMAC_XDMAC_CIM_CH0(t)    ((t) + 0x68U)

#define XDMAC_XDMAC_CIM_CH0_TCIM_CH0(x)     (((x) << 7U) & GENMASK(7U, 7U))
#define XDMAC_XDMAC_CIM_CH0_TCIM_CH0_M      GENMASK(7U, 7U)
#define XDMAC_XDMAC_CIM_CH0_TCIM_CH0_X(x)   (((x) & GENMASK(7U, 7U)) >> 7U)

#define XDMAC_XDMAC_CIM_CH0_ROIM_CH0(x)     (((x) << 6U) & GENMASK(6U, 6U))
#define XDMAC_XDMAC_CIM_CH0_ROIM_CH0_M      GENMASK(6U, 6U)
#define XDMAC_XDMAC_CIM_CH0_ROIM_CH0_X(x)   (((x) & GENMASK(6U, 6U)) >> 6U)

#define XDMAC_XDMAC_CIM_CH0_WBEIM_CH0(x)    (((x) << 5U) & GENMASK(5U, 5U))
#define XDMAC_XDMAC_CIM_CH0_WBEIM_CH0_M     GENMASK(5U, 5U)
#define XDMAC_XDMAC_CIM_CH0_WBEIM_CH0_X(x)  (((x) & GENMASK(5U, 5U)) >> 5U)

#define XDMAC_XDMAC_CIM_CH0_RBEIM_CH0(x)    (((x) << 4U) & GENMASK(4U, 4U))
#define XDMAC_XDMAC_CIM_CH0_RBEIM_CH0_M     GENMASK(4U, 4U)
#define XDMAC_XDMAC_CIM_CH0_RBEIM_CH0_X(x)  (((x) & GENMASK(4U, 4U)) >> 4U)

#define XDMAC_XDMAC_CIM_CH0_FIM_CH0(x)      (((x) << 3U) & GENMASK(3U, 3U))
#define XDMAC_XDMAC_CIM_CH0_FIM_CH0_M       GENMASK(3U, 3U)
#define XDMAC_XDMAC_CIM_CH0_FIM_CH0_X(x)    (((x) & GENMASK(3U, 3U)) >> 3U)

#define XDMAC_XDMAC_CIM_CH0_DIM_CH0(x)      (((x) << 2U) & GENMASK(2U, 2U))
#define XDMAC_XDMAC_CIM_CH0_DIM_CH0_M       GENMASK(2U, 2U)
#define XDMAC_XDMAC_CIM_CH0_DIM_CH0_X(x)    (((x) & GENMASK(2U, 2U)) >> 2U)

#define XDMAC_XDMAC_CIM_CH0_LIM_CH0(x)      (((x) << 1U) & GENMASK(1U, 1U))
#define XDMAC_XDMAC_CIM_CH0_LIM_CH0_M       GENMASK(1U, 1U)
#define XDMAC_XDMAC_CIM_CH0_LIM_CH0_X(x)    (((x) & GENMASK(1U, 1U)) >> 1U)

#define XDMAC_XDMAC_CIM_CH0_BIM_CH0(x)      ((x) & GENMASK(0U, 0U))
#define XDMAC_XDMAC_CIM_CH0_BIM_CH0_M       GENMASK(0U, 0U)
#define XDMAC_XDMAC_CIM_CH0_BIM_CH0_X(x)    ((x) & GENMASK(0U, 0U))

/*      XDMAC:XDMAC_REG:XDMAC_CIS_CH0 */
#define XDMAC_XDMAC_CIS_CH0(t)    ((t) + 0x6cU)

#define XDMAC_XDMAC_CIS_CH0_TCIS_CH0(x)     (((x) << 7U) & GENMASK(7U, 7U))
#define XDMAC_XDMAC_CIS_CH0_TCIS_CH0_M      GENMASK(7U, 7U)
#define XDMAC_XDMAC_CIS_CH0_TCIS_CH0_X(x)   (((x) & GENMASK(7U, 7U)) >> 7U)

#define XDMAC_XDMAC_CIS_CH0_ROIS_CH0(x)     (((x) << 6U) & GENMASK(6U, 6U))
#define XDMAC_XDMAC_CIS_CH0_ROIS_CH0_M      GENMASK(6U, 6U)
#define XDMAC_XDMAC_CIS_CH0_ROIS_CH0_X(x)   (((x) & GENMASK(6U, 6U)) >> 6U)

#define XDMAC_XDMAC_CIS_CH0_WBEIS_CH0(x)    (((x) << 5U) & GENMASK(5U, 5U))
#define XDMAC_XDMAC_CIS_CH0_WBEIS_CH0_M     GENMASK(5U, 5U)
#define XDMAC_XDMAC_CIS_CH0_WBEIS_CH0_X(x)  (((x) & GENMASK(5U, 5U)) >> 5U)

#define XDMAC_XDMAC_CIS_CH0_RBEIS_CH0(x)    (((x) << 4U) & GENMASK(4U, 4U))
#define XDMAC_XDMAC_CIS_CH0_RBEIS_CH0_M     GENMASK(4U, 4U)
#define XDMAC_XDMAC_CIS_CH0_RBEIS_CH0_X(x)  (((x) & GENMASK(4U, 4U)) >> 4U)

#define XDMAC_XDMAC_CIS_CH0_FIS_CH0(x)      (((x) << 3U) & GENMASK(3U, 3U))
#define XDMAC_XDMAC_CIS_CH0_FIS_CH0_M       GENMASK(3U, 3U)
#define XDMAC_XDMAC_CIS_CH0_FIS_CH0_X(x)    (((x) & GENMASK(3U, 3U)) >> 3U)

#define XDMAC_XDMAC_CIS_CH0_DIS_CH0(x)      (((x) << 2U) & GENMASK(2U, 2U))
#define XDMAC_XDMAC_CIS_CH0_DIS_CH0_M       GENMASK(2U, 2U)
#define XDMAC_XDMAC_CIS_CH0_DIS_CH0_X(x)    (((x) & GENMASK(2U, 2U)) >> 2U)

#define XDMAC_XDMAC_CIS_CH0_LIS_CH0(x)      (((x) << 1U) & GENMASK(1U, 1U))
#define XDMAC_XDMAC_CIS_CH0_LIS_CH0_M       GENMASK(1U, 1U)
#define XDMAC_XDMAC_CIS_CH0_LIS_CH0_X(x)    (((x) & GENMASK(1U, 1U)) >> 1U)

#define XDMAC_XDMAC_CIS_CH0_BIS_CH0(x)      ((x) & GENMASK(0U, 0U))
#define XDMAC_XDMAC_CIS_CH0_BIS_CH0_M       GENMASK(0U, 0U)
#define XDMAC_XDMAC_CIS_CH0_BIS_CH0_X(x)    ((x) & GENMASK(0U, 0U))

/*      XDMAC:XDMAC_REG:XDMAC_CSA_CH0 */
#define XDMAC_XDMAC_CSA_CH0(t)    ((t) + 0x70U)

/*      XDMAC:XDMAC_REG:XDMAC_CDA_CH0 */
#define XDMAC_XDMAC_CDA_CH0(t)    ((t) + 0x74U)

/*      XDMAC:XDMAC_REG:XDMAC_CNDA_CH0 */
#define XDMAC_XDMAC_CNDA_CH0(t)   ((t) + 0x78U)

#define XDMAC_XDMAC_CNDA_CH0_NDA_CH0(x)     (((x) << 2U) & GENMASK(31U, 2U))
#define XDMAC_XDMAC_CNDA_CH0_NDA_CH0_M      GENMASK(31U, 2U)
#define XDMAC_XDMAC_CNDA_CH0_NDA_CH0_X(x)   (((x) & GENMASK(31U, 2U)) >> 2U)

/*      XDMAC:XDMAC_REG:XDMAC_CNDC_CH0 */
#define XDMAC_XDMAC_CNDC_CH0(t)   ((t) + 0x7cU)

#define XDMAC_XDMAC_CNDC_CH0_QOS_CH0(x)     (((x) << 5U) & GENMASK(6U, 5U))
#define XDMAC_XDMAC_CNDC_CH0_QOS_CH0_M      GENMASK(6U, 5U)
#define XDMAC_XDMAC_CNDC_CH0_QOS_CH0_X(x)   (((x) & GENMASK(6U, 5U)) >> 5U)

#define XDMAC_XDMAC_CNDC_CH0_NDVIEW_CH0(x)  (((x) << 3U) & GENMASK(4U, 3U))
#define XDMAC_XDMAC_CNDC_CH0_NDVIEW_CH0_M   GENMASK(4U, 3U)
#define XDMAC_XDMAC_CNDC_CH0_NDVIEW_CH0_X(x) (((x) & GENMASK(4U, 3U)) >> 3U)

#define XDMAC_XDMAC_CNDC_CH0_NDDUP_CH0(x)   (((x) << 2U) & GENMASK(2U, 2U))
#define XDMAC_XDMAC_CNDC_CH0_NDDUP_CH0_M    GENMASK(2U, 2U)
#define XDMAC_XDMAC_CNDC_CH0_NDDUP_CH0_X(x) (((x) & GENMASK(2U, 2U)) >> 2U)

#define XDMAC_XDMAC_CNDC_CH0_NDSUP_CH0(x)   (((x) << 1U) & GENMASK(1U, 1U))
#define XDMAC_XDMAC_CNDC_CH0_NDSUP_CH0_M    GENMASK(1U, 1U)
#define XDMAC_XDMAC_CNDC_CH0_NDSUP_CH0_X(x) (((x) & GENMASK(1U, 1U)) >> 1U)

#define XDMAC_XDMAC_CNDC_CH0_NDE_CH0(x)     ((x) & GENMASK(0U, 0U))
#define XDMAC_XDMAC_CNDC_CH0_NDE_CH0_M      GENMASK(0U, 0U)
#define XDMAC_XDMAC_CNDC_CH0_NDE_CH0_X(x)   ((x) & GENMASK(0U, 0U))

/*      XDMAC:XDMAC_REG:XDMAC_CUBC_CH0 */
#define XDMAC_XDMAC_CUBC_CH0(t)   ((t) + 0x80U)

#define XDMAC_XDMAC_CUBC_CH0_UBLEN_CH0(x)   ((x) & GENMASK(23U, 0U))
#define XDMAC_XDMAC_CUBC_CH0_UBLEN_CH0_M    GENMASK(23U, 0U)
#define XDMAC_XDMAC_CUBC_CH0_UBLEN_CH0_X(x) ((x) & GENMASK(23U, 0U))

/*      XDMAC:XDMAC_REG:XDMAC_CBC_CH0 */
#define XDMAC_XDMAC_CBC_CH0(t)    ((t) + 0x84U)

#define XDMAC_XDMAC_CBC_CH0_BLEN_CH0(x)     ((x) & GENMASK(11U, 0U))
#define XDMAC_XDMAC_CBC_CH0_BLEN_CH0_M      GENMASK(11U, 0U)
#define XDMAC_XDMAC_CBC_CH0_BLEN_CH0_X(x)   ((x) & GENMASK(11U, 0U))

/*      XDMAC:XDMAC_REG:XDMAC_CC_CH0 */
#define XDMAC_XDMAC_CC_CH0(t)     ((t) + 0x88U)

#define XDMAC_XDMAC_CC_CH0_PERID_CH0(x)     (((x) << 24U) & GENMASK(30U, 24U))
#define XDMAC_XDMAC_CC_CH0_PERID_CH0_M      GENMASK(30U, 24U)
#define XDMAC_XDMAC_CC_CH0_PERID_CH0_X(x)   (((x) & GENMASK(30U, 24U)) >> 24U)

#define XDMAC_XDMAC_CC_CH0_WRIP_CH0(x)      (((x) << 23U) & GENMASK(23U, 23U))
#define XDMAC_XDMAC_CC_CH0_WRIP_CH0_M       GENMASK(23U, 23U)
#define XDMAC_XDMAC_CC_CH0_WRIP_CH0_X(x)    (((x) & GENMASK(23U, 23U)) >> 23U)

#define XDMAC_XDMAC_CC_CH0_RDIP_CH0(x)      (((x) << 22U) & GENMASK(22U, 22U))
#define XDMAC_XDMAC_CC_CH0_RDIP_CH0_M       GENMASK(22U, 22U)
#define XDMAC_XDMAC_CC_CH0_RDIP_CH0_X(x)    (((x) & GENMASK(22U, 22U)) >> 22U)

#define XDMAC_XDMAC_CC_CH0_INITD_CH0(x)     (((x) << 21U) & GENMASK(21U, 21U))
#define XDMAC_XDMAC_CC_CH0_INITD_CH0_M      GENMASK(21U, 21U)
#define XDMAC_XDMAC_CC_CH0_INITD_CH0_X(x)   (((x) & GENMASK(21U, 21U)) >> 21U)

#define XDMAC_XDMAC_CC_CH0_DAM_CH0(x)       (((x) << 18U) & GENMASK(19U, 18U))
#define XDMAC_XDMAC_CC_CH0_DAM_CH0_M        GENMASK(19U, 18U)
#define XDMAC_XDMAC_CC_CH0_DAM_CH0_X(x)     (((x) & GENMASK(19U, 18U)) >> 18U)

#define XDMAC_XDMAC_CC_CH0_SAM_CH0(x)       (((x) << 16U) & GENMASK(17U, 16U))
#define XDMAC_XDMAC_CC_CH0_SAM_CH0_M        GENMASK(17U, 16U)
#define XDMAC_XDMAC_CC_CH0_SAM_CH0_X(x)     (((x) & GENMASK(17U, 16U)) >> 16U)

#define XDMAC_XDMAC_CC_CH0_DWIDTH_CH0(x)    (((x) << 11U) & GENMASK(12U, 11U))
#define XDMAC_XDMAC_CC_CH0_DWIDTH_CH0_M     GENMASK(12U, 11U)
#define XDMAC_XDMAC_CC_CH0_DWIDTH_CH0_X(x)  (((x) & GENMASK(12U, 11U)) >> 11U)

#define XDMAC_XDMAC_CC_CH0_CSIZE_CH0(x)     (((x) << 8U) & GENMASK(10U, 8U))
#define XDMAC_XDMAC_CC_CH0_CSIZE_CH0_M      GENMASK(10U, 8U)
#define XDMAC_XDMAC_CC_CH0_CSIZE_CH0_X(x)   (((x) & GENMASK(10U, 8U)) >> 8U)

#define XDMAC_XDMAC_CC_CH0_MEMSET_CH0(x)    (((x) << 7U) & GENMASK(7U, 7U))
#define XDMAC_XDMAC_CC_CH0_MEMSET_CH0_M     GENMASK(7U, 7U)
#define XDMAC_XDMAC_CC_CH0_MEMSET_CH0_X(x)  (((x) & GENMASK(7U, 7U)) >> 7U)

#define XDMAC_XDMAC_CC_CH0_SWREQ_CH0(x)     (((x) << 6U) & GENMASK(6U, 6U))
#define XDMAC_XDMAC_CC_CH0_SWREQ_CH0_M      GENMASK(6U, 6U)
#define XDMAC_XDMAC_CC_CH0_SWREQ_CH0_X(x)   (((x) & GENMASK(6U, 6U)) >> 6U)

#define XDMAC_XDMAC_CC_CH0_PROT_CH0(x)      (((x) << 5U) & GENMASK(5U, 5U))
#define XDMAC_XDMAC_CC_CH0_PROT_CH0_M       GENMASK(5U, 5U)
#define XDMAC_XDMAC_CC_CH0_PROT_CH0_X(x)    (((x) & GENMASK(5U, 5U)) >> 5U)

#define XDMAC_XDMAC_CC_CH0_DSYNC_CH0(x)     (((x) << 4U) & GENMASK(4U, 4U))
#define XDMAC_XDMAC_CC_CH0_DSYNC_CH0_M      GENMASK(4U, 4U)
#define XDMAC_XDMAC_CC_CH0_DSYNC_CH0_X(x)   (((x) & GENMASK(4U, 4U)) >> 4U)

#define XDMAC_XDMAC_CC_CH0_MBSIZE_CH0(x)    (((x) << 1U) & GENMASK(2U, 1U))
#define XDMAC_XDMAC_CC_CH0_MBSIZE_CH0_M     GENMASK(2U, 1U)
#define XDMAC_XDMAC_CC_CH0_MBSIZE_CH0_X(x)  (((x) & GENMASK(2U, 1U)) >> 1U)

#define XDMAC_XDMAC_CC_CH0_TYPE_CH0(x)      ((x) & GENMASK(0U, 0U))
#define XDMAC_XDMAC_CC_CH0_TYPE_CH0_M       GENMASK(0U, 0U)
#define XDMAC_XDMAC_CC_CH0_TYPE_CH0_X(x)    ((x) & GENMASK(0U, 0U))

/*      XDMAC:XDMAC_REG:XDMAC_CDS_MSP_CH0 */
#define XDMAC_XDMAC_CDS_MSP_CH0(t) ((t) + 0x8cU)

#define XDMAC_XDMAC_CDS_MSP_CH0_DDS_MSP_CH0(x)\
	(((x) << 16U) & GENMASK(31U, 16U))
#define XDMAC_XDMAC_CDS_MSP_CH0_DDS_MSP_CH0_M GENMASK(31U, 16U)
#define XDMAC_XDMAC_CDS_MSP_CH0_DDS_MSP_CH0_X(x)\
	(((x) & GENMASK(31U, 16U)) >> 16U)

#define XDMAC_XDMAC_CDS_MSP_CH0_SDS_MSP_CH0(x) ((x) & GENMASK(15U, 0U))
#define XDMAC_XDMAC_CDS_MSP_CH0_SDS_MSP_CH0_M GENMASK(15U, 0U)
#define XDMAC_XDMAC_CDS_MSP_CH0_SDS_MSP_CH0_X(x) ((x) & GENMASK(15U, 0U))

/*      XDMAC:XDMAC_REG:XDMAC_CSUS_CH0 */
#define XDMAC_XDMAC_CSUS_CH0(t)   ((t) + 0x90U)

#define XDMAC_XDMAC_CSUS_CH0_SUBS_CH0(x)    ((x) & GENMASK(23U, 0U))
#define XDMAC_XDMAC_CSUS_CH0_SUBS_CH0_M     GENMASK(23U, 0U)
#define XDMAC_XDMAC_CSUS_CH0_SUBS_CH0_X(x)  ((x) & GENMASK(23U, 0U))

/*      XDMAC:XDMAC_REG:XDMAC_CDUS_CH0 */
#define XDMAC_XDMAC_CDUS_CH0(t)   ((t) + 0x94U)

#define XDMAC_XDMAC_CDUS_CH0_DUBS_CH0(x)    ((x) & GENMASK(23U, 0U))
#define XDMAC_XDMAC_CDUS_CH0_DUBS_CH0_M     GENMASK(23U, 0U)
#define XDMAC_XDMAC_CDUS_CH0_DUBS_CH0_X(x)  ((x) & GENMASK(23U, 0U))

/*      XDMAC:XDMAC_REG:XDMAC_CTCS_CH0 */
#define XDMAC_XDMAC_CTCS_CH0(t)   ((t) + 0x98U)

#define XDMAC_XDMAC_CTCS_CH0_TC_CH0(x)      ((x) & GENMASK(23U, 0U))
#define XDMAC_XDMAC_CTCS_CH0_TC_CH0_M       GENMASK(23U, 0U)
#define XDMAC_XDMAC_CTCS_CH0_TC_CH0_X(x)    ((x) & GENMASK(23U, 0U))

/*      XDMAC:XDMAC_REG:XDMAC_CIE_CH1 */
#define XDMAC_XDMAC_CIE_CH1(t)    ((t) + 0xa0U)

#define XDMAC_XDMAC_CIE_CH1_TCIE_CH1(x)     (((x) << 7U) & GENMASK(7U, 7U))
#define XDMAC_XDMAC_CIE_CH1_TCIE_CH1_M      GENMASK(7U, 7U)
#define XDMAC_XDMAC_CIE_CH1_TCIE_CH1_X(x)   (((x) & GENMASK(7U, 7U)) >> 7U)

#define XDMAC_XDMAC_CIE_CH1_ROIE_CH1(x)     (((x) << 6U) & GENMASK(6U, 6U))
#define XDMAC_XDMAC_CIE_CH1_ROIE_CH1_M      GENMASK(6U, 6U)
#define XDMAC_XDMAC_CIE_CH1_ROIE_CH1_X(x)   (((x) & GENMASK(6U, 6U)) >> 6U)

#define XDMAC_XDMAC_CIE_CH1_WBIE_CH1(x)     (((x) << 5U) & GENMASK(5U, 5U))
#define XDMAC_XDMAC_CIE_CH1_WBIE_CH1_M      GENMASK(5U, 5U)
#define XDMAC_XDMAC_CIE_CH1_WBIE_CH1_X(x)   (((x) & GENMASK(5U, 5U)) >> 5U)

#define XDMAC_XDMAC_CIE_CH1_RBIE_CH1(x)     (((x) << 4U) & GENMASK(4U, 4U))
#define XDMAC_XDMAC_CIE_CH1_RBIE_CH1_M      GENMASK(4U, 4U)
#define XDMAC_XDMAC_CIE_CH1_RBIE_CH1_X(x)   (((x) & GENMASK(4U, 4U)) >> 4U)

#define XDMAC_XDMAC_CIE_CH1_FIE_CH1(x)      (((x) << 3U) & GENMASK(3U, 3U))
#define XDMAC_XDMAC_CIE_CH1_FIE_CH1_M       GENMASK(3U, 3U)
#define XDMAC_XDMAC_CIE_CH1_FIE_CH1_X(x)    (((x) & GENMASK(3U, 3U)) >> 3U)

#define XDMAC_XDMAC_CIE_CH1_DIE_CH1(x)      (((x) << 2U) & GENMASK(2U, 2U))
#define XDMAC_XDMAC_CIE_CH1_DIE_CH1_M       GENMASK(2U, 2U)
#define XDMAC_XDMAC_CIE_CH1_DIE_CH1_X(x)    (((x) & GENMASK(2U, 2U)) >> 2U)

#define XDMAC_XDMAC_CIE_CH1_LIE_CH1(x)      (((x) << 1U) & GENMASK(1U, 1U))
#define XDMAC_XDMAC_CIE_CH1_LIE_CH1_M       GENMASK(1U, 1U)
#define XDMAC_XDMAC_CIE_CH1_LIE_CH1_X(x)    (((x) & GENMASK(1U, 1U)) >> 1U)

#define XDMAC_XDMAC_CIE_CH1_BIE_CH1(x)      ((x) & GENMASK(0U, 0U))
#define XDMAC_XDMAC_CIE_CH1_BIE_CH1_M       GENMASK(0U, 0U)
#define XDMAC_XDMAC_CIE_CH1_BIE_CH1_X(x)    ((x) & GENMASK(0U, 0U))

/*      XDMAC:XDMAC_REG:XDMAC_VERSION */
#define XDMAC_XDMAC_VERSION(t)    ((t) + 0xffcU)

#define XDMAC_XDMAC_VERSION_MFN(x)          (((x) << 16U) & GENMASK(18U, 16U))
#define XDMAC_XDMAC_VERSION_MFN_M           GENMASK(18U, 16U)
#define XDMAC_XDMAC_VERSION_MFN_X(x)        (((x) & GENMASK(18U, 16U)) >> 16U)

#define XDMAC_XDMAC_VERSION_VERSION(x)      ((x) & GENMASK(11U, 0U))
#define XDMAC_XDMAC_VERSION_VERSION_M       GENMASK(11U, 0U)
#define XDMAC_XDMAC_VERSION_VERSION_X(x)    ((x) & GENMASK(11U, 0U))


#endif /* LAN969X_REGS_A0_H */
