/*
 * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

/* This file is autogenerated by cml-utils 2024-01-10 14:33:37 +0100.
 * Commit ID: d1847eb3ea788e03ee92a1a26093c56981504365
 */

/* LAN966X registers */

#ifndef _LAN966X_REGS_SR_H_
#define _LAN966X_REGS_SR_H_

/*      AES:AES_REGS:AES_CR */
#define AES_AES_CR(t)             (t + 0x00)

#define AES_AES_CR_UNLOCK(x)                     (((x) << 24) & GENMASK(24, 24))
#define AES_AES_CR_UNLOCK_M                      GENMASK(24, 24)
#define AES_AES_CR_UNLOCK_X(x)                   (((x) & GENMASK(24, 24)) >> 24)

#define AES_AES_CR_LOADSEED(x)                   (((x) << 16) & GENMASK(16, 16))
#define AES_AES_CR_LOADSEED_M                    GENMASK(16, 16)
#define AES_AES_CR_LOADSEED_X(x)                 (((x) & GENMASK(16, 16)) >> 16)

#define AES_AES_CR_SWRST(x)                      (((x) << 8) & GENMASK(8, 8))
#define AES_AES_CR_SWRST_M                       GENMASK(8, 8)
#define AES_AES_CR_SWRST_X(x)                    (((x) & GENMASK(8, 8)) >> 8)

#define AES_AES_CR_KSWP(x)                       (((x) << 1) & GENMASK(1, 1))
#define AES_AES_CR_KSWP_M                        GENMASK(1, 1)
#define AES_AES_CR_KSWP_X(x)                     (((x) & GENMASK(1, 1)) >> 1)

#define AES_AES_CR_START(x)                      ((x) & GENMASK(0, 0))
#define AES_AES_CR_START_M                       GENMASK(0, 0)
#define AES_AES_CR_START_X(x)                    ((x) & GENMASK(0, 0))

/*      AES:AES_REGS:AES_MR */
#define AES_AES_MR(t)             (t + 0x04)

#define AES_AES_MR_TAMPCLR(x)                    (((x) << 31) & GENMASK(31, 31))
#define AES_AES_MR_TAMPCLR_M                     GENMASK(31, 31)
#define AES_AES_MR_TAMPCLR_X(x)                  (((x) & GENMASK(31, 31)) >> 31)

#define AES_AES_MR_CMTYP7(x)                     (((x) << 30) & GENMASK(30, 30))
#define AES_AES_MR_CMTYP7_M                      GENMASK(30, 30)
#define AES_AES_MR_CMTYP7_X(x)                   (((x) & GENMASK(30, 30)) >> 30)

#define AES_AES_MR_CMTYP6(x)                     (((x) << 29) & GENMASK(29, 29))
#define AES_AES_MR_CMTYP6_M                      GENMASK(29, 29)
#define AES_AES_MR_CMTYP6_X(x)                   (((x) & GENMASK(29, 29)) >> 29)

#define AES_AES_MR_CMTYP5(x)                     (((x) << 28) & GENMASK(28, 28))
#define AES_AES_MR_CMTYP5_M                      GENMASK(28, 28)
#define AES_AES_MR_CMTYP5_X(x)                   (((x) & GENMASK(28, 28)) >> 28)

#define AES_AES_MR_CMTYP4(x)                     (((x) << 27) & GENMASK(27, 27))
#define AES_AES_MR_CMTYP4_M                      GENMASK(27, 27)
#define AES_AES_MR_CMTYP4_X(x)                   (((x) & GENMASK(27, 27)) >> 27)

#define AES_AES_MR_CMTYP3(x)                     (((x) << 26) & GENMASK(26, 26))
#define AES_AES_MR_CMTYP3_M                      GENMASK(26, 26)
#define AES_AES_MR_CMTYP3_X(x)                   (((x) & GENMASK(26, 26)) >> 26)

#define AES_AES_MR_CMTYP2(x)                     (((x) << 25) & GENMASK(25, 25))
#define AES_AES_MR_CMTYP2_M                      GENMASK(25, 25)
#define AES_AES_MR_CMTYP2_X(x)                   (((x) & GENMASK(25, 25)) >> 25)

#define AES_AES_MR_CMTYP1(x)                     (((x) << 24) & GENMASK(24, 24))
#define AES_AES_MR_CMTYP1_M                      GENMASK(24, 24)
#define AES_AES_MR_CMTYP1_X(x)                   (((x) & GENMASK(24, 24)) >> 24)

#define AES_AES_MR_CKEY(x)                       (((x) << 20) & GENMASK(23, 20))
#define AES_AES_MR_CKEY_M                        GENMASK(23, 20)
#define AES_AES_MR_CKEY_X(x)                     (((x) & GENMASK(23, 20)) >> 20)

#define AES_AES_MR_CFBS(x)                       (((x) << 16) & GENMASK(18, 16))
#define AES_AES_MR_CFBS_M                        GENMASK(18, 16)
#define AES_AES_MR_CFBS_X(x)                     (((x) & GENMASK(18, 16)) >> 16)

#define AES_AES_MR_LOD(x)                        (((x) << 15) & GENMASK(15, 15))
#define AES_AES_MR_LOD_M                         GENMASK(15, 15)
#define AES_AES_MR_LOD_X(x)                      (((x) & GENMASK(15, 15)) >> 15)

#define AES_AES_MR_OPMOD(x)                      (((x) << 12) & GENMASK(14, 12))
#define AES_AES_MR_OPMOD_M                       GENMASK(14, 12)
#define AES_AES_MR_OPMOD_X(x)                    (((x) & GENMASK(14, 12)) >> 12)

#define AES_AES_MR_KEYSIZE(x)                    (((x) << 10) & GENMASK(11, 10))
#define AES_AES_MR_KEYSIZE_M                     GENMASK(11, 10)
#define AES_AES_MR_KEYSIZE_X(x)                  (((x) & GENMASK(11, 10)) >> 10)

#define AES_AES_MR_SMOD(x)                       (((x) << 8) & GENMASK(9, 8))
#define AES_AES_MR_SMOD_M                        GENMASK(9, 8)
#define AES_AES_MR_SMOD_X(x)                     (((x) & GENMASK(9, 8)) >> 8)

#define AES_AES_MR_PROCDLY(x)                    (((x) << 4) & GENMASK(7, 4))
#define AES_AES_MR_PROCDLY_M                     GENMASK(7, 4)
#define AES_AES_MR_PROCDLY_X(x)                  (((x) & GENMASK(7, 4)) >> 4)

#define AES_AES_MR_DUALBUFF(x)                   (((x) << 3) & GENMASK(3, 3))
#define AES_AES_MR_DUALBUFF_M                    GENMASK(3, 3)
#define AES_AES_MR_DUALBUFF_X(x)                 (((x) & GENMASK(3, 3)) >> 3)

#define AES_AES_MR_GTAGEN(x)                     (((x) << 1) & GENMASK(1, 1))
#define AES_AES_MR_GTAGEN_M                      GENMASK(1, 1)
#define AES_AES_MR_GTAGEN_X(x)                   (((x) & GENMASK(1, 1)) >> 1)

#define AES_AES_MR_CIPHER(x)                     ((x) & GENMASK(0, 0))
#define AES_AES_MR_CIPHER_M                      GENMASK(0, 0)
#define AES_AES_MR_CIPHER_X(x)                   ((x) & GENMASK(0, 0))

/*      AES:AES_REGS:AES_IER */
#define AES_AES_IER(t)            (t + 0x10)

#define AES_AES_IER_SECE(x)                      (((x) << 19) & GENMASK(19, 19))
#define AES_AES_IER_SECE_M                       GENMASK(19, 19)
#define AES_AES_IER_SECE_X(x)                    (((x) & GENMASK(19, 19)) >> 19)

#define AES_AES_IER_PLENERR(x)                   (((x) << 18) & GENMASK(18, 18))
#define AES_AES_IER_PLENERR_M                    GENMASK(18, 18)
#define AES_AES_IER_PLENERR_X(x)                 (((x) & GENMASK(18, 18)) >> 18)

#define AES_AES_IER_EOPAD(x)                     (((x) << 17) & GENMASK(17, 17))
#define AES_AES_IER_EOPAD_M                      GENMASK(17, 17)
#define AES_AES_IER_EOPAD_X(x)                   (((x) & GENMASK(17, 17)) >> 17)

#define AES_AES_IER_TAGRDY(x)                    (((x) << 16) & GENMASK(16, 16))
#define AES_AES_IER_TAGRDY_M                     GENMASK(16, 16)
#define AES_AES_IER_TAGRDY_X(x)                  (((x) & GENMASK(16, 16)) >> 16)

#define AES_AES_IER_URAD(x)                      (((x) << 8) & GENMASK(8, 8))
#define AES_AES_IER_URAD_M                       GENMASK(8, 8)
#define AES_AES_IER_URAD_X(x)                    (((x) & GENMASK(8, 8)) >> 8)

#define AES_AES_IER_DATRDY(x)                    ((x) & GENMASK(0, 0))
#define AES_AES_IER_DATRDY_M                     GENMASK(0, 0)
#define AES_AES_IER_DATRDY_X(x)                  ((x) & GENMASK(0, 0))

/*      AES:AES_REGS:AES_IDR */
#define AES_AES_IDR(t)            (t + 0x14)

#define AES_AES_IDR_SECE_IDR(x)                  (((x) << 19) & GENMASK(19, 19))
#define AES_AES_IDR_SECE_IDR_M                   GENMASK(19, 19)
#define AES_AES_IDR_SECE_IDR_X(x)                (((x) & GENMASK(19, 19)) >> 19)

#define AES_AES_IDR_PLENERR_IDR(x)               (((x) << 18) & GENMASK(18, 18))
#define AES_AES_IDR_PLENERR_IDR_M                GENMASK(18, 18)
#define AES_AES_IDR_PLENERR_IDR_X(x)             (((x) & GENMASK(18, 18)) >> 18)

#define AES_AES_IDR_EOPAD_IDR(x)                 (((x) << 17) & GENMASK(17, 17))
#define AES_AES_IDR_EOPAD_IDR_M                  GENMASK(17, 17)
#define AES_AES_IDR_EOPAD_IDR_X(x)               (((x) & GENMASK(17, 17)) >> 17)

#define AES_AES_IDR_TAGRDY_IDR(x)                (((x) << 16) & GENMASK(16, 16))
#define AES_AES_IDR_TAGRDY_IDR_M                 GENMASK(16, 16)
#define AES_AES_IDR_TAGRDY_IDR_X(x)              (((x) & GENMASK(16, 16)) >> 16)

#define AES_AES_IDR_URAD_IDR(x)                  (((x) << 8) & GENMASK(8, 8))
#define AES_AES_IDR_URAD_IDR_M                   GENMASK(8, 8)
#define AES_AES_IDR_URAD_IDR_X(x)                (((x) & GENMASK(8, 8)) >> 8)

#define AES_AES_IDR_DATRDY_IDR(x)                ((x) & GENMASK(0, 0))
#define AES_AES_IDR_DATRDY_IDR_M                 GENMASK(0, 0)
#define AES_AES_IDR_DATRDY_IDR_X(x)              ((x) & GENMASK(0, 0))

/*      AES:AES_REGS:AES_IMR */
#define AES_AES_IMR(t)            (t + 0x18)

#define AES_AES_IMR_SECE_IMR(x)                  (((x) << 19) & GENMASK(19, 19))
#define AES_AES_IMR_SECE_IMR_M                   GENMASK(19, 19)
#define AES_AES_IMR_SECE_IMR_X(x)                (((x) & GENMASK(19, 19)) >> 19)

#define AES_AES_IMR_PLENERR_IMR(x)               (((x) << 18) & GENMASK(18, 18))
#define AES_AES_IMR_PLENERR_IMR_M                GENMASK(18, 18)
#define AES_AES_IMR_PLENERR_IMR_X(x)             (((x) & GENMASK(18, 18)) >> 18)

#define AES_AES_IMR_EOPAD_IMR(x)                 (((x) << 17) & GENMASK(17, 17))
#define AES_AES_IMR_EOPAD_IMR_M                  GENMASK(17, 17)
#define AES_AES_IMR_EOPAD_IMR_X(x)               (((x) & GENMASK(17, 17)) >> 17)

#define AES_AES_IMR_TAGRDY_IMR(x)                (((x) << 16) & GENMASK(16, 16))
#define AES_AES_IMR_TAGRDY_IMR_M                 GENMASK(16, 16)
#define AES_AES_IMR_TAGRDY_IMR_X(x)              (((x) & GENMASK(16, 16)) >> 16)

#define AES_AES_IMR_URAD_IMR(x)                  (((x) << 8) & GENMASK(8, 8))
#define AES_AES_IMR_URAD_IMR_M                   GENMASK(8, 8)
#define AES_AES_IMR_URAD_IMR_X(x)                (((x) & GENMASK(8, 8)) >> 8)

#define AES_AES_IMR_DATRDY_IMR(x)                ((x) & GENMASK(0, 0))
#define AES_AES_IMR_DATRDY_IMR_M                 GENMASK(0, 0)
#define AES_AES_IMR_DATRDY_IMR_X(x)              ((x) & GENMASK(0, 0))

/*      AES:AES_REGS:AES_ISR */
#define AES_AES_ISR(t)            (t + 0x1c)

#define AES_AES_ISR_SECE_ISR(x)                  (((x) << 19) & GENMASK(19, 19))
#define AES_AES_ISR_SECE_ISR_M                   GENMASK(19, 19)
#define AES_AES_ISR_SECE_ISR_X(x)                (((x) & GENMASK(19, 19)) >> 19)

#define AES_AES_ISR_PLENERR_ISR(x)               (((x) << 18) & GENMASK(18, 18))
#define AES_AES_ISR_PLENERR_ISR_M                GENMASK(18, 18)
#define AES_AES_ISR_PLENERR_ISR_X(x)             (((x) & GENMASK(18, 18)) >> 18)

#define AES_AES_ISR_EOPAD_ISR(x)                 (((x) << 17) & GENMASK(17, 17))
#define AES_AES_ISR_EOPAD_ISR_M                  GENMASK(17, 17)
#define AES_AES_ISR_EOPAD_ISR_X(x)               (((x) & GENMASK(17, 17)) >> 17)

#define AES_AES_ISR_TAGRDY_ISR(x)                (((x) << 16) & GENMASK(16, 16))
#define AES_AES_ISR_TAGRDY_ISR_M                 GENMASK(16, 16)
#define AES_AES_ISR_TAGRDY_ISR_X(x)              (((x) & GENMASK(16, 16)) >> 16)

#define AES_AES_ISR_URAT_ISR(x)                  (((x) << 12) & GENMASK(15, 12))
#define AES_AES_ISR_URAT_ISR_M                   GENMASK(15, 12)
#define AES_AES_ISR_URAT_ISR_X(x)                (((x) & GENMASK(15, 12)) >> 12)

#define AES_AES_ISR_URAD_ISR(x)                  (((x) << 8) & GENMASK(8, 8))
#define AES_AES_ISR_URAD_ISR_M                   GENMASK(8, 8)
#define AES_AES_ISR_URAD_ISR_X(x)                (((x) & GENMASK(8, 8)) >> 8)

#define AES_AES_ISR_DATRDY_ISR(x)                ((x) & GENMASK(0, 0))
#define AES_AES_ISR_DATRDY_ISR_M                 GENMASK(0, 0)
#define AES_AES_ISR_DATRDY_ISR_X(x)              ((x) & GENMASK(0, 0))

/*      AES:AES_REGS:AES_KEYWR0 */
#define AES_AES_KEYWR0(t)         (t + 0x20)

/*      AES:AES_REGS:AES_KEYWR1 */
#define AES_AES_KEYWR1(t)         (t + 0x24)

/*      AES:AES_REGS:AES_KEYWR2 */
#define AES_AES_KEYWR2(t)         (t + 0x28)

/*      AES:AES_REGS:AES_KEYWR3 */
#define AES_AES_KEYWR3(t)         (t + 0x2c)

/*      AES:AES_REGS:AES_KEYWR4 */
#define AES_AES_KEYWR4(t)         (t + 0x30)

/*      AES:AES_REGS:AES_KEYWR5 */
#define AES_AES_KEYWR5(t)         (t + 0x34)

/*      AES:AES_REGS:AES_KEYWR6 */
#define AES_AES_KEYWR6(t)         (t + 0x38)

/*      AES:AES_REGS:AES_KEYWR7 */
#define AES_AES_KEYWR7(t)         (t + 0x3c)

/*      AES:AES_REGS:AES_IDATAR0 */
#define AES_AES_IDATAR0(t)        (t + 0x40)

/*      AES:AES_REGS:AES_IDATAR1 */
#define AES_AES_IDATAR1(t)        (t + 0x44)

/*      AES:AES_REGS:AES_IDATAR2 */
#define AES_AES_IDATAR2(t)        (t + 0x48)

/*      AES:AES_REGS:AES_IDATAR3 */
#define AES_AES_IDATAR3(t)        (t + 0x4c)

/*      AES:AES_REGS:AES_ODATAR0 */
#define AES_AES_ODATAR0(t)        (t + 0x50)

/*      AES:AES_REGS:AES_ODATAR1 */
#define AES_AES_ODATAR1(t)        (t + 0x54)

/*      AES:AES_REGS:AES_ODATAR2 */
#define AES_AES_ODATAR2(t)        (t + 0x58)

/*      AES:AES_REGS:AES_ODATAR3 */
#define AES_AES_ODATAR3(t)        (t + 0x5c)

/*      AES:AES_REGS:AES_IVR0 */
#define AES_AES_IVR0(t)           (t + 0x60)

/*      AES:AES_REGS:AES_IVR1 */
#define AES_AES_IVR1(t)           (t + 0x64)

/*      AES:AES_REGS:AES_IVR2 */
#define AES_AES_IVR2(t)           (t + 0x68)

/*      AES:AES_REGS:AES_IVR3 */
#define AES_AES_IVR3(t)           (t + 0x6c)

/*      AES:AES_REGS:AES_AADLENR */
#define AES_AES_AADLENR(t)        (t + 0x70)

/*      AES:AES_REGS:AES_CLENR */
#define AES_AES_CLENR(t)          (t + 0x74)

/*      AES:AES_REGS:AES_GHASHR0 */
#define AES_AES_GHASHR0(t)        (t + 0x78)

/*      AES:AES_REGS:AES_GHASHR1 */
#define AES_AES_GHASHR1(t)        (t + 0x7c)

/*      AES:AES_REGS:AES_GHASHR2 */
#define AES_AES_GHASHR2(t)        (t + 0x80)

/*      AES:AES_REGS:AES_GHASHR3 */
#define AES_AES_GHASHR3(t)        (t + 0x84)

/*      AES:AES_REGS:AES_TAGR0 */
#define AES_AES_TAGR0(t)          (t + 0x88)

/*      AES:AES_REGS:AES_TAGR1 */
#define AES_AES_TAGR1(t)          (t + 0x8c)

/*      AES:AES_REGS:AES_TAGR2 */
#define AES_AES_TAGR2(t)          (t + 0x90)

/*      AES:AES_REGS:AES_TAGR3 */
#define AES_AES_TAGR3(t)          (t + 0x94)

/*      AES:AES_REGS:AES_CTRR */
#define AES_AES_CTRR(t)           (t + 0x98)

/*      AES:AES_REGS:AES_GCMHR0 */
#define AES_AES_GCMHR0(t)         (t + 0x9c)

/*      AES:AES_REGS:AES_GCMHR1 */
#define AES_AES_GCMHR1(t)         (t + 0xa0)

/*      AES:AES_REGS:AES_GCMHR2 */
#define AES_AES_GCMHR2(t)         (t + 0xa4)

/*      AES:AES_REGS:AES_GCMHR3 */
#define AES_AES_GCMHR3(t)         (t + 0xa8)

/*      AES:AES_REGS:AES_EMR */
#define AES_AES_EMR(t)            (t + 0xb0)

#define AES_AES_EMR_BPE(x)                       (((x) << 31) & GENMASK(31, 31))
#define AES_AES_EMR_BPE_M                        GENMASK(31, 31)
#define AES_AES_EMR_BPE_X(x)                     (((x) & GENMASK(31, 31)) >> 31)

#define AES_AES_EMR_NHEAD(x)                     (((x) << 16) & GENMASK(23, 16))
#define AES_AES_EMR_NHEAD_M                      GENMASK(23, 16)
#define AES_AES_EMR_NHEAD_X(x)                   (((x) & GENMASK(23, 16)) >> 16)

#define AES_AES_EMR_PADLEN(x)                    (((x) << 8) & GENMASK(15, 8))
#define AES_AES_EMR_PADLEN_M                     GENMASK(15, 8)
#define AES_AES_EMR_PADLEN_X(x)                  (((x) & GENMASK(15, 8)) >> 8)

#define AES_AES_EMR_PKRS(x)                      (((x) << 7) & GENMASK(7, 7))
#define AES_AES_EMR_PKRS_M                       GENMASK(7, 7)
#define AES_AES_EMR_PKRS_X(x)                    (((x) & GENMASK(7, 7)) >> 7)

#define AES_AES_EMR_PKWL(x)                      (((x) << 6) & GENMASK(6, 6))
#define AES_AES_EMR_PKWL_M                       GENMASK(6, 6)
#define AES_AES_EMR_PKWL_X(x)                    (((x) & GENMASK(6, 6)) >> 6)

#define AES_AES_EMR_PLIPD(x)                     (((x) << 5) & GENMASK(5, 5))
#define AES_AES_EMR_PLIPD_M                      GENMASK(5, 5)
#define AES_AES_EMR_PLIPD_X(x)                   (((x) & GENMASK(5, 5)) >> 5)

#define AES_AES_EMR_PLIPEN(x)                    (((x) << 4) & GENMASK(4, 4))
#define AES_AES_EMR_PLIPEN_M                     GENMASK(4, 4)
#define AES_AES_EMR_PLIPEN_X(x)                  (((x) & GENMASK(4, 4)) >> 4)

#define AES_AES_EMR_APM(x)                       (((x) << 1) & GENMASK(1, 1))
#define AES_AES_EMR_APM_M                        GENMASK(1, 1)
#define AES_AES_EMR_APM_X(x)                     (((x) & GENMASK(1, 1)) >> 1)

#define AES_AES_EMR_APEN(x)                      ((x) & GENMASK(0, 0))
#define AES_AES_EMR_APEN_M                       GENMASK(0, 0)
#define AES_AES_EMR_APEN_X(x)                    ((x) & GENMASK(0, 0))

/*      AES:AES_REGS:AES_BCNT */
#define AES_AES_BCNT(t)           (t + 0xb4)

#define AES_AES_BCNT_BCNT(x)                     ((x) & GENMASK(30, 0))
#define AES_AES_BCNT_BCNT_M                      GENMASK(30, 0)
#define AES_AES_BCNT_BCNT_X(x)                   ((x) & GENMASK(30, 0))

/*      AES:AES_REGS:AES_TWR0 */
#define AES_AES_TWR0(t)           (t + 0xc0)

/*      AES:AES_REGS:AES_TWR1 */
#define AES_AES_TWR1(t)           (t + 0xc4)

/*      AES:AES_REGS:AES_TWR2 */
#define AES_AES_TWR2(t)           (t + 0xc8)

/*      AES:AES_REGS:AES_TWR3 */
#define AES_AES_TWR3(t)           (t + 0xcc)

/*      AES:AES_REGS:AES_ALPHAR0 */
#define AES_AES_ALPHAR0(t)        (t + 0xd0)

/*      AES:AES_REGS:AES_ALPHAR1 */
#define AES_AES_ALPHAR1(t)        (t + 0xd4)

/*      AES:AES_REGS:AES_ALPHAR2 */
#define AES_AES_ALPHAR2(t)        (t + 0xd8)

/*      AES:AES_REGS:AES_ALPHAR3 */
#define AES_AES_ALPHAR3(t)        (t + 0xdc)

/*      AES:AES_REGS:AES_WPMR */
#define AES_AES_WPMR(t)           (t + 0xe4)

#define AES_AES_WPMR_WPKEY(x)                    (((x) << 8) & GENMASK(31, 8))
#define AES_AES_WPMR_WPKEY_M                     GENMASK(31, 8)
#define AES_AES_WPMR_WPKEY_X(x)                  (((x) & GENMASK(31, 8)) >> 8)

#define AES_AES_WPMR_ACTION(x)                   (((x) << 5) & GENMASK(7, 5))
#define AES_AES_WPMR_ACTION_M                    GENMASK(7, 5)
#define AES_AES_WPMR_ACTION_X(x)                 (((x) & GENMASK(7, 5)) >> 5)

#define AES_AES_WPMR_FIRSTE(x)                   (((x) << 4) & GENMASK(4, 4))
#define AES_AES_WPMR_FIRSTE_M                    GENMASK(4, 4)
#define AES_AES_WPMR_FIRSTE_X(x)                 (((x) & GENMASK(4, 4)) >> 4)

#define AES_AES_WPMR_WPCREN(x)                   (((x) << 2) & GENMASK(2, 2))
#define AES_AES_WPMR_WPCREN_M                    GENMASK(2, 2)
#define AES_AES_WPMR_WPCREN_X(x)                 (((x) & GENMASK(2, 2)) >> 2)

#define AES_AES_WPMR_WPITEN(x)                   (((x) << 1) & GENMASK(1, 1))
#define AES_AES_WPMR_WPITEN_M                    GENMASK(1, 1)
#define AES_AES_WPMR_WPITEN_X(x)                 (((x) & GENMASK(1, 1)) >> 1)

#define AES_AES_WPMR_WPEN(x)                     ((x) & GENMASK(0, 0))
#define AES_AES_WPMR_WPEN_M                      GENMASK(0, 0)
#define AES_AES_WPMR_WPEN_X(x)                   ((x) & GENMASK(0, 0))

/*      AES:AES_REGS:AES_WPSR */
#define AES_AES_WPSR(t)           (t + 0xe8)

#define AES_AES_WPSR_ECLASS(x)                   (((x) << 31) & GENMASK(31, 31))
#define AES_AES_WPSR_ECLASS_M                    GENMASK(31, 31)
#define AES_AES_WPSR_ECLASS_X(x)                 (((x) & GENMASK(31, 31)) >> 31)

#define AES_AES_WPSR_SWETYP(x)                   (((x) << 24) & GENMASK(27, 24))
#define AES_AES_WPSR_SWETYP_M                    GENMASK(27, 24)
#define AES_AES_WPSR_SWETYP_X(x)                 (((x) & GENMASK(27, 24)) >> 24)

#define AES_AES_WPSR_WPVSRC(x)                   (((x) << 8) & GENMASK(15, 8))
#define AES_AES_WPSR_WPVSRC_M                    GENMASK(15, 8)
#define AES_AES_WPSR_WPVSRC_X(x)                 (((x) & GENMASK(15, 8)) >> 8)

#define AES_AES_WPSR_PKRPVS(x)                   (((x) << 4) & GENMASK(4, 4))
#define AES_AES_WPSR_PKRPVS_M                    GENMASK(4, 4)
#define AES_AES_WPSR_PKRPVS_X(x)                 (((x) & GENMASK(4, 4)) >> 4)

#define AES_AES_WPSR_SWE(x)                      (((x) << 3) & GENMASK(3, 3))
#define AES_AES_WPSR_SWE_M                       GENMASK(3, 3)
#define AES_AES_WPSR_SWE_X(x)                    (((x) & GENMASK(3, 3)) >> 3)

#define AES_AES_WPSR_SEQE(x)                     (((x) << 2) & GENMASK(2, 2))
#define AES_AES_WPSR_SEQE_M                      GENMASK(2, 2)
#define AES_AES_WPSR_SEQE_X(x)                   (((x) & GENMASK(2, 2)) >> 2)

#define AES_AES_WPSR_CGD(x)                      (((x) << 1) & GENMASK(1, 1))
#define AES_AES_WPSR_CGD_M                       GENMASK(1, 1)
#define AES_AES_WPSR_CGD_X(x)                    (((x) & GENMASK(1, 1)) >> 1)

#define AES_AES_WPSR_WPVS(x)                     ((x) & GENMASK(0, 0))
#define AES_AES_WPSR_WPVS_M                      GENMASK(0, 0)
#define AES_AES_WPSR_WPVS_X(x)                   ((x) & GENMASK(0, 0))

/*      AES:AES_REGS:AES_VERSION */
#define AES_AES_VERSION(t)        (t + 0xfc)

#define AES_AES_VERSION_MFN(x)                   (((x) << 16) & GENMASK(18, 16))
#define AES_AES_VERSION_MFN_M                    GENMASK(18, 16)
#define AES_AES_VERSION_MFN_X(x)                 (((x) & GENMASK(18, 16)) >> 16)

#define AES_AES_VERSION_VERSION(x)               ((x) & GENMASK(11, 0))
#define AES_AES_VERSION_VERSION_M                GENMASK(11, 0)
#define AES_AES_VERSION_VERSION_X(x)             ((x) & GENMASK(11, 0))

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RBAR0 */
#define AESB_ASC_TZAESBASC_RBAR0(t) (t + 0x00)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RTAR0 */
#define AESB_ASC_TZAESBASC_RTAR0(t) (t + 0x04)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RBAR1 */
#define AESB_ASC_TZAESBASC_RBAR1(t) (t + 0x08)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RTAR1 */
#define AESB_ASC_TZAESBASC_RTAR1(t) (t + 0x0c)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RBAR2 */
#define AESB_ASC_TZAESBASC_RBAR2(t) (t + 0x10)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RTAR2 */
#define AESB_ASC_TZAESBASC_RTAR2(t) (t + 0x14)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RBAR3 */
#define AESB_ASC_TZAESBASC_RBAR3(t) (t + 0x18)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RTAR3 */
#define AESB_ASC_TZAESBASC_RTAR3(t) (t + 0x1c)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RBAR4 */
#define AESB_ASC_TZAESBASC_RBAR4(t) (t + 0x20)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RTAR4 */
#define AESB_ASC_TZAESBASC_RTAR4(t) (t + 0x24)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RBAR5 */
#define AESB_ASC_TZAESBASC_RBAR5(t) (t + 0x28)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RTAR5 */
#define AESB_ASC_TZAESBASC_RTAR5(t) (t + 0x2c)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RBAR6 */
#define AESB_ASC_TZAESBASC_RBAR6(t) (t + 0x30)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RTAR6 */
#define AESB_ASC_TZAESBASC_RTAR6(t) (t + 0x34)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RBAR7 */
#define AESB_ASC_TZAESBASC_RBAR7(t) (t + 0x38)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RTAR7 */
#define AESB_ASC_TZAESBASC_RTAR7(t) (t + 0x3c)

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RSECR */
#define AESB_ASC_TZAESBASC_RSECR(t) (t + 0x80)

#define AESB_ASC_TZAESBASC_RSECR_SECX(x)         ((x) & GENMASK(7, 0))
#define AESB_ASC_TZAESBASC_RSECR_SECX_M          GENMASK(7, 0)
#define AESB_ASC_TZAESBASC_RSECR_SECX_X(x)       ((x) & GENMASK(7, 0))

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RER */
#define AESB_ASC_TZAESBASC_RER(t) (t + 0x84)

#define AESB_ASC_TZAESBASC_RER_ENX(x)            ((x) & GENMASK(7, 0))
#define AESB_ASC_TZAESBASC_RER_ENX_M             GENMASK(7, 0)
#define AESB_ASC_TZAESBASC_RER_ENX_X(x)          ((x) & GENMASK(7, 0))

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RDR */
#define AESB_ASC_TZAESBASC_RDR(t) (t + 0x88)

#define AESB_ASC_TZAESBASC_RDR_DISx(x)           ((x) & GENMASK(7, 0))
#define AESB_ASC_TZAESBASC_RDR_DISx_M            GENMASK(7, 0)
#define AESB_ASC_TZAESBASC_RDR_DISx_X(x)         ((x) & GENMASK(7, 0))

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RSR */
#define AESB_ASC_TZAESBASC_RSR(t) (t + 0x8c)

#define AESB_ASC_TZAESBASC_RSR_ESX(x)            ((x) & GENMASK(7, 0))
#define AESB_ASC_TZAESBASC_RSR_ESX_M             GENMASK(7, 0)
#define AESB_ASC_TZAESBASC_RSR_ESX_X(x)          ((x) & GENMASK(7, 0))

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RESR */
#define AESB_ASC_TZAESBASC_RESR(t) (t + 0x90)

#define AESB_ASC_TZAESBASC_RESR_AERx(x)          ((x) & GENMASK(7, 0))
#define AESB_ASC_TZAESBASC_RESR_AERx_M           GENMASK(7, 0)
#define AESB_ASC_TZAESBASC_RESR_AERx_X(x)        ((x) & GENMASK(7, 0))

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_RSSR */
#define AESB_ASC_TZAESBASC_RSSR(t) (t + 0x94)

#define AESB_ASC_TZAESBASC_RSSR_SYNC(x)          ((x) & GENMASK(0, 0))
#define AESB_ASC_TZAESBASC_RSSR_SYNC_M           GENMASK(0, 0)
#define AESB_ASC_TZAESBASC_RSSR_SYNC_X(x)        ((x) & GENMASK(0, 0))

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_WPMR */
#define AESB_ASC_TZAESBASC_WPMR(t) (t + 0xe4)

#define AESB_ASC_TZAESBASC_WPMR_WPKEY(x)         (((x) << 8) & GENMASK(31, 8))
#define AESB_ASC_TZAESBASC_WPMR_WPKEY_M          GENMASK(31, 8)
#define AESB_ASC_TZAESBASC_WPMR_WPKEY_X(x)       (((x) & GENMASK(31, 8)) >> 8)

#define AESB_ASC_TZAESBASC_WPMR_WPEN(x)          ((x) & GENMASK(0, 0))
#define AESB_ASC_TZAESBASC_WPMR_WPEN_M           GENMASK(0, 0)
#define AESB_ASC_TZAESBASC_WPMR_WPEN_X(x)        ((x) & GENMASK(0, 0))

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_WPSR */
#define AESB_ASC_TZAESBASC_WPSR(t) (t + 0xe8)

#define AESB_ASC_TZAESBASC_WPSR_WPSRC(x)         (((x) << 8) & GENMASK(23, 8))
#define AESB_ASC_TZAESBASC_WPSR_WPSRC_M          GENMASK(23, 8)
#define AESB_ASC_TZAESBASC_WPSR_WPSRC_X(x)       (((x) & GENMASK(23, 8)) >> 8)

#define AESB_ASC_TZAESBASC_WPSR_WPVS(x)          ((x) & GENMASK(0, 0))
#define AESB_ASC_TZAESBASC_WPSR_WPVS_M           GENMASK(0, 0)
#define AESB_ASC_TZAESBASC_WPSR_WPVS_X(x)        ((x) & GENMASK(0, 0))

/*      AESB_ASC:AESB_ASC_REGS:TZAESBASC_VERSION */
#define AESB_ASC_TZAESBASC_VERSION(t) (t + 0xfc)

#define AESB_ASC_TZAESBASC_VERSION_MFN(x)        (((x) << 16) & GENMASK(18, 16))
#define AESB_ASC_TZAESBASC_VERSION_MFN_M         GENMASK(18, 16)
#define AESB_ASC_TZAESBASC_VERSION_MFN_X(x)      (((x) & GENMASK(18, 16)) >> 16)

#define AESB_ASC_TZAESBASC_VERSION_VERSION(x)    ((x) & GENMASK(11, 0))
#define AESB_ASC_TZAESBASC_VERSION_VERSION_M     GENMASK(11, 0)
#define AESB_ASC_TZAESBASC_VERSION_VERSION_X(x)  ((x) & GENMASK(11, 0))

/*      CPU:CPU_REGS:GPR */
#define CPU_GPR(t, r)             (t + (0x00 + ((r) * 4)))

/*      CPU:CPU_REGS:BUILDID */
#define CPU_BUILDID(t)            (t + 0x80)

/*      CPU:CPU_REGS:RESET */
#define CPU_RESET(t)              (t + 0x84)

#define CPU_RESET_VCORE_RST(x)                   (((x) << 7) & GENMASK(7, 7))
#define CPU_RESET_VCORE_RST_M                    GENMASK(7, 7)
#define CPU_RESET_VCORE_RST_X(x)                 (((x) & GENMASK(7, 7)) >> 7)

#define CPU_RESET_CPU_CORE_0_WARM_RST(x)         (((x) << 6) & GENMASK(6, 6))
#define CPU_RESET_CPU_CORE_0_WARM_RST_M          GENMASK(6, 6)
#define CPU_RESET_CPU_CORE_0_WARM_RST_X(x)       (((x) & GENMASK(6, 6)) >> 6)

#define CPU_RESET_PROC_DBG_RST(x)                (((x) << 5) & GENMASK(5, 5))
#define CPU_RESET_PROC_DBG_RST_M                 GENMASK(5, 5)
#define CPU_RESET_PROC_DBG_RST_X(x)              (((x) & GENMASK(5, 5)) >> 5)

#define CPU_RESET_JTAG_RST(x)                    (((x) << 4) & GENMASK(4, 4))
#define CPU_RESET_JTAG_RST_M                     GENMASK(4, 4)
#define CPU_RESET_JTAG_RST_X(x)                  (((x) & GENMASK(4, 4)) >> 4)

#define CPU_RESET_CPU_L2_RST(x)                  (((x) << 3) & GENMASK(3, 3))
#define CPU_RESET_CPU_L2_RST_M                   GENMASK(3, 3)
#define CPU_RESET_CPU_L2_RST_X(x)                (((x) & GENMASK(3, 3)) >> 3)

#define CPU_RESET_MEM_RST(x)                     (((x) << 2) & GENMASK(2, 2))
#define CPU_RESET_MEM_RST_M                      GENMASK(2, 2)
#define CPU_RESET_MEM_RST_X(x)                   (((x) & GENMASK(2, 2)) >> 2)

#define CPU_RESET_WDT_FORCE_RST(x)               (((x) << 1) & GENMASK(1, 1))
#define CPU_RESET_WDT_FORCE_RST_M                GENMASK(1, 1)
#define CPU_RESET_WDT_FORCE_RST_X(x)             (((x) & GENMASK(1, 1)) >> 1)

#define CPU_RESET_CPU_CORE_0_COLD_RST(x)         ((x) & GENMASK(0, 0))
#define CPU_RESET_CPU_CORE_0_COLD_RST_M          GENMASK(0, 0)
#define CPU_RESET_CPU_CORE_0_COLD_RST_X(x)       ((x) & GENMASK(0, 0))

/*      CPU:CPU_REGS:RESET_PROT_STAT */
#define CPU_RESET_PROT_STAT(t)    (t + 0x88)

#define CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE(x) (((x) << 5) & GENMASK(5, 5))
#define CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE_M GENMASK(5, 5)
#define CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE_X(x) (((x) & GENMASK(5, 5)) >> 5)

#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_AMBA(x) (((x) << 4) & GENMASK(4, 4))
#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_AMBA_M GENMASK(4, 4)
#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_AMBA_X(x)\
	(((x) & GENMASK(4, 4)) >> 4)

#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_WDT(x) (((x) << 3) & GENMASK(3, 3))
#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_WDT_M GENMASK(3, 3)
#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_WDT_X(x) (((x) & GENMASK(3, 3)) >> 3)

#define CPU_RESET_PROT_STAT_VCORE_WDT_RST_PROT_WDT(x)\
	(((x) << 2) & GENMASK(2, 2))
#define CPU_RESET_PROT_STAT_VCORE_WDT_RST_PROT_WDT_M GENMASK(2, 2)
#define CPU_RESET_PROT_STAT_VCORE_WDT_RST_PROT_WDT_X(x)\
	(((x) & GENMASK(2, 2)) >> 2)

#define CPU_RESET_PROT_STAT_VCORE_WDT_RST_STAT(x) (((x) << 1) & GENMASK(1, 1))
#define CPU_RESET_PROT_STAT_VCORE_WDT_RST_STAT_M GENMASK(1, 1)
#define CPU_RESET_PROT_STAT_VCORE_WDT_RST_STAT_X(x) (((x) & GENMASK(1, 1)) >> 1)

#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_PCIE(x) ((x) & GENMASK(0, 0))
#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_PCIE_M GENMASK(0, 0)
#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_PCIE_X(x) ((x) & GENMASK(0, 0))

/*      CPU:CPU_REGS:GENERAL_CTRL */
#define CPU_GENERAL_CTRL(t)       (t + 0x8c)

#define CPU_GENERAL_CTRL_IF_MIIM_SLV_ENA(x)      (((x) << 2) & GENMASK(2, 2))
#define CPU_GENERAL_CTRL_IF_MIIM_SLV_ENA_M       GENMASK(2, 2)
#define CPU_GENERAL_CTRL_IF_MIIM_SLV_ENA_X(x)    (((x) & GENMASK(2, 2)) >> 2)

#define CPU_GENERAL_CTRL_VCORE_CPU_DIS(x)        (((x) << 1) & GENMASK(1, 1))
#define CPU_GENERAL_CTRL_VCORE_CPU_DIS_M         GENMASK(1, 1)
#define CPU_GENERAL_CTRL_VCORE_CPU_DIS_X(x)      (((x) & GENMASK(1, 1)) >> 1)

#define CPU_GENERAL_CTRL_IF_SI_OWNER(x)          ((x) & GENMASK(0, 0))
#define CPU_GENERAL_CTRL_IF_SI_OWNER_M           GENMASK(0, 0)
#define CPU_GENERAL_CTRL_IF_SI_OWNER_X(x)        ((x) & GENMASK(0, 0))

/*      CPU:CPU_REGS:GENERAL_STAT */
#define CPU_GENERAL_STAT(t)       (t + 0x90)

#define CPU_GENERAL_STAT_REG_IF_ERR(x)           (((x) << 7) & GENMASK(9, 7))
#define CPU_GENERAL_STAT_REG_IF_ERR_M            GENMASK(9, 7)
#define CPU_GENERAL_STAT_REG_IF_ERR_X(x)         (((x) & GENMASK(9, 7)) >> 7)

#define CPU_GENERAL_STAT_CSR_REG_IF_ERR(x)       (((x) << 4) & GENMASK(6, 4))
#define CPU_GENERAL_STAT_CSR_REG_IF_ERR_M        GENMASK(6, 4)
#define CPU_GENERAL_STAT_CSR_REG_IF_ERR_X(x)     (((x) & GENMASK(6, 4)) >> 4)

#define CPU_GENERAL_STAT_VCORE_CFG(x)            ((x) & GENMASK(3, 0))
#define CPU_GENERAL_STAT_VCORE_CFG_M             GENMASK(3, 0)
#define CPU_GENERAL_STAT_VCORE_CFG_X(x)          ((x) & GENMASK(3, 0))

/*      CPU:CPU_REGS:OTP_STAT */
#define CPU_OTP_STAT(t)           (t + 0x94)

#define CPU_OTP_STAT_OTP_PROGRAMMED(x)           (((x) << 4) & GENMASK(4, 4))
#define CPU_OTP_STAT_OTP_PROGRAMMED_M            GENMASK(4, 4)
#define CPU_OTP_STAT_OTP_PROGRAMMED_X(x)         (((x) & GENMASK(4, 4)) >> 4)

#define CPU_OTP_STAT_OTP_CPU_DISABLED(x)         (((x) << 3) & GENMASK(3, 3))
#define CPU_OTP_STAT_OTP_CPU_DISABLED_M          GENMASK(3, 3)
#define CPU_OTP_STAT_OTP_CPU_DISABLED_X(x)       (((x) & GENMASK(3, 3)) >> 3)

#define CPU_OTP_STAT_OTP_CPU_DBG_DISABLED(x)     (((x) << 2) & GENMASK(2, 2))
#define CPU_OTP_STAT_OTP_CPU_DBG_DISABLED_M      GENMASK(2, 2)
#define CPU_OTP_STAT_OTP_CPU_DBG_DISABLED_X(x)   (((x) & GENMASK(2, 2)) >> 2)

#define CPU_OTP_STAT_OTP_CPU_SEC_DBG_DISABLED(x) (((x) << 1) & GENMASK(1, 1))
#define CPU_OTP_STAT_OTP_CPU_SEC_DBG_DISABLED_M  GENMASK(1, 1)
#define CPU_OTP_STAT_OTP_CPU_SEC_DBG_DISABLED_X(x) (((x) & GENMASK(1, 1)) >> 1)

#define CPU_OTP_STAT_OTP_CAN_DISABLED(x)         ((x) & GENMASK(0, 0))
#define CPU_OTP_STAT_OTP_CAN_DISABLED_M          GENMASK(0, 0)
#define CPU_OTP_STAT_OTP_CAN_DISABLED_X(x)       ((x) & GENMASK(0, 0))

/*      CPU:CPU_REGS:CPU_DBG */
#define CPU_CPU_DBG(t)            (t + 0x98)

#define CPU_CPU_DBG_ENABLE_PROT_DEBUG_BIT(x)     (((x) << 5) & GENMASK(5, 5))
#define CPU_CPU_DBG_ENABLE_PROT_DEBUG_BIT_M      GENMASK(5, 5)
#define CPU_CPU_DBG_ENABLE_PROT_DEBUG_BIT_X(x)   (((x) & GENMASK(5, 5)) >> 5)

#define CPU_CPU_DBG_DBGEN(x)                     (((x) << 4) & GENMASK(4, 4))
#define CPU_CPU_DBG_DBGEN_M                      GENMASK(4, 4)
#define CPU_CPU_DBG_DBGEN_X(x)                   (((x) & GENMASK(4, 4)) >> 4)

#define CPU_CPU_DBG_SPIDEN(x)                    (((x) << 3) & GENMASK(3, 3))
#define CPU_CPU_DBG_SPIDEN_M                     GENMASK(3, 3)
#define CPU_CPU_DBG_SPIDEN_X(x)                  (((x) & GENMASK(3, 3)) >> 3)

#define CPU_CPU_DBG_NIDEN(x)                     (((x) << 2) & GENMASK(2, 2))
#define CPU_CPU_DBG_NIDEN_M                      GENMASK(2, 2)
#define CPU_CPU_DBG_NIDEN_X(x)                   (((x) & GENMASK(2, 2)) >> 2)

#define CPU_CPU_DBG_SPNIDEN(x)                   (((x) << 1) & GENMASK(1, 1))
#define CPU_CPU_DBG_SPNIDEN_M                    GENMASK(1, 1)
#define CPU_CPU_DBG_SPNIDEN_X(x)                 (((x) & GENMASK(1, 1)) >> 1)

#define CPU_CPU_DBG_CORE_IN_DBG(x)               ((x) & GENMASK(0, 0))
#define CPU_CPU_DBG_CORE_IN_DBG_M                GENMASK(0, 0)
#define CPU_CPU_DBG_CORE_IN_DBG_X(x)             ((x) & GENMASK(0, 0))

/*      CPU:CPU_REGS:ENDIANNESS */
#define CPU_ENDIANNESS(t)         (t + 0x9c)

#define CPU_ENDIANNESS_REG_IF_BIGENDIAN(x)       ((x) & GENMASK(0, 0))
#define CPU_ENDIANNESS_REG_IF_BIGENDIAN_M        GENMASK(0, 0)
#define CPU_ENDIANNESS_REG_IF_BIGENDIAN_X(x)     ((x) & GENMASK(0, 0))

/*      CPU:CPU_REGS:PROC_CTRL */
#define CPU_PROC_CTRL(t)          (t + 0xa0)

#define CPU_PROC_CTRL_BE_EXCEP_MODE(x)           (((x) << 4) & GENMASK(4, 4))
#define CPU_PROC_CTRL_BE_EXCEP_MODE_M            GENMASK(4, 4)
#define CPU_PROC_CTRL_BE_EXCEP_MODE_X(x)         (((x) & GENMASK(4, 4)) >> 4)

#define CPU_PROC_CTRL_VINITHI(x)                 (((x) << 3) & GENMASK(3, 3))
#define CPU_PROC_CTRL_VINITHI_M                  GENMASK(3, 3)
#define CPU_PROC_CTRL_VINITHI_X(x)               (((x) & GENMASK(3, 3)) >> 3)

#define CPU_PROC_CTRL_CFGTE(x)                   (((x) << 2) & GENMASK(2, 2))
#define CPU_PROC_CTRL_CFGTE_M                    GENMASK(2, 2)
#define CPU_PROC_CTRL_CFGTE_X(x)                 (((x) & GENMASK(2, 2)) >> 2)

#define CPU_PROC_CTRL_CP15S_DISABLE(x)           (((x) << 1) & GENMASK(1, 1))
#define CPU_PROC_CTRL_CP15S_DISABLE_M            GENMASK(1, 1)
#define CPU_PROC_CTRL_CP15S_DISABLE_X(x)         (((x) & GENMASK(1, 1)) >> 1)

#define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE(x)     ((x) & GENMASK(0, 0))
#define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_M      GENMASK(0, 0)
#define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_X(x)   ((x) & GENMASK(0, 0))

/*      CPU:CPU_REGS:PROC_STAT */
#define CPU_PROC_STAT(t)          (t + 0xa4)

#define CPU_PROC_STAT_DAP_JTAG_SW_MODE(x)        (((x) << 3) & GENMASK(3, 3))
#define CPU_PROC_STAT_DAP_JTAG_SW_MODE_M         GENMASK(3, 3)
#define CPU_PROC_STAT_DAP_JTAG_SW_MODE_X(x)      (((x) & GENMASK(3, 3)) >> 3)

#define CPU_PROC_STAT_WFI(x)                     (((x) << 2) & GENMASK(2, 2))
#define CPU_PROC_STAT_WFI_M                      GENMASK(2, 2)
#define CPU_PROC_STAT_WFI_X(x)                   (((x) & GENMASK(2, 2)) >> 2)

#define CPU_PROC_STAT_WFIL2(x)                   (((x) << 1) & GENMASK(1, 1))
#define CPU_PROC_STAT_WFIL2_M                    GENMASK(1, 1)
#define CPU_PROC_STAT_WFIL2_X(x)                 (((x) & GENMASK(1, 1)) >> 1)

#define CPU_PROC_STAT_WFE(x)                     ((x) & GENMASK(0, 0))
#define CPU_PROC_STAT_WFE_M                      GENMASK(0, 0)
#define CPU_PROC_STAT_WFE_X(x)                   ((x) & GENMASK(0, 0))

/*      CPU:GCK_REGS:GCK_CFG */
#define CPU_GCK_CFG(t, r)         (t + (0xa8 + ((r) * 4)))

#define CPU_GCK_CFG_GCK_PRESCALER(x)             (((x) << 16) & GENMASK(23, 16))
#define CPU_GCK_CFG_GCK_PRESCALER_M              GENMASK(23, 16)
#define CPU_GCK_CFG_GCK_PRESCALER_X(x)           (((x) & GENMASK(23, 16)) >> 16)

#define CPU_GCK_CFG_GCK_SRC_SEL(x)               (((x) << 8) & GENMASK(9, 8))
#define CPU_GCK_CFG_GCK_SRC_SEL_M                GENMASK(9, 8)
#define CPU_GCK_CFG_GCK_SRC_SEL_X(x)             (((x) & GENMASK(9, 8)) >> 8)

#define CPU_GCK_CFG_GCK_ENA(x)                   ((x) & GENMASK(0, 0))
#define CPU_GCK_CFG_GCK_ENA_M                    GENMASK(0, 0)
#define CPU_GCK_CFG_GCK_ENA_X(x)                 ((x) & GENMASK(0, 0))

/*      CPU:SFR_REGS:CLK_GATING */
#define CPU_CLK_GATING(t)         (t + 0x2cc)

#define CPU_CLK_GATING_UHPHS_CLK_GATING(x)       (((x) << 11) & GENMASK(11, 11))
#define CPU_CLK_GATING_UHPHS_CLK_GATING_M        GENMASK(11, 11)
#define CPU_CLK_GATING_UHPHS_CLK_GATING_X(x)     (((x) & GENMASK(11, 11)) >> 11)

#define CPU_CLK_GATING_UDPHS_CLK_GATING(x)       (((x) << 10) & GENMASK(10, 10))
#define CPU_CLK_GATING_UDPHS_CLK_GATING_M        GENMASK(10, 10)
#define CPU_CLK_GATING_UDPHS_CLK_GATING_X(x)     (((x) & GENMASK(10, 10)) >> 10)

#define CPU_CLK_GATING_MCRAMC_CLK_GATING(x)      (((x) << 9) & GENMASK(9, 9))
#define CPU_CLK_GATING_MCRAMC_CLK_GATING_M       GENMASK(9, 9)
#define CPU_CLK_GATING_MCRAMC_CLK_GATING_X(x)    (((x) & GENMASK(9, 9)) >> 9)

#define CPU_CLK_GATING_HMATRIX_CLK_GATING(x)     (((x) << 8) & GENMASK(8, 8))
#define CPU_CLK_GATING_HMATRIX_CLK_GATING_M      GENMASK(8, 8)
#define CPU_CLK_GATING_HMATRIX_CLK_GATING_X(x)   (((x) & GENMASK(8, 8)) >> 8)

#define CPU_CLK_GATING_HBRIDGE_CLK_GATING(x)     ((x) & GENMASK(3, 0))
#define CPU_CLK_GATING_HBRIDGE_CLK_GATING_M      GENMASK(3, 0)
#define CPU_CLK_GATING_HBRIDGE_CLK_GATING_X(x)   ((x) & GENMASK(3, 0))

/*      CPU:SFR_REGS:TZAESB */
#define CPU_TZAESB(t)             (t + 0x2d4)

#define CPU_TZAESB_TZAESB_LITE_EN(x)             ((x) & GENMASK(0, 0))
#define CPU_TZAESB_TZAESB_LITE_EN_M              GENMASK(0, 0)
#define CPU_TZAESB_TZAESB_LITE_EN_X(x)           ((x) & GENMASK(0, 0))

/*      CPU:USB2COMMON_REGS:USB_BIAS_TC */
#define CPU_USB_BIAS_TC(t)        (t + 0x2e8)

#define CPU_USB_BIAS_TC_TRIM(x)                  ((x) & GENMASK(4, 0))
#define CPU_USB_BIAS_TC_TRIM_M                   GENMASK(4, 0)
#define CPU_USB_BIAS_TC_TRIM_X(x)                ((x) & GENMASK(4, 0))

/*      CPU:USB2COMMON_REGS:USB_BIAS_MAG */
#define CPU_USB_BIAS_MAG(t)       (t + 0x2ec)

#define CPU_USB_BIAS_MAG_TRIM(x)                 ((x) & GENMASK(5, 0))
#define CPU_USB_BIAS_MAG_TRIM_M                  GENMASK(5, 0)
#define CPU_USB_BIAS_MAG_TRIM_X(x)               ((x) & GENMASK(5, 0))

/*      CPU:USB2COMMON_REGS:USB_RBIAS_MAG */
#define CPU_USB_RBIAS_MAG(t)      (t + 0x2f0)

#define CPU_USB_RBIAS_MAG_TRIM(x)                ((x) & GENMASK(5, 0))
#define CPU_USB_RBIAS_MAG_TRIM_M                 GENMASK(5, 0)
#define CPU_USB_RBIAS_MAG_TRIM_X(x)              ((x) & GENMASK(5, 0))

/*      CPU:ULPI_BRIDGE_REGS:ULPI_RST */
#define CPU_ULPI_RST(t)           (t + 0x338)

#define CPU_ULPI_RST_ULPI_RST(x)                 ((x) & GENMASK(0, 0))
#define CPU_ULPI_RST_ULPI_RST_M                  GENMASK(0, 0)
#define CPU_ULPI_RST_ULPI_RST_X(x)               ((x) & GENMASK(0, 0))

/*      CPU_SYSCNT:CXTSGEN_REGISTERS:CNTCR */
#define CPU_SYSCNT_CNTCR(t)       (t + 0x00)

#define CPU_SYSCNT_CNTCR_CNTCR_EN(x)             ((x) & GENMASK(0, 0))
#define CPU_SYSCNT_CNTCR_CNTCR_EN_M              GENMASK(0, 0)
#define CPU_SYSCNT_CNTCR_CNTCR_EN_X(x)           ((x) & GENMASK(0, 0))

#define CPU_SYSCNT_CNTCR_CNTCR_HDBG(x)           (((x) << 1) & GENMASK(1, 1))
#define CPU_SYSCNT_CNTCR_CNTCR_HDBG_M            GENMASK(1, 1)
#define CPU_SYSCNT_CNTCR_CNTCR_HDBG_X(x)         (((x) & GENMASK(1, 1)) >> 1)

/*      CPU_SYSCNT:CXTSGEN_REGISTERS:CNTSR */
#define CPU_SYSCNT_CNTSR(t)       (t + 0x04)

#define CPU_SYSCNT_CNTSR_CNTSR_DBGH(x)           (((x) << 1) & GENMASK(1, 1))
#define CPU_SYSCNT_CNTSR_CNTSR_DBGH_M            GENMASK(1, 1)
#define CPU_SYSCNT_CNTSR_CNTSR_DBGH_X(x)         (((x) & GENMASK(1, 1)) >> 1)

/*      CPU_SYSCNT:CXTSGEN_REGISTERS:CNTCVL */
#define CPU_SYSCNT_CNTCVL(t)      (t + 0x08)

/*      CPU_SYSCNT:CXTSGEN_REGISTERS:CNTCVU */
#define CPU_SYSCNT_CNTCVU(t)      (t + 0x0c)

/*      CPU_SYSCNT:CXTSGEN_REGISTERS:CNTFID0 */
#define CPU_SYSCNT_CNTFID0(t)     (t + 0x20)

/*      CPU_SYSCNT:CXTSGEN_REGISTERS:PIDR0 */
#define CPU_SYSCNT_PIDR0(t)       (t + 0xfe0)

#define CPU_SYSCNT_PIDR0_PART_0(x)               ((x) & GENMASK(7, 0))
#define CPU_SYSCNT_PIDR0_PART_0_M                GENMASK(7, 0)
#define CPU_SYSCNT_PIDR0_PART_0_X(x)             ((x) & GENMASK(7, 0))

/*      CPU_SYSCNT:CXTSGEN_REGISTERS:PIDR1 */
#define CPU_SYSCNT_PIDR1(t)       (t + 0xfe4)

#define CPU_SYSCNT_PIDR1_PART_1(x)               ((x) & GENMASK(3, 0))
#define CPU_SYSCNT_PIDR1_PART_1_M                GENMASK(3, 0)
#define CPU_SYSCNT_PIDR1_PART_1_X(x)             ((x) & GENMASK(3, 0))

#define CPU_SYSCNT_PIDR1_DES_0(x)                (((x) << 4) & GENMASK(7, 4))
#define CPU_SYSCNT_PIDR1_DES_0_M                 GENMASK(7, 4)
#define CPU_SYSCNT_PIDR1_DES_0_X(x)              (((x) & GENMASK(7, 4)) >> 4)

/*      CPU_SYSCNT:CXTSGEN_REGISTERS:PIDR2 */
#define CPU_SYSCNT_PIDR2(t)       (t + 0xfe8)

#define CPU_SYSCNT_PIDR2_DES_1(x)                ((x) & GENMASK(2, 0))
#define CPU_SYSCNT_PIDR2_DES_1_M                 GENMASK(2, 0)
#define CPU_SYSCNT_PIDR2_DES_1_X(x)              ((x) & GENMASK(2, 0))

#define CPU_SYSCNT_PIDR2_JEDEC(x)                (((x) << 3) & GENMASK(3, 3))
#define CPU_SYSCNT_PIDR2_JEDEC_M                 GENMASK(3, 3)
#define CPU_SYSCNT_PIDR2_JEDEC_X(x)              (((x) & GENMASK(3, 3)) >> 3)

#define CPU_SYSCNT_PIDR2_REVISION(x)             (((x) << 4) & GENMASK(7, 4))
#define CPU_SYSCNT_PIDR2_REVISION_M              GENMASK(7, 4)
#define CPU_SYSCNT_PIDR2_REVISION_X(x)           (((x) & GENMASK(7, 4)) >> 4)

/*      CPU_SYSCNT:CXTSGEN_REGISTERS:PIDR3 */
#define CPU_SYSCNT_PIDR3(t)       (t + 0xfec)

#define CPU_SYSCNT_PIDR3_CMOD(x)                 ((x) & GENMASK(3, 0))
#define CPU_SYSCNT_PIDR3_CMOD_M                  GENMASK(3, 0)
#define CPU_SYSCNT_PIDR3_CMOD_X(x)               ((x) & GENMASK(3, 0))

#define CPU_SYSCNT_PIDR3_REVAND(x)               (((x) << 4) & GENMASK(7, 4))
#define CPU_SYSCNT_PIDR3_REVAND_M                GENMASK(7, 4)
#define CPU_SYSCNT_PIDR3_REVAND_X(x)             (((x) & GENMASK(7, 4)) >> 4)

/*      CPU_SYSCNT:CXTSGEN_REGISTERS:PIDR4 */
#define CPU_SYSCNT_PIDR4(t)       (t + 0xfd0)

#define CPU_SYSCNT_PIDR4_DES_2(x)                ((x) & GENMASK(3, 0))
#define CPU_SYSCNT_PIDR4_DES_2_M                 GENMASK(3, 0)
#define CPU_SYSCNT_PIDR4_DES_2_X(x)              ((x) & GENMASK(3, 0))

#define CPU_SYSCNT_PIDR4_SIZE(x)                 (((x) << 4) & GENMASK(7, 4))
#define CPU_SYSCNT_PIDR4_SIZE_M                  GENMASK(7, 4)
#define CPU_SYSCNT_PIDR4_SIZE_X(x)               (((x) & GENMASK(7, 4)) >> 4)

/*      CPU_SYSCNT:CXTSGEN_REGISTERS:CIDR0 */
#define CPU_SYSCNT_CIDR0(t)       (t + 0xff0)

#define CPU_SYSCNT_CIDR0_PRMBL_0(x)              ((x) & GENMASK(7, 0))
#define CPU_SYSCNT_CIDR0_PRMBL_0_M               GENMASK(7, 0)
#define CPU_SYSCNT_CIDR0_PRMBL_0_X(x)            ((x) & GENMASK(7, 0))

/*      CPU_SYSCNT:CXTSGEN_REGISTERS:CIDR1 */
#define CPU_SYSCNT_CIDR1(t)       (t + 0xff4)

#define CPU_SYSCNT_CIDR1_PRMBL_1(x)              ((x) & GENMASK(3, 0))
#define CPU_SYSCNT_CIDR1_PRMBL_1_M               GENMASK(3, 0)
#define CPU_SYSCNT_CIDR1_PRMBL_1_X(x)            ((x) & GENMASK(3, 0))

#define CPU_SYSCNT_CIDR1_CLASS(x)                (((x) << 4) & GENMASK(7, 4))
#define CPU_SYSCNT_CIDR1_CLASS_M                 GENMASK(7, 4)
#define CPU_SYSCNT_CIDR1_CLASS_X(x)              (((x) & GENMASK(7, 4)) >> 4)

/*      CPU_SYSCNT:CXTSGEN_REGISTERS:CIDR2 */
#define CPU_SYSCNT_CIDR2(t)       (t + 0xff8)

#define CPU_SYSCNT_CIDR2_PRMBL_2(x)              ((x) & GENMASK(7, 0))
#define CPU_SYSCNT_CIDR2_PRMBL_2_M               GENMASK(7, 0)
#define CPU_SYSCNT_CIDR2_PRMBL_2_X(x)            ((x) & GENMASK(7, 0))

/*      CPU_SYSCNT:CXTSGEN_REGISTERS:CIDR3 */
#define CPU_SYSCNT_CIDR3(t)       (t + 0xffc)

#define CPU_SYSCNT_CIDR3_PRMBL_3(x)              ((x) & GENMASK(7, 0))
#define CPU_SYSCNT_CIDR3_PRMBL_3_M               GENMASK(7, 0)
#define CPU_SYSCNT_CIDR3_PRMBL_3_X(x)            ((x) & GENMASK(7, 0))

/*      CPU_SYSCNT_RO:CXTSGEN_READ_REGISTERS:CNTCVL */
#define CPU_SYSCNT_RO_CNTCVL(t)   (t + 0x00)

/*      CPU_SYSCNT_RO:CXTSGEN_READ_REGISTERS:CNTCVU */
#define CPU_SYSCNT_RO_CNTCVU(t)   (t + 0x04)

/*      CPU_SYSCNT_RO:CXTSGEN_READ_REGISTERS:PIDR0 */
#define CPU_SYSCNT_RO_PIDR0(t)    (t + 0xfe0)

#define CPU_SYSCNT_RO_PIDR0_PART_0(x)            ((x) & GENMASK(7, 0))
#define CPU_SYSCNT_RO_PIDR0_PART_0_M             GENMASK(7, 0)
#define CPU_SYSCNT_RO_PIDR0_PART_0_X(x)          ((x) & GENMASK(7, 0))

/*      CPU_SYSCNT_RO:CXTSGEN_READ_REGISTERS:PIDR1 */
#define CPU_SYSCNT_RO_PIDR1(t)    (t + 0xfe4)

#define CPU_SYSCNT_RO_PIDR1_PART_1(x)            ((x) & GENMASK(3, 0))
#define CPU_SYSCNT_RO_PIDR1_PART_1_M             GENMASK(3, 0)
#define CPU_SYSCNT_RO_PIDR1_PART_1_X(x)          ((x) & GENMASK(3, 0))

#define CPU_SYSCNT_RO_PIDR1_DES_0(x)             (((x) << 4) & GENMASK(7, 4))
#define CPU_SYSCNT_RO_PIDR1_DES_0_M              GENMASK(7, 4)
#define CPU_SYSCNT_RO_PIDR1_DES_0_X(x)           (((x) & GENMASK(7, 4)) >> 4)

/*      CPU_SYSCNT_RO:CXTSGEN_READ_REGISTERS:PIDR2 */
#define CPU_SYSCNT_RO_PIDR2(t)    (t + 0xfe8)

#define CPU_SYSCNT_RO_PIDR2_DES_1(x)             ((x) & GENMASK(2, 0))
#define CPU_SYSCNT_RO_PIDR2_DES_1_M              GENMASK(2, 0)
#define CPU_SYSCNT_RO_PIDR2_DES_1_X(x)           ((x) & GENMASK(2, 0))

#define CPU_SYSCNT_RO_PIDR2_JEDEC(x)             (((x) << 3) & GENMASK(3, 3))
#define CPU_SYSCNT_RO_PIDR2_JEDEC_M              GENMASK(3, 3)
#define CPU_SYSCNT_RO_PIDR2_JEDEC_X(x)           (((x) & GENMASK(3, 3)) >> 3)

#define CPU_SYSCNT_RO_PIDR2_REVISION(x)          (((x) << 4) & GENMASK(7, 4))
#define CPU_SYSCNT_RO_PIDR2_REVISION_M           GENMASK(7, 4)
#define CPU_SYSCNT_RO_PIDR2_REVISION_X(x)        (((x) & GENMASK(7, 4)) >> 4)

/*      CPU_SYSCNT_RO:CXTSGEN_READ_REGISTERS:PIDR3 */
#define CPU_SYSCNT_RO_PIDR3(t)    (t + 0xfec)

#define CPU_SYSCNT_RO_PIDR3_CMOD(x)              ((x) & GENMASK(3, 0))
#define CPU_SYSCNT_RO_PIDR3_CMOD_M               GENMASK(3, 0)
#define CPU_SYSCNT_RO_PIDR3_CMOD_X(x)            ((x) & GENMASK(3, 0))

#define CPU_SYSCNT_RO_PIDR3_REVAND(x)            (((x) << 4) & GENMASK(7, 4))
#define CPU_SYSCNT_RO_PIDR3_REVAND_M             GENMASK(7, 4)
#define CPU_SYSCNT_RO_PIDR3_REVAND_X(x)          (((x) & GENMASK(7, 4)) >> 4)

/*      CPU_SYSCNT_RO:CXTSGEN_READ_REGISTERS:PIDR4 */
#define CPU_SYSCNT_RO_PIDR4(t)    (t + 0xfd0)

#define CPU_SYSCNT_RO_PIDR4_DES_2(x)             ((x) & GENMASK(3, 0))
#define CPU_SYSCNT_RO_PIDR4_DES_2_M              GENMASK(3, 0)
#define CPU_SYSCNT_RO_PIDR4_DES_2_X(x)           ((x) & GENMASK(3, 0))

#define CPU_SYSCNT_RO_PIDR4_SIZE(x)              (((x) << 4) & GENMASK(7, 4))
#define CPU_SYSCNT_RO_PIDR4_SIZE_M               GENMASK(7, 4)
#define CPU_SYSCNT_RO_PIDR4_SIZE_X(x)            (((x) & GENMASK(7, 4)) >> 4)

/*      CPU_SYSCNT_RO:CXTSGEN_READ_REGISTERS:CIDR0 */
#define CPU_SYSCNT_RO_CIDR0(t)    (t + 0xff0)

#define CPU_SYSCNT_RO_CIDR0_PRMBL_0(x)           ((x) & GENMASK(7, 0))
#define CPU_SYSCNT_RO_CIDR0_PRMBL_0_M            GENMASK(7, 0)
#define CPU_SYSCNT_RO_CIDR0_PRMBL_0_X(x)         ((x) & GENMASK(7, 0))

/*      CPU_SYSCNT_RO:CXTSGEN_READ_REGISTERS:CIDR1 */
#define CPU_SYSCNT_RO_CIDR1(t)    (t + 0xff4)

#define CPU_SYSCNT_RO_CIDR1_PRMBL_1(x)           ((x) & GENMASK(3, 0))
#define CPU_SYSCNT_RO_CIDR1_PRMBL_1_M            GENMASK(3, 0)
#define CPU_SYSCNT_RO_CIDR1_PRMBL_1_X(x)         ((x) & GENMASK(3, 0))

#define CPU_SYSCNT_RO_CIDR1_CLASS(x)             (((x) << 4) & GENMASK(7, 4))
#define CPU_SYSCNT_RO_CIDR1_CLASS_M              GENMASK(7, 4)
#define CPU_SYSCNT_RO_CIDR1_CLASS_X(x)           (((x) & GENMASK(7, 4)) >> 4)

/*      CPU_SYSCNT_RO:CXTSGEN_READ_REGISTERS:CIDR2 */
#define CPU_SYSCNT_RO_CIDR2(t)    (t + 0xff8)

#define CPU_SYSCNT_RO_CIDR2_PRMBL_2(x)           ((x) & GENMASK(7, 0))
#define CPU_SYSCNT_RO_CIDR2_PRMBL_2_M            GENMASK(7, 0)
#define CPU_SYSCNT_RO_CIDR2_PRMBL_2_X(x)         ((x) & GENMASK(7, 0))

/*      CPU_SYSCNT_RO:CXTSGEN_READ_REGISTERS:CIDR3 */
#define CPU_SYSCNT_RO_CIDR3(t)    (t + 0xffc)

#define CPU_SYSCNT_RO_CIDR3_PRMBL_3(x)           ((x) & GENMASK(7, 0))
#define CPU_SYSCNT_RO_CIDR3_PRMBL_3_M            GENMASK(7, 0)
#define CPU_SYSCNT_RO_CIDR3_PRMBL_3_X(x)         ((x) & GENMASK(7, 0))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_CR */
#define FLEXCOM_FLEX_US_CR(t)     (t + 0x200)

#define FLEXCOM_FLEX_US_CR_FIFODIS(x)            (((x) << 31) & GENMASK(31, 31))
#define FLEXCOM_FLEX_US_CR_FIFODIS_M             GENMASK(31, 31)
#define FLEXCOM_FLEX_US_CR_FIFODIS_X(x)          (((x) & GENMASK(31, 31)) >> 31)

#define FLEXCOM_FLEX_US_CR_FIFOEN(x)             (((x) << 30) & GENMASK(30, 30))
#define FLEXCOM_FLEX_US_CR_FIFOEN_M              GENMASK(30, 30)
#define FLEXCOM_FLEX_US_CR_FIFOEN_X(x)           (((x) & GENMASK(30, 30)) >> 30)

#define FLEXCOM_FLEX_US_CR_USART_REQCLR(x)       (((x) << 28) & GENMASK(28, 28))
#define FLEXCOM_FLEX_US_CR_USART_REQCLR_M        GENMASK(28, 28)
#define FLEXCOM_FLEX_US_CR_USART_REQCLR_X(x)     (((x) & GENMASK(28, 28)) >> 28)

#define FLEXCOM_FLEX_US_CR_TXFLCLR(x)            (((x) << 26) & GENMASK(26, 26))
#define FLEXCOM_FLEX_US_CR_TXFLCLR_M             GENMASK(26, 26)
#define FLEXCOM_FLEX_US_CR_TXFLCLR_X(x)          (((x) & GENMASK(26, 26)) >> 26)

#define FLEXCOM_FLEX_US_CR_RXFCLR(x)             (((x) << 25) & GENMASK(25, 25))
#define FLEXCOM_FLEX_US_CR_RXFCLR_M              GENMASK(25, 25)
#define FLEXCOM_FLEX_US_CR_RXFCLR_X(x)           (((x) & GENMASK(25, 25)) >> 25)

#define FLEXCOM_FLEX_US_CR_TXFCLR(x)             (((x) << 24) & GENMASK(24, 24))
#define FLEXCOM_FLEX_US_CR_TXFCLR_M              GENMASK(24, 24)
#define FLEXCOM_FLEX_US_CR_TXFCLR_X(x)           (((x) & GENMASK(24, 24)) >> 24)

#define FLEXCOM_FLEX_US_CR_LINWKUP(x)            (((x) << 21) & GENMASK(21, 21))
#define FLEXCOM_FLEX_US_CR_LINWKUP_M             GENMASK(21, 21)
#define FLEXCOM_FLEX_US_CR_LINWKUP_X(x)          (((x) & GENMASK(21, 21)) >> 21)

#define FLEXCOM_FLEX_US_CR_LINABT(x)             (((x) << 20) & GENMASK(20, 20))
#define FLEXCOM_FLEX_US_CR_LINABT_M              GENMASK(20, 20)
#define FLEXCOM_FLEX_US_CR_LINABT_X(x)           (((x) & GENMASK(20, 20)) >> 20)

#define FLEXCOM_FLEX_US_CR_RTSDIS(x)             (((x) << 19) & GENMASK(19, 19))
#define FLEXCOM_FLEX_US_CR_RTSDIS_M              GENMASK(19, 19)
#define FLEXCOM_FLEX_US_CR_RTSDIS_X(x)           (((x) & GENMASK(19, 19)) >> 19)

#define FLEXCOM_FLEX_US_CR_RTSEN(x)              (((x) << 18) & GENMASK(18, 18))
#define FLEXCOM_FLEX_US_CR_RTSEN_M               GENMASK(18, 18)
#define FLEXCOM_FLEX_US_CR_RTSEN_X(x)            (((x) & GENMASK(18, 18)) >> 18)

#define FLEXCOM_FLEX_US_CR_DTRDIS(x)             (((x) << 17) & GENMASK(17, 17))
#define FLEXCOM_FLEX_US_CR_DTRDIS_M              GENMASK(17, 17)
#define FLEXCOM_FLEX_US_CR_DTRDIS_X(x)           (((x) & GENMASK(17, 17)) >> 17)

#define FLEXCOM_FLEX_US_CR_DTREN(x)              (((x) << 16) & GENMASK(16, 16))
#define FLEXCOM_FLEX_US_CR_DTREN_M               GENMASK(16, 16)
#define FLEXCOM_FLEX_US_CR_DTREN_X(x)            (((x) & GENMASK(16, 16)) >> 16)

#define FLEXCOM_FLEX_US_CR_RETTO(x)              (((x) << 15) & GENMASK(15, 15))
#define FLEXCOM_FLEX_US_CR_RETTO_M               GENMASK(15, 15)
#define FLEXCOM_FLEX_US_CR_RETTO_X(x)            (((x) & GENMASK(15, 15)) >> 15)

#define FLEXCOM_FLEX_US_CR_RSTNACK(x)            (((x) << 14) & GENMASK(14, 14))
#define FLEXCOM_FLEX_US_CR_RSTNACK_M             GENMASK(14, 14)
#define FLEXCOM_FLEX_US_CR_RSTNACK_X(x)          (((x) & GENMASK(14, 14)) >> 14)

#define FLEXCOM_FLEX_US_CR_RSTIT(x)              (((x) << 13) & GENMASK(13, 13))
#define FLEXCOM_FLEX_US_CR_RSTIT_M               GENMASK(13, 13)
#define FLEXCOM_FLEX_US_CR_RSTIT_X(x)            (((x) & GENMASK(13, 13)) >> 13)

#define FLEXCOM_FLEX_US_CR_SENDA(x)              (((x) << 12) & GENMASK(12, 12))
#define FLEXCOM_FLEX_US_CR_SENDA_M               GENMASK(12, 12)
#define FLEXCOM_FLEX_US_CR_SENDA_X(x)            (((x) & GENMASK(12, 12)) >> 12)

#define FLEXCOM_FLEX_US_CR_STTTO(x)              (((x) << 11) & GENMASK(11, 11))
#define FLEXCOM_FLEX_US_CR_STTTO_M               GENMASK(11, 11)
#define FLEXCOM_FLEX_US_CR_STTTO_X(x)            (((x) & GENMASK(11, 11)) >> 11)

#define FLEXCOM_FLEX_US_CR_STPBRK(x)             (((x) << 10) & GENMASK(10, 10))
#define FLEXCOM_FLEX_US_CR_STPBRK_M              GENMASK(10, 10)
#define FLEXCOM_FLEX_US_CR_STPBRK_X(x)           (((x) & GENMASK(10, 10)) >> 10)

#define FLEXCOM_FLEX_US_CR_STTBRK(x)             (((x) << 9) & GENMASK(9, 9))
#define FLEXCOM_FLEX_US_CR_STTBRK_M              GENMASK(9, 9)
#define FLEXCOM_FLEX_US_CR_STTBRK_X(x)           (((x) & GENMASK(9, 9)) >> 9)

#define FLEXCOM_FLEX_US_CR_RSTSTA(x)             (((x) << 8) & GENMASK(8, 8))
#define FLEXCOM_FLEX_US_CR_RSTSTA_M              GENMASK(8, 8)
#define FLEXCOM_FLEX_US_CR_RSTSTA_X(x)           (((x) & GENMASK(8, 8)) >> 8)

#define FLEXCOM_FLEX_US_CR_TXDIS(x)              (((x) << 7) & GENMASK(7, 7))
#define FLEXCOM_FLEX_US_CR_TXDIS_M               GENMASK(7, 7)
#define FLEXCOM_FLEX_US_CR_TXDIS_X(x)            (((x) & GENMASK(7, 7)) >> 7)

#define FLEXCOM_FLEX_US_CR_TXEN(x)               (((x) << 6) & GENMASK(6, 6))
#define FLEXCOM_FLEX_US_CR_TXEN_M                GENMASK(6, 6)
#define FLEXCOM_FLEX_US_CR_TXEN_X(x)             (((x) & GENMASK(6, 6)) >> 6)

#define FLEXCOM_FLEX_US_CR_RXDIS(x)              (((x) << 5) & GENMASK(5, 5))
#define FLEXCOM_FLEX_US_CR_RXDIS_M               GENMASK(5, 5)
#define FLEXCOM_FLEX_US_CR_RXDIS_X(x)            (((x) & GENMASK(5, 5)) >> 5)

#define FLEXCOM_FLEX_US_CR_RXEN(x)               (((x) << 4) & GENMASK(4, 4))
#define FLEXCOM_FLEX_US_CR_RXEN_M                GENMASK(4, 4)
#define FLEXCOM_FLEX_US_CR_RXEN_X(x)             (((x) & GENMASK(4, 4)) >> 4)

#define FLEXCOM_FLEX_US_CR_RSTTX(x)              (((x) << 3) & GENMASK(3, 3))
#define FLEXCOM_FLEX_US_CR_RSTTX_M               GENMASK(3, 3)
#define FLEXCOM_FLEX_US_CR_RSTTX_X(x)            (((x) & GENMASK(3, 3)) >> 3)

#define FLEXCOM_FLEX_US_CR_RSTRX(x)              (((x) << 2) & GENMASK(2, 2))
#define FLEXCOM_FLEX_US_CR_RSTRX_M               GENMASK(2, 2)
#define FLEXCOM_FLEX_US_CR_RSTRX_X(x)            (((x) & GENMASK(2, 2)) >> 2)

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_MR */
#define FLEXCOM_FLEX_US_MR(t)     (t + 0x204)

#define FLEXCOM_FLEX_US_MR_ONEBIT(x)             (((x) << 31) & GENMASK(31, 31))
#define FLEXCOM_FLEX_US_MR_ONEBIT_M              GENMASK(31, 31)
#define FLEXCOM_FLEX_US_MR_ONEBIT_X(x)           (((x) & GENMASK(31, 31)) >> 31)

#define FLEXCOM_FLEX_US_MR_MODSYNC(x)            (((x) << 30) & GENMASK(30, 30))
#define FLEXCOM_FLEX_US_MR_MODSYNC_M             GENMASK(30, 30)
#define FLEXCOM_FLEX_US_MR_MODSYNC_X(x)          (((x) & GENMASK(30, 30)) >> 30)

#define FLEXCOM_FLEX_US_MR_MAN(x)                (((x) << 29) & GENMASK(29, 29))
#define FLEXCOM_FLEX_US_MR_MAN_M                 GENMASK(29, 29)
#define FLEXCOM_FLEX_US_MR_MAN_X(x)              (((x) & GENMASK(29, 29)) >> 29)

#define FLEXCOM_FLEX_US_MR_FILTER(x)             (((x) << 28) & GENMASK(28, 28))
#define FLEXCOM_FLEX_US_MR_FILTER_M              GENMASK(28, 28)
#define FLEXCOM_FLEX_US_MR_FILTER_X(x)           (((x) & GENMASK(28, 28)) >> 28)

#define FLEXCOM_FLEX_US_MR_MAX_ITERATION(x)      (((x) << 24) & GENMASK(26, 24))
#define FLEXCOM_FLEX_US_MR_MAX_ITERATION_M       GENMASK(26, 24)
#define FLEXCOM_FLEX_US_MR_MAX_ITERATION_X(x)    (((x) & GENMASK(26, 24)) >> 24)

#define FLEXCOM_FLEX_US_MR_INVDATA(x)            (((x) << 23) & GENMASK(23, 23))
#define FLEXCOM_FLEX_US_MR_INVDATA_M             GENMASK(23, 23)
#define FLEXCOM_FLEX_US_MR_INVDATA_X(x)          (((x) & GENMASK(23, 23)) >> 23)

#define FLEXCOM_FLEX_US_MR_VAR_SYNC(x)           (((x) << 22) & GENMASK(22, 22))
#define FLEXCOM_FLEX_US_MR_VAR_SYNC_M            GENMASK(22, 22)
#define FLEXCOM_FLEX_US_MR_VAR_SYNC_X(x)         (((x) & GENMASK(22, 22)) >> 22)

#define FLEXCOM_FLEX_US_MR_DSNACK(x)             (((x) << 21) & GENMASK(21, 21))
#define FLEXCOM_FLEX_US_MR_DSNACK_M              GENMASK(21, 21)
#define FLEXCOM_FLEX_US_MR_DSNACK_X(x)           (((x) & GENMASK(21, 21)) >> 21)

#define FLEXCOM_FLEX_US_MR_INACK(x)              (((x) << 20) & GENMASK(20, 20))
#define FLEXCOM_FLEX_US_MR_INACK_M               GENMASK(20, 20)
#define FLEXCOM_FLEX_US_MR_INACK_X(x)            (((x) & GENMASK(20, 20)) >> 20)

#define FLEXCOM_FLEX_US_MR_OVER(x)               (((x) << 19) & GENMASK(19, 19))
#define FLEXCOM_FLEX_US_MR_OVER_M                GENMASK(19, 19)
#define FLEXCOM_FLEX_US_MR_OVER_X(x)             (((x) & GENMASK(19, 19)) >> 19)

#define FLEXCOM_FLEX_US_MR_CLKO(x)               (((x) << 18) & GENMASK(18, 18))
#define FLEXCOM_FLEX_US_MR_CLKO_M                GENMASK(18, 18)
#define FLEXCOM_FLEX_US_MR_CLKO_X(x)             (((x) & GENMASK(18, 18)) >> 18)

#define FLEXCOM_FLEX_US_MR_MODE9(x)              (((x) << 17) & GENMASK(17, 17))
#define FLEXCOM_FLEX_US_MR_MODE9_M               GENMASK(17, 17)
#define FLEXCOM_FLEX_US_MR_MODE9_X(x)            (((x) & GENMASK(17, 17)) >> 17)

#define FLEXCOM_FLEX_US_MR_MSBF(x)               (((x) << 16) & GENMASK(16, 16))
#define FLEXCOM_FLEX_US_MR_MSBF_M                GENMASK(16, 16)
#define FLEXCOM_FLEX_US_MR_MSBF_X(x)             (((x) & GENMASK(16, 16)) >> 16)

#define FLEXCOM_FLEX_US_MR_CHMODE(x)             (((x) << 14) & GENMASK(15, 14))
#define FLEXCOM_FLEX_US_MR_CHMODE_M              GENMASK(15, 14)
#define FLEXCOM_FLEX_US_MR_CHMODE_X(x)           (((x) & GENMASK(15, 14)) >> 14)

#define FLEXCOM_FLEX_US_MR_NBSTOP(x)             (((x) << 12) & GENMASK(13, 12))
#define FLEXCOM_FLEX_US_MR_NBSTOP_M              GENMASK(13, 12)
#define FLEXCOM_FLEX_US_MR_NBSTOP_X(x)           (((x) & GENMASK(13, 12)) >> 12)

#define FLEXCOM_FLEX_US_MR_PAR(x)                (((x) << 9) & GENMASK(11, 9))
#define FLEXCOM_FLEX_US_MR_PAR_M                 GENMASK(11, 9)
#define FLEXCOM_FLEX_US_MR_PAR_X(x)              (((x) & GENMASK(11, 9)) >> 9)

#define FLEXCOM_FLEX_US_MR_SYNC(x)               (((x) << 8) & GENMASK(8, 8))
#define FLEXCOM_FLEX_US_MR_SYNC_M                GENMASK(8, 8)
#define FLEXCOM_FLEX_US_MR_SYNC_X(x)             (((x) & GENMASK(8, 8)) >> 8)

#define FLEXCOM_FLEX_US_MR_CHRL(x)               (((x) << 6) & GENMASK(7, 6))
#define FLEXCOM_FLEX_US_MR_CHRL_M                GENMASK(7, 6)
#define FLEXCOM_FLEX_US_MR_CHRL_X(x)             (((x) & GENMASK(7, 6)) >> 6)

#define FLEXCOM_FLEX_US_MR_USCLKS(x)             (((x) << 4) & GENMASK(5, 4))
#define FLEXCOM_FLEX_US_MR_USCLKS_M              GENMASK(5, 4)
#define FLEXCOM_FLEX_US_MR_USCLKS_X(x)           (((x) & GENMASK(5, 4)) >> 4)

#define FLEXCOM_FLEX_US_MR_USART_MODE(x)         ((x) & GENMASK(3, 0))
#define FLEXCOM_FLEX_US_MR_USART_MODE_M          GENMASK(3, 0)
#define FLEXCOM_FLEX_US_MR_USART_MODE_X(x)       ((x) & GENMASK(3, 0))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_IER */
#define FLEXCOM_FLEX_US_IER(t)    (t + 0x208)

#define FLEXCOM_FLEX_US_IER_MANE_IE(x)           (((x) << 24) & GENMASK(24, 24))
#define FLEXCOM_FLEX_US_IER_MANE_IE_M            GENMASK(24, 24)
#define FLEXCOM_FLEX_US_IER_MANE_IE_X(x)         (((x) & GENMASK(24, 24)) >> 24)

#define FLEXCOM_FLEX_US_IER_CMP_IE(x)            (((x) << 22) & GENMASK(22, 22))
#define FLEXCOM_FLEX_US_IER_CMP_IE_M             GENMASK(22, 22)
#define FLEXCOM_FLEX_US_IER_CMP_IE_X(x)          (((x) & GENMASK(22, 22)) >> 22)

#define FLEXCOM_FLEX_US_IER_CTSIC_IE(x)          (((x) << 19) & GENMASK(19, 19))
#define FLEXCOM_FLEX_US_IER_CTSIC_IE_M           GENMASK(19, 19)
#define FLEXCOM_FLEX_US_IER_CTSIC_IE_X(x)        (((x) & GENMASK(19, 19)) >> 19)

#define FLEXCOM_FLEX_US_IER_DCDIC_IE(x)          (((x) << 18) & GENMASK(18, 18))
#define FLEXCOM_FLEX_US_IER_DCDIC_IE_M           GENMASK(18, 18)
#define FLEXCOM_FLEX_US_IER_DCDIC_IE_X(x)        (((x) & GENMASK(18, 18)) >> 18)

#define FLEXCOM_FLEX_US_IER_DSRIC_IE(x)          (((x) << 17) & GENMASK(17, 17))
#define FLEXCOM_FLEX_US_IER_DSRIC_IE_M           GENMASK(17, 17)
#define FLEXCOM_FLEX_US_IER_DSRIC_IE_X(x)        (((x) & GENMASK(17, 17)) >> 17)

#define FLEXCOM_FLEX_US_IER_RIIC_IE(x)           (((x) << 16) & GENMASK(16, 16))
#define FLEXCOM_FLEX_US_IER_RIIC_IE_M            GENMASK(16, 16)
#define FLEXCOM_FLEX_US_IER_RIIC_IE_X(x)         (((x) & GENMASK(16, 16)) >> 16)

#define FLEXCOM_FLEX_US_IER_NACK_IE(x)           (((x) << 13) & GENMASK(13, 13))
#define FLEXCOM_FLEX_US_IER_NACK_IE_M            GENMASK(13, 13)
#define FLEXCOM_FLEX_US_IER_NACK_IE_X(x)         (((x) & GENMASK(13, 13)) >> 13)

#define FLEXCOM_FLEX_US_IER_RXBUFF_IE(x)         (((x) << 12) & GENMASK(12, 12))
#define FLEXCOM_FLEX_US_IER_RXBUFF_IE_M          GENMASK(12, 12)
#define FLEXCOM_FLEX_US_IER_RXBUFF_IE_X(x)       (((x) & GENMASK(12, 12)) >> 12)

#define FLEXCOM_FLEX_US_IER_TXBUFE_IE(x)         (((x) << 11) & GENMASK(11, 11))
#define FLEXCOM_FLEX_US_IER_TXBUFE_IE_M          GENMASK(11, 11)
#define FLEXCOM_FLEX_US_IER_TXBUFE_IE_X(x)       (((x) & GENMASK(11, 11)) >> 11)

#define FLEXCOM_FLEX_US_IER_ITER_IE(x)           (((x) << 10) & GENMASK(10, 10))
#define FLEXCOM_FLEX_US_IER_ITER_IE_M            GENMASK(10, 10)
#define FLEXCOM_FLEX_US_IER_ITER_IE_X(x)         (((x) & GENMASK(10, 10)) >> 10)

#define FLEXCOM_FLEX_US_IER_TXEMPTY_IE(x)        (((x) << 9) & GENMASK(9, 9))
#define FLEXCOM_FLEX_US_IER_TXEMPTY_IE_M         GENMASK(9, 9)
#define FLEXCOM_FLEX_US_IER_TXEMPTY_IE_X(x)      (((x) & GENMASK(9, 9)) >> 9)

#define FLEXCOM_FLEX_US_IER_TIMEOUT_IE(x)        (((x) << 8) & GENMASK(8, 8))
#define FLEXCOM_FLEX_US_IER_TIMEOUT_IE_M         GENMASK(8, 8)
#define FLEXCOM_FLEX_US_IER_TIMEOUT_IE_X(x)      (((x) & GENMASK(8, 8)) >> 8)

#define FLEXCOM_FLEX_US_IER_PARE_IE(x)           (((x) << 7) & GENMASK(7, 7))
#define FLEXCOM_FLEX_US_IER_PARE_IE_M            GENMASK(7, 7)
#define FLEXCOM_FLEX_US_IER_PARE_IE_X(x)         (((x) & GENMASK(7, 7)) >> 7)

#define FLEXCOM_FLEX_US_IER_FRAME_IE(x)          (((x) << 6) & GENMASK(6, 6))
#define FLEXCOM_FLEX_US_IER_FRAME_IE_M           GENMASK(6, 6)
#define FLEXCOM_FLEX_US_IER_FRAME_IE_X(x)        (((x) & GENMASK(6, 6)) >> 6)

#define FLEXCOM_FLEX_US_IER_OVRE_IE(x)           (((x) << 5) & GENMASK(5, 5))
#define FLEXCOM_FLEX_US_IER_OVRE_IE_M            GENMASK(5, 5)
#define FLEXCOM_FLEX_US_IER_OVRE_IE_X(x)         (((x) & GENMASK(5, 5)) >> 5)

#define FLEXCOM_FLEX_US_IER_ENDTX_IE(x)          (((x) << 4) & GENMASK(4, 4))
#define FLEXCOM_FLEX_US_IER_ENDTX_IE_M           GENMASK(4, 4)
#define FLEXCOM_FLEX_US_IER_ENDTX_IE_X(x)        (((x) & GENMASK(4, 4)) >> 4)

#define FLEXCOM_FLEX_US_IER_ENDRX_IE(x)          (((x) << 3) & GENMASK(3, 3))
#define FLEXCOM_FLEX_US_IER_ENDRX_IE_M           GENMASK(3, 3)
#define FLEXCOM_FLEX_US_IER_ENDRX_IE_X(x)        (((x) & GENMASK(3, 3)) >> 3)

#define FLEXCOM_FLEX_US_IER_RXBRK_IE(x)          (((x) << 2) & GENMASK(2, 2))
#define FLEXCOM_FLEX_US_IER_RXBRK_IE_M           GENMASK(2, 2)
#define FLEXCOM_FLEX_US_IER_RXBRK_IE_X(x)        (((x) & GENMASK(2, 2)) >> 2)

#define FLEXCOM_FLEX_US_IER_TXRDY_IE(x)          (((x) << 1) & GENMASK(1, 1))
#define FLEXCOM_FLEX_US_IER_TXRDY_IE_M           GENMASK(1, 1)
#define FLEXCOM_FLEX_US_IER_TXRDY_IE_X(x)        (((x) & GENMASK(1, 1)) >> 1)

#define FLEXCOM_FLEX_US_IER_RXRDY_IE(x)          ((x) & GENMASK(0, 0))
#define FLEXCOM_FLEX_US_IER_RXRDY_IE_M           GENMASK(0, 0)
#define FLEXCOM_FLEX_US_IER_RXRDY_IE_X(x)        ((x) & GENMASK(0, 0))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_IDR */
#define FLEXCOM_FLEX_US_IDR(t)    (t + 0x20c)

#define FLEXCOM_FLEX_US_IDR_MANE_ID(x)           (((x) << 24) & GENMASK(24, 24))
#define FLEXCOM_FLEX_US_IDR_MANE_ID_M            GENMASK(24, 24)
#define FLEXCOM_FLEX_US_IDR_MANE_ID_X(x)         (((x) & GENMASK(24, 24)) >> 24)

#define FLEXCOM_FLEX_US_IDR_CMP_ID(x)            (((x) << 22) & GENMASK(22, 22))
#define FLEXCOM_FLEX_US_IDR_CMP_ID_M             GENMASK(22, 22)
#define FLEXCOM_FLEX_US_IDR_CMP_ID_X(x)          (((x) & GENMASK(22, 22)) >> 22)

#define FLEXCOM_FLEX_US_IDR_CTSIC_ID(x)          (((x) << 19) & GENMASK(19, 19))
#define FLEXCOM_FLEX_US_IDR_CTSIC_ID_M           GENMASK(19, 19)
#define FLEXCOM_FLEX_US_IDR_CTSIC_ID_X(x)        (((x) & GENMASK(19, 19)) >> 19)

#define FLEXCOM_FLEX_US_IDR_DCDIC_ID(x)          (((x) << 18) & GENMASK(18, 18))
#define FLEXCOM_FLEX_US_IDR_DCDIC_ID_M           GENMASK(18, 18)
#define FLEXCOM_FLEX_US_IDR_DCDIC_ID_X(x)        (((x) & GENMASK(18, 18)) >> 18)

#define FLEXCOM_FLEX_US_IDR_DSRIC_ID(x)          (((x) << 17) & GENMASK(17, 17))
#define FLEXCOM_FLEX_US_IDR_DSRIC_ID_M           GENMASK(17, 17)
#define FLEXCOM_FLEX_US_IDR_DSRIC_ID_X(x)        (((x) & GENMASK(17, 17)) >> 17)

#define FLEXCOM_FLEX_US_IDR_RIIC_ID(x)           (((x) << 16) & GENMASK(16, 16))
#define FLEXCOM_FLEX_US_IDR_RIIC_ID_M            GENMASK(16, 16)
#define FLEXCOM_FLEX_US_IDR_RIIC_ID_X(x)         (((x) & GENMASK(16, 16)) >> 16)

#define FLEXCOM_FLEX_US_IDR_NACK_ID(x)           (((x) << 13) & GENMASK(13, 13))
#define FLEXCOM_FLEX_US_IDR_NACK_ID_M            GENMASK(13, 13)
#define FLEXCOM_FLEX_US_IDR_NACK_ID_X(x)         (((x) & GENMASK(13, 13)) >> 13)

#define FLEXCOM_FLEX_US_IDR_RXBUFF_ID(x)         (((x) << 12) & GENMASK(12, 12))
#define FLEXCOM_FLEX_US_IDR_RXBUFF_ID_M          GENMASK(12, 12)
#define FLEXCOM_FLEX_US_IDR_RXBUFF_ID_X(x)       (((x) & GENMASK(12, 12)) >> 12)

#define FLEXCOM_FLEX_US_IDR_TXBUFE_ID(x)         (((x) << 11) & GENMASK(11, 11))
#define FLEXCOM_FLEX_US_IDR_TXBUFE_ID_M          GENMASK(11, 11)
#define FLEXCOM_FLEX_US_IDR_TXBUFE_ID_X(x)       (((x) & GENMASK(11, 11)) >> 11)

#define FLEXCOM_FLEX_US_IDR_ITER_ID(x)           (((x) << 10) & GENMASK(10, 10))
#define FLEXCOM_FLEX_US_IDR_ITER_ID_M            GENMASK(10, 10)
#define FLEXCOM_FLEX_US_IDR_ITER_ID_X(x)         (((x) & GENMASK(10, 10)) >> 10)

#define FLEXCOM_FLEX_US_IDR_TXEMPTY_ID(x)        (((x) << 9) & GENMASK(9, 9))
#define FLEXCOM_FLEX_US_IDR_TXEMPTY_ID_M         GENMASK(9, 9)
#define FLEXCOM_FLEX_US_IDR_TXEMPTY_ID_X(x)      (((x) & GENMASK(9, 9)) >> 9)

#define FLEXCOM_FLEX_US_IDR_TIMEOUT_ID(x)        (((x) << 8) & GENMASK(8, 8))
#define FLEXCOM_FLEX_US_IDR_TIMEOUT_ID_M         GENMASK(8, 8)
#define FLEXCOM_FLEX_US_IDR_TIMEOUT_ID_X(x)      (((x) & GENMASK(8, 8)) >> 8)

#define FLEXCOM_FLEX_US_IDR_PARE_ID(x)           (((x) << 7) & GENMASK(7, 7))
#define FLEXCOM_FLEX_US_IDR_PARE_ID_M            GENMASK(7, 7)
#define FLEXCOM_FLEX_US_IDR_PARE_ID_X(x)         (((x) & GENMASK(7, 7)) >> 7)

#define FLEXCOM_FLEX_US_IDR_FRAME_ID(x)          (((x) << 6) & GENMASK(6, 6))
#define FLEXCOM_FLEX_US_IDR_FRAME_ID_M           GENMASK(6, 6)
#define FLEXCOM_FLEX_US_IDR_FRAME_ID_X(x)        (((x) & GENMASK(6, 6)) >> 6)

#define FLEXCOM_FLEX_US_IDR_OVRE_ID(x)           (((x) << 5) & GENMASK(5, 5))
#define FLEXCOM_FLEX_US_IDR_OVRE_ID_M            GENMASK(5, 5)
#define FLEXCOM_FLEX_US_IDR_OVRE_ID_X(x)         (((x) & GENMASK(5, 5)) >> 5)

#define FLEXCOM_FLEX_US_IDR_ENDTX_ID(x)          (((x) << 4) & GENMASK(4, 4))
#define FLEXCOM_FLEX_US_IDR_ENDTX_ID_M           GENMASK(4, 4)
#define FLEXCOM_FLEX_US_IDR_ENDTX_ID_X(x)        (((x) & GENMASK(4, 4)) >> 4)

#define FLEXCOM_FLEX_US_IDR_ENDRX_ID(x)          (((x) << 3) & GENMASK(3, 3))
#define FLEXCOM_FLEX_US_IDR_ENDRX_ID_M           GENMASK(3, 3)
#define FLEXCOM_FLEX_US_IDR_ENDRX_ID_X(x)        (((x) & GENMASK(3, 3)) >> 3)

#define FLEXCOM_FLEX_US_IDR_RXBRK_ID(x)          (((x) << 2) & GENMASK(2, 2))
#define FLEXCOM_FLEX_US_IDR_RXBRK_ID_M           GENMASK(2, 2)
#define FLEXCOM_FLEX_US_IDR_RXBRK_ID_X(x)        (((x) & GENMASK(2, 2)) >> 2)

#define FLEXCOM_FLEX_US_IDR_TXRDY_ID(x)          (((x) << 1) & GENMASK(1, 1))
#define FLEXCOM_FLEX_US_IDR_TXRDY_ID_M           GENMASK(1, 1)
#define FLEXCOM_FLEX_US_IDR_TXRDY_ID_X(x)        (((x) & GENMASK(1, 1)) >> 1)

#define FLEXCOM_FLEX_US_IDR_RXRDY_ID(x)          ((x) & GENMASK(0, 0))
#define FLEXCOM_FLEX_US_IDR_RXRDY_ID_M           GENMASK(0, 0)
#define FLEXCOM_FLEX_US_IDR_RXRDY_ID_X(x)        ((x) & GENMASK(0, 0))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_IMR */
#define FLEXCOM_FLEX_US_IMR(t)    (t + 0x210)

#define FLEXCOM_FLEX_US_IMR_MANE_IM(x)           (((x) << 24) & GENMASK(24, 24))
#define FLEXCOM_FLEX_US_IMR_MANE_IM_M            GENMASK(24, 24)
#define FLEXCOM_FLEX_US_IMR_MANE_IM_X(x)         (((x) & GENMASK(24, 24)) >> 24)

#define FLEXCOM_FLEX_US_IMR_CMP_IM(x)            (((x) << 22) & GENMASK(22, 22))
#define FLEXCOM_FLEX_US_IMR_CMP_IM_M             GENMASK(22, 22)
#define FLEXCOM_FLEX_US_IMR_CMP_IM_X(x)          (((x) & GENMASK(22, 22)) >> 22)

#define FLEXCOM_FLEX_US_IMR_CTSIC_IM(x)          (((x) << 19) & GENMASK(19, 19))
#define FLEXCOM_FLEX_US_IMR_CTSIC_IM_M           GENMASK(19, 19)
#define FLEXCOM_FLEX_US_IMR_CTSIC_IM_X(x)        (((x) & GENMASK(19, 19)) >> 19)

#define FLEXCOM_FLEX_US_IMR_DCDIC_IM(x)          (((x) << 18) & GENMASK(18, 18))
#define FLEXCOM_FLEX_US_IMR_DCDIC_IM_M           GENMASK(18, 18)
#define FLEXCOM_FLEX_US_IMR_DCDIC_IM_X(x)        (((x) & GENMASK(18, 18)) >> 18)

#define FLEXCOM_FLEX_US_IMR_DSRIC_IM(x)          (((x) << 17) & GENMASK(17, 17))
#define FLEXCOM_FLEX_US_IMR_DSRIC_IM_M           GENMASK(17, 17)
#define FLEXCOM_FLEX_US_IMR_DSRIC_IM_X(x)        (((x) & GENMASK(17, 17)) >> 17)

#define FLEXCOM_FLEX_US_IMR_RIIC_IM(x)           (((x) << 16) & GENMASK(16, 16))
#define FLEXCOM_FLEX_US_IMR_RIIC_IM_M            GENMASK(16, 16)
#define FLEXCOM_FLEX_US_IMR_RIIC_IM_X(x)         (((x) & GENMASK(16, 16)) >> 16)

#define FLEXCOM_FLEX_US_IMR_NACK_IM(x)           (((x) << 13) & GENMASK(13, 13))
#define FLEXCOM_FLEX_US_IMR_NACK_IM_M            GENMASK(13, 13)
#define FLEXCOM_FLEX_US_IMR_NACK_IM_X(x)         (((x) & GENMASK(13, 13)) >> 13)

#define FLEXCOM_FLEX_US_IMR_RXBUFF_IM(x)         (((x) << 12) & GENMASK(12, 12))
#define FLEXCOM_FLEX_US_IMR_RXBUFF_IM_M          GENMASK(12, 12)
#define FLEXCOM_FLEX_US_IMR_RXBUFF_IM_X(x)       (((x) & GENMASK(12, 12)) >> 12)

#define FLEXCOM_FLEX_US_IMR_TXBUFE_IM(x)         (((x) << 11) & GENMASK(11, 11))
#define FLEXCOM_FLEX_US_IMR_TXBUFE_IM_M          GENMASK(11, 11)
#define FLEXCOM_FLEX_US_IMR_TXBUFE_IM_X(x)       (((x) & GENMASK(11, 11)) >> 11)

#define FLEXCOM_FLEX_US_IMR_ITER_IM(x)           (((x) << 10) & GENMASK(10, 10))
#define FLEXCOM_FLEX_US_IMR_ITER_IM_M            GENMASK(10, 10)
#define FLEXCOM_FLEX_US_IMR_ITER_IM_X(x)         (((x) & GENMASK(10, 10)) >> 10)

#define FLEXCOM_FLEX_US_IMR_TXEMPTY_IM(x)        (((x) << 9) & GENMASK(9, 9))
#define FLEXCOM_FLEX_US_IMR_TXEMPTY_IM_M         GENMASK(9, 9)
#define FLEXCOM_FLEX_US_IMR_TXEMPTY_IM_X(x)      (((x) & GENMASK(9, 9)) >> 9)

#define FLEXCOM_FLEX_US_IMR_TIMEOUT_IM(x)        (((x) << 8) & GENMASK(8, 8))
#define FLEXCOM_FLEX_US_IMR_TIMEOUT_IM_M         GENMASK(8, 8)
#define FLEXCOM_FLEX_US_IMR_TIMEOUT_IM_X(x)      (((x) & GENMASK(8, 8)) >> 8)

#define FLEXCOM_FLEX_US_IMR_PARE_IM(x)           (((x) << 7) & GENMASK(7, 7))
#define FLEXCOM_FLEX_US_IMR_PARE_IM_M            GENMASK(7, 7)
#define FLEXCOM_FLEX_US_IMR_PARE_IM_X(x)         (((x) & GENMASK(7, 7)) >> 7)

#define FLEXCOM_FLEX_US_IMR_FRAME_IM(x)          (((x) << 6) & GENMASK(6, 6))
#define FLEXCOM_FLEX_US_IMR_FRAME_IM_M           GENMASK(6, 6)
#define FLEXCOM_FLEX_US_IMR_FRAME_IM_X(x)        (((x) & GENMASK(6, 6)) >> 6)

#define FLEXCOM_FLEX_US_IMR_OVRE_IM(x)           (((x) << 5) & GENMASK(5, 5))
#define FLEXCOM_FLEX_US_IMR_OVRE_IM_M            GENMASK(5, 5)
#define FLEXCOM_FLEX_US_IMR_OVRE_IM_X(x)         (((x) & GENMASK(5, 5)) >> 5)

#define FLEXCOM_FLEX_US_IMR_ENDTX_IM(x)          (((x) << 4) & GENMASK(4, 4))
#define FLEXCOM_FLEX_US_IMR_ENDTX_IM_M           GENMASK(4, 4)
#define FLEXCOM_FLEX_US_IMR_ENDTX_IM_X(x)        (((x) & GENMASK(4, 4)) >> 4)

#define FLEXCOM_FLEX_US_IMR_ENDRX_IM(x)          (((x) << 3) & GENMASK(3, 3))
#define FLEXCOM_FLEX_US_IMR_ENDRX_IM_M           GENMASK(3, 3)
#define FLEXCOM_FLEX_US_IMR_ENDRX_IM_X(x)        (((x) & GENMASK(3, 3)) >> 3)

#define FLEXCOM_FLEX_US_IMR_RXBRK_IM(x)          (((x) << 2) & GENMASK(2, 2))
#define FLEXCOM_FLEX_US_IMR_RXBRK_IM_M           GENMASK(2, 2)
#define FLEXCOM_FLEX_US_IMR_RXBRK_IM_X(x)        (((x) & GENMASK(2, 2)) >> 2)

#define FLEXCOM_FLEX_US_IMR_TXRDY_IM(x)          (((x) << 1) & GENMASK(1, 1))
#define FLEXCOM_FLEX_US_IMR_TXRDY_IM_M           GENMASK(1, 1)
#define FLEXCOM_FLEX_US_IMR_TXRDY_IM_X(x)        (((x) & GENMASK(1, 1)) >> 1)

#define FLEXCOM_FLEX_US_IMR_RXRDY_IM(x)          ((x) & GENMASK(0, 0))
#define FLEXCOM_FLEX_US_IMR_RXRDY_IM_M           GENMASK(0, 0)
#define FLEXCOM_FLEX_US_IMR_RXRDY_IM_X(x)        ((x) & GENMASK(0, 0))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_CSR */
#define FLEXCOM_FLEX_US_CSR(t)    (t + 0x214)

#define FLEXCOM_FLEX_US_CSR_MANE(x)              (((x) << 24) & GENMASK(24, 24))
#define FLEXCOM_FLEX_US_CSR_MANE_M               GENMASK(24, 24)
#define FLEXCOM_FLEX_US_CSR_MANE_X(x)            (((x) & GENMASK(24, 24)) >> 24)

#define FLEXCOM_FLEX_US_CSR_CTS(x)               (((x) << 23) & GENMASK(23, 23))
#define FLEXCOM_FLEX_US_CSR_CTS_M                GENMASK(23, 23)
#define FLEXCOM_FLEX_US_CSR_CTS_X(x)             (((x) & GENMASK(23, 23)) >> 23)

#define FLEXCOM_FLEX_US_CSR_CMP(x)               (((x) << 22) & GENMASK(22, 22))
#define FLEXCOM_FLEX_US_CSR_CMP_M                GENMASK(22, 22)
#define FLEXCOM_FLEX_US_CSR_CMP_X(x)             (((x) & GENMASK(22, 22)) >> 22)

#define FLEXCOM_FLEX_US_CSR_CTSIC(x)             (((x) << 19) & GENMASK(19, 19))
#define FLEXCOM_FLEX_US_CSR_CTSIC_M              GENMASK(19, 19)
#define FLEXCOM_FLEX_US_CSR_CTSIC_X(x)           (((x) & GENMASK(19, 19)) >> 19)

#define FLEXCOM_FLEX_US_CSR_DCDIC(x)             (((x) << 18) & GENMASK(18, 18))
#define FLEXCOM_FLEX_US_CSR_DCDIC_M              GENMASK(18, 18)
#define FLEXCOM_FLEX_US_CSR_DCDIC_X(x)           (((x) & GENMASK(18, 18)) >> 18)

#define FLEXCOM_FLEX_US_CSR_DSRIC(x)             (((x) << 17) & GENMASK(17, 17))
#define FLEXCOM_FLEX_US_CSR_DSRIC_M              GENMASK(17, 17)
#define FLEXCOM_FLEX_US_CSR_DSRIC_X(x)           (((x) & GENMASK(17, 17)) >> 17)

#define FLEXCOM_FLEX_US_CSR_RIIC(x)              (((x) << 16) & GENMASK(16, 16))
#define FLEXCOM_FLEX_US_CSR_RIIC_M               GENMASK(16, 16)
#define FLEXCOM_FLEX_US_CSR_RIIC_X(x)            (((x) & GENMASK(16, 16)) >> 16)

#define FLEXCOM_FLEX_US_CSR_NACK(x)              (((x) << 13) & GENMASK(13, 13))
#define FLEXCOM_FLEX_US_CSR_NACK_M               GENMASK(13, 13)
#define FLEXCOM_FLEX_US_CSR_NACK_X(x)            (((x) & GENMASK(13, 13)) >> 13)

#define FLEXCOM_FLEX_US_CSR_RXBUFF(x)            (((x) << 12) & GENMASK(12, 12))
#define FLEXCOM_FLEX_US_CSR_RXBUFF_M             GENMASK(12, 12)
#define FLEXCOM_FLEX_US_CSR_RXBUFF_X(x)          (((x) & GENMASK(12, 12)) >> 12)

#define FLEXCOM_FLEX_US_CSR_TXBUFE(x)            (((x) << 11) & GENMASK(11, 11))
#define FLEXCOM_FLEX_US_CSR_TXBUFE_M             GENMASK(11, 11)
#define FLEXCOM_FLEX_US_CSR_TXBUFE_X(x)          (((x) & GENMASK(11, 11)) >> 11)

#define FLEXCOM_FLEX_US_CSR_ITER(x)              (((x) << 10) & GENMASK(10, 10))
#define FLEXCOM_FLEX_US_CSR_ITER_M               GENMASK(10, 10)
#define FLEXCOM_FLEX_US_CSR_ITER_X(x)            (((x) & GENMASK(10, 10)) >> 10)

#define FLEXCOM_FLEX_US_CSR_TXEMPTY(x)           (((x) << 9) & GENMASK(9, 9))
#define FLEXCOM_FLEX_US_CSR_TXEMPTY_M            GENMASK(9, 9)
#define FLEXCOM_FLEX_US_CSR_TXEMPTY_X(x)         (((x) & GENMASK(9, 9)) >> 9)

#define FLEXCOM_FLEX_US_CSR_TIMEOUT(x)           (((x) << 8) & GENMASK(8, 8))
#define FLEXCOM_FLEX_US_CSR_TIMEOUT_M            GENMASK(8, 8)
#define FLEXCOM_FLEX_US_CSR_TIMEOUT_X(x)         (((x) & GENMASK(8, 8)) >> 8)

#define FLEXCOM_FLEX_US_CSR_PARE(x)              (((x) << 7) & GENMASK(7, 7))
#define FLEXCOM_FLEX_US_CSR_PARE_M               GENMASK(7, 7)
#define FLEXCOM_FLEX_US_CSR_PARE_X(x)            (((x) & GENMASK(7, 7)) >> 7)

#define FLEXCOM_FLEX_US_CSR_FRAME(x)             (((x) << 6) & GENMASK(6, 6))
#define FLEXCOM_FLEX_US_CSR_FRAME_M              GENMASK(6, 6)
#define FLEXCOM_FLEX_US_CSR_FRAME_X(x)           (((x) & GENMASK(6, 6)) >> 6)

#define FLEXCOM_FLEX_US_CSR_OVRE(x)              (((x) << 5) & GENMASK(5, 5))
#define FLEXCOM_FLEX_US_CSR_OVRE_M               GENMASK(5, 5)
#define FLEXCOM_FLEX_US_CSR_OVRE_X(x)            (((x) & GENMASK(5, 5)) >> 5)

#define FLEXCOM_FLEX_US_CSR_ENDTX(x)             (((x) << 4) & GENMASK(4, 4))
#define FLEXCOM_FLEX_US_CSR_ENDTX_M              GENMASK(4, 4)
#define FLEXCOM_FLEX_US_CSR_ENDTX_X(x)           (((x) & GENMASK(4, 4)) >> 4)

#define FLEXCOM_FLEX_US_CSR_ENDRX(x)             (((x) << 3) & GENMASK(3, 3))
#define FLEXCOM_FLEX_US_CSR_ENDRX_M              GENMASK(3, 3)
#define FLEXCOM_FLEX_US_CSR_ENDRX_X(x)           (((x) & GENMASK(3, 3)) >> 3)

#define FLEXCOM_FLEX_US_CSR_RXBRK(x)             (((x) << 2) & GENMASK(2, 2))
#define FLEXCOM_FLEX_US_CSR_RXBRK_M              GENMASK(2, 2)
#define FLEXCOM_FLEX_US_CSR_RXBRK_X(x)           (((x) & GENMASK(2, 2)) >> 2)

#define FLEXCOM_FLEX_US_CSR_TXRDY(x)             (((x) << 1) & GENMASK(1, 1))
#define FLEXCOM_FLEX_US_CSR_TXRDY_M              GENMASK(1, 1)
#define FLEXCOM_FLEX_US_CSR_TXRDY_X(x)           (((x) & GENMASK(1, 1)) >> 1)

#define FLEXCOM_FLEX_US_CSR_RXRDY(x)             ((x) & GENMASK(0, 0))
#define FLEXCOM_FLEX_US_CSR_RXRDY_M              GENMASK(0, 0)
#define FLEXCOM_FLEX_US_CSR_RXRDY_X(x)           ((x) & GENMASK(0, 0))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_RHR */
#define FLEXCOM_FLEX_US_RHR(t)    (t + 0x218)

#define FLEXCOM_FLEX_US_RHR_RXSYNH(x)            (((x) << 15) & GENMASK(15, 15))
#define FLEXCOM_FLEX_US_RHR_RXSYNH_M             GENMASK(15, 15)
#define FLEXCOM_FLEX_US_RHR_RXSYNH_X(x)          (((x) & GENMASK(15, 15)) >> 15)

#define FLEXCOM_FLEX_US_RHR_RXCHR(x)             ((x) & GENMASK(7, 0))
#define FLEXCOM_FLEX_US_RHR_RXCHR_M              GENMASK(7, 0)
#define FLEXCOM_FLEX_US_RHR_RXCHR_X(x)           ((x) & GENMASK(7, 0))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_FMT_RHR */
#define FLEXCOM_FLEX_US_FMT_RHR(t) (t + 0x218)

#define FLEXCOM_FLEX_US_FMT_RHR_RXCHR3(x)        (((x) << 24) & GENMASK(31, 24))
#define FLEXCOM_FLEX_US_FMT_RHR_RXCHR3_M         GENMASK(31, 24)
#define FLEXCOM_FLEX_US_FMT_RHR_RXCHR3_X(x)      (((x) & GENMASK(31, 24)) >> 24)

#define FLEXCOM_FLEX_US_FMT_RHR_RXCHR2(x)        (((x) << 16) & GENMASK(23, 16))
#define FLEXCOM_FLEX_US_FMT_RHR_RXCHR2_M         GENMASK(23, 16)
#define FLEXCOM_FLEX_US_FMT_RHR_RXCHR2_X(x)      (((x) & GENMASK(23, 16)) >> 16)

#define FLEXCOM_FLEX_US_FMT_RHR_RXCHR1(x)        (((x) << 8) & GENMASK(15, 8))
#define FLEXCOM_FLEX_US_FMT_RHR_RXCHR1_M         GENMASK(15, 8)
#define FLEXCOM_FLEX_US_FMT_RHR_RXCHR1_X(x)      (((x) & GENMASK(15, 8)) >> 8)

#define FLEXCOM_FLEX_US_FMT_RHR_RXCHR0(x)        ((x) & GENMASK(7, 0))
#define FLEXCOM_FLEX_US_FMT_RHR_RXCHR0_M         GENMASK(7, 0)
#define FLEXCOM_FLEX_US_FMT_RHR_RXCHR0_X(x)      ((x) & GENMASK(7, 0))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_THR */
#define FLEXCOM_FLEX_US_THR(t)    (t + 0x21c)

#define FLEXCOM_FLEX_US_THR_TXSYNH(x)            (((x) << 15) & GENMASK(15, 15))
#define FLEXCOM_FLEX_US_THR_TXSYNH_M             GENMASK(15, 15)
#define FLEXCOM_FLEX_US_THR_TXSYNH_X(x)          (((x) & GENMASK(15, 15)) >> 15)

#define FLEXCOM_FLEX_US_THR_TXCHR(x)             ((x) & GENMASK(8, 0))
#define FLEXCOM_FLEX_US_THR_TXCHR_M              GENMASK(8, 0)
#define FLEXCOM_FLEX_US_THR_TXCHR_X(x)           ((x) & GENMASK(8, 0))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_FMT_THR */
#define FLEXCOM_FLEX_US_FMT_THR(t) (t + 0x21c)

#define FLEXCOM_FLEX_US_FMT_THR_TXCHR3(x)        (((x) << 24) & GENMASK(31, 24))
#define FLEXCOM_FLEX_US_FMT_THR_TXCHR3_M         GENMASK(31, 24)
#define FLEXCOM_FLEX_US_FMT_THR_TXCHR3_X(x)      (((x) & GENMASK(31, 24)) >> 24)

#define FLEXCOM_FLEX_US_FMT_THR_TXCHR2(x)        (((x) << 16) & GENMASK(23, 16))
#define FLEXCOM_FLEX_US_FMT_THR_TXCHR2_M         GENMASK(23, 16)
#define FLEXCOM_FLEX_US_FMT_THR_TXCHR2_X(x)      (((x) & GENMASK(23, 16)) >> 16)

#define FLEXCOM_FLEX_US_FMT_THR_TXCHR1(x)        (((x) << 8) & GENMASK(15, 8))
#define FLEXCOM_FLEX_US_FMT_THR_TXCHR1_M         GENMASK(15, 8)
#define FLEXCOM_FLEX_US_FMT_THR_TXCHR1_X(x)      (((x) & GENMASK(15, 8)) >> 8)

#define FLEXCOM_FLEX_US_FMT_THR_TXCHR0(x)        ((x) & GENMASK(7, 0))
#define FLEXCOM_FLEX_US_FMT_THR_TXCHR0_M         GENMASK(7, 0)
#define FLEXCOM_FLEX_US_FMT_THR_TXCHR0_X(x)      ((x) & GENMASK(7, 0))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_BRGR */
#define FLEXCOM_FLEX_US_BRGR(t)   (t + 0x220)

#define FLEXCOM_FLEX_US_BRGR_FP(x)               (((x) << 16) & GENMASK(18, 16))
#define FLEXCOM_FLEX_US_BRGR_FP_M                GENMASK(18, 16)
#define FLEXCOM_FLEX_US_BRGR_FP_X(x)             (((x) & GENMASK(18, 16)) >> 16)

#define FLEXCOM_FLEX_US_BRGR_CD(x)               ((x) & GENMASK(15, 0))
#define FLEXCOM_FLEX_US_BRGR_CD_M                GENMASK(15, 0)
#define FLEXCOM_FLEX_US_BRGR_CD_X(x)             ((x) & GENMASK(15, 0))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_RTOR */
#define FLEXCOM_FLEX_US_RTOR(t)   (t + 0x224)

#define FLEXCOM_FLEX_US_RTOR_TO(x)               ((x) & GENMASK(7, 0))
#define FLEXCOM_FLEX_US_RTOR_TO_M                GENMASK(7, 0)
#define FLEXCOM_FLEX_US_RTOR_TO_X(x)             ((x) & GENMASK(7, 0))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_TTGR */
#define FLEXCOM_FLEX_US_TTGR(t)   (t + 0x228)

#define FLEXCOM_FLEX_US_TTGR_TG(x)               ((x) & GENMASK(7, 0))
#define FLEXCOM_FLEX_US_TTGR_TG_M                GENMASK(7, 0)
#define FLEXCOM_FLEX_US_TTGR_TG_X(x)             ((x) & GENMASK(7, 0))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_MAN */
#define FLEXCOM_FLEX_US_MAN(t)    (t + 0x250)

#define FLEXCOM_FLEX_US_MAN_RXIDLEV(x)           (((x) << 31) & GENMASK(31, 31))
#define FLEXCOM_FLEX_US_MAN_RXIDLEV_M            GENMASK(31, 31)
#define FLEXCOM_FLEX_US_MAN_RXIDLEV_X(x)         (((x) & GENMASK(31, 31)) >> 31)

#define FLEXCOM_FLEX_US_MAN_DRIFT(x)             (((x) << 30) & GENMASK(30, 30))
#define FLEXCOM_FLEX_US_MAN_DRIFT_M              GENMASK(30, 30)
#define FLEXCOM_FLEX_US_MAN_DRIFT_X(x)           (((x) & GENMASK(30, 30)) >> 30)

#define FLEXCOM_FLEX_US_MAN_ONE(x)               (((x) << 29) & GENMASK(29, 29))
#define FLEXCOM_FLEX_US_MAN_ONE_M                GENMASK(29, 29)
#define FLEXCOM_FLEX_US_MAN_ONE_X(x)             (((x) & GENMASK(29, 29)) >> 29)

#define FLEXCOM_FLEX_US_MAN_RX_MPOL(x)           (((x) << 28) & GENMASK(28, 28))
#define FLEXCOM_FLEX_US_MAN_RX_MPOL_M            GENMASK(28, 28)
#define FLEXCOM_FLEX_US_MAN_RX_MPOL_X(x)         (((x) & GENMASK(28, 28)) >> 28)

#define FLEXCOM_FLEX_US_MAN_RX_PP(x)             (((x) << 24) & GENMASK(25, 24))
#define FLEXCOM_FLEX_US_MAN_RX_PP_M              GENMASK(25, 24)
#define FLEXCOM_FLEX_US_MAN_RX_PP_X(x)           (((x) & GENMASK(25, 24)) >> 24)

#define FLEXCOM_FLEX_US_MAN_RX_PL(x)             (((x) << 16) & GENMASK(19, 16))
#define FLEXCOM_FLEX_US_MAN_RX_PL_M              GENMASK(19, 16)
#define FLEXCOM_FLEX_US_MAN_RX_PL_X(x)           (((x) & GENMASK(19, 16)) >> 16)

#define FLEXCOM_FLEX_US_MAN_TX_MPOL(x)           (((x) << 12) & GENMASK(12, 12))
#define FLEXCOM_FLEX_US_MAN_TX_MPOL_M            GENMASK(12, 12)
#define FLEXCOM_FLEX_US_MAN_TX_MPOL_X(x)         (((x) & GENMASK(12, 12)) >> 12)

#define FLEXCOM_FLEX_US_MAN_TX_PP(x)             (((x) << 8) & GENMASK(9, 8))
#define FLEXCOM_FLEX_US_MAN_TX_PP_M              GENMASK(9, 8)
#define FLEXCOM_FLEX_US_MAN_TX_PP_X(x)           (((x) & GENMASK(9, 8)) >> 8)

#define FLEXCOM_FLEX_US_MAN_TX_PL(x)             ((x) & GENMASK(3, 0))
#define FLEXCOM_FLEX_US_MAN_TX_PL_M              GENMASK(3, 0)
#define FLEXCOM_FLEX_US_MAN_TX_PL_X(x)           ((x) & GENMASK(3, 0))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_CMPR */
#define FLEXCOM_FLEX_US_CMPR(t)   (t + 0x290)

#define FLEXCOM_FLEX_US_CMPR_VAL2(x)             (((x) << 16) & GENMASK(24, 16))
#define FLEXCOM_FLEX_US_CMPR_VAL2_M              GENMASK(24, 16)
#define FLEXCOM_FLEX_US_CMPR_VAL2_X(x)           (((x) & GENMASK(24, 16)) >> 16)

#define FLEXCOM_FLEX_US_CMPR_CMPPAR(x)           (((x) << 14) & GENMASK(14, 14))
#define FLEXCOM_FLEX_US_CMPR_CMPPAR_M            GENMASK(14, 14)
#define FLEXCOM_FLEX_US_CMPR_CMPPAR_X(x)         (((x) & GENMASK(14, 14)) >> 14)

#define FLEXCOM_FLEX_US_CMPR_CMPMODE(x)          (((x) << 12) & GENMASK(13, 12))
#define FLEXCOM_FLEX_US_CMPR_CMPMODE_M           GENMASK(13, 12)
#define FLEXCOM_FLEX_US_CMPR_CMPMODE_X(x)        (((x) & GENMASK(13, 12)) >> 12)

#define FLEXCOM_FLEX_US_CMPR_VAL1(x)             ((x) & GENMASK(8, 0))
#define FLEXCOM_FLEX_US_CMPR_VAL1_M              GENMASK(8, 0)
#define FLEXCOM_FLEX_US_CMPR_VAL1_X(x)           ((x) & GENMASK(8, 0))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_FMR */
#define FLEXCOM_FLEX_US_FMR(t)    (t + 0x2a0)

#define FLEXCOM_FLEX_US_FMR_RXFTHRES2(x)         (((x) << 24) & GENMASK(29, 24))
#define FLEXCOM_FLEX_US_FMR_RXFTHRES2_M          GENMASK(29, 24)
#define FLEXCOM_FLEX_US_FMR_RXFTHRES2_X(x)       (((x) & GENMASK(29, 24)) >> 24)

#define FLEXCOM_FLEX_US_FMR_RXFTHRES(x)          (((x) << 16) & GENMASK(21, 16))
#define FLEXCOM_FLEX_US_FMR_RXFTHRES_M           GENMASK(21, 16)
#define FLEXCOM_FLEX_US_FMR_RXFTHRES_X(x)        (((x) & GENMASK(21, 16)) >> 16)

#define FLEXCOM_FLEX_US_FMR_TXFTHRES(x)          (((x) << 8) & GENMASK(13, 8))
#define FLEXCOM_FLEX_US_FMR_TXFTHRES_M           GENMASK(13, 8)
#define FLEXCOM_FLEX_US_FMR_TXFTHRES_X(x)        (((x) & GENMASK(13, 8)) >> 8)

#define FLEXCOM_FLEX_US_FMR_FRTSC(x)             (((x) << 7) & GENMASK(7, 7))
#define FLEXCOM_FLEX_US_FMR_FRTSC_M              GENMASK(7, 7)
#define FLEXCOM_FLEX_US_FMR_FRTSC_X(x)           (((x) & GENMASK(7, 7)) >> 7)

#define FLEXCOM_FLEX_US_FMR_RXRDYM(x)            (((x) << 4) & GENMASK(5, 4))
#define FLEXCOM_FLEX_US_FMR_RXRDYM_M             GENMASK(5, 4)
#define FLEXCOM_FLEX_US_FMR_RXRDYM_X(x)          (((x) & GENMASK(5, 4)) >> 4)

#define FLEXCOM_FLEX_US_FMR_TXRDYM(x)            ((x) & GENMASK(1, 0))
#define FLEXCOM_FLEX_US_FMR_TXRDYM_M             GENMASK(1, 0)
#define FLEXCOM_FLEX_US_FMR_TXRDYM_X(x)          ((x) & GENMASK(1, 0))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_FLR */
#define FLEXCOM_FLEX_US_FLR(t)    (t + 0x2a4)

#define FLEXCOM_FLEX_US_FLR_RXFL(x)              (((x) << 16) & GENMASK(21, 16))
#define FLEXCOM_FLEX_US_FLR_RXFL_M               GENMASK(21, 16)
#define FLEXCOM_FLEX_US_FLR_RXFL_X(x)            (((x) & GENMASK(21, 16)) >> 16)

#define FLEXCOM_FLEX_US_FLR_TXFL(x)              ((x) & GENMASK(5, 0))
#define FLEXCOM_FLEX_US_FLR_TXFL_M               GENMASK(5, 0)
#define FLEXCOM_FLEX_US_FLR_TXFL_X(x)            ((x) & GENMASK(5, 0))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_FIER */
#define FLEXCOM_FLEX_US_FIER(t)   (t + 0x2a8)

#define FLEXCOM_FLEX_US_FIER_RXFTHF2_IE(x)       (((x) << 9) & GENMASK(9, 9))
#define FLEXCOM_FLEX_US_FIER_RXFTHF2_IE_M        GENMASK(9, 9)
#define FLEXCOM_FLEX_US_FIER_RXFTHF2_IE_X(x)     (((x) & GENMASK(9, 9)) >> 9)

#define FLEXCOM_FLEX_US_FIER_RXFPTEF_IE(x)       (((x) << 7) & GENMASK(7, 7))
#define FLEXCOM_FLEX_US_FIER_RXFPTEF_IE_M        GENMASK(7, 7)
#define FLEXCOM_FLEX_US_FIER_RXFPTEF_IE_X(x)     (((x) & GENMASK(7, 7)) >> 7)

#define FLEXCOM_FLEX_US_FIER_TXFPTEF_IE(x)       (((x) << 6) & GENMASK(6, 6))
#define FLEXCOM_FLEX_US_FIER_TXFPTEF_IE_M        GENMASK(6, 6)
#define FLEXCOM_FLEX_US_FIER_TXFPTEF_IE_X(x)     (((x) & GENMASK(6, 6)) >> 6)

#define FLEXCOM_FLEX_US_FIER_RXFTHF_IE(x)        (((x) << 5) & GENMASK(5, 5))
#define FLEXCOM_FLEX_US_FIER_RXFTHF_IE_M         GENMASK(5, 5)
#define FLEXCOM_FLEX_US_FIER_RXFTHF_IE_X(x)      (((x) & GENMASK(5, 5)) >> 5)

#define FLEXCOM_FLEX_US_FIER_RXFFF_IE(x)         (((x) << 4) & GENMASK(4, 4))
#define FLEXCOM_FLEX_US_FIER_RXFFF_IE_M          GENMASK(4, 4)
#define FLEXCOM_FLEX_US_FIER_RXFFF_IE_X(x)       (((x) & GENMASK(4, 4)) >> 4)

#define FLEXCOM_FLEX_US_FIER_RXFEF_IE(x)         (((x) << 3) & GENMASK(3, 3))
#define FLEXCOM_FLEX_US_FIER_RXFEF_IE_M          GENMASK(3, 3)
#define FLEXCOM_FLEX_US_FIER_RXFEF_IE_X(x)       (((x) & GENMASK(3, 3)) >> 3)

#define FLEXCOM_FLEX_US_FIER_TXFTHF_IE(x)        (((x) << 2) & GENMASK(2, 2))
#define FLEXCOM_FLEX_US_FIER_TXFTHF_IE_M         GENMASK(2, 2)
#define FLEXCOM_FLEX_US_FIER_TXFTHF_IE_X(x)      (((x) & GENMASK(2, 2)) >> 2)

#define FLEXCOM_FLEX_US_FIER_TXFFF_IE(x)         (((x) << 1) & GENMASK(1, 1))
#define FLEXCOM_FLEX_US_FIER_TXFFF_IE_M          GENMASK(1, 1)
#define FLEXCOM_FLEX_US_FIER_TXFFF_IE_X(x)       (((x) & GENMASK(1, 1)) >> 1)

#define FLEXCOM_FLEX_US_FIER_TXFEF_IE(x)         ((x) & GENMASK(0, 0))
#define FLEXCOM_FLEX_US_FIER_TXFEF_IE_M          GENMASK(0, 0)
#define FLEXCOM_FLEX_US_FIER_TXFEF_IE_X(x)       ((x) & GENMASK(0, 0))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_FIDR */
#define FLEXCOM_FLEX_US_FIDR(t)   (t + 0x2ac)

#define FLEXCOM_FLEX_US_FIDR_RXFTHF2_ID(x)       (((x) << 9) & GENMASK(9, 9))
#define FLEXCOM_FLEX_US_FIDR_RXFTHF2_ID_M        GENMASK(9, 9)
#define FLEXCOM_FLEX_US_FIDR_RXFTHF2_ID_X(x)     (((x) & GENMASK(9, 9)) >> 9)

#define FLEXCOM_FLEX_US_FIDR_RXFPTEF_ID(x)       (((x) << 7) & GENMASK(7, 7))
#define FLEXCOM_FLEX_US_FIDR_RXFPTEF_ID_M        GENMASK(7, 7)
#define FLEXCOM_FLEX_US_FIDR_RXFPTEF_ID_X(x)     (((x) & GENMASK(7, 7)) >> 7)

#define FLEXCOM_FLEX_US_FIDR_TXFPTEF_ID(x)       (((x) << 6) & GENMASK(6, 6))
#define FLEXCOM_FLEX_US_FIDR_TXFPTEF_ID_M        GENMASK(6, 6)
#define FLEXCOM_FLEX_US_FIDR_TXFPTEF_ID_X(x)     (((x) & GENMASK(6, 6)) >> 6)

#define FLEXCOM_FLEX_US_FIDR_RXFTHF_ID(x)        (((x) << 5) & GENMASK(5, 5))
#define FLEXCOM_FLEX_US_FIDR_RXFTHF_ID_M         GENMASK(5, 5)
#define FLEXCOM_FLEX_US_FIDR_RXFTHF_ID_X(x)      (((x) & GENMASK(5, 5)) >> 5)

#define FLEXCOM_FLEX_US_FIDR_RXFFF_ID(x)         (((x) << 4) & GENMASK(4, 4))
#define FLEXCOM_FLEX_US_FIDR_RXFFF_ID_M          GENMASK(4, 4)
#define FLEXCOM_FLEX_US_FIDR_RXFFF_ID_X(x)       (((x) & GENMASK(4, 4)) >> 4)

#define FLEXCOM_FLEX_US_FIDR_RXFEF_ID(x)         (((x) << 3) & GENMASK(3, 3))
#define FLEXCOM_FLEX_US_FIDR_RXFEF_ID_M          GENMASK(3, 3)
#define FLEXCOM_FLEX_US_FIDR_RXFEF_ID_X(x)       (((x) & GENMASK(3, 3)) >> 3)

#define FLEXCOM_FLEX_US_FIDR_TXFTHF_ID(x)        (((x) << 2) & GENMASK(2, 2))
#define FLEXCOM_FLEX_US_FIDR_TXFTHF_ID_M         GENMASK(2, 2)
#define FLEXCOM_FLEX_US_FIDR_TXFTHF_ID_X(x)      (((x) & GENMASK(2, 2)) >> 2)

#define FLEXCOM_FLEX_US_FIDR_TXFFF_ID(x)         (((x) << 1) & GENMASK(1, 1))
#define FLEXCOM_FLEX_US_FIDR_TXFFF_ID_M          GENMASK(1, 1)
#define FLEXCOM_FLEX_US_FIDR_TXFFF_ID_X(x)       (((x) & GENMASK(1, 1)) >> 1)

#define FLEXCOM_FLEX_US_FIDR_TXFEF_ID(x)         ((x) & GENMASK(0, 0))
#define FLEXCOM_FLEX_US_FIDR_TXFEF_ID_M          GENMASK(0, 0)
#define FLEXCOM_FLEX_US_FIDR_TXFEF_ID_X(x)       ((x) & GENMASK(0, 0))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_FIMR */
#define FLEXCOM_FLEX_US_FIMR(t)   (t + 0x2b0)

#define FLEXCOM_FLEX_US_FIMR_RXFTHF2_IM(x)       (((x) << 9) & GENMASK(9, 9))
#define FLEXCOM_FLEX_US_FIMR_RXFTHF2_IM_M        GENMASK(9, 9)
#define FLEXCOM_FLEX_US_FIMR_RXFTHF2_IM_X(x)     (((x) & GENMASK(9, 9)) >> 9)

#define FLEXCOM_FLEX_US_FIMR_RXFPTEF_IM(x)       (((x) << 7) & GENMASK(7, 7))
#define FLEXCOM_FLEX_US_FIMR_RXFPTEF_IM_M        GENMASK(7, 7)
#define FLEXCOM_FLEX_US_FIMR_RXFPTEF_IM_X(x)     (((x) & GENMASK(7, 7)) >> 7)

#define FLEXCOM_FLEX_US_FIMR_TXFPTEF_IM(x)       (((x) << 6) & GENMASK(6, 6))
#define FLEXCOM_FLEX_US_FIMR_TXFPTEF_IM_M        GENMASK(6, 6)
#define FLEXCOM_FLEX_US_FIMR_TXFPTEF_IM_X(x)     (((x) & GENMASK(6, 6)) >> 6)

#define FLEXCOM_FLEX_US_FIMR_RXFTHF_IM(x)        (((x) << 5) & GENMASK(5, 5))
#define FLEXCOM_FLEX_US_FIMR_RXFTHF_IM_M         GENMASK(5, 5)
#define FLEXCOM_FLEX_US_FIMR_RXFTHF_IM_X(x)      (((x) & GENMASK(5, 5)) >> 5)

#define FLEXCOM_FLEX_US_FIMR_RXFFF_IM(x)         (((x) << 4) & GENMASK(4, 4))
#define FLEXCOM_FLEX_US_FIMR_RXFFF_IM_M          GENMASK(4, 4)
#define FLEXCOM_FLEX_US_FIMR_RXFFF_IM_X(x)       (((x) & GENMASK(4, 4)) >> 4)

#define FLEXCOM_FLEX_US_FIMR_RXFEF_IM(x)         (((x) << 3) & GENMASK(3, 3))
#define FLEXCOM_FLEX_US_FIMR_RXFEF_IM_M          GENMASK(3, 3)
#define FLEXCOM_FLEX_US_FIMR_RXFEF_IM_X(x)       (((x) & GENMASK(3, 3)) >> 3)

#define FLEXCOM_FLEX_US_FIMR_TXFTHF_IM(x)        (((x) << 2) & GENMASK(2, 2))
#define FLEXCOM_FLEX_US_FIMR_TXFTHF_IM_M         GENMASK(2, 2)
#define FLEXCOM_FLEX_US_FIMR_TXFTHF_IM_X(x)      (((x) & GENMASK(2, 2)) >> 2)

#define FLEXCOM_FLEX_US_FIMR_TXFFF_IM(x)         (((x) << 1) & GENMASK(1, 1))
#define FLEXCOM_FLEX_US_FIMR_TXFFF_IM_M          GENMASK(1, 1)
#define FLEXCOM_FLEX_US_FIMR_TXFFF_IM_X(x)       (((x) & GENMASK(1, 1)) >> 1)

#define FLEXCOM_FLEX_US_FIMR_TXFEF_IM(x)         ((x) & GENMASK(0, 0))
#define FLEXCOM_FLEX_US_FIMR_TXFEF_IM_M          GENMASK(0, 0)
#define FLEXCOM_FLEX_US_FIMR_TXFEF_IM_X(x)       ((x) & GENMASK(0, 0))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_FESR */
#define FLEXCOM_FLEX_US_FESR(t)   (t + 0x2b4)

#define FLEXCOM_FLEX_US_FESR_RXFTHF2(x)          (((x) << 9) & GENMASK(9, 9))
#define FLEXCOM_FLEX_US_FESR_RXFTHF2_M           GENMASK(9, 9)
#define FLEXCOM_FLEX_US_FESR_RXFTHF2_X(x)        (((x) & GENMASK(9, 9)) >> 9)

#define FLEXCOM_FLEX_US_FESR_TXFLOCK(x)          (((x) << 8) & GENMASK(8, 8))
#define FLEXCOM_FLEX_US_FESR_TXFLOCK_M           GENMASK(8, 8)
#define FLEXCOM_FLEX_US_FESR_TXFLOCK_X(x)        (((x) & GENMASK(8, 8)) >> 8)

#define FLEXCOM_FLEX_US_FESR_RXFPTEF(x)          (((x) << 7) & GENMASK(7, 7))
#define FLEXCOM_FLEX_US_FESR_RXFPTEF_M           GENMASK(7, 7)
#define FLEXCOM_FLEX_US_FESR_RXFPTEF_X(x)        (((x) & GENMASK(7, 7)) >> 7)

#define FLEXCOM_FLEX_US_FESR_TXFPTEF(x)          (((x) << 6) & GENMASK(6, 6))
#define FLEXCOM_FLEX_US_FESR_TXFPTEF_M           GENMASK(6, 6)
#define FLEXCOM_FLEX_US_FESR_TXFPTEF_X(x)        (((x) & GENMASK(6, 6)) >> 6)

#define FLEXCOM_FLEX_US_FESR_RXFTHF(x)           (((x) << 5) & GENMASK(5, 5))
#define FLEXCOM_FLEX_US_FESR_RXFTHF_M            GENMASK(5, 5)
#define FLEXCOM_FLEX_US_FESR_RXFTHF_X(x)         (((x) & GENMASK(5, 5)) >> 5)

#define FLEXCOM_FLEX_US_FESR_RXFFF(x)            (((x) << 4) & GENMASK(4, 4))
#define FLEXCOM_FLEX_US_FESR_RXFFF_M             GENMASK(4, 4)
#define FLEXCOM_FLEX_US_FESR_RXFFF_X(x)          (((x) & GENMASK(4, 4)) >> 4)

#define FLEXCOM_FLEX_US_FESR_RXFEF(x)            (((x) << 3) & GENMASK(3, 3))
#define FLEXCOM_FLEX_US_FESR_RXFEF_M             GENMASK(3, 3)
#define FLEXCOM_FLEX_US_FESR_RXFEF_X(x)          (((x) & GENMASK(3, 3)) >> 3)

#define FLEXCOM_FLEX_US_FESR_TXFTHF(x)           (((x) << 2) & GENMASK(2, 2))
#define FLEXCOM_FLEX_US_FESR_TXFTHF_M            GENMASK(2, 2)
#define FLEXCOM_FLEX_US_FESR_TXFTHF_X(x)         (((x) & GENMASK(2, 2)) >> 2)

#define FLEXCOM_FLEX_US_FESR_TXFFF(x)            (((x) << 1) & GENMASK(1, 1))
#define FLEXCOM_FLEX_US_FESR_TXFFF_M             GENMASK(1, 1)
#define FLEXCOM_FLEX_US_FESR_TXFFF_X(x)          (((x) & GENMASK(1, 1)) >> 1)

#define FLEXCOM_FLEX_US_FESR_TXFEF(x)            ((x) & GENMASK(0, 0))
#define FLEXCOM_FLEX_US_FESR_TXFEF_M             GENMASK(0, 0)
#define FLEXCOM_FLEX_US_FESR_TXFEF_X(x)          ((x) & GENMASK(0, 0))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_WPMR */
#define FLEXCOM_FLEX_US_WPMR(t)   (t + 0x2e4)

#define FLEXCOM_FLEX_US_WPMR_WPKEY(x)            (((x) << 8) & GENMASK(31, 8))
#define FLEXCOM_FLEX_US_WPMR_WPKEY_M             GENMASK(31, 8)
#define FLEXCOM_FLEX_US_WPMR_WPKEY_X(x)          (((x) & GENMASK(31, 8)) >> 8)

#define FLEXCOM_FLEX_US_WPMR_WPCREN(x)           (((x) << 2) & GENMASK(2, 2))
#define FLEXCOM_FLEX_US_WPMR_WPCREN_M            GENMASK(2, 2)
#define FLEXCOM_FLEX_US_WPMR_WPCREN_X(x)         (((x) & GENMASK(2, 2)) >> 2)

#define FLEXCOM_FLEX_US_WPMR_WPITEN(x)           (((x) << 1) & GENMASK(1, 1))
#define FLEXCOM_FLEX_US_WPMR_WPITEN_M            GENMASK(1, 1)
#define FLEXCOM_FLEX_US_WPMR_WPITEN_X(x)         (((x) & GENMASK(1, 1)) >> 1)

#define FLEXCOM_FLEX_US_WPMR_WPEN(x)             ((x) & GENMASK(0, 0))
#define FLEXCOM_FLEX_US_WPMR_WPEN_M              GENMASK(0, 0)
#define FLEXCOM_FLEX_US_WPMR_WPEN_X(x)           ((x) & GENMASK(0, 0))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_WPSR */
#define FLEXCOM_FLEX_US_WPSR(t)   (t + 0x2e8)

#define FLEXCOM_FLEX_US_WPSR_WPVSRC(x)           (((x) << 8) & GENMASK(23, 8))
#define FLEXCOM_FLEX_US_WPSR_WPVSRC_M            GENMASK(23, 8)
#define FLEXCOM_FLEX_US_WPSR_WPVSRC_X(x)         (((x) & GENMASK(23, 8)) >> 8)

#define FLEXCOM_FLEX_US_WPSR_WPVS(x)             ((x) & GENMASK(0, 0))
#define FLEXCOM_FLEX_US_WPSR_WPVS_M              GENMASK(0, 0)
#define FLEXCOM_FLEX_US_WPSR_WPVS_X(x)           ((x) & GENMASK(0, 0))

/*      FLEXCOM:FLEXCOM_USART_REG:FLEX_US_VERSION */
#define FLEXCOM_FLEX_US_VERSION(t) (t + 0x2fc)

#define FLEXCOM_FLEX_US_VERSION_USART_MFN(x)     (((x) << 16) & GENMASK(18, 16))
#define FLEXCOM_FLEX_US_VERSION_USART_MFN_M      GENMASK(18, 16)
#define FLEXCOM_FLEX_US_VERSION_USART_MFN_X(x)   (((x) & GENMASK(18, 16)) >> 16)

#define FLEXCOM_FLEX_US_VERSION_USART_VERSION(x) ((x) & GENMASK(11, 0))
#define FLEXCOM_FLEX_US_VERSION_USART_VERSION_M  GENMASK(11, 0)
#define FLEXCOM_FLEX_US_VERSION_USART_VERSION_X(x) ((x) & GENMASK(11, 0))

/*      GCB:CHIP_REGS:CHIP_ID */
#define GCB_CHIP_ID(t)            (t + 0x00)

#define GCB_CHIP_ID_REV_ID(x)                    (((x) << 28) & GENMASK(31, 28))
#define GCB_CHIP_ID_REV_ID_M                     GENMASK(31, 28)
#define GCB_CHIP_ID_REV_ID_X(x)                  (((x) & GENMASK(31, 28)) >> 28)

#define GCB_CHIP_ID_PART_ID(x)                   (((x) << 12) & GENMASK(27, 12))
#define GCB_CHIP_ID_PART_ID_M                    GENMASK(27, 12)
#define GCB_CHIP_ID_PART_ID_X(x)                 (((x) & GENMASK(27, 12)) >> 12)

#define GCB_CHIP_ID_MFG_ID(x)                    (((x) << 1) & GENMASK(11, 1))
#define GCB_CHIP_ID_MFG_ID_M                     GENMASK(11, 1)
#define GCB_CHIP_ID_MFG_ID_X(x)                  (((x) & GENMASK(11, 1)) >> 1)

#define GCB_CHIP_ID_ONE(x)                       ((x) & GENMASK(0, 0))
#define GCB_CHIP_ID_ONE_M                        GENMASK(0, 0)
#define GCB_CHIP_ID_ONE_X(x)                     ((x) & GENMASK(0, 0))

/*      GCB:CHIP_REGS:SOFT_RST */
#define GCB_SOFT_RST(t)           (t + 0x0c)

#define GCB_SOFT_RST_SOFT_SWC_RST(x)             (((x) << 1) & GENMASK(1, 1))
#define GCB_SOFT_RST_SOFT_SWC_RST_M              GENMASK(1, 1)
#define GCB_SOFT_RST_SOFT_SWC_RST_X(x)           (((x) & GENMASK(1, 1)) >> 1)

#define GCB_SOFT_RST_SOFT_CHIP_RST(x)            ((x) & GENMASK(0, 0))
#define GCB_SOFT_RST_SOFT_CHIP_RST_M             GENMASK(0, 0)
#define GCB_SOFT_RST_SOFT_CHIP_RST_X(x)          ((x) & GENMASK(0, 0))

/*      GCB:GPIO:GPIO_OUT_SET */
#define GCB_GPIO_OUT_SET(t)       (t + 0x64)

/*      GCB:GPIO:GPIO_OUT_SET1 */
#define GCB_GPIO_OUT_SET1(t)      (t + 0x68)

/*      GCB:GPIO:GPIO_OUT_SET2 */
#define GCB_GPIO_OUT_SET2(t)      (t + 0x6c)

#define GCB_GPIO_OUT_SET2_G_OUT_SET2(x)          ((x) & GENMASK(13, 0))
#define GCB_GPIO_OUT_SET2_G_OUT_SET2_M           GENMASK(13, 0)
#define GCB_GPIO_OUT_SET2_G_OUT_SET2_X(x)        ((x) & GENMASK(13, 0))

/*      GCB:GPIO:GPIO_OUT_CLR */
#define GCB_GPIO_OUT_CLR(t)       (t + 0x70)

/*      GCB:GPIO:GPIO_OUT_CLR1 */
#define GCB_GPIO_OUT_CLR1(t)      (t + 0x74)

/*      GCB:GPIO:GPIO_OUT_CLR2 */
#define GCB_GPIO_OUT_CLR2(t)      (t + 0x78)

#define GCB_GPIO_OUT_CLR2_G_OUT_CLR2(x)          ((x) & GENMASK(13, 0))
#define GCB_GPIO_OUT_CLR2_G_OUT_CLR2_M           GENMASK(13, 0)
#define GCB_GPIO_OUT_CLR2_G_OUT_CLR2_X(x)        ((x) & GENMASK(13, 0))

/*      GCB:GPIO:GPIO_OUT */
#define GCB_GPIO_OUT(t)           (t + 0x7c)

/*      GCB:GPIO:GPIO_OUT1 */
#define GCB_GPIO_OUT1(t)          (t + 0x80)

/*      GCB:GPIO:GPIO_OUT2 */
#define GCB_GPIO_OUT2(t)          (t + 0x84)

#define GCB_GPIO_OUT2_G_OUT2(x)                  ((x) & GENMASK(13, 0))
#define GCB_GPIO_OUT2_G_OUT2_M                   GENMASK(13, 0)
#define GCB_GPIO_OUT2_G_OUT2_X(x)                ((x) & GENMASK(13, 0))

/*      GCB:GPIO:GPIO_IN */
#define GCB_GPIO_IN(t)            (t + 0x88)

/*      GCB:GPIO:GPIO_IN1 */
#define GCB_GPIO_IN1(t)           (t + 0x8c)

/*      GCB:GPIO:GPIO_IN2 */
#define GCB_GPIO_IN2(t)           (t + 0x90)

#define GCB_GPIO_IN2_G_IN2(x)                    ((x) & GENMASK(13, 0))
#define GCB_GPIO_IN2_G_IN2_M                     GENMASK(13, 0)
#define GCB_GPIO_IN2_G_IN2_X(x)                  ((x) & GENMASK(13, 0))

/*      GCB:GPIO:GPIO_OE */
#define GCB_GPIO_OE(t)            (t + 0x94)

/*      GCB:GPIO:GPIO_OE1 */
#define GCB_GPIO_OE1(t)           (t + 0x98)

/*      GCB:GPIO:GPIO_OE2 */
#define GCB_GPIO_OE2(t)           (t + 0x9c)

#define GCB_GPIO_OE2_G_OE2(x)                    ((x) & GENMASK(13, 0))
#define GCB_GPIO_OE2_G_OE2_M                     GENMASK(13, 0)
#define GCB_GPIO_OE2_G_OE2_X(x)                  ((x) & GENMASK(13, 0))

/*      GCB:GPIO:GPIO_INTR */
#define GCB_GPIO_INTR(t)          (t + 0xa0)

/*      GCB:GPIO:GPIO_INTR1 */
#define GCB_GPIO_INTR1(t)         (t + 0xa4)

/*      GCB:GPIO:GPIO_INTR2 */
#define GCB_GPIO_INTR2(t)         (t + 0xa8)

#define GCB_GPIO_INTR2_G_INTR2(x)                ((x) & GENMASK(13, 0))
#define GCB_GPIO_INTR2_G_INTR2_M                 GENMASK(13, 0)
#define GCB_GPIO_INTR2_G_INTR2_X(x)              ((x) & GENMASK(13, 0))

/*      GCB:GPIO:GPIO_INTR_ENA */
#define GCB_GPIO_INTR_ENA(t)      (t + 0xac)

/*      GCB:GPIO:GPIO_INTR_ENA1 */
#define GCB_GPIO_INTR_ENA1(t)     (t + 0xb0)

/*      GCB:GPIO:GPIO_INTR_ENA2 */
#define GCB_GPIO_INTR_ENA2(t)     (t + 0xb4)

#define GCB_GPIO_INTR_ENA2_G_INTR_ENA2(x)        ((x) & GENMASK(13, 0))
#define GCB_GPIO_INTR_ENA2_G_INTR_ENA2_M         GENMASK(13, 0)
#define GCB_GPIO_INTR_ENA2_G_INTR_ENA2_X(x)      ((x) & GENMASK(13, 0))

/*      GCB:GPIO:GPIO_INTR_IDENT */
#define GCB_GPIO_INTR_IDENT(t)    (t + 0xb8)

/*      GCB:GPIO:GPIO_INTR_IDENT1 */
#define GCB_GPIO_INTR_IDENT1(t)   (t + 0xbc)

/*      GCB:GPIO:GPIO_INTR_IDENT2 */
#define GCB_GPIO_INTR_IDENT2(t)   (t + 0xc0)

#define GCB_GPIO_INTR_IDENT2_G_INTR_IDENT2(x)    ((x) & GENMASK(13, 0))
#define GCB_GPIO_INTR_IDENT2_G_INTR_IDENT2_M     GENMASK(13, 0)
#define GCB_GPIO_INTR_IDENT2_G_INTR_IDENT2_X(x)  ((x) & GENMASK(13, 0))

/*      GCB:GPIO:GPIO_ALT */
#define GCB_GPIO_ALT(t, r)        (t + (0xc4 + ((r) * 4)))

/*      GCB:GPIO:GPIO_ALT1 */
#define GCB_GPIO_ALT1(t, r)       (t + (0xd0 + ((r) * 4)))

/*      GCB:GPIO:GPIO_ALT2 */
#define GCB_GPIO_ALT2(t, r)       (t + (0xdc + ((r) * 4)))

#define GCB_GPIO_ALT2_G_ALT2(x)                  ((x) & GENMASK(13, 0))
#define GCB_GPIO_ALT2_G_ALT2_M                   GENMASK(13, 0)
#define GCB_GPIO_ALT2_G_ALT2_X(x)                ((x) & GENMASK(13, 0))

/*      GCB:GPIO:GPIO_SD_DEV_MAP */
#define GCB_GPIO_SD_DEV_MAP(t, r) (t + (0xe8 + ((r) * 4)))

#define GCB_GPIO_SD_DEV_MAP_G_SD_DEV_MAP(x)      ((x) & GENMASK(2, 0))
#define GCB_GPIO_SD_DEV_MAP_G_SD_DEV_MAP_M       GENMASK(2, 0)
#define GCB_GPIO_SD_DEV_MAP_G_SD_DEV_MAP_X(x)    ((x) & GENMASK(2, 0))

/*      GCB:GPIO:GPIO_SD_SERDES_MAP */
#define GCB_GPIO_SD_SERDES_MAP(t, r) (t + (0x100 + ((r) * 4)))

#define GCB_GPIO_SD_SERDES_MAP_G_SD_SERDES_MAP(x) ((x) & GENMASK(1, 0))
#define GCB_GPIO_SD_SERDES_MAP_G_SD_SERDES_MAP_M GENMASK(1, 0)
#define GCB_GPIO_SD_SERDES_MAP_G_SD_SERDES_MAP_X(x) ((x) & GENMASK(1, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:PERIPH_ID_4 */
#define GPV_PERIPH_ID_4(t)        (t + 0x1fd0)

#define GPV_PERIPH_ID_4_PERIPH_ID_4(x)           ((x) & GENMASK(7, 0))
#define GPV_PERIPH_ID_4_PERIPH_ID_4_M            GENMASK(7, 0)
#define GPV_PERIPH_ID_4_PERIPH_ID_4_X(x)         ((x) & GENMASK(7, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:PERIPH_ID_5 */
#define GPV_PERIPH_ID_5(t)        (t + 0x1fd4)

#define GPV_PERIPH_ID_5_PERIPH_ID_5(x)           ((x) & GENMASK(7, 0))
#define GPV_PERIPH_ID_5_PERIPH_ID_5_M            GENMASK(7, 0)
#define GPV_PERIPH_ID_5_PERIPH_ID_5_X(x)         ((x) & GENMASK(7, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:PERIPH_ID_6 */
#define GPV_PERIPH_ID_6(t)        (t + 0x1fd8)

#define GPV_PERIPH_ID_6_PERIPH_ID_6(x)           ((x) & GENMASK(7, 0))
#define GPV_PERIPH_ID_6_PERIPH_ID_6_M            GENMASK(7, 0)
#define GPV_PERIPH_ID_6_PERIPH_ID_6_X(x)         ((x) & GENMASK(7, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:PERIPH_ID_7 */
#define GPV_PERIPH_ID_7(t)        (t + 0x1fdc)

#define GPV_PERIPH_ID_7_PERIPH_ID_7(x)           ((x) & GENMASK(7, 0))
#define GPV_PERIPH_ID_7_PERIPH_ID_7_M            GENMASK(7, 0)
#define GPV_PERIPH_ID_7_PERIPH_ID_7_X(x)         ((x) & GENMASK(7, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:PERIPH_ID_0 */
#define GPV_PERIPH_ID_0(t)        (t + 0x1fe0)

#define GPV_PERIPH_ID_0_PERIPH_ID_0(x)           ((x) & GENMASK(7, 0))
#define GPV_PERIPH_ID_0_PERIPH_ID_0_M            GENMASK(7, 0)
#define GPV_PERIPH_ID_0_PERIPH_ID_0_X(x)         ((x) & GENMASK(7, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:PERIPH_ID_1 */
#define GPV_PERIPH_ID_1(t)        (t + 0x1fe4)

#define GPV_PERIPH_ID_1_PERIPH_ID_1(x)           ((x) & GENMASK(7, 0))
#define GPV_PERIPH_ID_1_PERIPH_ID_1_M            GENMASK(7, 0)
#define GPV_PERIPH_ID_1_PERIPH_ID_1_X(x)         ((x) & GENMASK(7, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:PERIPH_ID_2 */
#define GPV_PERIPH_ID_2(t)        (t + 0x1fe8)

#define GPV_PERIPH_ID_2_PERIPH_ID_2(x)           ((x) & GENMASK(7, 0))
#define GPV_PERIPH_ID_2_PERIPH_ID_2_M            GENMASK(7, 0)
#define GPV_PERIPH_ID_2_PERIPH_ID_2_X(x)         ((x) & GENMASK(7, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:PERIPH_ID_3 */
#define GPV_PERIPH_ID_3(t)        (t + 0x1fec)

#define GPV_PERIPH_ID_3_CUST_MOD_NUM(x)          ((x) & GENMASK(3, 0))
#define GPV_PERIPH_ID_3_CUST_MOD_NUM_M           GENMASK(3, 0)
#define GPV_PERIPH_ID_3_CUST_MOD_NUM_X(x)        ((x) & GENMASK(3, 0))

#define GPV_PERIPH_ID_3_REV_AND(x)               (((x) << 4) & GENMASK(7, 4))
#define GPV_PERIPH_ID_3_REV_AND_M                GENMASK(7, 4)
#define GPV_PERIPH_ID_3_REV_AND_X(x)             (((x) & GENMASK(7, 4)) >> 4)

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:COMP_ID_0 */
#define GPV_COMP_ID_0(t)          (t + 0x1ff0)

#define GPV_COMP_ID_0_COMP_ID_0(x)               ((x) & GENMASK(7, 0))
#define GPV_COMP_ID_0_COMP_ID_0_M                GENMASK(7, 0)
#define GPV_COMP_ID_0_COMP_ID_0_X(x)             ((x) & GENMASK(7, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:COMP_ID_1 */
#define GPV_COMP_ID_1(t)          (t + 0x1ff4)

#define GPV_COMP_ID_1_COMP_ID_1(x)               ((x) & GENMASK(7, 0))
#define GPV_COMP_ID_1_COMP_ID_1_M                GENMASK(7, 0)
#define GPV_COMP_ID_1_COMP_ID_1_X(x)             ((x) & GENMASK(7, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:COMP_ID_2 */
#define GPV_COMP_ID_2(t)          (t + 0x1ff8)

#define GPV_COMP_ID_2_COMP_ID_2(x)               ((x) & GENMASK(7, 0))
#define GPV_COMP_ID_2_COMP_ID_2_M                GENMASK(7, 0)
#define GPV_COMP_ID_2_COMP_ID_2_X(x)             ((x) & GENMASK(7, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:COMP_ID_3 */
#define GPV_COMP_ID_3(t)          (t + 0x1ffc)

#define GPV_COMP_ID_3_COMP_ID_3(x)               ((x) & GENMASK(7, 0))
#define GPV_COMP_ID_3_COMP_ID_3_M                GENMASK(7, 0)
#define GPV_COMP_ID_3_COMP_ID_3_X(x)             ((x) & GENMASK(7, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:SECURITY_BOOT_RAM */
#define GPV_SECURITY_BOOT_RAM(t)  (t + 0x0c)

#define GPV_SECURITY_BOOT_RAM_SECURITY_BOOT_RAM(x) ((x) & GENMASK(0, 0))
#define GPV_SECURITY_BOOT_RAM_SECURITY_BOOT_RAM_M GENMASK(0, 0)
#define GPV_SECURITY_BOOT_RAM_SECURITY_BOOT_RAM_X(x) ((x) & GENMASK(0, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:SECURITY_DDR_CSS */
#define GPV_SECURITY_DDR_CSS(t)   (t + 0x14)

#define GPV_SECURITY_DDR_CSS_SECURITY_DDR_CSS(x) ((x) & GENMASK(0, 0))
#define GPV_SECURITY_DDR_CSS_SECURITY_DDR_CSS_M  GENMASK(0, 0)
#define GPV_SECURITY_DDR_CSS_SECURITY_DDR_CSS_X(x) ((x) & GENMASK(0, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:SECURITY_CSR_REGS */
#define GPV_SECURITY_CSR_REGS(t)  (t + 0x1c)

#define GPV_SECURITY_CSR_REGS_SECURITY_CSR_REGS(x) ((x) & GENMASK(0, 0))
#define GPV_SECURITY_CSR_REGS_SECURITY_CSR_REGS_M GENMASK(0, 0)
#define GPV_SECURITY_CSR_REGS_SECURITY_CSR_REGS_X(x) ((x) & GENMASK(0, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:SECURITY_CPU_REGS */
#define GPV_SECURITY_CPU_REGS(t)  (t + 0x20)

#define GPV_SECURITY_CPU_REGS_SECURITY_CPU_REGS(x) ((x) & GENMASK(0, 0))
#define GPV_SECURITY_CPU_REGS_SECURITY_CPU_REGS_M GENMASK(0, 0)
#define GPV_SECURITY_CPU_REGS_SECURITY_CPU_REGS_X(x) ((x) & GENMASK(0, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:SECURITY_PI */
#define GPV_SECURITY_PI(t)        (t + 0x30)

#define GPV_SECURITY_PI_SECURITY_PI(x)           ((x) & GENMASK(0, 0))
#define GPV_SECURITY_PI_SECURITY_PI_M            GENMASK(0, 0)
#define GPV_SECURITY_PI_SECURITY_PI_X(x)         ((x) & GENMASK(0, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:SECURITY_PCIE_DBI */
#define GPV_SECURITY_PCIE_DBI(t)  (t + 0x38)

#define GPV_SECURITY_PCIE_DBI_SECURITY_PCIE_DBI(x) ((x) & GENMASK(0, 0))
#define GPV_SECURITY_PCIE_DBI_SECURITY_PCIE_DBI_M GENMASK(0, 0)
#define GPV_SECURITY_PCIE_DBI_SECURITY_PCIE_DBI_X(x) ((x) & GENMASK(0, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:SECURITY_PCIE_OB */
#define GPV_SECURITY_PCIE_OB(t)   (t + 0x3c)

#define GPV_SECURITY_PCIE_OB_SECURITY_PCIE_OB(x) ((x) & GENMASK(0, 0))
#define GPV_SECURITY_PCIE_OB_SECURITY_PCIE_OB_M  GENMASK(0, 0)
#define GPV_SECURITY_PCIE_OB_SECURITY_PCIE_OB_X(x) ((x) & GENMASK(0, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:SECURITY_QSPI1 */
#define GPV_SECURITY_QSPI1(t)     (t + 0x40)

#define GPV_SECURITY_QSPI1_SECURITY_QSPI1(x)     ((x) & GENMASK(0, 0))
#define GPV_SECURITY_QSPI1_SECURITY_QSPI1_M      GENMASK(0, 0)
#define GPV_SECURITY_QSPI1_SECURITY_QSPI1_X(x)   ((x) & GENMASK(0, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:SECURITY_PCIE_CFG */
#define GPV_SECURITY_PCIE_CFG(t)  (t + 0x44)

#define GPV_SECURITY_PCIE_CFG_SECURITY_PCIE_CFG(x) ((x) & GENMASK(0, 0))
#define GPV_SECURITY_PCIE_CFG_SECURITY_PCIE_CFG_M GENMASK(0, 0)
#define GPV_SECURITY_PCIE_CFG_SECURITY_PCIE_CFG_X(x) ((x) & GENMASK(0, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:SECURITY_CuPHY */
#define GPV_SECURITY_CuPHY(t)     (t + 0x48)

#define GPV_SECURITY_CuPHY_SECURITY_CuPHY(x)     ((x) & GENMASK(0, 0))
#define GPV_SECURITY_CuPHY_SECURITY_CuPHY_M      GENMASK(0, 0)
#define GPV_SECURITY_CuPHY_SECURITY_CuPHY_X(x)   ((x) & GENMASK(0, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:SECURITY_APB_MAIN3 */
#define GPV_SECURITY_APB_MAIN3(t) (t + 0x50)

#define GPV_SECURITY_APB_MAIN3_SECURITY_APB_MAIN3(x) ((x) & GENMASK(15, 0))
#define GPV_SECURITY_APB_MAIN3_SECURITY_APB_MAIN3_M GENMASK(15, 0)
#define GPV_SECURITY_APB_MAIN3_SECURITY_APB_MAIN3_X(x) ((x) & GENMASK(15, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:SECURITY_APB_CSS2 */
#define GPV_SECURITY_APB_CSS2(t)  (t + 0x54)

#define GPV_SECURITY_APB_CSS2_SECURITY_APB_CSS2(x) ((x) & GENMASK(15, 0))
#define GPV_SECURITY_APB_CSS2_SECURITY_APB_CSS2_M GENMASK(15, 0)
#define GPV_SECURITY_APB_CSS2_SECURITY_APB_CSS2_X(x) ((x) & GENMASK(15, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:CA7_IB_FN_MOD */
#define GPV_CA7_IB_FN_MOD(t)      (t + 0x42108)

#define GPV_CA7_IB_FN_MOD_CA7_IB_FN_MOD_FN_MOD(x) ((x) & GENMASK(1, 0))
#define GPV_CA7_IB_FN_MOD_CA7_IB_FN_MOD_FN_MOD_M GENMASK(1, 0)
#define GPV_CA7_IB_FN_MOD_CA7_IB_FN_MOD_FN_MOD_X(x) ((x) & GENMASK(1, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:SECURITY_DDR_MAIN */
#define GPV_SECURITY_DDR_MAIN(t)  (t + 0x2c)

#define GPV_SECURITY_DDR_MAIN_SECURITY_DDR_MAIN(x) ((x) & GENMASK(0, 0))
#define GPV_SECURITY_DDR_MAIN_SECURITY_DDR_MAIN_M GENMASK(0, 0)
#define GPV_SECURITY_DDR_MAIN_SECURITY_DDR_MAIN_X(x) ((x) & GENMASK(0, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:CA7_DAP_IB_FN_MOD2 */
#define GPV_CA7_DAP_IB_FN_MOD2(t) (t + 0x43024)

#define GPV_CA7_DAP_IB_FN_MOD2_CA7_DAP_IB_FN_MOD2_BYPASS_MERGE(x)\
	((x) & GENMASK(0, 0))
#define GPV_CA7_DAP_IB_FN_MOD2_CA7_DAP_IB_FN_MOD2_BYPASS_MERGE_M GENMASK(0, 0)
#define GPV_CA7_DAP_IB_FN_MOD2_CA7_DAP_IB_FN_MOD2_BYPASS_MERGE_X(x)\
	((x) & GENMASK(0, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:CA7_DAP_IB_FN_MOD */
#define GPV_CA7_DAP_IB_FN_MOD(t)  (t + 0x43108)

#define GPV_CA7_DAP_IB_FN_MOD_CA7_DAP_IB_FN_MOD_FN_MOD(x) ((x) & GENMASK(1, 0))
#define GPV_CA7_DAP_IB_FN_MOD_CA7_DAP_IB_FN_MOD_FN_MOD_M GENMASK(1, 0)
#define GPV_CA7_DAP_IB_FN_MOD_CA7_DAP_IB_FN_MOD_FN_MOD_X(x)\
	((x) & GENMASK(1, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:EXT_INITIATOR_IB_FN_MOD2 */
#define GPV_EXT_INITIATOR_IB_FN_MOD2(t) (t + 0x44024)

#define GPV_EXT_INITIATOR_IB_FN_MOD2_EXT_INITIATOR_IB_FN_MOD2_BYPASS_MERGE(x)\
	((x) & GENMASK(0, 0))
#define GPV_EXT_INITIATOR_IB_FN_MOD2_EXT_INITIATOR_IB_FN_MOD2_BYPASS_MERGE_M\
	GENMASK(0, 0)
#define GPV_EXT_INITIATOR_IB_FN_MOD2_EXT_INITIATOR_IB_FN_MOD2_BYPASS_MERGE_X(x)\
	((x) & GENMASK(0, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:EXT_INITIATOR_IB_FN_MOD */
#define GPV_EXT_INITIATOR_IB_FN_MOD(t) (t + 0x44108)

#define GPV_EXT_INITIATOR_IB_FN_MOD_EXT_INITIATOR_IB_FN_MOD_FN_MOD(x)\
	((x) & GENMASK(1, 0))
#define GPV_EXT_INITIATOR_IB_FN_MOD_EXT_INITIATOR_IB_FN_MOD_FN_MOD_M\
	GENMASK(1, 0)
#define GPV_EXT_INITIATOR_IB_FN_MOD_EXT_INITIATOR_IB_FN_MOD_FN_MOD_X(x)\
	((x) & GENMASK(1, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:FDMA_FN_MOD */
#define GPV_FDMA_FN_MOD(t)        (t + 0x45108)

#define GPV_FDMA_FN_MOD_FDMA_FN_MOD_FN_MOD(x)    ((x) & GENMASK(1, 0))
#define GPV_FDMA_FN_MOD_FDMA_FN_MOD_FN_MOD_M     GENMASK(1, 0)
#define GPV_FDMA_FN_MOD_FDMA_FN_MOD_FN_MOD_X(x)  ((x) & GENMASK(1, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:PCIE_IB_FN_MOD */
#define GPV_PCIE_IB_FN_MOD(t)     (t + 0x46108)

#define GPV_PCIE_IB_FN_MOD_PCIE_IB_FN_MOD_FN_MOD(x) ((x) & GENMASK(1, 0))
#define GPV_PCIE_IB_FN_MOD_PCIE_IB_FN_MOD_FN_MOD_M GENMASK(1, 0)
#define GPV_PCIE_IB_FN_MOD_PCIE_IB_FN_MOD_FN_MOD_X(x) ((x) & GENMASK(1, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:XDMAC_FN_MOD */
#define GPV_XDMAC_FN_MOD(t)       (t + 0x47108)

#define GPV_XDMAC_FN_MOD_XDMAC_FN_MOD_FN_MOD(x)  ((x) & GENMASK(1, 0))
#define GPV_XDMAC_FN_MOD_XDMAC_FN_MOD_FN_MOD_M   GENMASK(1, 0)
#define GPV_XDMAC_FN_MOD_XDMAC_FN_MOD_FN_MOD_X(x) ((x) & GENMASK(1, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:RTE_IB_FN_MOD2 */
#define GPV_RTE_IB_FN_MOD2(t)     (t + 0x48024)

#define GPV_RTE_IB_FN_MOD2_RTE_IB_FN_MOD2_BYPASS_MERGE(x) ((x) & GENMASK(0, 0))
#define GPV_RTE_IB_FN_MOD2_RTE_IB_FN_MOD2_BYPASS_MERGE_M GENMASK(0, 0)
#define GPV_RTE_IB_FN_MOD2_RTE_IB_FN_MOD2_BYPASS_MERGE_X(x)\
	((x) & GENMASK(0, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:RTE_IB_FN_MOD */
#define GPV_RTE_IB_FN_MOD(t)      (t + 0x48108)

#define GPV_RTE_IB_FN_MOD_RTE_IB_FN_MOD_FN_MOD(x) ((x) & GENMASK(1, 0))
#define GPV_RTE_IB_FN_MOD_RTE_IB_FN_MOD_FN_MOD_M GENMASK(1, 0)
#define GPV_RTE_IB_FN_MOD_RTE_IB_FN_MOD_FN_MOD_X(x) ((x) & GENMASK(1, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:APB_CSS_AHB_CNTL */
#define GPV_APB_CSS_AHB_CNTL(t)   (t + 0x2044)

#define GPV_APB_CSS_AHB_CNTL_APB_CSS_AHB_CNTL_DECERR_EN(x) ((x) & GENMASK(0, 0))
#define GPV_APB_CSS_AHB_CNTL_APB_CSS_AHB_CNTL_DECERR_EN_M GENMASK(0, 0)
#define GPV_APB_CSS_AHB_CNTL_APB_CSS_AHB_CNTL_DECERR_EN_X(x)\
	((x) & GENMASK(0, 0))

#define GPV_APB_CSS_AHB_CNTL_APB_CSS_AHB_CNTL_FORCE_INCR(x)\
	(((x) << 1) & GENMASK(1, 1))
#define GPV_APB_CSS_AHB_CNTL_APB_CSS_AHB_CNTL_FORCE_INCR_M GENMASK(1, 1)
#define GPV_APB_CSS_AHB_CNTL_APB_CSS_AHB_CNTL_FORCE_INCR_X(x)\
	(((x) & GENMASK(1, 1)) >> 1)

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:APB_CSS_IB_FN_MOD2 */
#define GPV_APB_CSS_IB_FN_MOD2(t) (t + 0x2024)

#define GPV_APB_CSS_IB_FN_MOD2_APB_CSS_IB_FN_MOD2_BYPASS_MERGE(x)\
	((x) & GENMASK(0, 0))
#define GPV_APB_CSS_IB_FN_MOD2_APB_CSS_IB_FN_MOD2_BYPASS_MERGE_M GENMASK(0, 0)
#define GPV_APB_CSS_IB_FN_MOD2_APB_CSS_IB_FN_MOD2_BYPASS_MERGE_X(x)\
	((x) & GENMASK(0, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:APB_CSS_IB_FN_MOD_ISS_BM */
#define GPV_APB_CSS_IB_FN_MOD_ISS_BM(t) (t + 0x2008)

#define GPV_APB_CSS_IB_FN_MOD_ISS_BM_APB_CSS_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1, 0))
#define GPV_APB_CSS_IB_FN_MOD_ISS_BM_APB_CSS_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1, 0)
#define GPV_APB_CSS_IB_FN_MOD_ISS_BM_APB_CSS_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:BOOT_RAM_FN_MOD_ISS_BM */
#define GPV_BOOT_RAM_FN_MOD_ISS_BM(t) (t + 0x3008)

#define GPV_BOOT_RAM_FN_MOD_ISS_BM_BOOT_RAM_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1, 0))
#define GPV_BOOT_RAM_FN_MOD_ISS_BM_BOOT_RAM_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1, 0)
#define GPV_BOOT_RAM_FN_MOD_ISS_BM_BOOT_RAM_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:BOOT_RAM_AHB_CNTL */
#define GPV_BOOT_RAM_AHB_CNTL(t)  (t + 0x3044)

#define GPV_BOOT_RAM_AHB_CNTL_BOOT_RAM_AHB_CNTL_DECERR_EN(x)\
	((x) & GENMASK(0, 0))
#define GPV_BOOT_RAM_AHB_CNTL_BOOT_RAM_AHB_CNTL_DECERR_EN_M GENMASK(0, 0)
#define GPV_BOOT_RAM_AHB_CNTL_BOOT_RAM_AHB_CNTL_DECERR_EN_X(x)\
	((x) & GENMASK(0, 0))

#define GPV_BOOT_RAM_AHB_CNTL_BOOT_RAM_AHB_CNTL_FORCE_INCR(x)\
	(((x) << 1) & GENMASK(1, 1))
#define GPV_BOOT_RAM_AHB_CNTL_BOOT_RAM_AHB_CNTL_FORCE_INCR_M GENMASK(1, 1)
#define GPV_BOOT_RAM_AHB_CNTL_BOOT_RAM_AHB_CNTL_FORCE_INCR_X(x)\
	(((x) & GENMASK(1, 1)) >> 1)

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:CPKCC_AHB_CNTL */
#define GPV_CPKCC_AHB_CNTL(t)     (t + 0x4044)

#define GPV_CPKCC_AHB_CNTL_CPKCC_AHB_CNTL_DECERR_EN(x) ((x) & GENMASK(0, 0))
#define GPV_CPKCC_AHB_CNTL_CPKCC_AHB_CNTL_DECERR_EN_M GENMASK(0, 0)
#define GPV_CPKCC_AHB_CNTL_CPKCC_AHB_CNTL_DECERR_EN_X(x) ((x) & GENMASK(0, 0))

#define GPV_CPKCC_AHB_CNTL_CPKCC_AHB_CNTL_FORCE_INCR(x)\
	(((x) << 1) & GENMASK(1, 1))
#define GPV_CPKCC_AHB_CNTL_CPKCC_AHB_CNTL_FORCE_INCR_M GENMASK(1, 1)
#define GPV_CPKCC_AHB_CNTL_CPKCC_AHB_CNTL_FORCE_INCR_X(x)\
	(((x) & GENMASK(1, 1)) >> 1)

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:CPKCC_IB_FN_MOD2 */
#define GPV_CPKCC_IB_FN_MOD2(t)   (t + 0x4024)

#define GPV_CPKCC_IB_FN_MOD2_CPKCC_IB_FN_MOD2_BYPASS_MERGE(x)\
	((x) & GENMASK(0, 0))
#define GPV_CPKCC_IB_FN_MOD2_CPKCC_IB_FN_MOD2_BYPASS_MERGE_M GENMASK(0, 0)
#define GPV_CPKCC_IB_FN_MOD2_CPKCC_IB_FN_MOD2_BYPASS_MERGE_X(x)\
	((x) & GENMASK(0, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:CPKCC_IB_FN_MOD_ISS_BM */
#define GPV_CPKCC_IB_FN_MOD_ISS_BM(t) (t + 0x4008)

#define GPV_CPKCC_IB_FN_MOD_ISS_BM_CPKCC_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1, 0))
#define GPV_CPKCC_IB_FN_MOD_ISS_BM_CPKCC_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1, 0)
#define GPV_CPKCC_IB_FN_MOD_ISS_BM_CPKCC_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:DDR_CSS_FN_MOD_ISS_BM */
#define GPV_DDR_CSS_FN_MOD_ISS_BM(t) (t + 0x5008)

#define GPV_DDR_CSS_FN_MOD_ISS_BM_DDR_CSS_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1, 0))
#define GPV_DDR_CSS_FN_MOD_ISS_BM_DDR_CSS_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1, 0)
#define GPV_DDR_CSS_FN_MOD_ISS_BM_DDR_CSS_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:CSS2HSS_IB_FN_MOD2 */
#define GPV_CSS2HSS_IB_FN_MOD2(t) (t + 0x6024)

#define GPV_CSS2HSS_IB_FN_MOD2_CSS2HSS_IB_FN_MOD2_BYPASS_MERGE(x)\
	((x) & GENMASK(0, 0))
#define GPV_CSS2HSS_IB_FN_MOD2_CSS2HSS_IB_FN_MOD2_BYPASS_MERGE_M GENMASK(0, 0)
#define GPV_CSS2HSS_IB_FN_MOD2_CSS2HSS_IB_FN_MOD2_BYPASS_MERGE_X(x)\
	((x) & GENMASK(0, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:CSS2HSS_IB_FN_MOD_LB */
#define GPV_CSS2HSS_IB_FN_MOD_LB(t) (t + 0x602c)

#define GPV_CSS2HSS_IB_FN_MOD_LB_FN_MOD_LB(x)    ((x) & GENMASK(0, 0))
#define GPV_CSS2HSS_IB_FN_MOD_LB_FN_MOD_LB_M     GENMASK(0, 0)
#define GPV_CSS2HSS_IB_FN_MOD_LB_FN_MOD_LB_X(x)  ((x) & GENMASK(0, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:CSS2HSS_IB_FN_MOD_ISS_BM */
#define GPV_CSS2HSS_IB_FN_MOD_ISS_BM(t) (t + 0x6008)

#define GPV_CSS2HSS_IB_FN_MOD_ISS_BM_CSS2HSS_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1, 0))
#define GPV_CSS2HSS_IB_FN_MOD_ISS_BM_CSS2HSS_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1, 0)
#define GPV_CSS2HSS_IB_FN_MOD_ISS_BM_CSS2HSS_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:CSR_REGS_AHB_CNTL */
#define GPV_CSR_REGS_AHB_CNTL(t)  (t + 0x7044)

#define GPV_CSR_REGS_AHB_CNTL_CSR_REGS_AHB_CNTL_DECERR_EN(x)\
	((x) & GENMASK(0, 0))
#define GPV_CSR_REGS_AHB_CNTL_CSR_REGS_AHB_CNTL_DECERR_EN_M GENMASK(0, 0)
#define GPV_CSR_REGS_AHB_CNTL_CSR_REGS_AHB_CNTL_DECERR_EN_X(x)\
	((x) & GENMASK(0, 0))

#define GPV_CSR_REGS_AHB_CNTL_CSR_REGS_AHB_CNTL_FORCE_INCR(x)\
	(((x) << 1) & GENMASK(1, 1))
#define GPV_CSR_REGS_AHB_CNTL_CSR_REGS_AHB_CNTL_FORCE_INCR_M GENMASK(1, 1)
#define GPV_CSR_REGS_AHB_CNTL_CSR_REGS_AHB_CNTL_FORCE_INCR_X(x)\
	(((x) & GENMASK(1, 1)) >> 1)

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:CSR_REGS_IB_FN_MOD2 */
#define GPV_CSR_REGS_IB_FN_MOD2(t) (t + 0x7024)

#define GPV_CSR_REGS_IB_FN_MOD2_CSR_REGS_IB_FN_MOD2_BYPASS_MERGE(x)\
	((x) & GENMASK(0, 0))
#define GPV_CSR_REGS_IB_FN_MOD2_CSR_REGS_IB_FN_MOD2_BYPASS_MERGE_M GENMASK(0, 0)
#define GPV_CSR_REGS_IB_FN_MOD2_CSR_REGS_IB_FN_MOD2_BYPASS_MERGE_X(x)\
	((x) & GENMASK(0, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:CSR_REGS_IB_FN_MOD_ISS_BM */
#define GPV_CSR_REGS_IB_FN_MOD_ISS_BM(t) (t + 0x7008)

#define GPV_CSR_REGS_IB_FN_MOD_ISS_BM_CSR_REGS_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1, 0))
#define GPV_CSR_REGS_IB_FN_MOD_ISS_BM_CSR_REGS_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1, 0)
#define GPV_CSR_REGS_IB_FN_MOD_ISS_BM_CSR_REGS_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:CPU_REGS_AHB_CNTL */
#define GPV_CPU_REGS_AHB_CNTL(t)  (t + 0x8044)

#define GPV_CPU_REGS_AHB_CNTL_CPU_REGS_AHB_CNTL_DECERR_EN(x)\
	((x) & GENMASK(0, 0))
#define GPV_CPU_REGS_AHB_CNTL_CPU_REGS_AHB_CNTL_DECERR_EN_M GENMASK(0, 0)
#define GPV_CPU_REGS_AHB_CNTL_CPU_REGS_AHB_CNTL_DECERR_EN_X(x)\
	((x) & GENMASK(0, 0))

#define GPV_CPU_REGS_AHB_CNTL_CPU_REGS_AHB_CNTL_FORCE_INCR(x)\
	(((x) << 1) & GENMASK(1, 1))
#define GPV_CPU_REGS_AHB_CNTL_CPU_REGS_AHB_CNTL_FORCE_INCR_M GENMASK(1, 1)
#define GPV_CPU_REGS_AHB_CNTL_CPU_REGS_AHB_CNTL_FORCE_INCR_X(x)\
	(((x) & GENMASK(1, 1)) >> 1)

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:CPU_REGS_IB_FN_MOD2 */
#define GPV_CPU_REGS_IB_FN_MOD2(t) (t + 0x8024)

#define GPV_CPU_REGS_IB_FN_MOD2_CPU_REGS_IB_FN_MOD2_BYPASS_MERGE(x)\
	((x) & GENMASK(0, 0))
#define GPV_CPU_REGS_IB_FN_MOD2_CPU_REGS_IB_FN_MOD2_BYPASS_MERGE_M GENMASK(0, 0)
#define GPV_CPU_REGS_IB_FN_MOD2_CPU_REGS_IB_FN_MOD2_BYPASS_MERGE_X(x)\
	((x) & GENMASK(0, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:CPU_REGS_IB_FN_MOD_ISS_BM */
#define GPV_CPU_REGS_IB_FN_MOD_ISS_BM(t) (t + 0x8008)

#define GPV_CPU_REGS_IB_FN_MOD_ISS_BM_CPU_REGS_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1, 0))
#define GPV_CPU_REGS_IB_FN_MOD_ISS_BM_CPU_REGS_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1, 0)
#define GPV_CPU_REGS_IB_FN_MOD_ISS_BM_CPU_REGS_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:APB_MAIN1_FN_MOD_ISS_BM */
#define GPV_APB_MAIN1_FN_MOD_ISS_BM(t) (t + 0x9008)

#define GPV_APB_MAIN1_FN_MOD_ISS_BM_APB_MAIN1_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1, 0))
#define GPV_APB_MAIN1_FN_MOD_ISS_BM_APB_MAIN1_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1, 0)
#define GPV_APB_MAIN1_FN_MOD_ISS_BM_APB_MAIN1_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:APB_MAIN1_AHB_CNTL */
#define GPV_APB_MAIN1_AHB_CNTL(t) (t + 0x9044)

#define GPV_APB_MAIN1_AHB_CNTL_APB_MAIN1_AHB_CNTL_DECERR_EN(x)\
	((x) & GENMASK(0, 0))
#define GPV_APB_MAIN1_AHB_CNTL_APB_MAIN1_AHB_CNTL_DECERR_EN_M GENMASK(0, 0)
#define GPV_APB_MAIN1_AHB_CNTL_APB_MAIN1_AHB_CNTL_DECERR_EN_X(x)\
	((x) & GENMASK(0, 0))

#define GPV_APB_MAIN1_AHB_CNTL_APB_MAIN1_AHB_CNTL_FORCE_INCR(x)\
	(((x) << 1) & GENMASK(1, 1))
#define GPV_APB_MAIN1_AHB_CNTL_APB_MAIN1_AHB_CNTL_FORCE_INCR_M GENMASK(1, 1)
#define GPV_APB_MAIN1_AHB_CNTL_APB_MAIN1_AHB_CNTL_FORCE_INCR_X(x)\
	(((x) & GENMASK(1, 1)) >> 1)

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:APB_MAIN2_FN_MOD_ISS_BM */
#define GPV_APB_MAIN2_FN_MOD_ISS_BM(t) (t + 0xa008)

#define GPV_APB_MAIN2_FN_MOD_ISS_BM_APB_MAIN2_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1, 0))
#define GPV_APB_MAIN2_FN_MOD_ISS_BM_APB_MAIN2_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1, 0)
#define GPV_APB_MAIN2_FN_MOD_ISS_BM_APB_MAIN2_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:APB_MAIN2_AHB_CNTL */
#define GPV_APB_MAIN2_AHB_CNTL(t) (t + 0xa044)

#define GPV_APB_MAIN2_AHB_CNTL_APB_MAIN2_AHB_CNTL_DECERR_EN(x)\
	((x) & GENMASK(0, 0))
#define GPV_APB_MAIN2_AHB_CNTL_APB_MAIN2_AHB_CNTL_DECERR_EN_M GENMASK(0, 0)
#define GPV_APB_MAIN2_AHB_CNTL_APB_MAIN2_AHB_CNTL_DECERR_EN_X(x)\
	((x) & GENMASK(0, 0))

#define GPV_APB_MAIN2_AHB_CNTL_APB_MAIN2_AHB_CNTL_FORCE_INCR(x)\
	(((x) << 1) & GENMASK(1, 1))
#define GPV_APB_MAIN2_AHB_CNTL_APB_MAIN2_AHB_CNTL_FORCE_INCR_M GENMASK(1, 1)
#define GPV_APB_MAIN2_AHB_CNTL_APB_MAIN2_AHB_CNTL_FORCE_INCR_X(x)\
	(((x) & GENMASK(1, 1)) >> 1)

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:DDR_MAIN_FN_MOD_ISS_BM */
#define GPV_DDR_MAIN_FN_MOD_ISS_BM(t) (t + 0xb008)

#define GPV_DDR_MAIN_FN_MOD_ISS_BM_DDR_MAIN_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1, 0))
#define GPV_DDR_MAIN_FN_MOD_ISS_BM_DDR_MAIN_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1, 0)
#define GPV_DDR_MAIN_FN_MOD_ISS_BM_DDR_MAIN_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:PI_AHB_CNTL */
#define GPV_PI_AHB_CNTL(t)        (t + 0xc044)

#define GPV_PI_AHB_CNTL_PI_AHB_CNTL_DECERR_EN(x) ((x) & GENMASK(0, 0))
#define GPV_PI_AHB_CNTL_PI_AHB_CNTL_DECERR_EN_M  GENMASK(0, 0)
#define GPV_PI_AHB_CNTL_PI_AHB_CNTL_DECERR_EN_X(x) ((x) & GENMASK(0, 0))

#define GPV_PI_AHB_CNTL_PI_AHB_CNTL_FORCE_INCR(x) (((x) << 1) & GENMASK(1, 1))
#define GPV_PI_AHB_CNTL_PI_AHB_CNTL_FORCE_INCR_M GENMASK(1, 1)
#define GPV_PI_AHB_CNTL_PI_AHB_CNTL_FORCE_INCR_X(x) (((x) & GENMASK(1, 1)) >> 1)

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:PI_IB_FN_MOD2 */
#define GPV_PI_IB_FN_MOD2(t)      (t + 0xc024)

#define GPV_PI_IB_FN_MOD2_PI_IB_FN_MOD2_BYPASS_MERGE(x) ((x) & GENMASK(0, 0))
#define GPV_PI_IB_FN_MOD2_PI_IB_FN_MOD2_BYPASS_MERGE_M GENMASK(0, 0)
#define GPV_PI_IB_FN_MOD2_PI_IB_FN_MOD2_BYPASS_MERGE_X(x) ((x) & GENMASK(0, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:PI_IB_FN_MOD_ISS_BM */
#define GPV_PI_IB_FN_MOD_ISS_BM(t) (t + 0xc008)

#define GPV_PI_IB_FN_MOD_ISS_BM_PI_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1, 0))
#define GPV_PI_IB_FN_MOD_ISS_BM_PI_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1, 0)
#define GPV_PI_IB_FN_MOD_ISS_BM_PI_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:MAIN2HSS_FN_MOD_ISS_BM */
#define GPV_MAIN2HSS_FN_MOD_ISS_BM(t) (t + 0xd008)

#define GPV_MAIN2HSS_FN_MOD_ISS_BM_MAIN2HSS_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1, 0))
#define GPV_MAIN2HSS_FN_MOD_ISS_BM_MAIN2HSS_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1, 0)
#define GPV_MAIN2HSS_FN_MOD_ISS_BM_MAIN2HSS_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:PCIE_DBI_IB_FN_MOD2 */
#define GPV_PCIE_DBI_IB_FN_MOD2(t) (t + 0xe024)

#define GPV_PCIE_DBI_IB_FN_MOD2_PCIE_DBI_IB_FN_MOD2_BYPASS_MERGE(x)\
	((x) & GENMASK(0, 0))
#define GPV_PCIE_DBI_IB_FN_MOD2_PCIE_DBI_IB_FN_MOD2_BYPASS_MERGE_M GENMASK(0, 0)
#define GPV_PCIE_DBI_IB_FN_MOD2_PCIE_DBI_IB_FN_MOD2_BYPASS_MERGE_X(x)\
	((x) & GENMASK(0, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:PCIE_DBI_IB_FN_MOD_ISS_BM */
#define GPV_PCIE_DBI_IB_FN_MOD_ISS_BM(t) (t + 0xe008)

#define GPV_PCIE_DBI_IB_FN_MOD_ISS_BM_PCIE_DBI_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1, 0))
#define GPV_PCIE_DBI_IB_FN_MOD_ISS_BM_PCIE_DBI_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1, 0)
#define GPV_PCIE_DBI_IB_FN_MOD_ISS_BM_PCIE_DBI_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:PCIE_OB_FN_MOD_ISS_BM */
#define GPV_PCIE_OB_FN_MOD_ISS_BM(t) (t + 0xf008)

#define GPV_PCIE_OB_FN_MOD_ISS_BM_PCIE_OB_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1, 0))
#define GPV_PCIE_OB_FN_MOD_ISS_BM_PCIE_OB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1, 0)
#define GPV_PCIE_OB_FN_MOD_ISS_BM_PCIE_OB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:QSPI1_FN_MOD_ISS_BM */
#define GPV_QSPI1_FN_MOD_ISS_BM(t) (t + 0x10008)

#define GPV_QSPI1_FN_MOD_ISS_BM_QSPI1_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1, 0))
#define GPV_QSPI1_FN_MOD_ISS_BM_QSPI1_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1, 0)
#define GPV_QSPI1_FN_MOD_ISS_BM_QSPI1_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:QSPI1_AHB_CNTL */
#define GPV_QSPI1_AHB_CNTL(t)     (t + 0x10044)

#define GPV_QSPI1_AHB_CNTL_QSPI1_AHB_CNTL_DECERR_EN(x) ((x) & GENMASK(0, 0))
#define GPV_QSPI1_AHB_CNTL_QSPI1_AHB_CNTL_DECERR_EN_M GENMASK(0, 0)
#define GPV_QSPI1_AHB_CNTL_QSPI1_AHB_CNTL_DECERR_EN_X(x) ((x) & GENMASK(0, 0))

#define GPV_QSPI1_AHB_CNTL_QSPI1_AHB_CNTL_FORCE_INCR(x)\
	(((x) << 1) & GENMASK(1, 1))
#define GPV_QSPI1_AHB_CNTL_QSPI1_AHB_CNTL_FORCE_INCR_M GENMASK(1, 1)
#define GPV_QSPI1_AHB_CNTL_QSPI1_AHB_CNTL_FORCE_INCR_X(x)\
	(((x) & GENMASK(1, 1)) >> 1)

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:PCIE_CFG_AHB_CNTL */
#define GPV_PCIE_CFG_AHB_CNTL(t)  (t + 0x11044)

#define GPV_PCIE_CFG_AHB_CNTL_PCIE_CFG_AHB_CNTL_DECERR_EN(x)\
	((x) & GENMASK(0, 0))
#define GPV_PCIE_CFG_AHB_CNTL_PCIE_CFG_AHB_CNTL_DECERR_EN_M GENMASK(0, 0)
#define GPV_PCIE_CFG_AHB_CNTL_PCIE_CFG_AHB_CNTL_DECERR_EN_X(x)\
	((x) & GENMASK(0, 0))

#define GPV_PCIE_CFG_AHB_CNTL_PCIE_CFG_AHB_CNTL_FORCE_INCR(x)\
	(((x) << 1) & GENMASK(1, 1))
#define GPV_PCIE_CFG_AHB_CNTL_PCIE_CFG_AHB_CNTL_FORCE_INCR_M GENMASK(1, 1)
#define GPV_PCIE_CFG_AHB_CNTL_PCIE_CFG_AHB_CNTL_FORCE_INCR_X(x)\
	(((x) & GENMASK(1, 1)) >> 1)

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:PCIE_CFG_IB_FN_MOD2 */
#define GPV_PCIE_CFG_IB_FN_MOD2(t) (t + 0x11024)

#define GPV_PCIE_CFG_IB_FN_MOD2_PCIE_CFG_IB_FN_MOD2_BYPASS_MERGE(x)\
	((x) & GENMASK(0, 0))
#define GPV_PCIE_CFG_IB_FN_MOD2_PCIE_CFG_IB_FN_MOD2_BYPASS_MERGE_M GENMASK(0, 0)
#define GPV_PCIE_CFG_IB_FN_MOD2_PCIE_CFG_IB_FN_MOD2_BYPASS_MERGE_X(x)\
	((x) & GENMASK(0, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:PCIE_CFG_IB_FN_MOD_ISS_BM */
#define GPV_PCIE_CFG_IB_FN_MOD_ISS_BM(t) (t + 0x11008)

#define GPV_PCIE_CFG_IB_FN_MOD_ISS_BM_PCIE_CFG_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1, 0))
#define GPV_PCIE_CFG_IB_FN_MOD_ISS_BM_PCIE_CFG_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1, 0)
#define GPV_PCIE_CFG_IB_FN_MOD_ISS_BM_PCIE_CFG_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:CUPHY_AHB_CNTL */
#define GPV_CUPHY_AHB_CNTL(t)     (t + 0x12044)

#define GPV_CUPHY_AHB_CNTL_CUPHY_AHB_CNTL_DECERR_EN(x) ((x) & GENMASK(0, 0))
#define GPV_CUPHY_AHB_CNTL_CUPHY_AHB_CNTL_DECERR_EN_M GENMASK(0, 0)
#define GPV_CUPHY_AHB_CNTL_CUPHY_AHB_CNTL_DECERR_EN_X(x) ((x) & GENMASK(0, 0))

#define GPV_CUPHY_AHB_CNTL_CUPHY_AHB_CNTL_FORCE_INCR(x)\
	(((x) << 1) & GENMASK(1, 1))
#define GPV_CUPHY_AHB_CNTL_CUPHY_AHB_CNTL_FORCE_INCR_M GENMASK(1, 1)
#define GPV_CUPHY_AHB_CNTL_CUPHY_AHB_CNTL_FORCE_INCR_X(x)\
	(((x) & GENMASK(1, 1)) >> 1)

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:CUPHY_IB_FN_MOD2 */
#define GPV_CUPHY_IB_FN_MOD2(t)   (t + 0x12024)

#define GPV_CUPHY_IB_FN_MOD2_CUPHY_IB_FN_MOD2_BYPASS_MERGE(x)\
	((x) & GENMASK(0, 0))
#define GPV_CUPHY_IB_FN_MOD2_CUPHY_IB_FN_MOD2_BYPASS_MERGE_M GENMASK(0, 0)
#define GPV_CUPHY_IB_FN_MOD2_CUPHY_IB_FN_MOD2_BYPASS_MERGE_X(x)\
	((x) & GENMASK(0, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:CUPHY_IB_FN_MOD_ISS_BM */
#define GPV_CUPHY_IB_FN_MOD_ISS_BM(t) (t + 0x12008)

#define GPV_CUPHY_IB_FN_MOD_ISS_BM_CUPHY_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1, 0))
#define GPV_CUPHY_IB_FN_MOD_ISS_BM_CUPHY_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1, 0)
#define GPV_CUPHY_IB_FN_MOD_ISS_BM_CUPHY_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:FDMA_SLV_M_IB_FN_MOD2 */
#define GPV_FDMA_SLV_M_IB_FN_MOD2(t) (t + 0x13024)

#define GPV_FDMA_SLV_M_IB_FN_MOD2_FDMA_SLV_M_IB_FN_MOD2_BYPASS_MERGE(x)\
	((x) & GENMASK(0, 0))
#define GPV_FDMA_SLV_M_IB_FN_MOD2_FDMA_SLV_M_IB_FN_MOD2_BYPASS_MERGE_M\
	GENMASK(0, 0)
#define GPV_FDMA_SLV_M_IB_FN_MOD2_FDMA_SLV_M_IB_FN_MOD2_BYPASS_MERGE_X(x)\
	((x) & GENMASK(0, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:APB_MAIN3_IB_FN_MOD2 */
#define GPV_APB_MAIN3_IB_FN_MOD2(t) (t + 0x14024)

#define GPV_APB_MAIN3_IB_FN_MOD2_APB_MAIN3_IB_FN_MOD2_BYPASS_MERGE(x)\
	((x) & GENMASK(0, 0))
#define GPV_APB_MAIN3_IB_FN_MOD2_APB_MAIN3_IB_FN_MOD2_BYPASS_MERGE_M\
	GENMASK(0, 0)
#define GPV_APB_MAIN3_IB_FN_MOD2_APB_MAIN3_IB_FN_MOD2_BYPASS_MERGE_X(x)\
	((x) & GENMASK(0, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:APB_MAIN3_IB_FN_MOD_ISS_BM */
#define GPV_APB_MAIN3_IB_FN_MOD_ISS_BM(t) (t + 0x14008)

#define GPV_APB_MAIN3_IB_FN_MOD_ISS_BM_APB_MAIN3_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1, 0))
#define GPV_APB_MAIN3_IB_FN_MOD_ISS_BM_APB_MAIN3_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1, 0)
#define GPV_APB_MAIN3_IB_FN_MOD_ISS_BM_APB_MAIN3_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:APB_CSS2_IB_FN_MOD2 */
#define GPV_APB_CSS2_IB_FN_MOD2(t) (t + 0x15024)

#define GPV_APB_CSS2_IB_FN_MOD2_APB_CSS2_IB_FN_MOD2_BYPASS_MERGE(x)\
	((x) & GENMASK(0, 0))
#define GPV_APB_CSS2_IB_FN_MOD2_APB_CSS2_IB_FN_MOD2_BYPASS_MERGE_M GENMASK(0, 0)
#define GPV_APB_CSS2_IB_FN_MOD2_APB_CSS2_IB_FN_MOD2_BYPASS_MERGE_X(x)\
	((x) & GENMASK(0, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:APB_CSS2_IB_FN_MOD_ISS_BM */
#define GPV_APB_CSS2_IB_FN_MOD_ISS_BM(t) (t + 0x15008)

#define GPV_APB_CSS2_IB_FN_MOD_ISS_BM_APB_CSS2_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM(x)\
	((x) & GENMASK(1, 0))
#define GPV_APB_CSS2_IB_FN_MOD_ISS_BM_APB_CSS2_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M\
	GENMASK(1, 0)
#define GPV_APB_CSS2_IB_FN_MOD_ISS_BM_APB_CSS2_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_X(x)\
	((x) & GENMASK(1, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:CSS2HSS_IB_FN_MOD */
#define GPV_CSS2HSS_IB_FN_MOD(t)  (t + 0x6108)

#define GPV_CSS2HSS_IB_FN_MOD_CSS2HSS_IB_FN_MOD_FN_MOD(x) ((x) & GENMASK(1, 0))
#define GPV_CSS2HSS_IB_FN_MOD_CSS2HSS_IB_FN_MOD_FN_MOD_M GENMASK(1, 0)
#define GPV_CSS2HSS_IB_FN_MOD_CSS2HSS_IB_FN_MOD_FN_MOD_X(x)\
	((x) & GENMASK(1, 0))

/*      GPV:ADDRESSBLOCK_DEFAULT_0XE8B00000_CA7:PCIE_DBI_IB_FN_MOD */
#define GPV_PCIE_DBI_IB_FN_MOD(t) (t + 0xe108)

#define GPV_PCIE_DBI_IB_FN_MOD_PCIE_DBI_IB_FN_MOD_FN_MOD(x)\
	((x) & GENMASK(1, 0))
#define GPV_PCIE_DBI_IB_FN_MOD_PCIE_DBI_IB_FN_MOD_FN_MOD_M GENMASK(1, 0)
#define GPV_PCIE_DBI_IB_FN_MOD_PCIE_DBI_IB_FN_MOD_FN_MOD_X(x)\
	((x) & GENMASK(1, 0))

/*      HMATRIX2:HMATRIX2_REGS:MATRIX_SRTSR0 */
#define HMATRIX2_MATRIX_SRTSR0(t) (t + 0x280)

#define HMATRIX2_MATRIX_SRTSR0_SRTOP7_SRTSR0(x)  (((x) << 28) & GENMASK(31, 28))
#define HMATRIX2_MATRIX_SRTSR0_SRTOP7_SRTSR0_M   GENMASK(31, 28)
#define HMATRIX2_MATRIX_SRTSR0_SRTOP7_SRTSR0_X(x)\
	(((x) & GENMASK(31, 28)) >> 28)

#define HMATRIX2_MATRIX_SRTSR0_SRTOP6_SRTSR0(x)  (((x) << 24) & GENMASK(27, 24))
#define HMATRIX2_MATRIX_SRTSR0_SRTOP6_SRTSR0_M   GENMASK(27, 24)
#define HMATRIX2_MATRIX_SRTSR0_SRTOP6_SRTSR0_X(x)\
	(((x) & GENMASK(27, 24)) >> 24)

#define HMATRIX2_MATRIX_SRTSR0_SRTOP5_SRTSR0(x)  (((x) << 20) & GENMASK(23, 20))
#define HMATRIX2_MATRIX_SRTSR0_SRTOP5_SRTSR0_M   GENMASK(23, 20)
#define HMATRIX2_MATRIX_SRTSR0_SRTOP5_SRTSR0_X(x)\
	(((x) & GENMASK(23, 20)) >> 20)

#define HMATRIX2_MATRIX_SRTSR0_SRTOP4_SRTSR0(x)  (((x) << 16) & GENMASK(19, 16))
#define HMATRIX2_MATRIX_SRTSR0_SRTOP4_SRTSR0_M   GENMASK(19, 16)
#define HMATRIX2_MATRIX_SRTSR0_SRTOP4_SRTSR0_X(x)\
	(((x) & GENMASK(19, 16)) >> 16)

#define HMATRIX2_MATRIX_SRTSR0_SRTOP3_SRTSR0(x)  (((x) << 12) & GENMASK(15, 12))
#define HMATRIX2_MATRIX_SRTSR0_SRTOP3_SRTSR0_M   GENMASK(15, 12)
#define HMATRIX2_MATRIX_SRTSR0_SRTOP3_SRTSR0_X(x)\
	(((x) & GENMASK(15, 12)) >> 12)

#define HMATRIX2_MATRIX_SRTSR0_SRTOP2_SRTSR0(x)  (((x) << 8) & GENMASK(11, 8))
#define HMATRIX2_MATRIX_SRTSR0_SRTOP2_SRTSR0_M   GENMASK(11, 8)
#define HMATRIX2_MATRIX_SRTSR0_SRTOP2_SRTSR0_X(x) (((x) & GENMASK(11, 8)) >> 8)

#define HMATRIX2_MATRIX_SRTSR0_SRTOP1_SRTSR0(x)  (((x) << 4) & GENMASK(7, 4))
#define HMATRIX2_MATRIX_SRTSR0_SRTOP1_SRTSR0_M   GENMASK(7, 4)
#define HMATRIX2_MATRIX_SRTSR0_SRTOP1_SRTSR0_X(x) (((x) & GENMASK(7, 4)) >> 4)

#define HMATRIX2_MATRIX_SRTSR0_SRTOP0_SRTSR0(x)  ((x) & GENMASK(3, 0))
#define HMATRIX2_MATRIX_SRTSR0_SRTOP0_SRTSR0_M   GENMASK(3, 0)
#define HMATRIX2_MATRIX_SRTSR0_SRTOP0_SRTSR0_X(x) ((x) & GENMASK(3, 0))

/*      OTP:OTP_REGS:OTP_PWR_DN */
#define OTP_OTP_PWR_DN(t)         (t + 0x00)

#define OTP_OTP_PWR_DN_OTP_PWRDN_N(x)            ((x) & GENMASK(0, 0))
#define OTP_OTP_PWR_DN_OTP_PWRDN_N_M             GENMASK(0, 0)
#define OTP_OTP_PWR_DN_OTP_PWRDN_N_X(x)          ((x) & GENMASK(0, 0))

/*      OTP:OTP_REGS:OTP_ADDR_HI */
#define OTP_OTP_ADDR_HI(t)        (t + 0x04)

#define OTP_OTP_ADDR_HI_OTP_ADDR_15_11(x)        ((x) & GENMASK(4, 0))
#define OTP_OTP_ADDR_HI_OTP_ADDR_15_11_M         GENMASK(4, 0)
#define OTP_OTP_ADDR_HI_OTP_ADDR_15_11_X(x)      ((x) & GENMASK(4, 0))

/*      OTP:OTP_REGS:OTP_ADDR_LO */
#define OTP_OTP_ADDR_LO(t)        (t + 0x08)

#define OTP_OTP_ADDR_LO_OTP_ADDR_10_3(x)         ((x) & GENMASK(7, 0))
#define OTP_OTP_ADDR_LO_OTP_ADDR_10_3_M          GENMASK(7, 0)
#define OTP_OTP_ADDR_LO_OTP_ADDR_10_3_X(x)       ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_ADDR_BITS */
#define OTP_OTP_ADDR_BITS(t)      (t + 0x0c)

#define OTP_OTP_ADDR_BITS_OTP_ADDR_2_0(x)        ((x) & GENMASK(2, 0))
#define OTP_OTP_ADDR_BITS_OTP_ADDR_2_0_M         GENMASK(2, 0)
#define OTP_OTP_ADDR_BITS_OTP_ADDR_2_0_X(x)      ((x) & GENMASK(2, 0))

/*      OTP:OTP_REGS:OTP_PRGM_DATA */
#define OTP_OTP_PRGM_DATA(t)      (t + 0x10)

#define OTP_OTP_PRGM_DATA_OTP_WR_DATA(x)         ((x) & GENMASK(7, 0))
#define OTP_OTP_PRGM_DATA_OTP_WR_DATA_M          GENMASK(7, 0)
#define OTP_OTP_PRGM_DATA_OTP_WR_DATA_X(x)       ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_PRGM_MODE */
#define OTP_OTP_PRGM_MODE(t)      (t + 0x14)

#define OTP_OTP_PRGM_MODE_OTP_PGM_MODE_BYTE(x)   ((x) & GENMASK(0, 0))
#define OTP_OTP_PRGM_MODE_OTP_PGM_MODE_BYTE_M    GENMASK(0, 0)
#define OTP_OTP_PRGM_MODE_OTP_PGM_MODE_BYTE_X(x) ((x) & GENMASK(0, 0))

/*      OTP:OTP_REGS:OTP_RD_DATA */
#define OTP_OTP_RD_DATA(t)        (t + 0x18)

#define OTP_OTP_RD_DATA_OTP_RD_DATA_FLD(x)       ((x) & GENMASK(7, 0))
#define OTP_OTP_RD_DATA_OTP_RD_DATA_FLD_M        GENMASK(7, 0)
#define OTP_OTP_RD_DATA_OTP_RD_DATA_FLD_X(x)     ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_FUNC_CMD */
#define OTP_OTP_FUNC_CMD(t)       (t + 0x20)

#define OTP_OTP_FUNC_CMD_OTP_FW_SMART_PGM_INIT_ACCESS(x)\
	(((x) << 4) & GENMASK(4, 4))
#define OTP_OTP_FUNC_CMD_OTP_FW_SMART_PGM_INIT_ACCESS_M GENMASK(4, 4)
#define OTP_OTP_FUNC_CMD_OTP_FW_SMART_PGM_INIT_ACCESS_X(x)\
	(((x) & GENMASK(4, 4)) >> 4)

#define OTP_OTP_FUNC_CMD_OTP_FW_SMART_PGM_EN(x)  (((x) << 3) & GENMASK(3, 3))
#define OTP_OTP_FUNC_CMD_OTP_FW_SMART_PGM_EN_M   GENMASK(3, 3)
#define OTP_OTP_FUNC_CMD_OTP_FW_SMART_PGM_EN_X(x) (((x) & GENMASK(3, 3)) >> 3)

#define OTP_OTP_FUNC_CMD_OTP_RESET(x)            (((x) << 2) & GENMASK(2, 2))
#define OTP_OTP_FUNC_CMD_OTP_RESET_M             GENMASK(2, 2)
#define OTP_OTP_FUNC_CMD_OTP_RESET_X(x)          (((x) & GENMASK(2, 2)) >> 2)

#define OTP_OTP_FUNC_CMD_OTP_PROGRAM(x)          (((x) << 1) & GENMASK(1, 1))
#define OTP_OTP_FUNC_CMD_OTP_PROGRAM_M           GENMASK(1, 1)
#define OTP_OTP_FUNC_CMD_OTP_PROGRAM_X(x)        (((x) & GENMASK(1, 1)) >> 1)

#define OTP_OTP_FUNC_CMD_OTP_READ(x)             ((x) & GENMASK(0, 0))
#define OTP_OTP_FUNC_CMD_OTP_READ_M              GENMASK(0, 0)
#define OTP_OTP_FUNC_CMD_OTP_READ_X(x)           ((x) & GENMASK(0, 0))

/*      OTP:OTP_REGS:OTP_TEST_CMD */
#define OTP_OTP_TEST_CMD(t)       (t + 0x24)

#define OTP_OTP_TEST_CMD_OTP_TEST_DEC_SEL(x)     (((x) << 4) & GENMASK(4, 4))
#define OTP_OTP_TEST_CMD_OTP_TEST_DEC_SEL_M      GENMASK(4, 4)
#define OTP_OTP_TEST_CMD_OTP_TEST_DEC_SEL_X(x)   (((x) & GENMASK(4, 4)) >> 4)

#define OTP_OTP_TEST_CMD_OTP_WRTEST(x)           (((x) << 2) & GENMASK(2, 2))
#define OTP_OTP_TEST_CMD_OTP_WRTEST_M            GENMASK(2, 2)
#define OTP_OTP_TEST_CMD_OTP_WRTEST_X(x)         (((x) & GENMASK(2, 2)) >> 2)

#define OTP_OTP_TEST_CMD_OTP_TESTDEC(x)          (((x) << 1) & GENMASK(1, 1))
#define OTP_OTP_TEST_CMD_OTP_TESTDEC_M           GENMASK(1, 1)
#define OTP_OTP_TEST_CMD_OTP_TESTDEC_X(x)        (((x) & GENMASK(1, 1)) >> 1)

#define OTP_OTP_TEST_CMD_OTP_BLANKCHECK(x)       ((x) & GENMASK(0, 0))
#define OTP_OTP_TEST_CMD_OTP_BLANKCHECK_M        GENMASK(0, 0)
#define OTP_OTP_TEST_CMD_OTP_BLANKCHECK_X(x)     ((x) & GENMASK(0, 0))

/*      OTP:OTP_REGS:OTP_CMD_GO */
#define OTP_OTP_CMD_GO(t)         (t + 0x28)

#define OTP_OTP_CMD_GO_OTP_GO(x)                 ((x) & GENMASK(0, 0))
#define OTP_OTP_CMD_GO_OTP_GO_M                  GENMASK(0, 0)
#define OTP_OTP_CMD_GO_OTP_GO_X(x)               ((x) & GENMASK(0, 0))

/*      OTP:OTP_REGS:OTP_PASS_FAIL */
#define OTP_OTP_PASS_FAIL(t)      (t + 0x2c)

#define OTP_OTP_PASS_FAIL_OTP_READ_PROHIBITED(x) (((x) << 3) & GENMASK(3, 3))
#define OTP_OTP_PASS_FAIL_OTP_READ_PROHIBITED_M  GENMASK(3, 3)
#define OTP_OTP_PASS_FAIL_OTP_READ_PROHIBITED_X(x) (((x) & GENMASK(3, 3)) >> 3)

#define OTP_OTP_PASS_FAIL_OTP_WRITE_PROHIBITED(x) (((x) << 2) & GENMASK(2, 2))
#define OTP_OTP_PASS_FAIL_OTP_WRITE_PROHIBITED_M GENMASK(2, 2)
#define OTP_OTP_PASS_FAIL_OTP_WRITE_PROHIBITED_X(x) (((x) & GENMASK(2, 2)) >> 2)

#define OTP_OTP_PASS_FAIL_OTP_PASS(x)            (((x) << 1) & GENMASK(1, 1))
#define OTP_OTP_PASS_FAIL_OTP_PASS_M             GENMASK(1, 1)
#define OTP_OTP_PASS_FAIL_OTP_PASS_X(x)          (((x) & GENMASK(1, 1)) >> 1)

#define OTP_OTP_PASS_FAIL_OTP_FAIL(x)            ((x) & GENMASK(0, 0))
#define OTP_OTP_PASS_FAIL_OTP_FAIL_M             GENMASK(0, 0)
#define OTP_OTP_PASS_FAIL_OTP_FAIL_X(x)          ((x) & GENMASK(0, 0))

/*      OTP:OTP_REGS:OTP_STATUS */
#define OTP_OTP_STATUS(t)         (t + 0x30)

#define OTP_OTP_STATUS_OTP_WEB(x)                (((x) << 3) & GENMASK(3, 3))
#define OTP_OTP_STATUS_OTP_WEB_M                 GENMASK(3, 3)
#define OTP_OTP_STATUS_OTP_WEB_X(x)              (((x) & GENMASK(3, 3)) >> 3)

#define OTP_OTP_STATUS_OTP_PGMEN(x)              (((x) << 2) & GENMASK(2, 2))
#define OTP_OTP_STATUS_OTP_PGMEN_M               GENMASK(2, 2)
#define OTP_OTP_STATUS_OTP_PGMEN_X(x)            (((x) & GENMASK(2, 2)) >> 2)

#define OTP_OTP_STATUS_OTP_CPUMPEN(x)            (((x) << 1) & GENMASK(1, 1))
#define OTP_OTP_STATUS_OTP_CPUMPEN_M             GENMASK(1, 1)
#define OTP_OTP_STATUS_OTP_CPUMPEN_X(x)          (((x) & GENMASK(1, 1)) >> 1)

#define OTP_OTP_STATUS_OTP_BUSY(x)               ((x) & GENMASK(0, 0))
#define OTP_OTP_STATUS_OTP_BUSY_M                GENMASK(0, 0)
#define OTP_OTP_STATUS_OTP_BUSY_X(x)             ((x) & GENMASK(0, 0))

/*      OTP:OTP_REGS:OTP_MAX_PRG */
#define OTP_OTP_MAX_PRG(t)        (t + 0x34)

#define OTP_OTP_MAX_PRG_OTP_MAX_PROG(x)          ((x) & GENMASK(4, 0))
#define OTP_OTP_MAX_PRG_OTP_MAX_PROG_M           GENMASK(4, 0)
#define OTP_OTP_MAX_PRG_OTP_MAX_PROG_X(x)        ((x) & GENMASK(4, 0))

/*      OTP:OTP_REGS:OTP_INTR_STATUS */
#define OTP_OTP_INTR_STATUS(t)    (t + 0x40)

#define OTP_OTP_INTR_STATUS_OTP_READY_INTR_STATUS(x) ((x) & GENMASK(0, 0))
#define OTP_OTP_INTR_STATUS_OTP_READY_INTR_STATUS_M GENMASK(0, 0)
#define OTP_OTP_INTR_STATUS_OTP_READY_INTR_STATUS_X(x) ((x) & GENMASK(0, 0))

/*      OTP:OTP_REGS:OTP_INTR_MASK */
#define OTP_OTP_INTR_MASK(t)      (t + 0x44)

#define OTP_OTP_INTR_MASK_OTP_READY_INTR_MASK(x) ((x) & GENMASK(0, 0))
#define OTP_OTP_INTR_MASK_OTP_READY_INTR_MASK_M  GENMASK(0, 0)
#define OTP_OTP_INTR_MASK_OTP_READY_INTR_MASK_X(x) ((x) & GENMASK(0, 0))

/*      OTP:OTP_REGS:OTP_RSTB_PW_HI */
#define OTP_OTP_RSTB_PW_HI(t)     (t + 0x50)

#define OTP_OTP_RSTB_PW_HI_OTP_RSTW_15_8(x)      ((x) & GENMASK(7, 0))
#define OTP_OTP_RSTB_PW_HI_OTP_RSTW_15_8_M       GENMASK(7, 0)
#define OTP_OTP_RSTB_PW_HI_OTP_RSTW_15_8_X(x)    ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_RSTB_PW_LO */
#define OTP_OTP_RSTB_PW_LO(t)     (t + 0x54)

#define OTP_OTP_RSTB_PW_LO_OTP_RSTW_7_0(x)       ((x) & GENMASK(7, 0))
#define OTP_OTP_RSTB_PW_LO_OTP_RSTW_7_0_M        GENMASK(7, 0)
#define OTP_OTP_RSTB_PW_LO_OTP_RSTW_7_0_X(x)     ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_PGM_PW_HI */
#define OTP_OTP_PGM_PW_HI(t)      (t + 0x60)

#define OTP_OTP_PGM_PW_HI_OTP_PPW_HI(x)          ((x) & GENMASK(7, 0))
#define OTP_OTP_PGM_PW_HI_OTP_PPW_HI_M           GENMASK(7, 0)
#define OTP_OTP_PGM_PW_HI_OTP_PPW_HI_X(x)        ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_PGM_PW_LO */
#define OTP_OTP_PGM_PW_LO(t)      (t + 0x64)

#define OTP_OTP_PGM_PW_LO_OTP_PPW_LO(x)          ((x) & GENMASK(7, 0))
#define OTP_OTP_PGM_PW_LO_OTP_PPW_LO_M           GENMASK(7, 0)
#define OTP_OTP_PGM_PW_LO_OTP_PPW_LO_X(x)        ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_READ_PW_HI */
#define OTP_OTP_READ_PW_HI(t)     (t + 0x70)

#define OTP_OTP_READ_PW_HI_OTP_RPW_HI(x)         ((x) & GENMASK(7, 0))
#define OTP_OTP_READ_PW_HI_OTP_RPW_HI_M          GENMASK(7, 0)
#define OTP_OTP_READ_PW_HI_OTP_RPW_HI_X(x)       ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_READ_PW_LO */
#define OTP_OTP_READ_PW_LO(t)     (t + 0x74)

#define OTP_OTP_READ_PW_LO_OTP_RPW_LO(x)         ((x) & GENMASK(7, 0))
#define OTP_OTP_READ_PW_LO_OTP_RPW_LO_M          GENMASK(7, 0)
#define OTP_OTP_READ_PW_LO_OTP_RPW_LO_X(x)       ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TCRST_VAL */
#define OTP_OTP_TCRST_VAL(t)      (t + 0x80)

#define OTP_OTP_TCRST_VAL_OTP_TCRST(x)           ((x) & GENMASK(7, 0))
#define OTP_OTP_TCRST_VAL_OTP_TCRST_M            GENMASK(7, 0)
#define OTP_OTP_TCRST_VAL_OTP_TCRST_X(x)         ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TRSRD_VAL */
#define OTP_OTP_TRSRD_VAL(t)      (t + 0x84)

#define OTP_OTP_TRSRD_VAL_OTP_TRSRD(x)           ((x) & GENMASK(7, 0))
#define OTP_OTP_TRSRD_VAL_OTP_TRSRD_M            GENMASK(7, 0)
#define OTP_OTP_TRSRD_VAL_OTP_TRSRD_X(x)         ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TREADEN_VAL */
#define OTP_OTP_TREADEN_VAL(t)    (t + 0x88)

#define OTP_OTP_TREADEN_VAL_OTP_TREADEN(x)       ((x) & GENMASK(7, 0))
#define OTP_OTP_TREADEN_VAL_OTP_TREADEN_M        GENMASK(7, 0)
#define OTP_OTP_TREADEN_VAL_OTP_TREADEN_X(x)     ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TDLES_VAL */
#define OTP_OTP_TDLES_VAL(t)      (t + 0x8c)

#define OTP_OTP_TDLES_VAL_OTP_TDLES(x)           ((x) & GENMASK(7, 0))
#define OTP_OTP_TDLES_VAL_OTP_TDLES_M            GENMASK(7, 0)
#define OTP_OTP_TDLES_VAL_OTP_TDLES_X(x)         ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TWWL_VAL */
#define OTP_OTP_TWWL_VAL(t)       (t + 0x90)

#define OTP_OTP_TWWL_VAL_OTP_TWWL(x)             ((x) & GENMASK(7, 0))
#define OTP_OTP_TWWL_VAL_OTP_TWWL_M              GENMASK(7, 0)
#define OTP_OTP_TWWL_VAL_OTP_TWWL_X(x)           ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TDLEH_VAL */
#define OTP_OTP_TDLEH_VAL(t)      (t + 0x94)

#define OTP_OTP_TDLEH_VAL_OTP_TDLEH(x)           ((x) & GENMASK(7, 0))
#define OTP_OTP_TDLEH_VAL_OTP_TDLEH_M            GENMASK(7, 0)
#define OTP_OTP_TDLEH_VAL_OTP_TDLEH_X(x)         ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TWPED_VAL */
#define OTP_OTP_TWPED_VAL(t)      (t + 0x98)

#define OTP_OTP_TWPED_VAL_OTP_TWPED(x)           ((x) & GENMASK(7, 0))
#define OTP_OTP_TWPED_VAL_OTP_TWPED_M            GENMASK(7, 0)
#define OTP_OTP_TWPED_VAL_OTP_TWPED_X(x)         ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TPES_VAL */
#define OTP_OTP_TPES_VAL(t)       (t + 0x9c)

#define OTP_OTP_TPES_VAL_OTP_TPES(x)             ((x) & GENMASK(7, 0))
#define OTP_OTP_TPES_VAL_OTP_TPES_M              GENMASK(7, 0)
#define OTP_OTP_TPES_VAL_OTP_TPES_X(x)           ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TCPS_VAL */
#define OTP_OTP_TCPS_VAL(t)       (t + 0xa0)

#define OTP_OTP_TCPS_VAL_OTP_TCPS(x)             ((x) & GENMASK(7, 0))
#define OTP_OTP_TCPS_VAL_OTP_TCPS_M              GENMASK(7, 0)
#define OTP_OTP_TCPS_VAL_OTP_TCPS_X(x)           ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TCPH_VAL */
#define OTP_OTP_TCPH_VAL(t)       (t + 0xa4)

#define OTP_OTP_TCPH_VAL_OTP_TCPH(x)             ((x) & GENMASK(7, 0))
#define OTP_OTP_TCPH_VAL_OTP_TCPH_M              GENMASK(7, 0)
#define OTP_OTP_TCPH_VAL_OTP_TCPH_X(x)           ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TPGMVFY_VAL */
#define OTP_OTP_TPGMVFY_VAL(t)    (t + 0xa8)

#define OTP_OTP_TPGMVFY_VAL_OTP_TPGMVFY(x)       ((x) & GENMASK(7, 0))
#define OTP_OTP_TPGMVFY_VAL_OTP_TPGMVFY_M        GENMASK(7, 0)
#define OTP_OTP_TPGMVFY_VAL_OTP_TPGMVFY_X(x)     ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TPEH_VAL */
#define OTP_OTP_TPEH_VAL(t)       (t + 0xac)

#define OTP_OTP_TPEH_VAL_OTP_TPEH(x)             ((x) & GENMASK(7, 0))
#define OTP_OTP_TPEH_VAL_OTP_TPEH_M              GENMASK(7, 0)
#define OTP_OTP_TPEH_VAL_OTP_TPEH_X(x)           ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TPGRST_VAL */
#define OTP_OTP_TPGRST_VAL(t)     (t + 0xb0)

#define OTP_OTP_TPGRST_VAL_OTP_TPGRST(x)         ((x) & GENMASK(7, 0))
#define OTP_OTP_TPGRST_VAL_OTP_TPGRST_M          GENMASK(7, 0)
#define OTP_OTP_TPGRST_VAL_OTP_TPGRST_X(x)       ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TCLES_VAL */
#define OTP_OTP_TCLES_VAL(t)      (t + 0xb4)

#define OTP_OTP_TCLES_VAL_OTP_TCLES(x)           ((x) & GENMASK(7, 0))
#define OTP_OTP_TCLES_VAL_OTP_TCLES_M            GENMASK(7, 0)
#define OTP_OTP_TCLES_VAL_OTP_TCLES_X(x)         ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TCLEH_VAL */
#define OTP_OTP_TCLEH_VAL(t)      (t + 0xb8)

#define OTP_OTP_TCLEH_VAL_OTP_TCLEH(x)           ((x) & GENMASK(7, 0))
#define OTP_OTP_TCLEH_VAL_OTP_TCLEH_M            GENMASK(7, 0)
#define OTP_OTP_TCLEH_VAL_OTP_TCLEH_X(x)         ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TRDES_VAL */
#define OTP_OTP_TRDES_VAL(t)      (t + 0xbc)

#define OTP_OTP_TRDES_VAL_OTP_TRDES(x)           ((x) & GENMASK(7, 0))
#define OTP_OTP_TRDES_VAL_OTP_TRDES_M            GENMASK(7, 0)
#define OTP_OTP_TRDES_VAL_OTP_TRDES_X(x)         ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TBCAAC_VAL */
#define OTP_OTP_TBCAAC_VAL(t)     (t + 0xc0)

#define OTP_OTP_TBCAAC_VAL_OTP_TBCAAC(x)         ((x) & GENMASK(7, 0))
#define OTP_OTP_TBCAAC_VAL_OTP_TBCAAC_M          GENMASK(7, 0)
#define OTP_OTP_TBCAAC_VAL_OTP_TBCAAC_X(x)       ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TAAC_VAL */
#define OTP_OTP_TAAC_VAL(t)       (t + 0xc4)

#define OTP_OTP_TAAC_VAL_OTP_TAAC(x)             ((x) & GENMASK(7, 0))
#define OTP_OTP_TAAC_VAL_OTP_TAAC_M              GENMASK(7, 0)
#define OTP_OTP_TAAC_VAL_OTP_TAAC_X(x)           ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TACCT_VAL */
#define OTP_OTP_TACCT_VAL(t)      (t + 0xc8)

#define OTP_OTP_TACCT_VAL_OTP_TACCT(x)           ((x) & GENMASK(7, 0))
#define OTP_OTP_TACCT_VAL_OTP_TACCT_M            GENMASK(7, 0)
#define OTP_OTP_TACCT_VAL_OTP_TACCT_X(x)         ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TPWAD_VAL */
#define OTP_OTP_TPWAD_VAL(t)      (t + 0xcc)

#define OTP_OTP_TPWAD_VAL_OTP_TPWAD(x)           ((x) & GENMASK(7, 0))
#define OTP_OTP_TPWAD_VAL_OTP_TPWAD_M            GENMASK(7, 0)
#define OTP_OTP_TPWAD_VAL_OTP_TPWAD_X(x)         ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TWCAD_VAL_HI */
#define OTP_OTP_TWCAD_VAL_HI(t)   (t + 0xd0)

#define OTP_OTP_TWCAD_VAL_HI_OTP_TWCAD_15_8(x)   ((x) & GENMASK(7, 0))
#define OTP_OTP_TWCAD_VAL_HI_OTP_TWCAD_15_8_M    GENMASK(7, 0)
#define OTP_OTP_TWCAD_VAL_HI_OTP_TWCAD_15_8_X(x) ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TWCAD_VAL_LO */
#define OTP_OTP_TWCAD_VAL_LO(t)   (t + 0xd4)

#define OTP_OTP_TWCAD_VAL_LO_OTP_TWCAD_7_0(x)    ((x) & GENMASK(7, 0))
#define OTP_OTP_TWCAD_VAL_LO_OTP_TWCAD_7_0_M     GENMASK(7, 0)
#define OTP_OTP_TWCAD_VAL_LO_OTP_TWCAD_7_0_X(x)  ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TAS_VAL */
#define OTP_OTP_TAS_VAL(t)        (t + 0xd8)

#define OTP_OTP_TAS_VAL_OTP_TAS(x)               ((x) & GENMASK(7, 0))
#define OTP_OTP_TAS_VAL_OTP_TAS_M                GENMASK(7, 0)
#define OTP_OTP_TAS_VAL_OTP_TAS_X(x)             ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TDS_VAL */
#define OTP_OTP_TDS_VAL(t)        (t + 0xdc)

#define OTP_OTP_TDS_VAL_OTP_TDS(x)               ((x) & GENMASK(7, 0))
#define OTP_OTP_TDS_VAL_OTP_TDS_M                GENMASK(7, 0)
#define OTP_OTP_TDS_VAL_OTP_TDS_X(x)             ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TPVSR_VAL */
#define OTP_OTP_TPVSR_VAL(t)      (t + 0xe8)

#define OTP_OTP_TPVSR_VAL_OTP_TPVSR(x)           ((x) & GENMASK(7, 0))
#define OTP_OTP_TPVSR_VAL_OTP_TPVSR_M            GENMASK(7, 0)
#define OTP_OTP_TPVSR_VAL_OTP_TPVSR_X(x)         ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TVHR_VAL */
#define OTP_OTP_TVHR_VAL(t)       (t + 0xec)

#define OTP_OTP_TVHR_VAL_OTP_TPVHR(x)            ((x) & GENMASK(7, 0))
#define OTP_OTP_TVHR_VAL_OTP_TPVHR_M             GENMASK(7, 0)
#define OTP_OTP_TVHR_VAL_OTP_TPVHR_X(x)          ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TPGMAS_VAL */
#define OTP_OTP_TPGMAS_VAL(t)     (t + 0xf0)

#define OTP_OTP_TPGMAS_VAL_OTP_TPGMAS(x)         ((x) & GENMASK(7, 0))
#define OTP_OTP_TPGMAS_VAL_OTP_TPGMAS_M          GENMASK(7, 0)
#define OTP_OTP_TPGMAS_VAL_OTP_TPGMAS_X(x)       ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TCWDD_VAL */
#define OTP_OTP_TCWDD_VAL(t)      (t + 0xf4)

#define OTP_OTP_TCWDD_VAL_OTP_TCWDD(x)           ((x) & GENMASK(7, 0))
#define OTP_OTP_TCWDD_VAL_OTP_TCWDD_M            GENMASK(7, 0)
#define OTP_OTP_TCWDD_VAL_OTP_TCWDD_X(x)         ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TCPRD_VAL */
#define OTP_OTP_TCPRD_VAL(t)      (t + 0x100)

#define OTP_OTP_TCPRD_VAL_OTP_TCPRD(x)           ((x) & GENMASK(7, 0))
#define OTP_OTP_TCPRD_VAL_OTP_TCPRD_M            GENMASK(7, 0)
#define OTP_OTP_TCPRD_VAL_OTP_TCPRD_X(x)         ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_TRDCP_VAL */
#define OTP_OTP_TRDCP_VAL(t)      (t + 0x104)

#define OTP_OTP_TRDCP_VAL_OTP_TRDCP(x)           ((x) & GENMASK(7, 0))
#define OTP_OTP_TRDCP_VAL_OTP_TRDCP_M            GENMASK(7, 0)
#define OTP_OTP_TRDCP_VAL_OTP_TRDCP_X(x)         ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_NP1_VAL */
#define OTP_OTP_NP1_VAL(t)        (t + 0x114)

#define OTP_OTP_NP1_VAL_OTP_NP1(x)               ((x) & GENMASK(3, 0))
#define OTP_OTP_NP1_VAL_OTP_NP1_M                GENMASK(3, 0)
#define OTP_OTP_NP1_VAL_OTP_NP1_X(x)             ((x) & GENMASK(3, 0))

/*      OTP:OTP_REGS:OTP_NP2_VAL */
#define OTP_OTP_NP2_VAL(t)        (t + 0x118)

#define OTP_OTP_NP2_VAL_OTP_NP2(x)               ((x) & GENMASK(3, 0))
#define OTP_OTP_NP2_VAL_OTP_NP2_M                GENMASK(3, 0)
#define OTP_OTP_NP2_VAL_OTP_NP2_X(x)             ((x) & GENMASK(3, 0))

/*      OTP:OTP_REGS:OTP_READ_PROTECT */
#define OTP_OTP_READ_PROTECT(t)   (t + 0x200)

#define OTP_OTP_READ_PROTECT_OTP_READ_PROTECT_7_0(x) ((x) & GENMASK(7, 0))
#define OTP_OTP_READ_PROTECT_OTP_READ_PROTECT_7_0_M GENMASK(7, 0)
#define OTP_OTP_READ_PROTECT_OTP_READ_PROTECT_7_0_X(x) ((x) & GENMASK(7, 0))

/*      OTP:OTP_REGS:OTP_FPGA_PROM_CTL */
#define OTP_OTP_FPGA_PROM_CTL(t)  (t + 0x300)

#define OTP_OTP_FPGA_PROM_CTL_FPGA_OTP_PROM_BUSY(x) (((x) << 3) & GENMASK(3, 3))
#define OTP_OTP_FPGA_PROM_CTL_FPGA_OTP_PROM_BUSY_M GENMASK(3, 3)
#define OTP_OTP_FPGA_PROM_CTL_FPGA_OTP_PROM_BUSY_X(x)\
	(((x) & GENMASK(3, 3)) >> 3)

#define OTP_OTP_FPGA_PROM_CTL_FPGA_OTP_CLR_PROM(x) (((x) << 2) & GENMASK(2, 2))
#define OTP_OTP_FPGA_PROM_CTL_FPGA_OTP_CLR_PROM_M GENMASK(2, 2)
#define OTP_OTP_FPGA_PROM_CTL_FPGA_OTP_CLR_PROM_X(x)\
	(((x) & GENMASK(2, 2)) >> 2)

#define OTP_OTP_FPGA_PROM_CTL_FPGA_OTP_PROM_ERR_CTL(x) ((x) & GENMASK(1, 0))
#define OTP_OTP_FPGA_PROM_CTL_FPGA_OTP_PROM_ERR_CTL_M GENMASK(1, 0)
#define OTP_OTP_FPGA_PROM_CTL_FPGA_OTP_PROM_ERR_CTL_X(x) ((x) & GENMASK(1, 0))

/*      PCIE_CFG:PCIE:PCIE_CFG */
#define PCIE_CFG_PCIE_CFG(t)      (t + 0x04)

#define PCIE_CFG_PCIE_CFG_REQ_RETRY_ENA(x)       (((x) << 19) & GENMASK(19, 19))
#define PCIE_CFG_PCIE_CFG_REQ_RETRY_ENA_M        GENMASK(19, 19)
#define PCIE_CFG_PCIE_CFG_REQ_RETRY_ENA_X(x)     (((x) & GENMASK(19, 19)) >> 19)

#define PCIE_CFG_PCIE_CFG_SRIS_MODE(x)           (((x) << 18) & GENMASK(18, 18))
#define PCIE_CFG_PCIE_CFG_SRIS_MODE_M            GENMASK(18, 18)
#define PCIE_CFG_PCIE_CFG_SRIS_MODE_X(x)         (((x) & GENMASK(18, 18)) >> 18)

#define PCIE_CFG_PCIE_CFG_LTSSM_ENA(x)           (((x) << 17) & GENMASK(17, 17))
#define PCIE_CFG_PCIE_CFG_LTSSM_ENA_M            GENMASK(17, 17)
#define PCIE_CFG_PCIE_CFG_LTSSM_ENA_X(x)         (((x) & GENMASK(17, 17)) >> 17)

#define PCIE_CFG_PCIE_CFG_DBI_RO_WR_DIS(x)       (((x) << 16) & GENMASK(16, 16))
#define PCIE_CFG_PCIE_CFG_DBI_RO_WR_DIS_M        GENMASK(16, 16)
#define PCIE_CFG_PCIE_CFG_DBI_RO_WR_DIS_X(x)     (((x) & GENMASK(16, 16)) >> 16)

#define PCIE_CFG_PCIE_CFG_HOLD_PHY_RST(x)        (((x) << 15) & GENMASK(15, 15))
#define PCIE_CFG_PCIE_CFG_HOLD_PHY_RST_M         GENMASK(15, 15)
#define PCIE_CFG_PCIE_CFG_HOLD_PHY_RST_X(x)      (((x) & GENMASK(15, 15)) >> 15)

#define PCIE_CFG_PCIE_CFG_MEM_RING_CORE_ENA(x)   (((x) << 14) & GENMASK(14, 14))
#define PCIE_CFG_PCIE_CFG_MEM_RING_CORE_ENA_M    GENMASK(14, 14)
#define PCIE_CFG_PCIE_CFG_MEM_RING_CORE_ENA_X(x) (((x) & GENMASK(14, 14)) >> 14)

#define PCIE_CFG_PCIE_CFG_MSTR_XFER_PENDING(x)   (((x) << 13) & GENMASK(13, 13))
#define PCIE_CFG_PCIE_CFG_MSTR_XFER_PENDING_M    GENMASK(13, 13)
#define PCIE_CFG_PCIE_CFG_MSTR_XFER_PENDING_X(x) (((x) & GENMASK(13, 13)) >> 13)

#define PCIE_CFG_PCIE_CFG_WAKE_DIS(x)            (((x) << 12) & GENMASK(12, 12))
#define PCIE_CFG_PCIE_CFG_WAKE_DIS_M             GENMASK(12, 12)
#define PCIE_CFG_PCIE_CFG_WAKE_DIS_X(x)          (((x) & GENMASK(12, 12)) >> 12)

#define PCIE_CFG_PCIE_CFG_WAKE_POL(x)            (((x) << 11) & GENMASK(11, 11))
#define PCIE_CFG_PCIE_CFG_WAKE_POL_M             GENMASK(11, 11)
#define PCIE_CFG_PCIE_CFG_WAKE_POL_X(x)          (((x) & GENMASK(11, 11)) >> 11)

#define PCIE_CFG_PCIE_CFG_WAKE_OE(x)             (((x) << 10) & GENMASK(10, 10))
#define PCIE_CFG_PCIE_CFG_WAKE_OE_M              GENMASK(10, 10)
#define PCIE_CFG_PCIE_CFG_WAKE_OE_X(x)           (((x) & GENMASK(10, 10)) >> 10)

#define PCIE_CFG_PCIE_CFG_DBI_ADDR_31_22(x)      ((x) & GENMASK(9, 0))
#define PCIE_CFG_PCIE_CFG_DBI_ADDR_31_22_M       GENMASK(9, 0)
#define PCIE_CFG_PCIE_CFG_DBI_ADDR_31_22_X(x)    ((x) & GENMASK(9, 0))

/*      PCIE_DBI:PF0_TYPE0_HDR:DEVICE_ID_VENDOR_ID_REG */
#define PCIE_DBI_DEVICE_ID_VENDOR_ID_REG(t) (t + 0x00)

#define PCIE_DBI_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID(x)\
	((x) & GENMASK(15, 0))
#define PCIE_DBI_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_M GENMASK(15, 0)
#define PCIE_DBI_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_X(x)\
	((x) & GENMASK(15, 0))

#define PCIE_DBI_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID(x)\
	(((x) << 16) & GENMASK(31, 16))
#define PCIE_DBI_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_M GENMASK(31, 16)
#define PCIE_DBI_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      PCIE_DBI:PF0_TYPE0_HDR:CLASS_CODE_REVISION_ID */
#define PCIE_DBI_CLASS_CODE_REVISION_ID(t) (t + 0x08)

#define PCIE_DBI_CLASS_CODE_REVISION_ID_REVISION_ID(x) ((x) & GENMASK(7, 0))
#define PCIE_DBI_CLASS_CODE_REVISION_ID_REVISION_ID_M GENMASK(7, 0)
#define PCIE_DBI_CLASS_CODE_REVISION_ID_REVISION_ID_X(x) ((x) & GENMASK(7, 0))

#define PCIE_DBI_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE(x)\
	(((x) << 8) & GENMASK(15, 8))
#define PCIE_DBI_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_M GENMASK(15, 8)
#define PCIE_DBI_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_X(x)\
	(((x) & GENMASK(15, 8)) >> 8)

#define PCIE_DBI_CLASS_CODE_REVISION_ID_SUBCLASS_CODE(x)\
	(((x) << 16) & GENMASK(23, 16))
#define PCIE_DBI_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_M GENMASK(23, 16)
#define PCIE_DBI_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_X(x)\
	(((x) & GENMASK(23, 16)) >> 16)

#define PCIE_DBI_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE(x)\
	(((x) << 24) & GENMASK(31, 24))
#define PCIE_DBI_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_M GENMASK(31, 24)
#define PCIE_DBI_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      PCIE_DBI:PF0_TYPE0_HDR:SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG */
#define PCIE_DBI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG(t) (t + 0x2c)

#define PCIE_DBI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID(x)\
	((x) & GENMASK(15, 0))
#define PCIE_DBI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_M\
	GENMASK(15, 0)
#define PCIE_DBI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_X(x)\
	((x) & GENMASK(15, 0))

#define PCIE_DBI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID(x)\
	(((x) << 16) & GENMASK(31, 16))
#define PCIE_DBI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_M\
	GENMASK(31, 16)
#define PCIE_DBI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      PCIE_DBI:PF0_TYPE0_HDR_DBI2:BAR0_MASK_REG */
#define PCIE_DBI_BAR0_MASK_REG(t) (t + 0x100010)

#define PCIE_DBI_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED(x) ((x) & GENMASK(0, 0))
#define PCIE_DBI_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_M GENMASK(0, 0)
#define PCIE_DBI_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_X(x) ((x) & GENMASK(0, 0))

#define PCIE_DBI_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK(x)\
	(((x) << 1) & GENMASK(31, 1))
#define PCIE_DBI_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_M GENMASK(31, 1)
#define PCIE_DBI_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_X(x)\
	(((x) & GENMASK(31, 1)) >> 1)

/*      PCIE_DBI:PF0_TYPE0_HDR_DBI2:BAR1_MASK_REG */
#define PCIE_DBI_BAR1_MASK_REG(t) (t + 0x100014)

#define PCIE_DBI_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED(x) ((x) & GENMASK(0, 0))
#define PCIE_DBI_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_M GENMASK(0, 0)
#define PCIE_DBI_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_X(x) ((x) & GENMASK(0, 0))

#define PCIE_DBI_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK(x)\
	(((x) << 1) & GENMASK(31, 1))
#define PCIE_DBI_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_M GENMASK(31, 1)
#define PCIE_DBI_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_X(x)\
	(((x) & GENMASK(31, 1)) >> 1)

/*      PCIE_DBI:PF0_TYPE0_HDR_DBI2:BAR2_MASK_REG */
#define PCIE_DBI_BAR2_MASK_REG(t) (t + 0x100018)

#define PCIE_DBI_BAR2_MASK_REG_PCI_TYPE0_BAR2_ENABLED(x) ((x) & GENMASK(0, 0))
#define PCIE_DBI_BAR2_MASK_REG_PCI_TYPE0_BAR2_ENABLED_M GENMASK(0, 0)
#define PCIE_DBI_BAR2_MASK_REG_PCI_TYPE0_BAR2_ENABLED_X(x) ((x) & GENMASK(0, 0))

#define PCIE_DBI_BAR2_MASK_REG_PCI_TYPE0_BAR2_MASK(x)\
	(((x) << 1) & GENMASK(31, 1))
#define PCIE_DBI_BAR2_MASK_REG_PCI_TYPE0_BAR2_MASK_M GENMASK(31, 1)
#define PCIE_DBI_BAR2_MASK_REG_PCI_TYPE0_BAR2_MASK_X(x)\
	(((x) & GENMASK(31, 1)) >> 1)

/*      PCIE_DBI:PF0_TYPE0_HDR_DBI2:BAR3_MASK_REG */
#define PCIE_DBI_BAR3_MASK_REG(t) (t + 0x10001c)

#define PCIE_DBI_BAR3_MASK_REG_PCI_TYPE0_BAR3_ENABLED(x) ((x) & GENMASK(0, 0))
#define PCIE_DBI_BAR3_MASK_REG_PCI_TYPE0_BAR3_ENABLED_M GENMASK(0, 0)
#define PCIE_DBI_BAR3_MASK_REG_PCI_TYPE0_BAR3_ENABLED_X(x) ((x) & GENMASK(0, 0))

#define PCIE_DBI_BAR3_MASK_REG_PCI_TYPE0_BAR3_MASK(x)\
	(((x) << 1) & GENMASK(31, 1))
#define PCIE_DBI_BAR3_MASK_REG_PCI_TYPE0_BAR3_MASK_M GENMASK(31, 1)
#define PCIE_DBI_BAR3_MASK_REG_PCI_TYPE0_BAR3_MASK_X(x)\
	(((x) & GENMASK(31, 1)) >> 1)

/*      PCIE_DBI:PF0_TYPE0_HDR_DBI2:BAR4_MASK_REG */
#define PCIE_DBI_BAR4_MASK_REG(t) (t + 0x100020)

#define PCIE_DBI_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED(x) ((x) & GENMASK(0, 0))
#define PCIE_DBI_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_M GENMASK(0, 0)
#define PCIE_DBI_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_X(x) ((x) & GENMASK(0, 0))

#define PCIE_DBI_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK(x)\
	(((x) << 1) & GENMASK(31, 1))
#define PCIE_DBI_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_M GENMASK(31, 1)
#define PCIE_DBI_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_X(x)\
	(((x) & GENMASK(31, 1)) >> 1)

/*      PCIE_DBI:PF0_TYPE0_HDR_DBI2:BAR5_MASK_REG */
#define PCIE_DBI_BAR5_MASK_REG(t) (t + 0x100024)

#define PCIE_DBI_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED(x) ((x) & GENMASK(0, 0))
#define PCIE_DBI_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_M GENMASK(0, 0)
#define PCIE_DBI_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_X(x) ((x) & GENMASK(0, 0))

#define PCIE_DBI_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK(x)\
	(((x) << 1) & GENMASK(31, 1))
#define PCIE_DBI_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_M GENMASK(31, 1)
#define PCIE_DBI_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_X(x)\
	(((x) & GENMASK(31, 1)) >> 1)

/*      PCIE_DBI:PF0_PCIE_CAP:LINK_CAPABILITIES_REG */
#define PCIE_DBI_LINK_CAPABILITIES_REG(t) (t + 0x7c)

#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED(x)\
	((x) & GENMASK(3, 0))
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_M GENMASK(3, 0)
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_X(x)\
	((x) & GENMASK(3, 0))

#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH(x)\
	(((x) << 4) & GENMASK(9, 4))
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_M GENMASK(9, 4)
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_X(x)\
	(((x) & GENMASK(9, 4)) >> 4)

#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT(x)\
	(((x) << 10) & GENMASK(11, 10))
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_M\
	GENMASK(11, 10)
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_X(x)\
	(((x) & GENMASK(11, 10)) >> 10)

#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY(x)\
	(((x) << 12) & GENMASK(14, 12))
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_M\
	GENMASK(14, 12)
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_X(x)\
	(((x) & GENMASK(14, 12)) >> 12)

#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY(x)\
	(((x) << 15) & GENMASK(17, 15))
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_M\
	GENMASK(17, 15)
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_X(x)\
	(((x) & GENMASK(17, 15)) >> 15)

#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN(x)\
	(((x) << 18) & GENMASK(18, 18))
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_M\
	GENMASK(18, 18)
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_X(x)\
	(((x) & GENMASK(18, 18)) >> 18)

#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP(x)\
	(((x) << 19) & GENMASK(19, 19))
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_M\
	GENMASK(19, 19)
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_X(x)\
	(((x) & GENMASK(19, 19)) >> 19)

#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP(x)\
	(((x) << 20) & GENMASK(20, 20))
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_M\
	GENMASK(20, 20)
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_X(x)\
	(((x) & GENMASK(20, 20)) >> 20)

#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP(x)\
	(((x) << 21) & GENMASK(21, 21))
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_M\
	GENMASK(21, 21)
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_X(x)\
	(((x) & GENMASK(21, 21)) >> 21)

#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE(x)\
	(((x) << 22) & GENMASK(22, 22))
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_M\
	GENMASK(22, 22)
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_X(x)\
	(((x) & GENMASK(22, 22)) >> 22)

#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM(x)\
	(((x) << 24) & GENMASK(31, 24))
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_M GENMASK(31, 24)
#define PCIE_DBI_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      PCIE_DBI:PF0_ATU_CAP:IATU_REGION_CTRL_2_OFF_INBOUND_0 */
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0(t) (t + 0x300104)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE(x)\
	((x) & GENMASK(7, 0))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_M\
	GENMASK(7, 0)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_X(x)\
	((x) & GENMASK(7, 0))

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM(x)\
	(((x) << 8) & GENMASK(10, 8))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_M\
	GENMASK(10, 8)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_X(x)\
	(((x) & GENMASK(10, 8)) >> 8)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE(x)\
	(((x) << 13) & GENMASK(13, 13))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_M\
	GENMASK(13, 13)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_X(x)\
	(((x) & GENMASK(13, 13)) >> 13)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN(x)\
	(((x) << 14) & GENMASK(14, 14))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_M\
	GENMASK(14, 14)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_X(x)\
	(((x) & GENMASK(14, 14)) >> 14)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN(x)\
	(((x) << 15) & GENMASK(15, 15))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_M\
	GENMASK(15, 15)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_X(x)\
	(((x) & GENMASK(15, 15)) >> 15)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN(x)\
	(((x) << 16) & GENMASK(16, 16))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_M\
	GENMASK(16, 16)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_X(x)\
	(((x) & GENMASK(16, 16)) >> 16)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN(x)\
	(((x) << 19) & GENMASK(19, 19))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_M\
	GENMASK(19, 19)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_X(x)\
	(((x) & GENMASK(19, 19)) >> 19)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN(x)\
	(((x) << 21) & GENMASK(21, 21))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_M\
	GENMASK(21, 21)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_X(x)\
	(((x) & GENMASK(21, 21)) >> 21)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN(x)\
	(((x) << 23) & GENMASK(23, 23))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_M\
	GENMASK(23, 23)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_X(x)\
	(((x) & GENMASK(23, 23)) >> 23)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE(x)\
	(((x) << 24) & GENMASK(25, 24))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_M\
	GENMASK(25, 24)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_X(x)\
	(((x) & GENMASK(25, 24)) >> 24)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE(x)\
	(((x) << 27) & GENMASK(27, 27))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_M\
	GENMASK(27, 27)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_X(x)\
	(((x) & GENMASK(27, 27)) >> 27)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE(x)\
	(((x) << 28) & GENMASK(28, 28))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_M\
	GENMASK(28, 28)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_X(x)\
	(((x) & GENMASK(28, 28)) >> 28)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE(x)\
	(((x) << 29) & GENMASK(29, 29))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_M\
	GENMASK(29, 29)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_X(x)\
	(((x) & GENMASK(29, 29)) >> 29)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE(x)\
	(((x) << 30) & GENMASK(30, 30))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_M\
	GENMASK(30, 30)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_X(x)\
	(((x) & GENMASK(30, 30)) >> 30)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN(x)\
	(((x) << 31) & GENMASK(31, 31))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_M\
	GENMASK(31, 31)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_0_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_X(x)\
	(((x) & GENMASK(31, 31)) >> 31)

/*      PCIE_DBI:PF0_ATU_CAP:IATU_LWR_TARGET_ADDR_OFF_INBOUND_0 */
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0(t) (t + 0x300114)

#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW(x)\
	((x) & GENMASK(15, 0))
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_M\
	GENMASK(15, 0)
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_X(x)\
	((x) & GENMASK(15, 0))

#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW(x)\
	(((x) << 16) & GENMASK(31, 16))
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_M\
	GENMASK(31, 16)
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      PCIE_DBI:PF0_ATU_CAP:IATU_REGION_CTRL_2_OFF_INBOUND_1 */
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1(t) (t + 0x300304)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE(x)\
	((x) & GENMASK(7, 0))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_M\
	GENMASK(7, 0)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_X(x)\
	((x) & GENMASK(7, 0))

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM(x)\
	(((x) << 8) & GENMASK(10, 8))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_M\
	GENMASK(10, 8)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_X(x)\
	(((x) & GENMASK(10, 8)) >> 8)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE(x)\
	(((x) << 13) & GENMASK(13, 13))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_M\
	GENMASK(13, 13)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_X(x)\
	(((x) & GENMASK(13, 13)) >> 13)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN(x)\
	(((x) << 14) & GENMASK(14, 14))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_M\
	GENMASK(14, 14)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_X(x)\
	(((x) & GENMASK(14, 14)) >> 14)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN(x)\
	(((x) << 15) & GENMASK(15, 15))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_M\
	GENMASK(15, 15)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_X(x)\
	(((x) & GENMASK(15, 15)) >> 15)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN(x)\
	(((x) << 16) & GENMASK(16, 16))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_M\
	GENMASK(16, 16)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_X(x)\
	(((x) & GENMASK(16, 16)) >> 16)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN(x)\
	(((x) << 19) & GENMASK(19, 19))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_M\
	GENMASK(19, 19)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_X(x)\
	(((x) & GENMASK(19, 19)) >> 19)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN(x)\
	(((x) << 21) & GENMASK(21, 21))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_M\
	GENMASK(21, 21)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_X(x)\
	(((x) & GENMASK(21, 21)) >> 21)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN(x)\
	(((x) << 23) & GENMASK(23, 23))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_M\
	GENMASK(23, 23)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_X(x)\
	(((x) & GENMASK(23, 23)) >> 23)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE(x)\
	(((x) << 24) & GENMASK(25, 24))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_M\
	GENMASK(25, 24)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_X(x)\
	(((x) & GENMASK(25, 24)) >> 24)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE(x)\
	(((x) << 27) & GENMASK(27, 27))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_M\
	GENMASK(27, 27)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_X(x)\
	(((x) & GENMASK(27, 27)) >> 27)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE(x)\
	(((x) << 28) & GENMASK(28, 28))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_M\
	GENMASK(28, 28)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_X(x)\
	(((x) & GENMASK(28, 28)) >> 28)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE(x)\
	(((x) << 29) & GENMASK(29, 29))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_M\
	GENMASK(29, 29)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_X(x)\
	(((x) & GENMASK(29, 29)) >> 29)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE(x)\
	(((x) << 30) & GENMASK(30, 30))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_M\
	GENMASK(30, 30)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_X(x)\
	(((x) & GENMASK(30, 30)) >> 30)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN(x)\
	(((x) << 31) & GENMASK(31, 31))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_M\
	GENMASK(31, 31)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_1_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_X(x)\
	(((x) & GENMASK(31, 31)) >> 31)

/*      PCIE_DBI:PF0_ATU_CAP:IATU_LWR_TARGET_ADDR_OFF_INBOUND_1 */
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1(t) (t + 0x300314)

#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW(x)\
	((x) & GENMASK(15, 0))
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_M\
	GENMASK(15, 0)
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_X(x)\
	((x) & GENMASK(15, 0))

#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW(x)\
	(((x) << 16) & GENMASK(31, 16))
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_M\
	GENMASK(31, 16)
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      PCIE_DBI:PF0_ATU_CAP:IATU_REGION_CTRL_2_OFF_INBOUND_2 */
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2(t) (t + 0x300504)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE(x)\
	((x) & GENMASK(7, 0))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_M\
	GENMASK(7, 0)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_X(x)\
	((x) & GENMASK(7, 0))

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM(x)\
	(((x) << 8) & GENMASK(10, 8))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_M\
	GENMASK(10, 8)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_X(x)\
	(((x) & GENMASK(10, 8)) >> 8)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE(x)\
	(((x) << 13) & GENMASK(13, 13))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_M\
	GENMASK(13, 13)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_X(x)\
	(((x) & GENMASK(13, 13)) >> 13)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN(x)\
	(((x) << 14) & GENMASK(14, 14))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_M\
	GENMASK(14, 14)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_X(x)\
	(((x) & GENMASK(14, 14)) >> 14)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN(x)\
	(((x) << 15) & GENMASK(15, 15))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_M\
	GENMASK(15, 15)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_X(x)\
	(((x) & GENMASK(15, 15)) >> 15)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN(x)\
	(((x) << 16) & GENMASK(16, 16))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_M\
	GENMASK(16, 16)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_X(x)\
	(((x) & GENMASK(16, 16)) >> 16)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN(x)\
	(((x) << 19) & GENMASK(19, 19))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_M\
	GENMASK(19, 19)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_X(x)\
	(((x) & GENMASK(19, 19)) >> 19)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN(x)\
	(((x) << 21) & GENMASK(21, 21))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_M\
	GENMASK(21, 21)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_X(x)\
	(((x) & GENMASK(21, 21)) >> 21)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN(x)\
	(((x) << 23) & GENMASK(23, 23))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_M\
	GENMASK(23, 23)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_X(x)\
	(((x) & GENMASK(23, 23)) >> 23)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE(x)\
	(((x) << 24) & GENMASK(25, 24))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_M\
	GENMASK(25, 24)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_X(x)\
	(((x) & GENMASK(25, 24)) >> 24)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE(x)\
	(((x) << 27) & GENMASK(27, 27))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_M\
	GENMASK(27, 27)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_X(x)\
	(((x) & GENMASK(27, 27)) >> 27)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE(x)\
	(((x) << 28) & GENMASK(28, 28))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_M\
	GENMASK(28, 28)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_X(x)\
	(((x) & GENMASK(28, 28)) >> 28)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE(x)\
	(((x) << 29) & GENMASK(29, 29))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_M\
	GENMASK(29, 29)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_X(x)\
	(((x) & GENMASK(29, 29)) >> 29)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE(x)\
	(((x) << 30) & GENMASK(30, 30))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_M\
	GENMASK(30, 30)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_X(x)\
	(((x) & GENMASK(30, 30)) >> 30)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN(x)\
	(((x) << 31) & GENMASK(31, 31))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_M\
	GENMASK(31, 31)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_2_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_X(x)\
	(((x) & GENMASK(31, 31)) >> 31)

/*      PCIE_DBI:PF0_ATU_CAP:IATU_LWR_TARGET_ADDR_OFF_INBOUND_2 */
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2(t) (t + 0x300514)

#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW(x)\
	((x) & GENMASK(15, 0))
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_M\
	GENMASK(15, 0)
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_X(x)\
	((x) & GENMASK(15, 0))

#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW(x)\
	(((x) << 16) & GENMASK(31, 16))
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_M\
	GENMASK(31, 16)
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      PCIE_DBI:PF0_ATU_CAP:IATU_REGION_CTRL_2_OFF_INBOUND_3 */
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3(t) (t + 0x300704)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE(x)\
	((x) & GENMASK(7, 0))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_M\
	GENMASK(7, 0)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_X(x)\
	((x) & GENMASK(7, 0))

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM(x)\
	(((x) << 8) & GENMASK(10, 8))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_M\
	GENMASK(10, 8)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_X(x)\
	(((x) & GENMASK(10, 8)) >> 8)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE(x)\
	(((x) << 13) & GENMASK(13, 13))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_M\
	GENMASK(13, 13)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_X(x)\
	(((x) & GENMASK(13, 13)) >> 13)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN(x)\
	(((x) << 14) & GENMASK(14, 14))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_M\
	GENMASK(14, 14)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_X(x)\
	(((x) & GENMASK(14, 14)) >> 14)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN(x)\
	(((x) << 15) & GENMASK(15, 15))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_M\
	GENMASK(15, 15)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_X(x)\
	(((x) & GENMASK(15, 15)) >> 15)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN(x)\
	(((x) << 16) & GENMASK(16, 16))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_M\
	GENMASK(16, 16)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_X(x)\
	(((x) & GENMASK(16, 16)) >> 16)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN(x)\
	(((x) << 19) & GENMASK(19, 19))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_M\
	GENMASK(19, 19)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_X(x)\
	(((x) & GENMASK(19, 19)) >> 19)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN(x)\
	(((x) << 21) & GENMASK(21, 21))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_M\
	GENMASK(21, 21)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_X(x)\
	(((x) & GENMASK(21, 21)) >> 21)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN(x)\
	(((x) << 23) & GENMASK(23, 23))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_M\
	GENMASK(23, 23)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_X(x)\
	(((x) & GENMASK(23, 23)) >> 23)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE(x)\
	(((x) << 24) & GENMASK(25, 24))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_M\
	GENMASK(25, 24)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_X(x)\
	(((x) & GENMASK(25, 24)) >> 24)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE(x)\
	(((x) << 27) & GENMASK(27, 27))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_M\
	GENMASK(27, 27)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_X(x)\
	(((x) & GENMASK(27, 27)) >> 27)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE(x)\
	(((x) << 28) & GENMASK(28, 28))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_M\
	GENMASK(28, 28)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_X(x)\
	(((x) & GENMASK(28, 28)) >> 28)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE(x)\
	(((x) << 29) & GENMASK(29, 29))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_M\
	GENMASK(29, 29)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_X(x)\
	(((x) & GENMASK(29, 29)) >> 29)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE(x)\
	(((x) << 30) & GENMASK(30, 30))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_M\
	GENMASK(30, 30)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_X(x)\
	(((x) & GENMASK(30, 30)) >> 30)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN(x)\
	(((x) << 31) & GENMASK(31, 31))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_M\
	GENMASK(31, 31)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_3_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_X(x)\
	(((x) & GENMASK(31, 31)) >> 31)

/*      PCIE_DBI:PF0_ATU_CAP:IATU_LWR_TARGET_ADDR_OFF_INBOUND_3 */
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3(t) (t + 0x300714)

#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW(x)\
	((x) & GENMASK(15, 0))
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_M\
	GENMASK(15, 0)
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_X(x)\
	((x) & GENMASK(15, 0))

#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW(x)\
	(((x) << 16) & GENMASK(31, 16))
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_M\
	GENMASK(31, 16)
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      PCIE_DBI:PF0_ATU_CAP:IATU_REGION_CTRL_2_OFF_INBOUND_4 */
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4(t) (t + 0x300904)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE(x)\
	((x) & GENMASK(7, 0))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_M\
	GENMASK(7, 0)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_X(x)\
	((x) & GENMASK(7, 0))

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM(x)\
	(((x) << 8) & GENMASK(10, 8))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_M\
	GENMASK(10, 8)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_X(x)\
	(((x) & GENMASK(10, 8)) >> 8)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE(x)\
	(((x) << 13) & GENMASK(13, 13))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_M\
	GENMASK(13, 13)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_X(x)\
	(((x) & GENMASK(13, 13)) >> 13)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN(x)\
	(((x) << 14) & GENMASK(14, 14))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_M\
	GENMASK(14, 14)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_X(x)\
	(((x) & GENMASK(14, 14)) >> 14)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN(x)\
	(((x) << 15) & GENMASK(15, 15))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_M\
	GENMASK(15, 15)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_X(x)\
	(((x) & GENMASK(15, 15)) >> 15)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN(x)\
	(((x) << 16) & GENMASK(16, 16))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_M\
	GENMASK(16, 16)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_X(x)\
	(((x) & GENMASK(16, 16)) >> 16)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN(x)\
	(((x) << 19) & GENMASK(19, 19))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_M\
	GENMASK(19, 19)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_X(x)\
	(((x) & GENMASK(19, 19)) >> 19)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN(x)\
	(((x) << 21) & GENMASK(21, 21))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_M\
	GENMASK(21, 21)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_X(x)\
	(((x) & GENMASK(21, 21)) >> 21)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN(x)\
	(((x) << 23) & GENMASK(23, 23))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_M\
	GENMASK(23, 23)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_X(x)\
	(((x) & GENMASK(23, 23)) >> 23)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE(x)\
	(((x) << 24) & GENMASK(25, 24))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_M\
	GENMASK(25, 24)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_X(x)\
	(((x) & GENMASK(25, 24)) >> 24)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE(x)\
	(((x) << 27) & GENMASK(27, 27))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_M\
	GENMASK(27, 27)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_X(x)\
	(((x) & GENMASK(27, 27)) >> 27)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE(x)\
	(((x) << 28) & GENMASK(28, 28))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_M\
	GENMASK(28, 28)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_X(x)\
	(((x) & GENMASK(28, 28)) >> 28)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE(x)\
	(((x) << 29) & GENMASK(29, 29))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_M\
	GENMASK(29, 29)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_X(x)\
	(((x) & GENMASK(29, 29)) >> 29)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE(x)\
	(((x) << 30) & GENMASK(30, 30))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_M\
	GENMASK(30, 30)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_X(x)\
	(((x) & GENMASK(30, 30)) >> 30)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN(x)\
	(((x) << 31) & GENMASK(31, 31))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_M\
	GENMASK(31, 31)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_4_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_X(x)\
	(((x) & GENMASK(31, 31)) >> 31)

/*      PCIE_DBI:PF0_ATU_CAP:IATU_LWR_TARGET_ADDR_OFF_INBOUND_4 */
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4(t) (t + 0x300914)

#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW(x)\
	((x) & GENMASK(15, 0))
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_M\
	GENMASK(15, 0)
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_X(x)\
	((x) & GENMASK(15, 0))

#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW(x)\
	(((x) << 16) & GENMASK(31, 16))
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_M\
	GENMASK(31, 16)
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      PCIE_DBI:PF0_ATU_CAP:IATU_REGION_CTRL_2_OFF_INBOUND_5 */
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5(t) (t + 0x300b04)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE(x)\
	((x) & GENMASK(7, 0))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_M\
	GENMASK(7, 0)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_X(x)\
	((x) & GENMASK(7, 0))

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM(x)\
	(((x) << 8) & GENMASK(10, 8))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_M\
	GENMASK(10, 8)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_X(x)\
	(((x) & GENMASK(10, 8)) >> 8)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE(x)\
	(((x) << 13) & GENMASK(13, 13))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_M\
	GENMASK(13, 13)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_X(x)\
	(((x) & GENMASK(13, 13)) >> 13)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN(x)\
	(((x) << 14) & GENMASK(14, 14))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_M\
	GENMASK(14, 14)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_X(x)\
	(((x) & GENMASK(14, 14)) >> 14)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN(x)\
	(((x) << 15) & GENMASK(15, 15))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_M\
	GENMASK(15, 15)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_X(x)\
	(((x) & GENMASK(15, 15)) >> 15)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN(x)\
	(((x) << 16) & GENMASK(16, 16))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_M\
	GENMASK(16, 16)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_X(x)\
	(((x) & GENMASK(16, 16)) >> 16)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN(x)\
	(((x) << 19) & GENMASK(19, 19))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_M\
	GENMASK(19, 19)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_X(x)\
	(((x) & GENMASK(19, 19)) >> 19)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN(x)\
	(((x) << 21) & GENMASK(21, 21))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_M\
	GENMASK(21, 21)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_X(x)\
	(((x) & GENMASK(21, 21)) >> 21)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN(x)\
	(((x) << 23) & GENMASK(23, 23))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_M\
	GENMASK(23, 23)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_X(x)\
	(((x) & GENMASK(23, 23)) >> 23)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE(x)\
	(((x) << 24) & GENMASK(25, 24))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_M\
	GENMASK(25, 24)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_X(x)\
	(((x) & GENMASK(25, 24)) >> 24)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE(x)\
	(((x) << 27) & GENMASK(27, 27))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_M\
	GENMASK(27, 27)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_X(x)\
	(((x) & GENMASK(27, 27)) >> 27)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE(x)\
	(((x) << 28) & GENMASK(28, 28))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_M\
	GENMASK(28, 28)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_X(x)\
	(((x) & GENMASK(28, 28)) >> 28)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE(x)\
	(((x) << 29) & GENMASK(29, 29))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_M\
	GENMASK(29, 29)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_X(x)\
	(((x) & GENMASK(29, 29)) >> 29)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE(x)\
	(((x) << 30) & GENMASK(30, 30))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_M\
	GENMASK(30, 30)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_X(x)\
	(((x) & GENMASK(30, 30)) >> 30)

#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN(x)\
	(((x) << 31) & GENMASK(31, 31))
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_M\
	GENMASK(31, 31)
#define PCIE_DBI_IATU_REGION_CTRL_2_OFF_INBOUND_5_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_X(x)\
	(((x) & GENMASK(31, 31)) >> 31)

/*      PCIE_DBI:PF0_ATU_CAP:IATU_LWR_TARGET_ADDR_OFF_INBOUND_5 */
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5(t) (t + 0x300b14)

#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW(x)\
	((x) & GENMASK(15, 0))
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_M\
	GENMASK(15, 0)
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_X(x)\
	((x) & GENMASK(15, 0))

#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW(x)\
	(((x) << 16) & GENMASK(31, 16))
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_M\
	GENMASK(31, 16)
#define PCIE_DBI_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      PCIE_DBI:PF0_PORT_LOGIC:MISC_CONTROL_1_OFF */
#define PCIE_DBI_MISC_CONTROL_1_OFF(t) (t + 0x8bc)

#define PCIE_DBI_MISC_CONTROL_1_OFF_DBI_RO_WR_EN(x) ((x) & GENMASK(0, 0))
#define PCIE_DBI_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_M GENMASK(0, 0)
#define PCIE_DBI_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_X(x) ((x) & GENMASK(0, 0))

#define PCIE_DBI_MISC_CONTROL_1_OFF_DEFAULT_TARGET(x)\
	(((x) << 1) & GENMASK(1, 1))
#define PCIE_DBI_MISC_CONTROL_1_OFF_DEFAULT_TARGET_M GENMASK(1, 1)
#define PCIE_DBI_MISC_CONTROL_1_OFF_DEFAULT_TARGET_X(x)\
	(((x) & GENMASK(1, 1)) >> 1)

#define PCIE_DBI_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1(x)\
	(((x) << 2) & GENMASK(2, 2))
#define PCIE_DBI_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_M GENMASK(2, 2)
#define PCIE_DBI_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_X(x)\
	(((x) & GENMASK(2, 2)) >> 2)

#define PCIE_DBI_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER(x)\
	(((x) << 3) & GENMASK(3, 3))
#define PCIE_DBI_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_M GENMASK(3, 3)
#define PCIE_DBI_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_X(x)\
	(((x) & GENMASK(3, 3)) >> 3)

#define PCIE_DBI_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER(x)\
	(((x) << 5) & GENMASK(5, 5))
#define PCIE_DBI_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_M GENMASK(5, 5)
#define PCIE_DBI_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_X(x)\
	(((x) & GENMASK(5, 5)) >> 5)

#define PCIE_DBI_MISC_CONTROL_1_OFF_CPLQ_MNG_EN(x) (((x) << 6) & GENMASK(6, 6))
#define PCIE_DBI_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_M GENMASK(6, 6)
#define PCIE_DBI_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_X(x)\
	(((x) & GENMASK(6, 6)) >> 6)

#define PCIE_DBI_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG(x)\
	(((x) << 7) & GENMASK(7, 7))
#define PCIE_DBI_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_M GENMASK(7, 7)
#define PCIE_DBI_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_X(x)\
	(((x) & GENMASK(7, 7)) >> 7)

#define PCIE_DBI_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG(x)\
	(((x) << 8) & GENMASK(17, 8))
#define PCIE_DBI_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_M GENMASK(17, 8)
#define PCIE_DBI_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_X(x)\
	(((x) & GENMASK(17, 8)) >> 8)

#define PCIE_DBI_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG(x)\
	(((x) << 18) & GENMASK(19, 18))
#define PCIE_DBI_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_M\
	GENMASK(19, 18)
#define PCIE_DBI_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_X(x)\
	(((x) & GENMASK(19, 18)) >> 18)

#define PCIE_DBI_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG(x)\
	(((x) << 20) & GENMASK(20, 20))
#define PCIE_DBI_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_M GENMASK(20, 20)
#define PCIE_DBI_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_X(x)\
	(((x) & GENMASK(20, 20)) >> 20)

#define PCIE_DBI_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL(x)\
	(((x) << 21) & GENMASK(21, 21))
#define PCIE_DBI_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_M GENMASK(21, 21)
#define PCIE_DBI_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_X(x)\
	(((x) & GENMASK(21, 21)) >> 21)

#define PCIE_DBI_MISC_CONTROL_1_OFF_PORT_LOGIC_WR_DISABLE(x)\
	(((x) << 22) & GENMASK(22, 22))
#define PCIE_DBI_MISC_CONTROL_1_OFF_PORT_LOGIC_WR_DISABLE_M GENMASK(22, 22)
#define PCIE_DBI_MISC_CONTROL_1_OFF_PORT_LOGIC_WR_DISABLE_X(x)\
	(((x) & GENMASK(22, 22)) >> 22)

/*      SHA:SHA_REGS:SHA_CR */
#define SHA_SHA_CR(t)             (t + 0x00)

#define SHA_SHA_CR_UNLOCK(x)                     (((x) << 24) & GENMASK(24, 24))
#define SHA_SHA_CR_UNLOCK_M                      GENMASK(24, 24)
#define SHA_SHA_CR_UNLOCK_X(x)                   (((x) & GENMASK(24, 24)) >> 24)

#define SHA_SHA_CR_WUIEHV(x)                     (((x) << 13) & GENMASK(13, 13))
#define SHA_SHA_CR_WUIEHV_M                      GENMASK(13, 13)
#define SHA_SHA_CR_WUIEHV_X(x)                   (((x) & GENMASK(13, 13)) >> 13)

#define SHA_SHA_CR_WUIHV(x)                      (((x) << 12) & GENMASK(12, 12))
#define SHA_SHA_CR_WUIHV_M                       GENMASK(12, 12)
#define SHA_SHA_CR_WUIHV_X(x)                    (((x) & GENMASK(12, 12)) >> 12)

#define SHA_SHA_CR_SWRST(x)                      (((x) << 8) & GENMASK(8, 8))
#define SHA_SHA_CR_SWRST_M                       GENMASK(8, 8)
#define SHA_SHA_CR_SWRST_X(x)                    (((x) & GENMASK(8, 8)) >> 8)

#define SHA_SHA_CR_FIRST(x)                      (((x) << 4) & GENMASK(4, 4))
#define SHA_SHA_CR_FIRST_M                       GENMASK(4, 4)
#define SHA_SHA_CR_FIRST_X(x)                    (((x) & GENMASK(4, 4)) >> 4)

#define SHA_SHA_CR_START(x)                      ((x) & GENMASK(0, 0))
#define SHA_SHA_CR_START_M                       GENMASK(0, 0)
#define SHA_SHA_CR_START_X(x)                    ((x) & GENMASK(0, 0))

/*      SHA:SHA_REGS:SHA_MR */
#define SHA_SHA_MR(t)             (t + 0x04)

#define SHA_SHA_MR_CHKCNT(x)                     (((x) << 28) & GENMASK(31, 28))
#define SHA_SHA_MR_CHKCNT_M                      GENMASK(31, 28)
#define SHA_SHA_MR_CHKCNT_X(x)                   (((x) & GENMASK(31, 28)) >> 28)

#define SHA_SHA_MR_CHECK(x)                      (((x) << 24) & GENMASK(25, 24))
#define SHA_SHA_MR_CHECK_M                       GENMASK(25, 24)
#define SHA_SHA_MR_CHECK_X(x)                    (((x) & GENMASK(25, 24)) >> 24)

#define SHA_SHA_MR_DUALBUFF(x)                   (((x) << 16) & GENMASK(16, 16))
#define SHA_SHA_MR_DUALBUFF_M                    GENMASK(16, 16)
#define SHA_SHA_MR_DUALBUFF_X(x)                 (((x) & GENMASK(16, 16)) >> 16)

#define SHA_SHA_MR_TMPLCK(x)                     (((x) << 15) & GENMASK(15, 15))
#define SHA_SHA_MR_TMPLCK_M                      GENMASK(15, 15)
#define SHA_SHA_MR_TMPLCK_X(x)                   (((x) & GENMASK(15, 15)) >> 15)

#define SHA_SHA_MR_ALGO(x)                       (((x) << 8) & GENMASK(11, 8))
#define SHA_SHA_MR_ALGO_M                        GENMASK(11, 8)
#define SHA_SHA_MR_ALGO_X(x)                     (((x) & GENMASK(11, 8)) >> 8)

#define SHA_SHA_MR_BPE(x)                        (((x) << 7) & GENMASK(7, 7))
#define SHA_SHA_MR_BPE_M                         GENMASK(7, 7)
#define SHA_SHA_MR_BPE_X(x)                      (((x) & GENMASK(7, 7)) >> 7)

#define SHA_SHA_MR_UIEHV(x)                      (((x) << 6) & GENMASK(6, 6))
#define SHA_SHA_MR_UIEHV_M                       GENMASK(6, 6)
#define SHA_SHA_MR_UIEHV_X(x)                    (((x) & GENMASK(6, 6)) >> 6)

#define SHA_SHA_MR_UIHV(x)                       (((x) << 5) & GENMASK(5, 5))
#define SHA_SHA_MR_UIHV_M                        GENMASK(5, 5)
#define SHA_SHA_MR_UIHV_X(x)                     (((x) & GENMASK(5, 5)) >> 5)

#define SHA_SHA_MR_PROCDLY(x)                    (((x) << 4) & GENMASK(4, 4))
#define SHA_SHA_MR_PROCDLY_M                     GENMASK(4, 4)
#define SHA_SHA_MR_PROCDLY_X(x)                  (((x) & GENMASK(4, 4)) >> 4)

#define SHA_SHA_MR_SMOD(x)                       ((x) & GENMASK(1, 0))
#define SHA_SHA_MR_SMOD_M                        GENMASK(1, 0)
#define SHA_SHA_MR_SMOD_X(x)                     ((x) & GENMASK(1, 0))

/*      SHA:SHA_REGS:SHA_IER */
#define SHA_SHA_IER(t)            (t + 0x10)

#define SHA_SHA_IER_SECE(x)                      (((x) << 24) & GENMASK(24, 24))
#define SHA_SHA_IER_SECE_M                       GENMASK(24, 24)
#define SHA_SHA_IER_SECE_X(x)                    (((x) & GENMASK(24, 24)) >> 24)

#define SHA_SHA_IER_CHECKF(x)                    (((x) << 16) & GENMASK(16, 16))
#define SHA_SHA_IER_CHECKF_M                     GENMASK(16, 16)
#define SHA_SHA_IER_CHECKF_X(x)                  (((x) & GENMASK(16, 16)) >> 16)

#define SHA_SHA_IER_URAD(x)                      (((x) << 8) & GENMASK(8, 8))
#define SHA_SHA_IER_URAD_M                       GENMASK(8, 8)
#define SHA_SHA_IER_URAD_X(x)                    (((x) & GENMASK(8, 8)) >> 8)

#define SHA_SHA_IER_DATRDY(x)                    ((x) & GENMASK(0, 0))
#define SHA_SHA_IER_DATRDY_M                     GENMASK(0, 0)
#define SHA_SHA_IER_DATRDY_X(x)                  ((x) & GENMASK(0, 0))

/*      SHA:SHA_REGS:SHA_IDR */
#define SHA_SHA_IDR(t)            (t + 0x14)

#define SHA_SHA_IDR_SECE_IDR(x)                  (((x) << 24) & GENMASK(24, 24))
#define SHA_SHA_IDR_SECE_IDR_M                   GENMASK(24, 24)
#define SHA_SHA_IDR_SECE_IDR_X(x)                (((x) & GENMASK(24, 24)) >> 24)

#define SHA_SHA_IDR_CHECKF_IDR(x)                (((x) << 16) & GENMASK(16, 16))
#define SHA_SHA_IDR_CHECKF_IDR_M                 GENMASK(16, 16)
#define SHA_SHA_IDR_CHECKF_IDR_X(x)              (((x) & GENMASK(16, 16)) >> 16)

#define SHA_SHA_IDR_URAD_IDR(x)                  (((x) << 8) & GENMASK(8, 8))
#define SHA_SHA_IDR_URAD_IDR_M                   GENMASK(8, 8)
#define SHA_SHA_IDR_URAD_IDR_X(x)                (((x) & GENMASK(8, 8)) >> 8)

#define SHA_SHA_IDR_DATRDY_IDR(x)                ((x) & GENMASK(0, 0))
#define SHA_SHA_IDR_DATRDY_IDR_M                 GENMASK(0, 0)
#define SHA_SHA_IDR_DATRDY_IDR_X(x)              ((x) & GENMASK(0, 0))

/*      SHA:SHA_REGS:SHA_IMR */
#define SHA_SHA_IMR(t)            (t + 0x18)

#define SHA_SHA_IMR_SECE_IMR(x)                  (((x) << 24) & GENMASK(24, 24))
#define SHA_SHA_IMR_SECE_IMR_M                   GENMASK(24, 24)
#define SHA_SHA_IMR_SECE_IMR_X(x)                (((x) & GENMASK(24, 24)) >> 24)

#define SHA_SHA_IMR_CHECKF_IMR(x)                (((x) << 16) & GENMASK(16, 16))
#define SHA_SHA_IMR_CHECKF_IMR_M                 GENMASK(16, 16)
#define SHA_SHA_IMR_CHECKF_IMR_X(x)              (((x) & GENMASK(16, 16)) >> 16)

#define SHA_SHA_IMR_URAD_IMR(x)                  (((x) << 8) & GENMASK(8, 8))
#define SHA_SHA_IMR_URAD_IMR_M                   GENMASK(8, 8)
#define SHA_SHA_IMR_URAD_IMR_X(x)                (((x) & GENMASK(8, 8)) >> 8)

#define SHA_SHA_IMR_DATRDY_IMR(x)                ((x) & GENMASK(0, 0))
#define SHA_SHA_IMR_DATRDY_IMR_M                 GENMASK(0, 0)
#define SHA_SHA_IMR_DATRDY_IMR_X(x)              ((x) & GENMASK(0, 0))

/*      SHA:SHA_REGS:SHA_ISR */
#define SHA_SHA_ISR(t)            (t + 0x1c)

#define SHA_SHA_ISR_SECE_ISR(x)                  (((x) << 24) & GENMASK(24, 24))
#define SHA_SHA_ISR_SECE_ISR_M                   GENMASK(24, 24)
#define SHA_SHA_ISR_SECE_ISR_X(x)                (((x) & GENMASK(24, 24)) >> 24)

#define SHA_SHA_ISR_CHKST_ISR(x)                 (((x) << 20) & GENMASK(23, 20))
#define SHA_SHA_ISR_CHKST_ISR_M                  GENMASK(23, 20)
#define SHA_SHA_ISR_CHKST_ISR_X(x)               (((x) & GENMASK(23, 20)) >> 20)

#define SHA_SHA_ISR_CHECKF_ISR(x)                (((x) << 16) & GENMASK(16, 16))
#define SHA_SHA_ISR_CHECKF_ISR_M                 GENMASK(16, 16)
#define SHA_SHA_ISR_CHECKF_ISR_X(x)              (((x) & GENMASK(16, 16)) >> 16)

#define SHA_SHA_ISR_URAT_ISR(x)                  (((x) << 12) & GENMASK(14, 12))
#define SHA_SHA_ISR_URAT_ISR_M                   GENMASK(14, 12)
#define SHA_SHA_ISR_URAT_ISR_X(x)                (((x) & GENMASK(14, 12)) >> 12)

#define SHA_SHA_ISR_URAD_ISR(x)                  (((x) << 8) & GENMASK(8, 8))
#define SHA_SHA_ISR_URAD_ISR_M                   GENMASK(8, 8)
#define SHA_SHA_ISR_URAD_ISR_X(x)                (((x) & GENMASK(8, 8)) >> 8)

#define SHA_SHA_ISR_WRDY_ISR(x)                  (((x) << 4) & GENMASK(4, 4))
#define SHA_SHA_ISR_WRDY_ISR_M                   GENMASK(4, 4)
#define SHA_SHA_ISR_WRDY_ISR_X(x)                (((x) & GENMASK(4, 4)) >> 4)

#define SHA_SHA_ISR_DATRDY_ISR(x)                ((x) & GENMASK(0, 0))
#define SHA_SHA_ISR_DATRDY_ISR_M                 GENMASK(0, 0)
#define SHA_SHA_ISR_DATRDY_ISR_X(x)              ((x) & GENMASK(0, 0))

/*      SHA:SHA_REGS:SHA_MSR */
#define SHA_SHA_MSR(t)            (t + 0x20)

/*      SHA:SHA_REGS:SHA_BCR */
#define SHA_SHA_BCR(t)            (t + 0x30)

/*      SHA:SHA_REGS:SHA_IDATAR0 */
#define SHA_SHA_IDATAR0(t)        (t + 0x40)

/*      SHA:SHA_REGS:SHA_IDATAR1 */
#define SHA_SHA_IDATAR1(t)        (t + 0x44)

/*      SHA:SHA_REGS:SHA_IDATAR2 */
#define SHA_SHA_IDATAR2(t)        (t + 0x48)

/*      SHA:SHA_REGS:SHA_IDATAR3 */
#define SHA_SHA_IDATAR3(t)        (t + 0x4c)

/*      SHA:SHA_REGS:SHA_IDATAR4 */
#define SHA_SHA_IDATAR4(t)        (t + 0x50)

/*      SHA:SHA_REGS:SHA_IDATAR5 */
#define SHA_SHA_IDATAR5(t)        (t + 0x54)

/*      SHA:SHA_REGS:SHA_IDATAR6 */
#define SHA_SHA_IDATAR6(t)        (t + 0x58)

/*      SHA:SHA_REGS:SHA_IDATAR7 */
#define SHA_SHA_IDATAR7(t)        (t + 0x5c)

/*      SHA:SHA_REGS:SHA_IDATAR8 */
#define SHA_SHA_IDATAR8(t)        (t + 0x60)

/*      SHA:SHA_REGS:SHA_IDATAR9 */
#define SHA_SHA_IDATAR9(t)        (t + 0x64)

/*      SHA:SHA_REGS:SHA_IDATAR10 */
#define SHA_SHA_IDATAR10(t)       (t + 0x68)

/*      SHA:SHA_REGS:SHA_IDATAR11 */
#define SHA_SHA_IDATAR11(t)       (t + 0x6c)

/*      SHA:SHA_REGS:SHA_IDATAR12 */
#define SHA_SHA_IDATAR12(t)       (t + 0x70)

/*      SHA:SHA_REGS:SHA_IDATAR13 */
#define SHA_SHA_IDATAR13(t)       (t + 0x74)

/*      SHA:SHA_REGS:SHA_IDATAR14 */
#define SHA_SHA_IDATAR14(t)       (t + 0x78)

/*      SHA:SHA_REGS:SHA_IDATAR15 */
#define SHA_SHA_IDATAR15(t)       (t + 0x7c)

/*      SHA:SHA_REGS:SHA_IODATAR0 */
#define SHA_SHA_IODATAR0(t)       (t + 0x80)

/*      SHA:SHA_REGS:SHA_IODATAR1 */
#define SHA_SHA_IODATAR1(t)       (t + 0x84)

/*      SHA:SHA_REGS:SHA_IODATAR2 */
#define SHA_SHA_IODATAR2(t)       (t + 0x88)

/*      SHA:SHA_REGS:SHA_IODATAR3 */
#define SHA_SHA_IODATAR3(t)       (t + 0x8c)

/*      SHA:SHA_REGS:SHA_IODATAR4 */
#define SHA_SHA_IODATAR4(t)       (t + 0x90)

/*      SHA:SHA_REGS:SHA_IODATAR5 */
#define SHA_SHA_IODATAR5(t)       (t + 0x94)

/*      SHA:SHA_REGS:SHA_IODATAR6 */
#define SHA_SHA_IODATAR6(t)       (t + 0x98)

/*      SHA:SHA_REGS:SHA_IODATAR7 */
#define SHA_SHA_IODATAR7(t)       (t + 0x9c)

/*      SHA:SHA_REGS:SHA_IODATAR8 */
#define SHA_SHA_IODATAR8(t)       (t + 0xa0)

/*      SHA:SHA_REGS:SHA_IODATAR9 */
#define SHA_SHA_IODATAR9(t)       (t + 0xa4)

/*      SHA:SHA_REGS:SHA_IODATAR10 */
#define SHA_SHA_IODATAR10(t)      (t + 0xa8)

/*      SHA:SHA_REGS:SHA_IODATAR11 */
#define SHA_SHA_IODATAR11(t)      (t + 0xac)

/*      SHA:SHA_REGS:SHA_IODATAR12 */
#define SHA_SHA_IODATAR12(t)      (t + 0xb0)

/*      SHA:SHA_REGS:SHA_IODATAR13 */
#define SHA_SHA_IODATAR13(t)      (t + 0xb4)

/*      SHA:SHA_REGS:SHA_IODATAR14 */
#define SHA_SHA_IODATAR14(t)      (t + 0xb8)

/*      SHA:SHA_REGS:SHA_IODATAR15 */
#define SHA_SHA_IODATAR15(t)      (t + 0xbc)

/*      SHA:SHA_REGS:SHA_WPMR */
#define SHA_SHA_WPMR(t)           (t + 0xe4)

#define SHA_SHA_WPMR_WPKEY(x)                    (((x) << 8) & GENMASK(31, 8))
#define SHA_SHA_WPMR_WPKEY_M                     GENMASK(31, 8)
#define SHA_SHA_WPMR_WPKEY_X(x)                  (((x) & GENMASK(31, 8)) >> 8)

#define SHA_SHA_WPMR_ACTION(x)                   (((x) << 5) & GENMASK(6, 5))
#define SHA_SHA_WPMR_ACTION_M                    GENMASK(6, 5)
#define SHA_SHA_WPMR_ACTION_X(x)                 (((x) & GENMASK(6, 5)) >> 5)

#define SHA_SHA_WPMR_FIRSTE(x)                   (((x) << 4) & GENMASK(4, 4))
#define SHA_SHA_WPMR_FIRSTE_M                    GENMASK(4, 4)
#define SHA_SHA_WPMR_FIRSTE_X(x)                 (((x) & GENMASK(4, 4)) >> 4)

#define SHA_SHA_WPMR_WPCREN(x)                   (((x) << 2) & GENMASK(2, 2))
#define SHA_SHA_WPMR_WPCREN_M                    GENMASK(2, 2)
#define SHA_SHA_WPMR_WPCREN_X(x)                 (((x) & GENMASK(2, 2)) >> 2)

#define SHA_SHA_WPMR_WPITEN(x)                   (((x) << 1) & GENMASK(1, 1))
#define SHA_SHA_WPMR_WPITEN_M                    GENMASK(1, 1)
#define SHA_SHA_WPMR_WPITEN_X(x)                 (((x) & GENMASK(1, 1)) >> 1)

#define SHA_SHA_WPMR_WPEN(x)                     ((x) & GENMASK(0, 0))
#define SHA_SHA_WPMR_WPEN_M                      GENMASK(0, 0)
#define SHA_SHA_WPMR_WPEN_X(x)                   ((x) & GENMASK(0, 0))

/*      SHA:SHA_REGS:SHA_WPSR */
#define SHA_SHA_WPSR(t)           (t + 0xe8)

#define SHA_SHA_WPSR_ECLASS(x)                   (((x) << 31) & GENMASK(31, 31))
#define SHA_SHA_WPSR_ECLASS_M                    GENMASK(31, 31)
#define SHA_SHA_WPSR_ECLASS_X(x)                 (((x) & GENMASK(31, 31)) >> 31)

#define SHA_SHA_WPSR_SWETYP(x)                   (((x) << 24) & GENMASK(27, 24))
#define SHA_SHA_WPSR_SWETYP_M                    GENMASK(27, 24)
#define SHA_SHA_WPSR_SWETYP_X(x)                 (((x) & GENMASK(27, 24)) >> 24)

#define SHA_SHA_WPSR_WPVSRC(x)                   (((x) << 8) & GENMASK(15, 8))
#define SHA_SHA_WPSR_WPVSRC_M                    GENMASK(15, 8)
#define SHA_SHA_WPSR_WPVSRC_X(x)                 (((x) & GENMASK(15, 8)) >> 8)

#define SHA_SHA_WPSR_SWE(x)                      (((x) << 3) & GENMASK(3, 3))
#define SHA_SHA_WPSR_SWE_M                       GENMASK(3, 3)
#define SHA_SHA_WPSR_SWE_X(x)                    (((x) & GENMASK(3, 3)) >> 3)

#define SHA_SHA_WPSR_SEQE(x)                     (((x) << 2) & GENMASK(2, 2))
#define SHA_SHA_WPSR_SEQE_M                      GENMASK(2, 2)
#define SHA_SHA_WPSR_SEQE_X(x)                   (((x) & GENMASK(2, 2)) >> 2)

#define SHA_SHA_WPSR_CGD(x)                      (((x) << 1) & GENMASK(1, 1))
#define SHA_SHA_WPSR_CGD_M                       GENMASK(1, 1)
#define SHA_SHA_WPSR_CGD_X(x)                    (((x) & GENMASK(1, 1)) >> 1)

#define SHA_SHA_WPSR_WPVS(x)                     ((x) & GENMASK(0, 0))
#define SHA_SHA_WPSR_WPVS_M                      GENMASK(0, 0)
#define SHA_SHA_WPSR_WPVS_X(x)                   ((x) & GENMASK(0, 0))

/*      SJTAG:SJTAG_REGS:CTL */
#define SJTAG_CTL(t)              (t + 0x00)

#define SJTAG_CTL_BLOCK_RESET(x)                 (((x) << 31) & GENMASK(31, 31))
#define SJTAG_CTL_BLOCK_RESET_M                  GENMASK(31, 31)
#define SJTAG_CTL_BLOCK_RESET_X(x)               (((x) & GENMASK(31, 31)) >> 31)

#define SJTAG_CTL_SJTAG_UNLOCK_STS(x)            (((x) << 11) & GENMASK(11, 11))
#define SJTAG_CTL_SJTAG_UNLOCK_STS_M             GENMASK(11, 11)
#define SJTAG_CTL_SJTAG_UNLOCK_STS_X(x)          (((x) & GENMASK(11, 11)) >> 11)

#define SJTAG_CTL_SJTAG_MODE_STS(x)              (((x) << 9) & GENMASK(10, 9))
#define SJTAG_CTL_SJTAG_MODE_STS_M               GENMASK(10, 9)
#define SJTAG_CTL_SJTAG_MODE_STS_X(x)            (((x) & GENMASK(10, 9)) >> 9)

#define SJTAG_CTL_SJTAG_HC_TO_UNITS_DBG(x)       (((x) << 8) & GENMASK(8, 8))
#define SJTAG_CTL_SJTAG_HC_TO_UNITS_DBG_M        GENMASK(8, 8)
#define SJTAG_CTL_SJTAG_HC_TO_UNITS_DBG_X(x)     (((x) & GENMASK(8, 8)) >> 8)

#define SJTAG_CTL_SJTAG_HC_TO_EN(x)              (((x) << 7) & GENMASK(7, 7))
#define SJTAG_CTL_SJTAG_HC_TO_EN_M               GENMASK(7, 7)
#define SJTAG_CTL_SJTAG_HC_TO_EN_X(x)            (((x) & GENMASK(7, 7)) >> 7)

#define SJTAG_CTL_SJTAG_DIGEST_CMP(x)            (((x) << 6) & GENMASK(6, 6))
#define SJTAG_CTL_SJTAG_DIGEST_CMP_M             GENMASK(6, 6)
#define SJTAG_CTL_SJTAG_DIGEST_CMP_X(x)          (((x) & GENMASK(6, 6)) >> 6)

#define SJTAG_CTL_SJTAG_FREEZE(x)                (((x) << 5) & GENMASK(5, 5))
#define SJTAG_CTL_SJTAG_FREEZE_M                 GENMASK(5, 5)
#define SJTAG_CTL_SJTAG_FREEZE_X(x)              (((x) & GENMASK(5, 5)) >> 5)

#define SJTAG_CTL_SJTAG_MODE(x)                  (((x) << 3) & GENMASK(4, 3))
#define SJTAG_CTL_SJTAG_MODE_M                   GENMASK(4, 3)
#define SJTAG_CTL_SJTAG_MODE_X(x)                (((x) & GENMASK(4, 3)) >> 3)

#define SJTAG_CTL_SJTAG_EN(x)                    (((x) << 2) & GENMASK(2, 2))
#define SJTAG_CTL_SJTAG_EN_M                     GENMASK(2, 2)
#define SJTAG_CTL_SJTAG_EN_X(x)                  (((x) & GENMASK(2, 2)) >> 2)

#define SJTAG_CTL_SJTAG_CPU_EN(x)                (((x) << 1) & GENMASK(1, 1))
#define SJTAG_CTL_SJTAG_CPU_EN_M                 GENMASK(1, 1)
#define SJTAG_CTL_SJTAG_CPU_EN_X(x)              (((x) & GENMASK(1, 1)) >> 1)

#define SJTAG_CTL_SJTAG_TST_EN(x)                ((x) & GENMASK(0, 0))
#define SJTAG_CTL_SJTAG_TST_EN_M                 GENMASK(0, 0)
#define SJTAG_CTL_SJTAG_TST_EN_X(x)              ((x) & GENMASK(0, 0))

/*      SJTAG:SJTAG_REGS:INT_STATUS */
#define SJTAG_INT_STATUS(t)       (t + 0x04)

#define SJTAG_INT_STATUS_SJTAG_TO_STS(x)         (((x) << 7) & GENMASK(7, 7))
#define SJTAG_INT_STATUS_SJTAG_TO_STS_M          GENMASK(7, 7)
#define SJTAG_INT_STATUS_SJTAG_TO_STS_X(x)       (((x) & GENMASK(7, 7)) >> 7)

#define SJTAG_INT_STATUS_SJTAG_READ_UUID_RX(x)   (((x) << 6) & GENMASK(6, 6))
#define SJTAG_INT_STATUS_SJTAG_READ_UUID_RX_M    GENMASK(6, 6)
#define SJTAG_INT_STATUS_SJTAG_READ_UUID_RX_X(x) (((x) & GENMASK(6, 6)) >> 6)

#define SJTAG_INT_STATUS_SJTAG_READ_MODE_RX(x)   (((x) << 5) & GENMASK(5, 5))
#define SJTAG_INT_STATUS_SJTAG_READ_MODE_RX_M    GENMASK(5, 5)
#define SJTAG_INT_STATUS_SJTAG_READ_MODE_RX_X(x) (((x) & GENMASK(5, 5)) >> 5)

#define SJTAG_INT_STATUS_SJTAG_DIGEST_FAIL(x)    (((x) << 4) & GENMASK(4, 4))
#define SJTAG_INT_STATUS_SJTAG_DIGEST_FAIL_M     GENMASK(4, 4)
#define SJTAG_INT_STATUS_SJTAG_DIGEST_FAIL_X(x)  (((x) & GENMASK(4, 4)) >> 4)

#define SJTAG_INT_STATUS_SJTAG_DIGEST_PASS(x)    (((x) << 3) & GENMASK(3, 3))
#define SJTAG_INT_STATUS_SJTAG_DIGEST_PASS_M     GENMASK(3, 3)
#define SJTAG_INT_STATUS_SJTAG_DIGEST_PASS_X(x)  (((x) & GENMASK(3, 3)) >> 3)

#define SJTAG_INT_STATUS_SJTAG_READ_NONCE_RX(x)  (((x) << 2) & GENMASK(2, 2))
#define SJTAG_INT_STATUS_SJTAG_READ_NONCE_RX_M   GENMASK(2, 2)
#define SJTAG_INT_STATUS_SJTAG_READ_NONCE_RX_X(x) (((x) & GENMASK(2, 2)) >> 2)

#define SJTAG_INT_STATUS_SJTAG_DIGEST_RX(x)      (((x) << 1) & GENMASK(1, 1))
#define SJTAG_INT_STATUS_SJTAG_DIGEST_RX_M       GENMASK(1, 1)
#define SJTAG_INT_STATUS_SJTAG_DIGEST_RX_X(x)    (((x) & GENMASK(1, 1)) >> 1)

#define SJTAG_INT_STATUS_SJTAG_UNLOCK_RX(x)      ((x) & GENMASK(0, 0))
#define SJTAG_INT_STATUS_SJTAG_UNLOCK_RX_M       GENMASK(0, 0)
#define SJTAG_INT_STATUS_SJTAG_UNLOCK_RX_X(x)    ((x) & GENMASK(0, 0))

/*      SJTAG:SJTAG_REGS:INT_MASK */
#define SJTAG_INT_MASK(t)         (t + 0x08)

#define SJTAG_INT_MASK_SJTAG_TO_STS_MSK(x)       (((x) << 7) & GENMASK(7, 7))
#define SJTAG_INT_MASK_SJTAG_TO_STS_MSK_M        GENMASK(7, 7)
#define SJTAG_INT_MASK_SJTAG_TO_STS_MSK_X(x)     (((x) & GENMASK(7, 7)) >> 7)

#define SJTAG_INT_MASK_SJTAG_UUID_RX_MSK(x)      (((x) << 6) & GENMASK(6, 6))
#define SJTAG_INT_MASK_SJTAG_UUID_RX_MSK_M       GENMASK(6, 6)
#define SJTAG_INT_MASK_SJTAG_UUID_RX_MSK_X(x)    (((x) & GENMASK(6, 6)) >> 6)

#define SJTAG_INT_MASK_SJTAG_READ_MODE_RX_MSK(x) (((x) << 5) & GENMASK(5, 5))
#define SJTAG_INT_MASK_SJTAG_READ_MODE_RX_MSK_M  GENMASK(5, 5)
#define SJTAG_INT_MASK_SJTAG_READ_MODE_RX_MSK_X(x) (((x) & GENMASK(5, 5)) >> 5)

#define SJTAG_INT_MASK_SJTAG_DIGEST_FAIL_MSK(x)  (((x) << 4) & GENMASK(4, 4))
#define SJTAG_INT_MASK_SJTAG_DIGEST_FAIL_MSK_M   GENMASK(4, 4)
#define SJTAG_INT_MASK_SJTAG_DIGEST_FAIL_MSK_X(x) (((x) & GENMASK(4, 4)) >> 4)

#define SJTAG_INT_MASK_SJTAG_DIGEST_PASS_MSK(x)  (((x) << 3) & GENMASK(3, 3))
#define SJTAG_INT_MASK_SJTAG_DIGEST_PASS_MSK_M   GENMASK(3, 3)
#define SJTAG_INT_MASK_SJTAG_DIGEST_PASS_MSK_X(x) (((x) & GENMASK(3, 3)) >> 3)

#define SJTAG_INT_MASK_SJTAG_NONCE_RX_MSK(x)     (((x) << 2) & GENMASK(2, 2))
#define SJTAG_INT_MASK_SJTAG_NONCE_RX_MSK_M      GENMASK(2, 2)
#define SJTAG_INT_MASK_SJTAG_NONCE_RX_MSK_X(x)   (((x) & GENMASK(2, 2)) >> 2)

#define SJTAG_INT_MASK_SJTAG_DIGEST_RX_MSK(x)    (((x) << 1) & GENMASK(1, 1))
#define SJTAG_INT_MASK_SJTAG_DIGEST_RX_MSK_M     GENMASK(1, 1)
#define SJTAG_INT_MASK_SJTAG_DIGEST_RX_MSK_X(x)  (((x) & GENMASK(1, 1)) >> 1)

#define SJTAG_INT_MASK_SJTAG_UNLOCK_RX_MSK(x)    ((x) & GENMASK(0, 0))
#define SJTAG_INT_MASK_SJTAG_UNLOCK_RX_MSK_M     GENMASK(0, 0)
#define SJTAG_INT_MASK_SJTAG_UNLOCK_RX_MSK_X(x)  ((x) & GENMASK(0, 0))

/*      SJTAG:SJTAG_REGS:NONCE */
#define SJTAG_NONCE(t, r)         (t + (0x10 + ((r) * 4)))

/*      SJTAG:SJTAG_REGS:HOST_DIGEST */
#define SJTAG_HOST_DIGEST(t, r)   (t + (0x30 + ((r) * 4)))

/*      SJTAG:SJTAG_REGS:DEVICE_DIGEST */
#define SJTAG_DEVICE_DIGEST(t, r) (t + (0x50 + ((r) * 4)))

/*      SJTAG:SJTAG_REGS:UUID */
#define SJTAG_UUID(t, r)          (t + (0x70 + ((r) * 4)))

/*      SJTAG:SJTAG_REGS:HC_TO */
#define SJTAG_HC_TO(t)            (t + 0x80)

/*      TRNG:TRNG_REGS:TRNG_CR */
#define TRNG_TRNG_CR(t)           (t + 0x00)

#define TRNG_TRNG_CR_WAKEY(x)                    (((x) << 8) & GENMASK(31, 8))
#define TRNG_TRNG_CR_WAKEY_M                     GENMASK(31, 8)
#define TRNG_TRNG_CR_WAKEY_X(x)                  (((x) & GENMASK(31, 8)) >> 8)

#define TRNG_TRNG_CR_ENABLE(x)                   ((x) & GENMASK(0, 0))
#define TRNG_TRNG_CR_ENABLE_M                    GENMASK(0, 0)
#define TRNG_TRNG_CR_ENABLE_X(x)                 ((x) & GENMASK(0, 0))

/*      TRNG:TRNG_REGS:TRNG_MR */
#define TRNG_TRNG_MR(t)           (t + 0x04)

#define TRNG_TRNG_MR_HALFR(x)                    ((x) & GENMASK(0, 0))
#define TRNG_TRNG_MR_HALFR_M                     GENMASK(0, 0)
#define TRNG_TRNG_MR_HALFR_X(x)                  ((x) & GENMASK(0, 0))

/*      TRNG:TRNG_REGS:TRNG_PKBCR */
#define TRNG_TRNG_PKBCR(t)        (t + 0x08)

#define TRNG_TRNG_PKBCR_WAKEY_PKBCR(x)           (((x) << 16) & GENMASK(31, 16))
#define TRNG_TRNG_PKBCR_WAKEY_PKBCR_M            GENMASK(31, 16)
#define TRNG_TRNG_PKBCR_WAKEY_PKBCR_X(x)         (((x) & GENMASK(31, 16)) >> 16)

#define TRNG_TRNG_PKBCR_KLENGTH(x)               (((x) << 8) & GENMASK(15, 8))
#define TRNG_TRNG_PKBCR_KLENGTH_M                GENMASK(15, 8)
#define TRNG_TRNG_PKBCR_KLENGTH_X(x)             (((x) & GENMASK(15, 8)) >> 8)

#define TRNG_TRNG_PKBCR_KTARGET(x)               (((x) << 4) & GENMASK(5, 4))
#define TRNG_TRNG_PKBCR_KTARGET_M                GENMASK(5, 4)
#define TRNG_TRNG_PKBCR_KTARGET_X(x)             (((x) & GENMASK(5, 4)) >> 4)

#define TRNG_TRNG_PKBCR_KID(x)                   ((x) & GENMASK(0, 0))
#define TRNG_TRNG_PKBCR_KID_M                    GENMASK(0, 0)
#define TRNG_TRNG_PKBCR_KID_X(x)                 ((x) & GENMASK(0, 0))

/*      TRNG:TRNG_REGS:TRNG_IER */
#define TRNG_TRNG_IER(t)          (t + 0x10)

#define TRNG_TRNG_IER_EOTPKB(x)                  (((x) << 2) & GENMASK(2, 2))
#define TRNG_TRNG_IER_EOTPKB_M                   GENMASK(2, 2)
#define TRNG_TRNG_IER_EOTPKB_X(x)                (((x) & GENMASK(2, 2)) >> 2)

#define TRNG_TRNG_IER_SECE(x)                    (((x) << 1) & GENMASK(1, 1))
#define TRNG_TRNG_IER_SECE_M                     GENMASK(1, 1)
#define TRNG_TRNG_IER_SECE_X(x)                  (((x) & GENMASK(1, 1)) >> 1)

#define TRNG_TRNG_IER_DATRDY(x)                  ((x) & GENMASK(0, 0))
#define TRNG_TRNG_IER_DATRDY_M                   GENMASK(0, 0)
#define TRNG_TRNG_IER_DATRDY_X(x)                ((x) & GENMASK(0, 0))

/*      TRNG:TRNG_REGS:TRNG_IDR */
#define TRNG_TRNG_IDR(t)          (t + 0x14)

#define TRNG_TRNG_IDR_EOTPKB_IDR(x)              (((x) << 2) & GENMASK(2, 2))
#define TRNG_TRNG_IDR_EOTPKB_IDR_M               GENMASK(2, 2)
#define TRNG_TRNG_IDR_EOTPKB_IDR_X(x)            (((x) & GENMASK(2, 2)) >> 2)

#define TRNG_TRNG_IDR_SECE_IDR(x)                (((x) << 1) & GENMASK(1, 1))
#define TRNG_TRNG_IDR_SECE_IDR_M                 GENMASK(1, 1)
#define TRNG_TRNG_IDR_SECE_IDR_X(x)              (((x) & GENMASK(1, 1)) >> 1)

#define TRNG_TRNG_IDR_DATRDY_IDR(x)              ((x) & GENMASK(0, 0))
#define TRNG_TRNG_IDR_DATRDY_IDR_M               GENMASK(0, 0)
#define TRNG_TRNG_IDR_DATRDY_IDR_X(x)            ((x) & GENMASK(0, 0))

/*      TRNG:TRNG_REGS:TRNG_IMR */
#define TRNG_TRNG_IMR(t)          (t + 0x18)

#define TRNG_TRNG_IMR_EOTPKB_IMR(x)              (((x) << 2) & GENMASK(2, 2))
#define TRNG_TRNG_IMR_EOTPKB_IMR_M               GENMASK(2, 2)
#define TRNG_TRNG_IMR_EOTPKB_IMR_X(x)            (((x) & GENMASK(2, 2)) >> 2)

#define TRNG_TRNG_IMR_SECE_IMR(x)                (((x) << 1) & GENMASK(1, 1))
#define TRNG_TRNG_IMR_SECE_IMR_M                 GENMASK(1, 1)
#define TRNG_TRNG_IMR_SECE_IMR_X(x)              (((x) & GENMASK(1, 1)) >> 1)

#define TRNG_TRNG_IMR_DATRDY_IMR(x)              ((x) & GENMASK(0, 0))
#define TRNG_TRNG_IMR_DATRDY_IMR_M               GENMASK(0, 0)
#define TRNG_TRNG_IMR_DATRDY_IMR_X(x)            ((x) & GENMASK(0, 0))

/*      TRNG:TRNG_REGS:TRNG_ISR */
#define TRNG_TRNG_ISR(t)          (t + 0x1c)

#define TRNG_TRNG_ISR_EOTPKB_ISR(x)              (((x) << 2) & GENMASK(2, 2))
#define TRNG_TRNG_ISR_EOTPKB_ISR_M               GENMASK(2, 2)
#define TRNG_TRNG_ISR_EOTPKB_ISR_X(x)            (((x) & GENMASK(2, 2)) >> 2)

#define TRNG_TRNG_ISR_SECE_ISR(x)                (((x) << 1) & GENMASK(1, 1))
#define TRNG_TRNG_ISR_SECE_ISR_M                 GENMASK(1, 1)
#define TRNG_TRNG_ISR_SECE_ISR_X(x)              (((x) & GENMASK(1, 1)) >> 1)

#define TRNG_TRNG_ISR_DATRDY_ISR(x)              ((x) & GENMASK(0, 0))
#define TRNG_TRNG_ISR_DATRDY_ISR_M               GENMASK(0, 0)
#define TRNG_TRNG_ISR_DATRDY_ISR_X(x)            ((x) & GENMASK(0, 0))

/*      TRNG:TRNG_REGS:TRNG_ODATA */
#define TRNG_TRNG_ODATA(t)        (t + 0x50)

/*      TRNG:TRNG_REGS:TRNG_WPMR */
#define TRNG_TRNG_WPMR(t)         (t + 0xe4)

#define TRNG_TRNG_WPMR_WPKEY(x)                  (((x) << 8) & GENMASK(31, 8))
#define TRNG_TRNG_WPMR_WPKEY_M                   GENMASK(31, 8)
#define TRNG_TRNG_WPMR_WPKEY_X(x)                (((x) & GENMASK(31, 8)) >> 8)

#define TRNG_TRNG_WPMR_FIRSTE(x)                 (((x) << 4) & GENMASK(4, 4))
#define TRNG_TRNG_WPMR_FIRSTE_M                  GENMASK(4, 4)
#define TRNG_TRNG_WPMR_FIRSTE_X(x)               (((x) & GENMASK(4, 4)) >> 4)

#define TRNG_TRNG_WPMR_WPCREN(x)                 (((x) << 2) & GENMASK(2, 2))
#define TRNG_TRNG_WPMR_WPCREN_M                  GENMASK(2, 2)
#define TRNG_TRNG_WPMR_WPCREN_X(x)               (((x) & GENMASK(2, 2)) >> 2)

#define TRNG_TRNG_WPMR_WPITEN(x)                 (((x) << 1) & GENMASK(1, 1))
#define TRNG_TRNG_WPMR_WPITEN_M                  GENMASK(1, 1)
#define TRNG_TRNG_WPMR_WPITEN_X(x)               (((x) & GENMASK(1, 1)) >> 1)

#define TRNG_TRNG_WPMR_WPEN(x)                   ((x) & GENMASK(0, 0))
#define TRNG_TRNG_WPMR_WPEN_M                    GENMASK(0, 0)
#define TRNG_TRNG_WPMR_WPEN_X(x)                 ((x) & GENMASK(0, 0))

/*      TRNG:TRNG_REGS:TRNG_WPSR */
#define TRNG_TRNG_WPSR(t)         (t + 0xe8)

#define TRNG_TRNG_WPSR_ECLASS(x)                 (((x) << 31) & GENMASK(31, 31))
#define TRNG_TRNG_WPSR_ECLASS_M                  GENMASK(31, 31)
#define TRNG_TRNG_WPSR_ECLASS_X(x)               (((x) & GENMASK(31, 31)) >> 31)

#define TRNG_TRNG_WPSR_SWETYP(x)                 (((x) << 24) & GENMASK(27, 24))
#define TRNG_TRNG_WPSR_SWETYP_M                  GENMASK(27, 24)
#define TRNG_TRNG_WPSR_SWETYP_X(x)               (((x) & GENMASK(27, 24)) >> 24)

#define TRNG_TRNG_WPSR_WPVSRC(x)                 (((x) << 8) & GENMASK(23, 8))
#define TRNG_TRNG_WPSR_WPVSRC_M                  GENMASK(23, 8)
#define TRNG_TRNG_WPSR_WPVSRC_X(x)               (((x) & GENMASK(23, 8)) >> 8)

#define TRNG_TRNG_WPSR_SWE(x)                    (((x) << 3) & GENMASK(3, 3))
#define TRNG_TRNG_WPSR_SWE_M                     GENMASK(3, 3)
#define TRNG_TRNG_WPSR_SWE_X(x)                  (((x) & GENMASK(3, 3)) >> 3)

#define TRNG_TRNG_WPSR_SEQE(x)                   (((x) << 2) & GENMASK(2, 2))
#define TRNG_TRNG_WPSR_SEQE_M                    GENMASK(2, 2)
#define TRNG_TRNG_WPSR_SEQE_X(x)                 (((x) & GENMASK(2, 2)) >> 2)

#define TRNG_TRNG_WPSR_CGD(x)                    (((x) << 1) & GENMASK(1, 1))
#define TRNG_TRNG_WPSR_CGD_M                     GENMASK(1, 1)
#define TRNG_TRNG_WPSR_CGD_X(x)                  (((x) & GENMASK(1, 1)) >> 1)

#define TRNG_TRNG_WPSR_WPVS(x)                   ((x) & GENMASK(0, 0))
#define TRNG_TRNG_WPSR_WPVS_M                    GENMASK(0, 0)
#define TRNG_TRNG_WPSR_WPVS_X(x)                 ((x) & GENMASK(0, 0))

/*      TRNG:TRNG_REGS:TRNG_VERSION */
#define TRNG_TRNG_VERSION(t)      (t + 0xfc)

#define TRNG_TRNG_VERSION_MFN(x)                 (((x) << 16) & GENMASK(18, 16))
#define TRNG_TRNG_VERSION_MFN_M                  GENMASK(18, 16)
#define TRNG_TRNG_VERSION_MFN_X(x)               (((x) & GENMASK(18, 16)) >> 16)

#define TRNG_TRNG_VERSION_VERSION(x)             ((x) & GENMASK(11, 0))
#define TRNG_TRNG_VERSION_VERSION_M              GENMASK(11, 0)
#define TRNG_TRNG_VERSION_VERSION_X(x)           ((x) & GENMASK(11, 0))

/*      TZAESBNS:TZAESB_REGS:TZAESB_CR */
#define TZAESBNS_TZAESB_CR(t)     (t + 0x00)

#define TZAESBNS_TZAESB_CR_UNLOCK(x)             (((x) << 24) & GENMASK(24, 24))
#define TZAESBNS_TZAESB_CR_UNLOCK_M              GENMASK(24, 24)
#define TZAESBNS_TZAESB_CR_UNLOCK_X(x)           (((x) & GENMASK(24, 24)) >> 24)

#define TZAESBNS_TZAESB_CR_LOADSEED(x)           (((x) << 16) & GENMASK(16, 16))
#define TZAESBNS_TZAESB_CR_LOADSEED_M            GENMASK(16, 16)
#define TZAESBNS_TZAESB_CR_LOADSEED_X(x)         (((x) & GENMASK(16, 16)) >> 16)

#define TZAESBNS_TZAESB_CR_SWRST(x)              (((x) << 8) & GENMASK(8, 8))
#define TZAESBNS_TZAESB_CR_SWRST_M               GENMASK(8, 8)
#define TZAESBNS_TZAESB_CR_SWRST_X(x)            (((x) & GENMASK(8, 8)) >> 8)

#define TZAESBNS_TZAESB_CR_START(x)              ((x) & GENMASK(0, 0))
#define TZAESBNS_TZAESB_CR_START_M               GENMASK(0, 0)
#define TZAESBNS_TZAESB_CR_START_X(x)            ((x) & GENMASK(0, 0))

/*      TZAESBNS:TZAESB_REGS:TZAESB_MR */
#define TZAESBNS_TZAESB_MR(t)     (t + 0x04)

#define TZAESBNS_TZAESB_MR_TAMPCLR(x)            (((x) << 31) & GENMASK(31, 31))
#define TZAESBNS_TZAESB_MR_TAMPCLR_M             GENMASK(31, 31)
#define TZAESBNS_TZAESB_MR_TAMPCLR_X(x)          (((x) & GENMASK(31, 31)) >> 31)

#define TZAESBNS_TZAESB_MR_CMTYP7(x)             (((x) << 30) & GENMASK(30, 30))
#define TZAESBNS_TZAESB_MR_CMTYP7_M              GENMASK(30, 30)
#define TZAESBNS_TZAESB_MR_CMTYP7_X(x)           (((x) & GENMASK(30, 30)) >> 30)

#define TZAESBNS_TZAESB_MR_CMTYP6(x)             (((x) << 29) & GENMASK(29, 29))
#define TZAESBNS_TZAESB_MR_CMTYP6_M              GENMASK(29, 29)
#define TZAESBNS_TZAESB_MR_CMTYP6_X(x)           (((x) & GENMASK(29, 29)) >> 29)

#define TZAESBNS_TZAESB_MR_CMTYP5(x)             (((x) << 28) & GENMASK(28, 28))
#define TZAESBNS_TZAESB_MR_CMTYP5_M              GENMASK(28, 28)
#define TZAESBNS_TZAESB_MR_CMTYP5_X(x)           (((x) & GENMASK(28, 28)) >> 28)

#define TZAESBNS_TZAESB_MR_CMTYP4(x)             (((x) << 27) & GENMASK(27, 27))
#define TZAESBNS_TZAESB_MR_CMTYP4_M              GENMASK(27, 27)
#define TZAESBNS_TZAESB_MR_CMTYP4_X(x)           (((x) & GENMASK(27, 27)) >> 27)

#define TZAESBNS_TZAESB_MR_CMTYP3(x)             (((x) << 26) & GENMASK(26, 26))
#define TZAESBNS_TZAESB_MR_CMTYP3_M              GENMASK(26, 26)
#define TZAESBNS_TZAESB_MR_CMTYP3_X(x)           (((x) & GENMASK(26, 26)) >> 26)

#define TZAESBNS_TZAESB_MR_CMTYP2(x)             (((x) << 25) & GENMASK(25, 25))
#define TZAESBNS_TZAESB_MR_CMTYP2_M              GENMASK(25, 25)
#define TZAESBNS_TZAESB_MR_CMTYP2_X(x)           (((x) & GENMASK(25, 25)) >> 25)

#define TZAESBNS_TZAESB_MR_CMTYP1(x)             (((x) << 24) & GENMASK(24, 24))
#define TZAESBNS_TZAESB_MR_CMTYP1_M              GENMASK(24, 24)
#define TZAESBNS_TZAESB_MR_CMTYP1_X(x)           (((x) & GENMASK(24, 24)) >> 24)

#define TZAESBNS_TZAESB_MR_CKEY(x)               (((x) << 20) & GENMASK(23, 20))
#define TZAESBNS_TZAESB_MR_CKEY_M                GENMASK(23, 20)
#define TZAESBNS_TZAESB_MR_CKEY_X(x)             (((x) & GENMASK(23, 20)) >> 20)

#define TZAESBNS_TZAESB_MR_OPMOD(x)              (((x) << 12) & GENMASK(14, 12))
#define TZAESBNS_TZAESB_MR_OPMOD_M               GENMASK(14, 12)
#define TZAESBNS_TZAESB_MR_OPMOD_X(x)            (((x) & GENMASK(14, 12)) >> 12)

#define TZAESBNS_TZAESB_MR_PROCDLY(x)            (((x) << 4) & GENMASK(7, 4))
#define TZAESBNS_TZAESB_MR_PROCDLY_M             GENMASK(7, 4)
#define TZAESBNS_TZAESB_MR_PROCDLY_X(x)          (((x) & GENMASK(7, 4)) >> 4)

#define TZAESBNS_TZAESB_MR_DUALBUFF(x)           (((x) << 3) & GENMASK(3, 3))
#define TZAESBNS_TZAESB_MR_DUALBUFF_M            GENMASK(3, 3)
#define TZAESBNS_TZAESB_MR_DUALBUFF_X(x)         (((x) & GENMASK(3, 3)) >> 3)

#define TZAESBNS_TZAESB_MR_AAHB(x)               (((x) << 2) & GENMASK(2, 2))
#define TZAESBNS_TZAESB_MR_AAHB_M                GENMASK(2, 2)
#define TZAESBNS_TZAESB_MR_AAHB_X(x)             (((x) & GENMASK(2, 2)) >> 2)

/*      TZAESBNS:TZAESB_REGS:TZAESB_IER */
#define TZAESBNS_TZAESB_IER(t)    (t + 0x10)

#define TZAESBNS_TZAESB_IER_SECE(x)              (((x) << 19) & GENMASK(19, 19))
#define TZAESBNS_TZAESB_IER_SECE_M               GENMASK(19, 19)
#define TZAESBNS_TZAESB_IER_SECE_X(x)            (((x) & GENMASK(19, 19)) >> 19)

#define TZAESBNS_TZAESB_IER_URAD(x)              (((x) << 8) & GENMASK(8, 8))
#define TZAESBNS_TZAESB_IER_URAD_M               GENMASK(8, 8)
#define TZAESBNS_TZAESB_IER_URAD_X(x)            (((x) & GENMASK(8, 8)) >> 8)

/*      TZAESBNS:TZAESB_REGS:TZAESB_IDR */
#define TZAESBNS_TZAESB_IDR(t)    (t + 0x14)

#define TZAESBNS_TZAESB_IDR_SECE_IDR(x)          (((x) << 19) & GENMASK(19, 19))
#define TZAESBNS_TZAESB_IDR_SECE_IDR_M           GENMASK(19, 19)
#define TZAESBNS_TZAESB_IDR_SECE_IDR_X(x)        (((x) & GENMASK(19, 19)) >> 19)

#define TZAESBNS_TZAESB_IDR_URAD_IDR(x)          (((x) << 8) & GENMASK(8, 8))
#define TZAESBNS_TZAESB_IDR_URAD_IDR_M           GENMASK(8, 8)
#define TZAESBNS_TZAESB_IDR_URAD_IDR_X(x)        (((x) & GENMASK(8, 8)) >> 8)

/*      TZAESBNS:TZAESB_REGS:TZAESB_IMR */
#define TZAESBNS_TZAESB_IMR(t)    (t + 0x18)

#define TZAESBNS_TZAESB_IMR_SECE_IMR(x)          (((x) << 19) & GENMASK(19, 19))
#define TZAESBNS_TZAESB_IMR_SECE_IMR_M           GENMASK(19, 19)
#define TZAESBNS_TZAESB_IMR_SECE_IMR_X(x)        (((x) & GENMASK(19, 19)) >> 19)

#define TZAESBNS_TZAESB_IMR_URAD_IMR(x)          (((x) << 8) & GENMASK(8, 8))
#define TZAESBNS_TZAESB_IMR_URAD_IMR_M           GENMASK(8, 8)
#define TZAESBNS_TZAESB_IMR_URAD_IMR_X(x)        (((x) & GENMASK(8, 8)) >> 8)

/*      TZAESBNS:TZAESB_REGS:TZAESB_ISR */
#define TZAESBNS_TZAESB_ISR(t)    (t + 0x1c)

#define TZAESBNS_TZAESB_ISR_SECE_ISR(x)          (((x) << 19) & GENMASK(19, 19))
#define TZAESBNS_TZAESB_ISR_SECE_ISR_M           GENMASK(19, 19)
#define TZAESBNS_TZAESB_ISR_SECE_ISR_X(x)        (((x) & GENMASK(19, 19)) >> 19)

#define TZAESBNS_TZAESB_ISR_URAT_ISR(x)          (((x) << 12) & GENMASK(15, 12))
#define TZAESBNS_TZAESB_ISR_URAT_ISR_M           GENMASK(15, 12)
#define TZAESBNS_TZAESB_ISR_URAT_ISR_X(x)        (((x) & GENMASK(15, 12)) >> 12)

#define TZAESBNS_TZAESB_ISR_URAD_ISR(x)          (((x) << 8) & GENMASK(8, 8))
#define TZAESBNS_TZAESB_ISR_URAD_ISR_M           GENMASK(8, 8)
#define TZAESBNS_TZAESB_ISR_URAD_ISR_X(x)        (((x) & GENMASK(8, 8)) >> 8)

/*      TZAESBNS:TZAESB_REGS:TZAESB_KEYWR0 */
#define TZAESBNS_TZAESB_KEYWR0(t) (t + 0x20)

/*      TZAESBNS:TZAESB_REGS:TZAESB_KEYWR1 */
#define TZAESBNS_TZAESB_KEYWR1(t) (t + 0x24)

/*      TZAESBNS:TZAESB_REGS:TZAESB_KEYWR2 */
#define TZAESBNS_TZAESB_KEYWR2(t) (t + 0x28)

/*      TZAESBNS:TZAESB_REGS:TZAESB_KEYWR3 */
#define TZAESBNS_TZAESB_KEYWR3(t) (t + 0x2c)

/*      TZAESBNS:TZAESB_REGS:TZAESB_IVR0 */
#define TZAESBNS_TZAESB_IVR0(t)   (t + 0x60)

/*      TZAESBNS:TZAESB_REGS:TZAESB_IVR1 */
#define TZAESBNS_TZAESB_IVR1(t)   (t + 0x64)

/*      TZAESBNS:TZAESB_REGS:TZAESB_IVR2 */
#define TZAESBNS_TZAESB_IVR2(t)   (t + 0x68)

/*      TZAESBNS:TZAESB_REGS:TZAESB_IVR3 */
#define TZAESBNS_TZAESB_IVR3(t)   (t + 0x6c)

/*      TZAESBNS:TZAESB_REGS:TZAESB_EMR */
#define TZAESBNS_TZAESB_EMR(t)    (t + 0xb0)

#define TZAESBNS_TZAESB_EMR_PKRS(x)              (((x) << 7) & GENMASK(7, 7))
#define TZAESBNS_TZAESB_EMR_PKRS_M               GENMASK(7, 7)
#define TZAESBNS_TZAESB_EMR_PKRS_X(x)            (((x) & GENMASK(7, 7)) >> 7)

#define TZAESBNS_TZAESB_EMR_PKWO(x)              (((x) << 6) & GENMASK(6, 6))
#define TZAESBNS_TZAESB_EMR_PKWO_M               GENMASK(6, 6)
#define TZAESBNS_TZAESB_EMR_PKWO_X(x)            (((x) & GENMASK(6, 6)) >> 6)

/*      TZAESBNS:TZAESB_REGS:TZAESB_WPMR */
#define TZAESBNS_TZAESB_WPMR(t)   (t + 0xe4)

#define TZAESBNS_TZAESB_WPMR_WPKEY(x)            (((x) << 8) & GENMASK(31, 8))
#define TZAESBNS_TZAESB_WPMR_WPKEY_M             GENMASK(31, 8)
#define TZAESBNS_TZAESB_WPMR_WPKEY_X(x)          (((x) & GENMASK(31, 8)) >> 8)

#define TZAESBNS_TZAESB_WPMR_ACTION(x)           (((x) << 5) & GENMASK(7, 5))
#define TZAESBNS_TZAESB_WPMR_ACTION_M            GENMASK(7, 5)
#define TZAESBNS_TZAESB_WPMR_ACTION_X(x)         (((x) & GENMASK(7, 5)) >> 5)

#define TZAESBNS_TZAESB_WPMR_FIRSTE(x)           (((x) << 4) & GENMASK(4, 4))
#define TZAESBNS_TZAESB_WPMR_FIRSTE_M            GENMASK(4, 4)
#define TZAESBNS_TZAESB_WPMR_FIRSTE_X(x)         (((x) & GENMASK(4, 4)) >> 4)

#define TZAESBNS_TZAESB_WPMR_WPCREN(x)           (((x) << 2) & GENMASK(2, 2))
#define TZAESBNS_TZAESB_WPMR_WPCREN_M            GENMASK(2, 2)
#define TZAESBNS_TZAESB_WPMR_WPCREN_X(x)         (((x) & GENMASK(2, 2)) >> 2)

#define TZAESBNS_TZAESB_WPMR_WPITEN(x)           (((x) << 1) & GENMASK(1, 1))
#define TZAESBNS_TZAESB_WPMR_WPITEN_M            GENMASK(1, 1)
#define TZAESBNS_TZAESB_WPMR_WPITEN_X(x)         (((x) & GENMASK(1, 1)) >> 1)

#define TZAESBNS_TZAESB_WPMR_WPEN(x)             ((x) & GENMASK(0, 0))
#define TZAESBNS_TZAESB_WPMR_WPEN_M              GENMASK(0, 0)
#define TZAESBNS_TZAESB_WPMR_WPEN_X(x)           ((x) & GENMASK(0, 0))

/*      TZAESBNS:TZAESB_REGS:TZAESB_WPSR */
#define TZAESBNS_TZAESB_WPSR(t)   (t + 0xe8)

#define TZAESBNS_TZAESB_WPSR_ECLASS(x)           (((x) << 31) & GENMASK(31, 31))
#define TZAESBNS_TZAESB_WPSR_ECLASS_M            GENMASK(31, 31)
#define TZAESBNS_TZAESB_WPSR_ECLASS_X(x)         (((x) & GENMASK(31, 31)) >> 31)

#define TZAESBNS_TZAESB_WPSR_SWETYP(x)           (((x) << 24) & GENMASK(27, 24))
#define TZAESBNS_TZAESB_WPSR_SWETYP_M            GENMASK(27, 24)
#define TZAESBNS_TZAESB_WPSR_SWETYP_X(x)         (((x) & GENMASK(27, 24)) >> 24)

#define TZAESBNS_TZAESB_WPSR_WPVSRC(x)           (((x) << 8) & GENMASK(15, 8))
#define TZAESBNS_TZAESB_WPSR_WPVSRC_M            GENMASK(15, 8)
#define TZAESBNS_TZAESB_WPSR_WPVSRC_X(x)         (((x) & GENMASK(15, 8)) >> 8)

#define TZAESBNS_TZAESB_WPSR_PKRPVS(x)           (((x) << 4) & GENMASK(4, 4))
#define TZAESBNS_TZAESB_WPSR_PKRPVS_M            GENMASK(4, 4)
#define TZAESBNS_TZAESB_WPSR_PKRPVS_X(x)         (((x) & GENMASK(4, 4)) >> 4)

#define TZAESBNS_TZAESB_WPSR_SWE(x)              (((x) << 3) & GENMASK(3, 3))
#define TZAESBNS_TZAESB_WPSR_SWE_M               GENMASK(3, 3)
#define TZAESBNS_TZAESB_WPSR_SWE_X(x)            (((x) & GENMASK(3, 3)) >> 3)

#define TZAESBNS_TZAESB_WPSR_SEQE(x)             (((x) << 2) & GENMASK(2, 2))
#define TZAESBNS_TZAESB_WPSR_SEQE_M              GENMASK(2, 2)
#define TZAESBNS_TZAESB_WPSR_SEQE_X(x)           (((x) & GENMASK(2, 2)) >> 2)

#define TZAESBNS_TZAESB_WPSR_CGD(x)              (((x) << 1) & GENMASK(1, 1))
#define TZAESBNS_TZAESB_WPSR_CGD_M               GENMASK(1, 1)
#define TZAESBNS_TZAESB_WPSR_CGD_X(x)            (((x) & GENMASK(1, 1)) >> 1)

#define TZAESBNS_TZAESB_WPSR_WPVS(x)             ((x) & GENMASK(0, 0))
#define TZAESBNS_TZAESB_WPSR_WPVS_M              GENMASK(0, 0)
#define TZAESBNS_TZAESB_WPSR_WPVS_X(x)           ((x) & GENMASK(0, 0))

/*      TZAESBNS:TZAESB_REGS:TZAESB_VERSION */
#define TZAESBNS_TZAESB_VERSION(t) (t + 0xfc)

#define TZAESBNS_TZAESB_VERSION_MFN(x)           (((x) << 16) & GENMASK(18, 16))
#define TZAESBNS_TZAESB_VERSION_MFN_M            GENMASK(18, 16)
#define TZAESBNS_TZAESB_VERSION_MFN_X(x)         (((x) & GENMASK(18, 16)) >> 16)

#define TZAESBNS_TZAESB_VERSION_VERSION(x)       ((x) & GENMASK(11, 0))
#define TZAESBNS_TZAESB_VERSION_VERSION_M        GENMASK(11, 0)
#define TZAESBNS_TZAESB_VERSION_VERSION_X(x)     ((x) & GENMASK(11, 0))

/*      TZAESBS:TZAESB_REGS:TZAESB_CR */
#define TZAESBS_TZAESB_CR(t)      (t + 0x00)

#define TZAESBS_TZAESB_CR_UNLOCK(x)              (((x) << 24) & GENMASK(24, 24))
#define TZAESBS_TZAESB_CR_UNLOCK_M               GENMASK(24, 24)
#define TZAESBS_TZAESB_CR_UNLOCK_X(x)            (((x) & GENMASK(24, 24)) >> 24)

#define TZAESBS_TZAESB_CR_LOADSEED(x)            (((x) << 16) & GENMASK(16, 16))
#define TZAESBS_TZAESB_CR_LOADSEED_M             GENMASK(16, 16)
#define TZAESBS_TZAESB_CR_LOADSEED_X(x)          (((x) & GENMASK(16, 16)) >> 16)

#define TZAESBS_TZAESB_CR_SWRST(x)               (((x) << 8) & GENMASK(8, 8))
#define TZAESBS_TZAESB_CR_SWRST_M                GENMASK(8, 8)
#define TZAESBS_TZAESB_CR_SWRST_X(x)             (((x) & GENMASK(8, 8)) >> 8)

#define TZAESBS_TZAESB_CR_START(x)               ((x) & GENMASK(0, 0))
#define TZAESBS_TZAESB_CR_START_M                GENMASK(0, 0)
#define TZAESBS_TZAESB_CR_START_X(x)             ((x) & GENMASK(0, 0))

/*      TZAESBS:TZAESB_REGS:TZAESB_MR */
#define TZAESBS_TZAESB_MR(t)      (t + 0x04)

#define TZAESBS_TZAESB_MR_TAMPCLR(x)             (((x) << 31) & GENMASK(31, 31))
#define TZAESBS_TZAESB_MR_TAMPCLR_M              GENMASK(31, 31)
#define TZAESBS_TZAESB_MR_TAMPCLR_X(x)           (((x) & GENMASK(31, 31)) >> 31)

#define TZAESBS_TZAESB_MR_CMTYP7(x)              (((x) << 30) & GENMASK(30, 30))
#define TZAESBS_TZAESB_MR_CMTYP7_M               GENMASK(30, 30)
#define TZAESBS_TZAESB_MR_CMTYP7_X(x)            (((x) & GENMASK(30, 30)) >> 30)

#define TZAESBS_TZAESB_MR_CMTYP6(x)              (((x) << 29) & GENMASK(29, 29))
#define TZAESBS_TZAESB_MR_CMTYP6_M               GENMASK(29, 29)
#define TZAESBS_TZAESB_MR_CMTYP6_X(x)            (((x) & GENMASK(29, 29)) >> 29)

#define TZAESBS_TZAESB_MR_CMTYP5(x)              (((x) << 28) & GENMASK(28, 28))
#define TZAESBS_TZAESB_MR_CMTYP5_M               GENMASK(28, 28)
#define TZAESBS_TZAESB_MR_CMTYP5_X(x)            (((x) & GENMASK(28, 28)) >> 28)

#define TZAESBS_TZAESB_MR_CMTYP4(x)              (((x) << 27) & GENMASK(27, 27))
#define TZAESBS_TZAESB_MR_CMTYP4_M               GENMASK(27, 27)
#define TZAESBS_TZAESB_MR_CMTYP4_X(x)            (((x) & GENMASK(27, 27)) >> 27)

#define TZAESBS_TZAESB_MR_CMTYP3(x)              (((x) << 26) & GENMASK(26, 26))
#define TZAESBS_TZAESB_MR_CMTYP3_M               GENMASK(26, 26)
#define TZAESBS_TZAESB_MR_CMTYP3_X(x)            (((x) & GENMASK(26, 26)) >> 26)

#define TZAESBS_TZAESB_MR_CMTYP2(x)              (((x) << 25) & GENMASK(25, 25))
#define TZAESBS_TZAESB_MR_CMTYP2_M               GENMASK(25, 25)
#define TZAESBS_TZAESB_MR_CMTYP2_X(x)            (((x) & GENMASK(25, 25)) >> 25)

#define TZAESBS_TZAESB_MR_CMTYP1(x)              (((x) << 24) & GENMASK(24, 24))
#define TZAESBS_TZAESB_MR_CMTYP1_M               GENMASK(24, 24)
#define TZAESBS_TZAESB_MR_CMTYP1_X(x)            (((x) & GENMASK(24, 24)) >> 24)

#define TZAESBS_TZAESB_MR_CKEY(x)                (((x) << 20) & GENMASK(23, 20))
#define TZAESBS_TZAESB_MR_CKEY_M                 GENMASK(23, 20)
#define TZAESBS_TZAESB_MR_CKEY_X(x)              (((x) & GENMASK(23, 20)) >> 20)

#define TZAESBS_TZAESB_MR_OPMOD(x)               (((x) << 12) & GENMASK(14, 12))
#define TZAESBS_TZAESB_MR_OPMOD_M                GENMASK(14, 12)
#define TZAESBS_TZAESB_MR_OPMOD_X(x)             (((x) & GENMASK(14, 12)) >> 12)

#define TZAESBS_TZAESB_MR_PROCDLY(x)             (((x) << 4) & GENMASK(7, 4))
#define TZAESBS_TZAESB_MR_PROCDLY_M              GENMASK(7, 4)
#define TZAESBS_TZAESB_MR_PROCDLY_X(x)           (((x) & GENMASK(7, 4)) >> 4)

#define TZAESBS_TZAESB_MR_DUALBUFF(x)            (((x) << 3) & GENMASK(3, 3))
#define TZAESBS_TZAESB_MR_DUALBUFF_M             GENMASK(3, 3)
#define TZAESBS_TZAESB_MR_DUALBUFF_X(x)          (((x) & GENMASK(3, 3)) >> 3)

#define TZAESBS_TZAESB_MR_AAHB(x)                (((x) << 2) & GENMASK(2, 2))
#define TZAESBS_TZAESB_MR_AAHB_M                 GENMASK(2, 2)
#define TZAESBS_TZAESB_MR_AAHB_X(x)              (((x) & GENMASK(2, 2)) >> 2)

/*      TZAESBS:TZAESB_REGS:TZAESB_IER */
#define TZAESBS_TZAESB_IER(t)     (t + 0x10)

#define TZAESBS_TZAESB_IER_SECE(x)               (((x) << 19) & GENMASK(19, 19))
#define TZAESBS_TZAESB_IER_SECE_M                GENMASK(19, 19)
#define TZAESBS_TZAESB_IER_SECE_X(x)             (((x) & GENMASK(19, 19)) >> 19)

#define TZAESBS_TZAESB_IER_URAD(x)               (((x) << 8) & GENMASK(8, 8))
#define TZAESBS_TZAESB_IER_URAD_M                GENMASK(8, 8)
#define TZAESBS_TZAESB_IER_URAD_X(x)             (((x) & GENMASK(8, 8)) >> 8)

/*      TZAESBS:TZAESB_REGS:TZAESB_IDR */
#define TZAESBS_TZAESB_IDR(t)     (t + 0x14)

#define TZAESBS_TZAESB_IDR_SECE_IDR(x)           (((x) << 19) & GENMASK(19, 19))
#define TZAESBS_TZAESB_IDR_SECE_IDR_M            GENMASK(19, 19)
#define TZAESBS_TZAESB_IDR_SECE_IDR_X(x)         (((x) & GENMASK(19, 19)) >> 19)

#define TZAESBS_TZAESB_IDR_URAD_IDR(x)           (((x) << 8) & GENMASK(8, 8))
#define TZAESBS_TZAESB_IDR_URAD_IDR_M            GENMASK(8, 8)
#define TZAESBS_TZAESB_IDR_URAD_IDR_X(x)         (((x) & GENMASK(8, 8)) >> 8)

/*      TZAESBS:TZAESB_REGS:TZAESB_IMR */
#define TZAESBS_TZAESB_IMR(t)     (t + 0x18)

#define TZAESBS_TZAESB_IMR_SECE_IMR(x)           (((x) << 19) & GENMASK(19, 19))
#define TZAESBS_TZAESB_IMR_SECE_IMR_M            GENMASK(19, 19)
#define TZAESBS_TZAESB_IMR_SECE_IMR_X(x)         (((x) & GENMASK(19, 19)) >> 19)

#define TZAESBS_TZAESB_IMR_URAD_IMR(x)           (((x) << 8) & GENMASK(8, 8))
#define TZAESBS_TZAESB_IMR_URAD_IMR_M            GENMASK(8, 8)
#define TZAESBS_TZAESB_IMR_URAD_IMR_X(x)         (((x) & GENMASK(8, 8)) >> 8)

/*      TZAESBS:TZAESB_REGS:TZAESB_ISR */
#define TZAESBS_TZAESB_ISR(t)     (t + 0x1c)

#define TZAESBS_TZAESB_ISR_SECE_ISR(x)           (((x) << 19) & GENMASK(19, 19))
#define TZAESBS_TZAESB_ISR_SECE_ISR_M            GENMASK(19, 19)
#define TZAESBS_TZAESB_ISR_SECE_ISR_X(x)         (((x) & GENMASK(19, 19)) >> 19)

#define TZAESBS_TZAESB_ISR_URAT_ISR(x)           (((x) << 12) & GENMASK(15, 12))
#define TZAESBS_TZAESB_ISR_URAT_ISR_M            GENMASK(15, 12)
#define TZAESBS_TZAESB_ISR_URAT_ISR_X(x)         (((x) & GENMASK(15, 12)) >> 12)

#define TZAESBS_TZAESB_ISR_URAD_ISR(x)           (((x) << 8) & GENMASK(8, 8))
#define TZAESBS_TZAESB_ISR_URAD_ISR_M            GENMASK(8, 8)
#define TZAESBS_TZAESB_ISR_URAD_ISR_X(x)         (((x) & GENMASK(8, 8)) >> 8)

/*      TZAESBS:TZAESB_REGS:TZAESB_KEYWR0 */
#define TZAESBS_TZAESB_KEYWR0(t)  (t + 0x20)

/*      TZAESBS:TZAESB_REGS:TZAESB_KEYWR1 */
#define TZAESBS_TZAESB_KEYWR1(t)  (t + 0x24)

/*      TZAESBS:TZAESB_REGS:TZAESB_KEYWR2 */
#define TZAESBS_TZAESB_KEYWR2(t)  (t + 0x28)

/*      TZAESBS:TZAESB_REGS:TZAESB_KEYWR3 */
#define TZAESBS_TZAESB_KEYWR3(t)  (t + 0x2c)

/*      TZAESBS:TZAESB_REGS:TZAESB_IVR0 */
#define TZAESBS_TZAESB_IVR0(t)    (t + 0x60)

/*      TZAESBS:TZAESB_REGS:TZAESB_IVR1 */
#define TZAESBS_TZAESB_IVR1(t)    (t + 0x64)

/*      TZAESBS:TZAESB_REGS:TZAESB_IVR2 */
#define TZAESBS_TZAESB_IVR2(t)    (t + 0x68)

/*      TZAESBS:TZAESB_REGS:TZAESB_IVR3 */
#define TZAESBS_TZAESB_IVR3(t)    (t + 0x6c)

/*      TZAESBS:TZAESB_REGS:TZAESB_EMR */
#define TZAESBS_TZAESB_EMR(t)     (t + 0xb0)

#define TZAESBS_TZAESB_EMR_PKRS(x)               (((x) << 7) & GENMASK(7, 7))
#define TZAESBS_TZAESB_EMR_PKRS_M                GENMASK(7, 7)
#define TZAESBS_TZAESB_EMR_PKRS_X(x)             (((x) & GENMASK(7, 7)) >> 7)

#define TZAESBS_TZAESB_EMR_PKWO(x)               (((x) << 6) & GENMASK(6, 6))
#define TZAESBS_TZAESB_EMR_PKWO_M                GENMASK(6, 6)
#define TZAESBS_TZAESB_EMR_PKWO_X(x)             (((x) & GENMASK(6, 6)) >> 6)

/*      TZAESBS:TZAESB_REGS:TZAESB_WPMR */
#define TZAESBS_TZAESB_WPMR(t)    (t + 0xe4)

#define TZAESBS_TZAESB_WPMR_WPKEY(x)             (((x) << 8) & GENMASK(31, 8))
#define TZAESBS_TZAESB_WPMR_WPKEY_M              GENMASK(31, 8)
#define TZAESBS_TZAESB_WPMR_WPKEY_X(x)           (((x) & GENMASK(31, 8)) >> 8)

#define TZAESBS_TZAESB_WPMR_ACTION(x)            (((x) << 5) & GENMASK(7, 5))
#define TZAESBS_TZAESB_WPMR_ACTION_M             GENMASK(7, 5)
#define TZAESBS_TZAESB_WPMR_ACTION_X(x)          (((x) & GENMASK(7, 5)) >> 5)

#define TZAESBS_TZAESB_WPMR_FIRSTE(x)            (((x) << 4) & GENMASK(4, 4))
#define TZAESBS_TZAESB_WPMR_FIRSTE_M             GENMASK(4, 4)
#define TZAESBS_TZAESB_WPMR_FIRSTE_X(x)          (((x) & GENMASK(4, 4)) >> 4)

#define TZAESBS_TZAESB_WPMR_WPCREN(x)            (((x) << 2) & GENMASK(2, 2))
#define TZAESBS_TZAESB_WPMR_WPCREN_M             GENMASK(2, 2)
#define TZAESBS_TZAESB_WPMR_WPCREN_X(x)          (((x) & GENMASK(2, 2)) >> 2)

#define TZAESBS_TZAESB_WPMR_WPITEN(x)            (((x) << 1) & GENMASK(1, 1))
#define TZAESBS_TZAESB_WPMR_WPITEN_M             GENMASK(1, 1)
#define TZAESBS_TZAESB_WPMR_WPITEN_X(x)          (((x) & GENMASK(1, 1)) >> 1)

#define TZAESBS_TZAESB_WPMR_WPEN(x)              ((x) & GENMASK(0, 0))
#define TZAESBS_TZAESB_WPMR_WPEN_M               GENMASK(0, 0)
#define TZAESBS_TZAESB_WPMR_WPEN_X(x)            ((x) & GENMASK(0, 0))

/*      TZAESBS:TZAESB_REGS:TZAESB_WPSR */
#define TZAESBS_TZAESB_WPSR(t)    (t + 0xe8)

#define TZAESBS_TZAESB_WPSR_ECLASS(x)            (((x) << 31) & GENMASK(31, 31))
#define TZAESBS_TZAESB_WPSR_ECLASS_M             GENMASK(31, 31)
#define TZAESBS_TZAESB_WPSR_ECLASS_X(x)          (((x) & GENMASK(31, 31)) >> 31)

#define TZAESBS_TZAESB_WPSR_SWETYP(x)            (((x) << 24) & GENMASK(27, 24))
#define TZAESBS_TZAESB_WPSR_SWETYP_M             GENMASK(27, 24)
#define TZAESBS_TZAESB_WPSR_SWETYP_X(x)          (((x) & GENMASK(27, 24)) >> 24)

#define TZAESBS_TZAESB_WPSR_WPVSRC(x)            (((x) << 8) & GENMASK(15, 8))
#define TZAESBS_TZAESB_WPSR_WPVSRC_M             GENMASK(15, 8)
#define TZAESBS_TZAESB_WPSR_WPVSRC_X(x)          (((x) & GENMASK(15, 8)) >> 8)

#define TZAESBS_TZAESB_WPSR_PKRPVS(x)            (((x) << 4) & GENMASK(4, 4))
#define TZAESBS_TZAESB_WPSR_PKRPVS_M             GENMASK(4, 4)
#define TZAESBS_TZAESB_WPSR_PKRPVS_X(x)          (((x) & GENMASK(4, 4)) >> 4)

#define TZAESBS_TZAESB_WPSR_SWE(x)               (((x) << 3) & GENMASK(3, 3))
#define TZAESBS_TZAESB_WPSR_SWE_M                GENMASK(3, 3)
#define TZAESBS_TZAESB_WPSR_SWE_X(x)             (((x) & GENMASK(3, 3)) >> 3)

#define TZAESBS_TZAESB_WPSR_SEQE(x)              (((x) << 2) & GENMASK(2, 2))
#define TZAESBS_TZAESB_WPSR_SEQE_M               GENMASK(2, 2)
#define TZAESBS_TZAESB_WPSR_SEQE_X(x)            (((x) & GENMASK(2, 2)) >> 2)

#define TZAESBS_TZAESB_WPSR_CGD(x)               (((x) << 1) & GENMASK(1, 1))
#define TZAESBS_TZAESB_WPSR_CGD_M                GENMASK(1, 1)
#define TZAESBS_TZAESB_WPSR_CGD_X(x)             (((x) & GENMASK(1, 1)) >> 1)

#define TZAESBS_TZAESB_WPSR_WPVS(x)              ((x) & GENMASK(0, 0))
#define TZAESBS_TZAESB_WPSR_WPVS_M               GENMASK(0, 0)
#define TZAESBS_TZAESB_WPSR_WPVS_X(x)            ((x) & GENMASK(0, 0))

/*      TZAESBS:TZAESB_REGS:TZAESB_VERSION */
#define TZAESBS_TZAESB_VERSION(t) (t + 0xfc)

#define TZAESBS_TZAESB_VERSION_MFN(x)            (((x) << 16) & GENMASK(18, 16))
#define TZAESBS_TZAESB_VERSION_MFN_M             GENMASK(18, 16)
#define TZAESBS_TZAESB_VERSION_MFN_X(x)          (((x) & GENMASK(18, 16)) >> 16)

#define TZAESBS_TZAESB_VERSION_VERSION(x)        ((x) & GENMASK(11, 0))
#define TZAESBS_TZAESB_VERSION_VERSION_M         GENMASK(11, 0)
#define TZAESBS_TZAESB_VERSION_VERSION_X(x)      ((x) & GENMASK(11, 0))

/*      TZPM:TZPM_REGS:TZPM_EN */
#define TZPM_TZPM_EN(t)           (t + 0x00)

#define TZPM_TZPM_EN_TZPM_EN(x)                  ((x) & GENMASK(0, 0))
#define TZPM_TZPM_EN_TZPM_EN_M                   GENMASK(0, 0)
#define TZPM_TZPM_EN_TZPM_EN_X(x)                ((x) & GENMASK(0, 0))

/*      TZPM:TZPM_REGS:TZPM_KEY */
#define TZPM_TZPM_KEY(t)          (t + 0x04)

/*      TZPM:TZPM_REGS:TZPCTL0 */
#define TZPM_TZPCTL0(t)           (t + 0x08)

#define TZPM_TZPCTL0_QSPI2(x)                    (((x) << 13) & GENMASK(13, 13))
#define TZPM_TZPCTL0_QSPI2_M                     GENMASK(13, 13)
#define TZPM_TZPCTL0_QSPI2_X(x)                  (((x) & GENMASK(13, 13)) >> 13)

#define TZPM_TZPCTL0_SDMMC(x)                    (((x) << 12) & GENMASK(12, 12))
#define TZPM_TZPCTL0_SDMMC_M                     GENMASK(12, 12)
#define TZPM_TZPCTL0_SDMMC_X(x)                  (((x) & GENMASK(12, 12)) >> 12)

#define TZPM_TZPCTL0_TC1(x)                      (((x) << 9) & GENMASK(9, 9))
#define TZPM_TZPCTL0_TC1_M                       GENMASK(9, 9)
#define TZPM_TZPCTL0_TC1_X(x)                    (((x) & GENMASK(9, 9)) >> 9)

#define TZPM_TZPCTL0_MCAN1(x)                    (((x) << 8) & GENMASK(8, 8))
#define TZPM_TZPCTL0_MCAN1_M                     GENMASK(8, 8)
#define TZPM_TZPCTL0_MCAN1_X(x)                  (((x) & GENMASK(8, 8)) >> 8)

#define TZPM_TZPCTL0_MCAN0(x)                    (((x) << 7) & GENMASK(7, 7))
#define TZPM_TZPCTL0_MCAN0_M                     GENMASK(7, 7)
#define TZPM_TZPCTL0_MCAN0_X(x)                  (((x) & GENMASK(7, 7)) >> 7)

#define TZPM_TZPCTL0_TZAESBS(x)                  (((x) << 6) & GENMASK(6, 6))
#define TZPM_TZPCTL0_TZAESBS_M                   GENMASK(6, 6)
#define TZPM_TZPCTL0_TZAESBS_X(x)                (((x) & GENMASK(6, 6)) >> 6)

#define TZPM_TZPCTL0_TZAESBNS(x)                 (((x) << 5) & GENMASK(5, 5))
#define TZPM_TZPCTL0_TZAESBNS_M                  GENMASK(5, 5)
#define TZPM_TZPCTL0_TZAESBNS_X(x)               (((x) & GENMASK(5, 5)) >> 5)

#define TZPM_TZPCTL0_ICM(x)                      (((x) << 4) & GENMASK(4, 4))
#define TZPM_TZPCTL0_ICM_M                       GENMASK(4, 4)
#define TZPM_TZPCTL0_ICM_X(x)                    (((x) & GENMASK(4, 4)) >> 4)

#define TZPM_TZPCTL0_UDPHS0(x)                   (((x) << 2) & GENMASK(2, 2))
#define TZPM_TZPCTL0_UDPHS0_M                    GENMASK(2, 2)
#define TZPM_TZPCTL0_UDPHS0_X(x)                 (((x) & GENMASK(2, 2)) >> 2)

#define TZPM_TZPCTL0_QSPI0(x)                    (((x) << 1) & GENMASK(1, 1))
#define TZPM_TZPCTL0_QSPI0_M                     GENMASK(1, 1)
#define TZPM_TZPCTL0_QSPI0_X(x)                  (((x) & GENMASK(1, 1)) >> 1)

#define TZPM_TZPCTL0_HMATRIX(x)                  ((x) & GENMASK(0, 0))
#define TZPM_TZPCTL0_HMATRIX_M                   GENMASK(0, 0)
#define TZPM_TZPCTL0_HMATRIX_X(x)                ((x) & GENMASK(0, 0))

/*      TZPM:TZPM_REGS:TZPCTL1 */
#define TZPM_TZPCTL1(t)           (t + 0x0c)

#define TZPM_TZPCTL1_FLEXCOM4(x)                 (((x) << 20) & GENMASK(20, 20))
#define TZPM_TZPCTL1_FLEXCOM4_M                  GENMASK(20, 20)
#define TZPM_TZPCTL1_FLEXCOM4_X(x)               (((x) & GENMASK(20, 20)) >> 20)

#define TZPM_TZPCTL1_SHA(x)                      (((x) << 19) & GENMASK(19, 19))
#define TZPM_TZPCTL1_SHA_M                       GENMASK(19, 19)
#define TZPM_TZPCTL1_SHA_X(x)                    (((x) & GENMASK(19, 19)) >> 19)

#define TZPM_TZPCTL1_XDMA(x)                     (((x) << 18) & GENMASK(18, 18))
#define TZPM_TZPCTL1_XDMA_M                      GENMASK(18, 18)
#define TZPM_TZPCTL1_XDMA_X(x)                   (((x) & GENMASK(18, 18)) >> 18)

#define TZPM_TZPCTL1_FLEXCOM3(x)                 (((x) << 17) & GENMASK(17, 17))
#define TZPM_TZPCTL1_FLEXCOM3_M                  GENMASK(17, 17)
#define TZPM_TZPCTL1_FLEXCOM3_X(x)               (((x) & GENMASK(17, 17)) >> 17)

#define TZPM_TZPCTL1_FLEXCOM2(x)                 (((x) << 16) & GENMASK(16, 16))
#define TZPM_TZPCTL1_FLEXCOM2_M                  GENMASK(16, 16)
#define TZPM_TZPCTL1_FLEXCOM2_X(x)               (((x) & GENMASK(16, 16)) >> 16)

#define TZPM_TZPCTL1_QSPI1(x)                    (((x) << 5) & GENMASK(5, 5))
#define TZPM_TZPCTL1_QSPI1_M                     GENMASK(5, 5)
#define TZPM_TZPCTL1_QSPI1_X(x)                  (((x) & GENMASK(5, 5)) >> 5)

#define TZPM_TZPCTL1_AESB_ASC(x)                 (((x) << 4) & GENMASK(4, 4))
#define TZPM_TZPCTL1_AESB_ASC_M                  GENMASK(4, 4)
#define TZPM_TZPCTL1_AESB_ASC_X(x)               (((x) & GENMASK(4, 4)) >> 4)

#define TZPM_TZPCTL1_AES(x)                      (((x) << 3) & GENMASK(3, 3))
#define TZPM_TZPCTL1_AES_M                       GENMASK(3, 3)
#define TZPM_TZPCTL1_AES_X(x)                    (((x) & GENMASK(3, 3)) >> 3)

#define TZPM_TZPCTL1_TRNG(x)                     (((x) << 2) & GENMASK(2, 2))
#define TZPM_TZPCTL1_TRNG_M                      GENMASK(2, 2)
#define TZPM_TZPCTL1_TRNG_X(x)                   (((x) & GENMASK(2, 2)) >> 2)

#define TZPM_TZPCTL1_FLEXCOM1(x)                 (((x) << 1) & GENMASK(1, 1))
#define TZPM_TZPCTL1_FLEXCOM1_M                  GENMASK(1, 1)
#define TZPM_TZPCTL1_FLEXCOM1_X(x)               (((x) & GENMASK(1, 1)) >> 1)

#define TZPM_TZPCTL1_FLEXCOM0(x)                 ((x) & GENMASK(0, 0))
#define TZPM_TZPCTL1_FLEXCOM0_M                  GENMASK(0, 0)
#define TZPM_TZPCTL1_FLEXCOM0_X(x)               ((x) & GENMASK(0, 0))

/*      TZPM:TZPM_REGS:TZPCTL2 */
#define TZPM_TZPCTL2(t)           (t + 0x10)

#define TZPM_TZPCTL2_TZPM(x)                     (((x) << 1) & GENMASK(1, 1))
#define TZPM_TZPCTL2_TZPM_M                      GENMASK(1, 1)
#define TZPM_TZPCTL2_TZPM_X(x)                   (((x) & GENMASK(1, 1)) >> 1)

#define TZPM_TZPCTL2_PKCC(x)                     ((x) & GENMASK(0, 0))
#define TZPM_TZPCTL2_PKCC_M                      GENMASK(0, 0)
#define TZPM_TZPCTL2_PKCC_X(x)                   ((x) & GENMASK(0, 0))

/*      TZPM:TZPM_REGS:TZPCTL3 */
#define TZPM_TZPCTL3(t)           (t + 0x14)

#define TZPM_TZPCTL3_PCIE_IB(x)                  (((x) << 27) & GENMASK(27, 27))
#define TZPM_TZPCTL3_PCIE_IB_M                   GENMASK(27, 27)
#define TZPM_TZPCTL3_PCIE_IB_X(x)                (((x) & GENMASK(27, 27)) >> 27)

#define TZPM_TZPCTL3_RTE(x)                      (((x) << 26) & GENMASK(26, 26))
#define TZPM_TZPCTL3_RTE_M                       GENMASK(26, 26)
#define TZPM_TZPCTL3_RTE_X(x)                    (((x) & GENMASK(26, 26)) >> 26)

#define TZPM_TZPCTL3_FDMA(x)                     (((x) << 25) & GENMASK(25, 25))
#define TZPM_TZPCTL3_FDMA_M                      GENMASK(25, 25)
#define TZPM_TZPCTL3_FDMA_X(x)                   (((x) & GENMASK(25, 25)) >> 25)

#define TZPM_TZPCTL3_EXT_INITIATOR(x)            (((x) << 24) & GENMASK(24, 24))
#define TZPM_TZPCTL3_EXT_INITIATOR_M             GENMASK(24, 24)
#define TZPM_TZPCTL3_EXT_INITIATOR_X(x)          (((x) & GENMASK(24, 24)) >> 24)

/*      UDPHS0:UDPHS_REGS:UDPHS_CTRL */
#define UDPHS0_UDPHS_CTRL(t)      (t + 0x00)

#define UDPHS0_UDPHS_CTRL_PULLD_DIS(x)           (((x) << 11) & GENMASK(11, 11))
#define UDPHS0_UDPHS_CTRL_PULLD_DIS_M            GENMASK(11, 11)
#define UDPHS0_UDPHS_CTRL_PULLD_DIS_X(x)         (((x) & GENMASK(11, 11)) >> 11)

#define UDPHS0_UDPHS_CTRL_REWAKEUP(x)            (((x) << 10) & GENMASK(10, 10))
#define UDPHS0_UDPHS_CTRL_REWAKEUP_M             GENMASK(10, 10)
#define UDPHS0_UDPHS_CTRL_REWAKEUP_X(x)          (((x) & GENMASK(10, 10)) >> 10)

#define UDPHS0_UDPHS_CTRL_DETACH(x)              (((x) << 9) & GENMASK(9, 9))
#define UDPHS0_UDPHS_CTRL_DETACH_M               GENMASK(9, 9)
#define UDPHS0_UDPHS_CTRL_DETACH_X(x)            (((x) & GENMASK(9, 9)) >> 9)

#define UDPHS0_UDPHS_CTRL_EN_UDPHS(x)            (((x) << 8) & GENMASK(8, 8))
#define UDPHS0_UDPHS_CTRL_EN_UDPHS_M             GENMASK(8, 8)
#define UDPHS0_UDPHS_CTRL_EN_UDPHS_X(x)          (((x) & GENMASK(8, 8)) >> 8)

#define UDPHS0_UDPHS_CTRL_FADDR_EN(x)            (((x) << 7) & GENMASK(7, 7))
#define UDPHS0_UDPHS_CTRL_FADDR_EN_M             GENMASK(7, 7)
#define UDPHS0_UDPHS_CTRL_FADDR_EN_X(x)          (((x) & GENMASK(7, 7)) >> 7)

#define UDPHS0_UDPHS_CTRL_DEV_ADDR(x)            ((x) & GENMASK(6, 0))
#define UDPHS0_UDPHS_CTRL_DEV_ADDR_M             GENMASK(6, 0)
#define UDPHS0_UDPHS_CTRL_DEV_ADDR_X(x)          ((x) & GENMASK(6, 0))

/*      UDPHS0:UDPHS_REGS:UDPHS_IEN */
#define UDPHS0_UDPHS_IEN(t)       (t + 0x10)

#define UDPHS0_UDPHS_IEN_DMA(x)                  (((x) << 25) & GENMASK(31, 25))
#define UDPHS0_UDPHS_IEN_DMA_M                   GENMASK(31, 25)
#define UDPHS0_UDPHS_IEN_DMA_X(x)                (((x) & GENMASK(31, 25)) >> 25)

#define UDPHS0_UDPHS_IEN_EPT(x)                  (((x) << 8) & GENMASK(23, 8))
#define UDPHS0_UDPHS_IEN_EPT_M                   GENMASK(23, 8)
#define UDPHS0_UDPHS_IEN_EPT_X(x)                (((x) & GENMASK(23, 8)) >> 8)

#define UDPHS0_UDPHS_IEN_UPSTR_RES(x)            (((x) << 7) & GENMASK(7, 7))
#define UDPHS0_UDPHS_IEN_UPSTR_RES_M             GENMASK(7, 7)
#define UDPHS0_UDPHS_IEN_UPSTR_RES_X(x)          (((x) & GENMASK(7, 7)) >> 7)

#define UDPHS0_UDPHS_IEN_ENDOFRSM(x)             (((x) << 6) & GENMASK(6, 6))
#define UDPHS0_UDPHS_IEN_ENDOFRSM_M              GENMASK(6, 6)
#define UDPHS0_UDPHS_IEN_ENDOFRSM_X(x)           (((x) & GENMASK(6, 6)) >> 6)

#define UDPHS0_UDPHS_IEN_WAKE_UP(x)              (((x) << 5) & GENMASK(5, 5))
#define UDPHS0_UDPHS_IEN_WAKE_UP_M               GENMASK(5, 5)
#define UDPHS0_UDPHS_IEN_WAKE_UP_X(x)            (((x) & GENMASK(5, 5)) >> 5)

#define UDPHS0_UDPHS_IEN_ENDRESET(x)             (((x) << 4) & GENMASK(4, 4))
#define UDPHS0_UDPHS_IEN_ENDRESET_M              GENMASK(4, 4)
#define UDPHS0_UDPHS_IEN_ENDRESET_X(x)           (((x) & GENMASK(4, 4)) >> 4)

#define UDPHS0_UDPHS_IEN_INT_SOF(x)              (((x) << 3) & GENMASK(3, 3))
#define UDPHS0_UDPHS_IEN_INT_SOF_M               GENMASK(3, 3)
#define UDPHS0_UDPHS_IEN_INT_SOF_X(x)            (((x) & GENMASK(3, 3)) >> 3)

#define UDPHS0_UDPHS_IEN_MICRO_SOF(x)            (((x) << 2) & GENMASK(2, 2))
#define UDPHS0_UDPHS_IEN_MICRO_SOF_M             GENMASK(2, 2)
#define UDPHS0_UDPHS_IEN_MICRO_SOF_X(x)          (((x) & GENMASK(2, 2)) >> 2)

#define UDPHS0_UDPHS_IEN_DET_SUSPD(x)            (((x) << 1) & GENMASK(1, 1))
#define UDPHS0_UDPHS_IEN_DET_SUSPD_M             GENMASK(1, 1)
#define UDPHS0_UDPHS_IEN_DET_SUSPD_X(x)          (((x) & GENMASK(1, 1)) >> 1)

/*      UDPHS0:UDPHS_REGS:UDPHS_INTSTA */
#define UDPHS0_UDPHS_INTSTA(t)    (t + 0x14)

#define UDPHS0_UDPHS_INTSTA_DMA_INTSTA(x)        (((x) << 25) & GENMASK(31, 25))
#define UDPHS0_UDPHS_INTSTA_DMA_INTSTA_M         GENMASK(31, 25)
#define UDPHS0_UDPHS_INTSTA_DMA_INTSTA_X(x)      (((x) & GENMASK(31, 25)) >> 25)

#define UDPHS0_UDPHS_INTSTA_EPT_INTSTA(x)        (((x) << 8) & GENMASK(23, 8))
#define UDPHS0_UDPHS_INTSTA_EPT_INTSTA_M         GENMASK(23, 8)
#define UDPHS0_UDPHS_INTSTA_EPT_INTSTA_X(x)      (((x) & GENMASK(23, 8)) >> 8)

#define UDPHS0_UDPHS_INTSTA_UPSTR_RES_INTSTA(x)  (((x) << 7) & GENMASK(7, 7))
#define UDPHS0_UDPHS_INTSTA_UPSTR_RES_INTSTA_M   GENMASK(7, 7)
#define UDPHS0_UDPHS_INTSTA_UPSTR_RES_INTSTA_X(x) (((x) & GENMASK(7, 7)) >> 7)

#define UDPHS0_UDPHS_INTSTA_ENDOFRSM_INTSTA(x)   (((x) << 6) & GENMASK(6, 6))
#define UDPHS0_UDPHS_INTSTA_ENDOFRSM_INTSTA_M    GENMASK(6, 6)
#define UDPHS0_UDPHS_INTSTA_ENDOFRSM_INTSTA_X(x) (((x) & GENMASK(6, 6)) >> 6)

#define UDPHS0_UDPHS_INTSTA_WAKE_UP_INTSTA(x)    (((x) << 5) & GENMASK(5, 5))
#define UDPHS0_UDPHS_INTSTA_WAKE_UP_INTSTA_M     GENMASK(5, 5)
#define UDPHS0_UDPHS_INTSTA_WAKE_UP_INTSTA_X(x)  (((x) & GENMASK(5, 5)) >> 5)

#define UDPHS0_UDPHS_INTSTA_ENDRESET_INTSTA(x)   (((x) << 4) & GENMASK(4, 4))
#define UDPHS0_UDPHS_INTSTA_ENDRESET_INTSTA_M    GENMASK(4, 4)
#define UDPHS0_UDPHS_INTSTA_ENDRESET_INTSTA_X(x) (((x) & GENMASK(4, 4)) >> 4)

#define UDPHS0_UDPHS_INTSTA_INT_SOF_INTSTA(x)    (((x) << 3) & GENMASK(3, 3))
#define UDPHS0_UDPHS_INTSTA_INT_SOF_INTSTA_M     GENMASK(3, 3)
#define UDPHS0_UDPHS_INTSTA_INT_SOF_INTSTA_X(x)  (((x) & GENMASK(3, 3)) >> 3)

#define UDPHS0_UDPHS_INTSTA_MICRO_SOF_INTSTA(x)  (((x) << 2) & GENMASK(2, 2))
#define UDPHS0_UDPHS_INTSTA_MICRO_SOF_INTSTA_M   GENMASK(2, 2)
#define UDPHS0_UDPHS_INTSTA_MICRO_SOF_INTSTA_X(x) (((x) & GENMASK(2, 2)) >> 2)

#define UDPHS0_UDPHS_INTSTA_DET_SUSPD_INTSTA(x)  (((x) << 1) & GENMASK(1, 1))
#define UDPHS0_UDPHS_INTSTA_DET_SUSPD_INTSTA_M   GENMASK(1, 1)
#define UDPHS0_UDPHS_INTSTA_DET_SUSPD_INTSTA_X(x) (((x) & GENMASK(1, 1)) >> 1)

#define UDPHS0_UDPHS_INTSTA_SPEED(x)             ((x) & GENMASK(0, 0))
#define UDPHS0_UDPHS_INTSTA_SPEED_M              GENMASK(0, 0)
#define UDPHS0_UDPHS_INTSTA_SPEED_X(x)           ((x) & GENMASK(0, 0))

/*      UDPHS0:UDPHS_REGS:UDPHS_CLRINT */
#define UDPHS0_UDPHS_CLRINT(t)    (t + 0x18)

#define UDPHS0_UDPHS_CLRINT_UPSTR_RES_CLRINT(x)  (((x) << 7) & GENMASK(7, 7))
#define UDPHS0_UDPHS_CLRINT_UPSTR_RES_CLRINT_M   GENMASK(7, 7)
#define UDPHS0_UDPHS_CLRINT_UPSTR_RES_CLRINT_X(x) (((x) & GENMASK(7, 7)) >> 7)

#define UDPHS0_UDPHS_CLRINT_ENDOFRSM_CLRINT(x)   (((x) << 6) & GENMASK(6, 6))
#define UDPHS0_UDPHS_CLRINT_ENDOFRSM_CLRINT_M    GENMASK(6, 6)
#define UDPHS0_UDPHS_CLRINT_ENDOFRSM_CLRINT_X(x) (((x) & GENMASK(6, 6)) >> 6)

#define UDPHS0_UDPHS_CLRINT_WAKE_UP_CLRINT(x)    (((x) << 5) & GENMASK(5, 5))
#define UDPHS0_UDPHS_CLRINT_WAKE_UP_CLRINT_M     GENMASK(5, 5)
#define UDPHS0_UDPHS_CLRINT_WAKE_UP_CLRINT_X(x)  (((x) & GENMASK(5, 5)) >> 5)

#define UDPHS0_UDPHS_CLRINT_ENDRESET_CLRINT(x)   (((x) << 4) & GENMASK(4, 4))
#define UDPHS0_UDPHS_CLRINT_ENDRESET_CLRINT_M    GENMASK(4, 4)
#define UDPHS0_UDPHS_CLRINT_ENDRESET_CLRINT_X(x) (((x) & GENMASK(4, 4)) >> 4)

#define UDPHS0_UDPHS_CLRINT_INT_SOF_CLRINT(x)    (((x) << 3) & GENMASK(3, 3))
#define UDPHS0_UDPHS_CLRINT_INT_SOF_CLRINT_M     GENMASK(3, 3)
#define UDPHS0_UDPHS_CLRINT_INT_SOF_CLRINT_X(x)  (((x) & GENMASK(3, 3)) >> 3)

#define UDPHS0_UDPHS_CLRINT_MICRO_SOF_CLRINT(x)  (((x) << 2) & GENMASK(2, 2))
#define UDPHS0_UDPHS_CLRINT_MICRO_SOF_CLRINT_M   GENMASK(2, 2)
#define UDPHS0_UDPHS_CLRINT_MICRO_SOF_CLRINT_X(x) (((x) & GENMASK(2, 2)) >> 2)

#define UDPHS0_UDPHS_CLRINT_DET_SUSPD_CLRINT(x)  (((x) << 1) & GENMASK(1, 1))
#define UDPHS0_UDPHS_CLRINT_DET_SUSPD_CLRINT_M   GENMASK(1, 1)
#define UDPHS0_UDPHS_CLRINT_DET_SUSPD_CLRINT_X(x) (((x) & GENMASK(1, 1)) >> 1)

/*      UDPHS0:UDPHS_REGS:UDPHS_EPTCFG0 */
#define UDPHS0_UDPHS_EPTCFG0(t)   (t + 0x100)

#define UDPHS0_UDPHS_EPTCFG0_EPT_MAPD_EPTCFG0(x) (((x) << 31) & GENMASK(31, 31))
#define UDPHS0_UDPHS_EPTCFG0_EPT_MAPD_EPTCFG0_M  GENMASK(31, 31)
#define UDPHS0_UDPHS_EPTCFG0_EPT_MAPD_EPTCFG0_X(x)\
	(((x) & GENMASK(31, 31)) >> 31)

#define UDPHS0_UDPHS_EPTCFG0_NB_TRANS_EPTCFG0(x) (((x) << 8) & GENMASK(9, 8))
#define UDPHS0_UDPHS_EPTCFG0_NB_TRANS_EPTCFG0_M  GENMASK(9, 8)
#define UDPHS0_UDPHS_EPTCFG0_NB_TRANS_EPTCFG0_X(x) (((x) & GENMASK(9, 8)) >> 8)

#define UDPHS0_UDPHS_EPTCFG0_BK_NUMBER_EPTCFG0(x) (((x) << 6) & GENMASK(7, 6))
#define UDPHS0_UDPHS_EPTCFG0_BK_NUMBER_EPTCFG0_M GENMASK(7, 6)
#define UDPHS0_UDPHS_EPTCFG0_BK_NUMBER_EPTCFG0_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define UDPHS0_UDPHS_EPTCFG0_EPT_TYPE_EPTCFG0(x) (((x) << 4) & GENMASK(5, 4))
#define UDPHS0_UDPHS_EPTCFG0_EPT_TYPE_EPTCFG0_M  GENMASK(5, 4)
#define UDPHS0_UDPHS_EPTCFG0_EPT_TYPE_EPTCFG0_X(x) (((x) & GENMASK(5, 4)) >> 4)

#define UDPHS0_UDPHS_EPTCFG0_EPT_DIR_EPTCFG0(x)  (((x) << 3) & GENMASK(3, 3))
#define UDPHS0_UDPHS_EPTCFG0_EPT_DIR_EPTCFG0_M   GENMASK(3, 3)
#define UDPHS0_UDPHS_EPTCFG0_EPT_DIR_EPTCFG0_X(x) (((x) & GENMASK(3, 3)) >> 3)

#define UDPHS0_UDPHS_EPTCFG0_EPT_SIZE_EPTCFG0(x) ((x) & GENMASK(2, 0))
#define UDPHS0_UDPHS_EPTCFG0_EPT_SIZE_EPTCFG0_M  GENMASK(2, 0)
#define UDPHS0_UDPHS_EPTCFG0_EPT_SIZE_EPTCFG0_X(x) ((x) & GENMASK(2, 0))

/*      UDPHS0:UDPHS_REGS:UDPHS_EPTCTLENB0 */
#define UDPHS0_UDPHS_EPTCTLENB0(t) (t + 0x104)

#define UDPHS0_UDPHS_EPTCTLENB0_SHRT_PCKT_EPTCTLENB0(x)\
	(((x) << 31) & GENMASK(31, 31))
#define UDPHS0_UDPHS_EPTCTLENB0_SHRT_PCKT_EPTCTLENB0_M GENMASK(31, 31)
#define UDPHS0_UDPHS_EPTCTLENB0_SHRT_PCKT_EPTCTLENB0_X(x)\
	(((x) & GENMASK(31, 31)) >> 31)

#define UDPHS0_UDPHS_EPTCTLENB0_BUSY_BANK_EPTCTLENB0(x)\
	(((x) << 18) & GENMASK(18, 18))
#define UDPHS0_UDPHS_EPTCTLENB0_BUSY_BANK_EPTCTLENB0_M GENMASK(18, 18)
#define UDPHS0_UDPHS_EPTCTLENB0_BUSY_BANK_EPTCTLENB0_X(x)\
	(((x) & GENMASK(18, 18)) >> 18)

#define UDPHS0_UDPHS_EPTCTLENB0_NAK_OUT_EPTCTLENB0(x)\
	(((x) << 15) & GENMASK(15, 15))
#define UDPHS0_UDPHS_EPTCTLENB0_NAK_OUT_EPTCTLENB0_M GENMASK(15, 15)
#define UDPHS0_UDPHS_EPTCTLENB0_NAK_OUT_EPTCTLENB0_X(x)\
	(((x) & GENMASK(15, 15)) >> 15)

#define UDPHS0_UDPHS_EPTCTLENB0_NAK_IN_EPTCTLENB0(x)\
	(((x) << 14) & GENMASK(14, 14))
#define UDPHS0_UDPHS_EPTCTLENB0_NAK_IN_EPTCTLENB0_M GENMASK(14, 14)
#define UDPHS0_UDPHS_EPTCTLENB0_NAK_IN_EPTCTLENB0_X(x)\
	(((x) & GENMASK(14, 14)) >> 14)

#define UDPHS0_UDPHS_EPTCTLENB0_STALL_SNT_EPTCTLENB0(x)\
	(((x) << 13) & GENMASK(13, 13))
#define UDPHS0_UDPHS_EPTCTLENB0_STALL_SNT_EPTCTLENB0_M GENMASK(13, 13)
#define UDPHS0_UDPHS_EPTCTLENB0_STALL_SNT_EPTCTLENB0_X(x)\
	(((x) & GENMASK(13, 13)) >> 13)

#define UDPHS0_UDPHS_EPTCTLENB0_RX_SETUP_EPTCTLENB0(x)\
	(((x) << 12) & GENMASK(12, 12))
#define UDPHS0_UDPHS_EPTCTLENB0_RX_SETUP_EPTCTLENB0_M GENMASK(12, 12)
#define UDPHS0_UDPHS_EPTCTLENB0_RX_SETUP_EPTCTLENB0_X(x)\
	(((x) & GENMASK(12, 12)) >> 12)

#define UDPHS0_UDPHS_EPTCTLENB0_TXRDY_EPTCTLENB0(x)\
	(((x) << 11) & GENMASK(11, 11))
#define UDPHS0_UDPHS_EPTCTLENB0_TXRDY_EPTCTLENB0_M GENMASK(11, 11)
#define UDPHS0_UDPHS_EPTCTLENB0_TXRDY_EPTCTLENB0_X(x)\
	(((x) & GENMASK(11, 11)) >> 11)

#define UDPHS0_UDPHS_EPTCTLENB0_TX_COMPLT_EPTCTLENB0(x)\
	(((x) << 10) & GENMASK(10, 10))
#define UDPHS0_UDPHS_EPTCTLENB0_TX_COMPLT_EPTCTLENB0_M GENMASK(10, 10)
#define UDPHS0_UDPHS_EPTCTLENB0_TX_COMPLT_EPTCTLENB0_X(x)\
	(((x) & GENMASK(10, 10)) >> 10)

#define UDPHS0_UDPHS_EPTCTLENB0_RXRDY_TXKL_EPTCTLENB0(x)\
	(((x) << 9) & GENMASK(9, 9))
#define UDPHS0_UDPHS_EPTCTLENB0_RXRDY_TXKL_EPTCTLENB0_M GENMASK(9, 9)
#define UDPHS0_UDPHS_EPTCTLENB0_RXRDY_TXKL_EPTCTLENB0_X(x)\
	(((x) & GENMASK(9, 9)) >> 9)

#define UDPHS0_UDPHS_EPTCTLENB0_ERR_OVFLW_EPTCTLENB0(x)\
	(((x) << 8) & GENMASK(8, 8))
#define UDPHS0_UDPHS_EPTCTLENB0_ERR_OVFLW_EPTCTLENB0_M GENMASK(8, 8)
#define UDPHS0_UDPHS_EPTCTLENB0_ERR_OVFLW_EPTCTLENB0_X(x)\
	(((x) & GENMASK(8, 8)) >> 8)

#define UDPHS0_UDPHS_EPTCTLENB0_NYET_DIS_EPTCTLENB0(x)\
	(((x) << 4) & GENMASK(4, 4))
#define UDPHS0_UDPHS_EPTCTLENB0_NYET_DIS_EPTCTLENB0_M GENMASK(4, 4)
#define UDPHS0_UDPHS_EPTCTLENB0_NYET_DIS_EPTCTLENB0_X(x)\
	(((x) & GENMASK(4, 4)) >> 4)

#define UDPHS0_UDPHS_EPTCTLENB0_INTDIS_DMA_EPTCTLENB0(x)\
	(((x) << 3) & GENMASK(3, 3))
#define UDPHS0_UDPHS_EPTCTLENB0_INTDIS_DMA_EPTCTLENB0_M GENMASK(3, 3)
#define UDPHS0_UDPHS_EPTCTLENB0_INTDIS_DMA_EPTCTLENB0_X(x)\
	(((x) & GENMASK(3, 3)) >> 3)

#define UDPHS0_UDPHS_EPTCTLENB0_AUTO_VALID_EPTCTLENB0(x)\
	(((x) << 1) & GENMASK(1, 1))
#define UDPHS0_UDPHS_EPTCTLENB0_AUTO_VALID_EPTCTLENB0_M GENMASK(1, 1)
#define UDPHS0_UDPHS_EPTCTLENB0_AUTO_VALID_EPTCTLENB0_X(x)\
	(((x) & GENMASK(1, 1)) >> 1)

#define UDPHS0_UDPHS_EPTCTLENB0_EPT_ENABL_EPTCTLENB0(x) ((x) & GENMASK(0, 0))
#define UDPHS0_UDPHS_EPTCTLENB0_EPT_ENABL_EPTCTLENB0_M GENMASK(0, 0)
#define UDPHS0_UDPHS_EPTCTLENB0_EPT_ENABL_EPTCTLENB0_X(x) ((x) & GENMASK(0, 0))

/*      UDPHS0:UDPHS_REGS:UDPHS_EPTSETSTA0 */
#define UDPHS0_UDPHS_EPTSETSTA0(t) (t + 0x114)

#define UDPHS0_UDPHS_EPTSETSTA0_TXRDY_EPTSETSTA0(x)\
	(((x) << 11) & GENMASK(11, 11))
#define UDPHS0_UDPHS_EPTSETSTA0_TXRDY_EPTSETSTA0_M GENMASK(11, 11)
#define UDPHS0_UDPHS_EPTSETSTA0_TXRDY_EPTSETSTA0_X(x)\
	(((x) & GENMASK(11, 11)) >> 11)

#define UDPHS0_UDPHS_EPTSETSTA0_RXRDY_TXKL_EPTSETSTA0(x)\
	(((x) << 9) & GENMASK(9, 9))
#define UDPHS0_UDPHS_EPTSETSTA0_RXRDY_TXKL_EPTSETSTA0_M GENMASK(9, 9)
#define UDPHS0_UDPHS_EPTSETSTA0_RXRDY_TXKL_EPTSETSTA0_X(x)\
	(((x) & GENMASK(9, 9)) >> 9)

#define UDPHS0_UDPHS_EPTSETSTA0_FRCESTALL_EPTSETSTA0(x)\
	(((x) << 5) & GENMASK(5, 5))
#define UDPHS0_UDPHS_EPTSETSTA0_FRCESTALL_EPTSETSTA0_M GENMASK(5, 5)
#define UDPHS0_UDPHS_EPTSETSTA0_FRCESTALL_EPTSETSTA0_X(x)\
	(((x) & GENMASK(5, 5)) >> 5)

/*      UDPHS0:UDPHS_REGS:UDPHS_EPTCLRSTA0 */
#define UDPHS0_UDPHS_EPTCLRSTA0(t) (t + 0x118)

#define UDPHS0_UDPHS_EPTCLRSTA0_NAK_OUT_EPTCLRSTA0(x)\
	(((x) << 15) & GENMASK(15, 15))
#define UDPHS0_UDPHS_EPTCLRSTA0_NAK_OUT_EPTCLRSTA0_M GENMASK(15, 15)
#define UDPHS0_UDPHS_EPTCLRSTA0_NAK_OUT_EPTCLRSTA0_X(x)\
	(((x) & GENMASK(15, 15)) >> 15)

#define UDPHS0_UDPHS_EPTCLRSTA0_NAK_IN_EPTCLRSTA0(x)\
	(((x) << 14) & GENMASK(14, 14))
#define UDPHS0_UDPHS_EPTCLRSTA0_NAK_IN_EPTCLRSTA0_M GENMASK(14, 14)
#define UDPHS0_UDPHS_EPTCLRSTA0_NAK_IN_EPTCLRSTA0_X(x)\
	(((x) & GENMASK(14, 14)) >> 14)

#define UDPHS0_UDPHS_EPTCLRSTA0_STALL_SNT_EPTCLRSTA0(x)\
	(((x) << 13) & GENMASK(13, 13))
#define UDPHS0_UDPHS_EPTCLRSTA0_STALL_SNT_EPTCLRSTA0_M GENMASK(13, 13)
#define UDPHS0_UDPHS_EPTCLRSTA0_STALL_SNT_EPTCLRSTA0_X(x)\
	(((x) & GENMASK(13, 13)) >> 13)

#define UDPHS0_UDPHS_EPTCLRSTA0_RX_SETUP_EPTCLRSTA0(x)\
	(((x) << 12) & GENMASK(12, 12))
#define UDPHS0_UDPHS_EPTCLRSTA0_RX_SETUP_EPTCLRSTA0_M GENMASK(12, 12)
#define UDPHS0_UDPHS_EPTCLRSTA0_RX_SETUP_EPTCLRSTA0_X(x)\
	(((x) & GENMASK(12, 12)) >> 12)

#define UDPHS0_UDPHS_EPTCLRSTA0_TX_COMPLT_EPTCLRSTA0(x)\
	(((x) << 10) & GENMASK(10, 10))
#define UDPHS0_UDPHS_EPTCLRSTA0_TX_COMPLT_EPTCLRSTA0_M GENMASK(10, 10)
#define UDPHS0_UDPHS_EPTCLRSTA0_TX_COMPLT_EPTCLRSTA0_X(x)\
	(((x) & GENMASK(10, 10)) >> 10)

#define UDPHS0_UDPHS_EPTCLRSTA0_RXRDY_TXKL_EPTCLRSTA0(x)\
	(((x) << 9) & GENMASK(9, 9))
#define UDPHS0_UDPHS_EPTCLRSTA0_RXRDY_TXKL_EPTCLRSTA0_M GENMASK(9, 9)
#define UDPHS0_UDPHS_EPTCLRSTA0_RXRDY_TXKL_EPTCLRSTA0_X(x)\
	(((x) & GENMASK(9, 9)) >> 9)

#define UDPHS0_UDPHS_EPTCLRSTA0_TOGGLESQ_EPTCLRSTA0(x)\
	(((x) << 6) & GENMASK(6, 6))
#define UDPHS0_UDPHS_EPTCLRSTA0_TOGGLESQ_EPTCLRSTA0_M GENMASK(6, 6)
#define UDPHS0_UDPHS_EPTCLRSTA0_TOGGLESQ_EPTCLRSTA0_X(x)\
	(((x) & GENMASK(6, 6)) >> 6)

#define UDPHS0_UDPHS_EPTCLRSTA0_FRCESTALL_EPTCLRSTA0(x)\
	(((x) << 5) & GENMASK(5, 5))
#define UDPHS0_UDPHS_EPTCLRSTA0_FRCESTALL_EPTCLRSTA0_M GENMASK(5, 5)
#define UDPHS0_UDPHS_EPTCLRSTA0_FRCESTALL_EPTCLRSTA0_X(x)\
	(((x) & GENMASK(5, 5)) >> 5)

/*      UDPHS0:UDPHS_REGS:UDPHS_EPTSTA0 */
#define UDPHS0_UDPHS_EPTSTA0(t)   (t + 0x11c)

#define UDPHS0_UDPHS_EPTSTA0_SHRT_PCKT_EPTSTA0(x)\
	(((x) << 31) & GENMASK(31, 31))
#define UDPHS0_UDPHS_EPTSTA0_SHRT_PCKT_EPTSTA0_M GENMASK(31, 31)
#define UDPHS0_UDPHS_EPTSTA0_SHRT_PCKT_EPTSTA0_X(x)\
	(((x) & GENMASK(31, 31)) >> 31)

#define UDPHS0_UDPHS_EPTSTA0_BYTE_COUNT_EPTSTA0(x)\
	(((x) << 20) & GENMASK(30, 20))
#define UDPHS0_UDPHS_EPTSTA0_BYTE_COUNT_EPTSTA0_M GENMASK(30, 20)
#define UDPHS0_UDPHS_EPTSTA0_BYTE_COUNT_EPTSTA0_X(x)\
	(((x) & GENMASK(30, 20)) >> 20)

#define UDPHS0_UDPHS_EPTSTA0_BUSY_BANK_STA_EPTSTA0(x)\
	(((x) << 18) & GENMASK(19, 18))
#define UDPHS0_UDPHS_EPTSTA0_BUSY_BANK_STA_EPTSTA0_M GENMASK(19, 18)
#define UDPHS0_UDPHS_EPTSTA0_BUSY_BANK_STA_EPTSTA0_X(x)\
	(((x) & GENMASK(19, 18)) >> 18)

#define UDPHS0_UDPHS_EPTSTA0_CURBK_CTLDIR_EPTSTA0(x)\
	(((x) << 16) & GENMASK(17, 16))
#define UDPHS0_UDPHS_EPTSTA0_CURBK_CTLDIR_EPTSTA0_M GENMASK(17, 16)
#define UDPHS0_UDPHS_EPTSTA0_CURBK_CTLDIR_EPTSTA0_X(x)\
	(((x) & GENMASK(17, 16)) >> 16)

#define UDPHS0_UDPHS_EPTSTA0_NAK_OUT_EPTSTA0(x)  (((x) << 15) & GENMASK(15, 15))
#define UDPHS0_UDPHS_EPTSTA0_NAK_OUT_EPTSTA0_M   GENMASK(15, 15)
#define UDPHS0_UDPHS_EPTSTA0_NAK_OUT_EPTSTA0_X(x)\
	(((x) & GENMASK(15, 15)) >> 15)

#define UDPHS0_UDPHS_EPTSTA0_NAK_IN_EPTSTA0(x)   (((x) << 14) & GENMASK(14, 14))
#define UDPHS0_UDPHS_EPTSTA0_NAK_IN_EPTSTA0_M    GENMASK(14, 14)
#define UDPHS0_UDPHS_EPTSTA0_NAK_IN_EPTSTA0_X(x) (((x) & GENMASK(14, 14)) >> 14)

#define UDPHS0_UDPHS_EPTSTA0_STALL_SNT_EPTSTA0(x)\
	(((x) << 13) & GENMASK(13, 13))
#define UDPHS0_UDPHS_EPTSTA0_STALL_SNT_EPTSTA0_M GENMASK(13, 13)
#define UDPHS0_UDPHS_EPTSTA0_STALL_SNT_EPTSTA0_X(x)\
	(((x) & GENMASK(13, 13)) >> 13)

#define UDPHS0_UDPHS_EPTSTA0_RX_SETUP_EPTSTA0(x) (((x) << 12) & GENMASK(12, 12))
#define UDPHS0_UDPHS_EPTSTA0_RX_SETUP_EPTSTA0_M  GENMASK(12, 12)
#define UDPHS0_UDPHS_EPTSTA0_RX_SETUP_EPTSTA0_X(x)\
	(((x) & GENMASK(12, 12)) >> 12)

#define UDPHS0_UDPHS_EPTSTA0_TXRDY_EPTSTA0(x)    (((x) << 11) & GENMASK(11, 11))
#define UDPHS0_UDPHS_EPTSTA0_TXRDY_EPTSTA0_M     GENMASK(11, 11)
#define UDPHS0_UDPHS_EPTSTA0_TXRDY_EPTSTA0_X(x)  (((x) & GENMASK(11, 11)) >> 11)

#define UDPHS0_UDPHS_EPTSTA0_TX_COMPLT_EPTSTA0(x)\
	(((x) << 10) & GENMASK(10, 10))
#define UDPHS0_UDPHS_EPTSTA0_TX_COMPLT_EPTSTA0_M GENMASK(10, 10)
#define UDPHS0_UDPHS_EPTSTA0_TX_COMPLT_EPTSTA0_X(x)\
	(((x) & GENMASK(10, 10)) >> 10)

#define UDPHS0_UDPHS_EPTSTA0_RXRDY_TXKL_EPTSTA0(x) (((x) << 9) & GENMASK(9, 9))
#define UDPHS0_UDPHS_EPTSTA0_RXRDY_TXKL_EPTSTA0_M GENMASK(9, 9)
#define UDPHS0_UDPHS_EPTSTA0_RXRDY_TXKL_EPTSTA0_X(x)\
	(((x) & GENMASK(9, 9)) >> 9)

#define UDPHS0_UDPHS_EPTSTA0_ERR_OVFLW_EPTSTA0(x) (((x) << 8) & GENMASK(8, 8))
#define UDPHS0_UDPHS_EPTSTA0_ERR_OVFLW_EPTSTA0_M GENMASK(8, 8)
#define UDPHS0_UDPHS_EPTSTA0_ERR_OVFLW_EPTSTA0_X(x) (((x) & GENMASK(8, 8)) >> 8)

#define UDPHS0_UDPHS_EPTSTA0_TOGGLESQ_STA_EPTSTA0(x)\
	(((x) << 6) & GENMASK(7, 6))
#define UDPHS0_UDPHS_EPTSTA0_TOGGLESQ_STA_EPTSTA0_M GENMASK(7, 6)
#define UDPHS0_UDPHS_EPTSTA0_TOGGLESQ_STA_EPTSTA0_X(x)\
	(((x) & GENMASK(7, 6)) >> 6)

#define UDPHS0_UDPHS_EPTSTA0_FRCESTALL_EPTSTA0(x) (((x) << 5) & GENMASK(5, 5))
#define UDPHS0_UDPHS_EPTSTA0_FRCESTALL_EPTSTA0_M GENMASK(5, 5)
#define UDPHS0_UDPHS_EPTSTA0_FRCESTALL_EPTSTA0_X(x) (((x) & GENMASK(5, 5)) >> 5)

/*      UDPHS0:UDPHS_REGS:UDPHS_EPTCFG1 */
#define UDPHS0_UDPHS_EPTCFG1(t)   (t + 0x120)

#define UDPHS0_UDPHS_EPTCFG1_EPT_MAPD_EPTCFG1(x) (((x) << 31) & GENMASK(31, 31))
#define UDPHS0_UDPHS_EPTCFG1_EPT_MAPD_EPTCFG1_M  GENMASK(31, 31)
#define UDPHS0_UDPHS_EPTCFG1_EPT_MAPD_EPTCFG1_X(x)\
	(((x) & GENMASK(31, 31)) >> 31)

#define UDPHS0_UDPHS_EPTCFG1_NB_TRANS_EPTCFG1(x) (((x) << 8) & GENMASK(9, 8))
#define UDPHS0_UDPHS_EPTCFG1_NB_TRANS_EPTCFG1_M  GENMASK(9, 8)
#define UDPHS0_UDPHS_EPTCFG1_NB_TRANS_EPTCFG1_X(x) (((x) & GENMASK(9, 8)) >> 8)

#define UDPHS0_UDPHS_EPTCFG1_BK_NUMBER_EPTCFG1(x) (((x) << 6) & GENMASK(7, 6))
#define UDPHS0_UDPHS_EPTCFG1_BK_NUMBER_EPTCFG1_M GENMASK(7, 6)
#define UDPHS0_UDPHS_EPTCFG1_BK_NUMBER_EPTCFG1_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define UDPHS0_UDPHS_EPTCFG1_EPT_TYPE_EPTCFG1(x) (((x) << 4) & GENMASK(5, 4))
#define UDPHS0_UDPHS_EPTCFG1_EPT_TYPE_EPTCFG1_M  GENMASK(5, 4)
#define UDPHS0_UDPHS_EPTCFG1_EPT_TYPE_EPTCFG1_X(x) (((x) & GENMASK(5, 4)) >> 4)

#define UDPHS0_UDPHS_EPTCFG1_EPT_DIR_EPTCFG1(x)  (((x) << 3) & GENMASK(3, 3))
#define UDPHS0_UDPHS_EPTCFG1_EPT_DIR_EPTCFG1_M   GENMASK(3, 3)
#define UDPHS0_UDPHS_EPTCFG1_EPT_DIR_EPTCFG1_X(x) (((x) & GENMASK(3, 3)) >> 3)

#define UDPHS0_UDPHS_EPTCFG1_EPT_SIZE_EPTCFG1(x) ((x) & GENMASK(2, 0))
#define UDPHS0_UDPHS_EPTCFG1_EPT_SIZE_EPTCFG1_M  GENMASK(2, 0)
#define UDPHS0_UDPHS_EPTCFG1_EPT_SIZE_EPTCFG1_X(x) ((x) & GENMASK(2, 0))

/*      UDPHS0:UDPHS_REGS:UDPHS_EPTCTLENB1 */
#define UDPHS0_UDPHS_EPTCTLENB1(t) (t + 0x124)

#define UDPHS0_UDPHS_EPTCTLENB1_SHRT_PCKT_EPTCTLENB1(x)\
	(((x) << 31) & GENMASK(31, 31))
#define UDPHS0_UDPHS_EPTCTLENB1_SHRT_PCKT_EPTCTLENB1_M GENMASK(31, 31)
#define UDPHS0_UDPHS_EPTCTLENB1_SHRT_PCKT_EPTCTLENB1_X(x)\
	(((x) & GENMASK(31, 31)) >> 31)

#define UDPHS0_UDPHS_EPTCTLENB1_BUSY_BANK_EPTCTLENB1(x)\
	(((x) << 18) & GENMASK(18, 18))
#define UDPHS0_UDPHS_EPTCTLENB1_BUSY_BANK_EPTCTLENB1_M GENMASK(18, 18)
#define UDPHS0_UDPHS_EPTCTLENB1_BUSY_BANK_EPTCTLENB1_X(x)\
	(((x) & GENMASK(18, 18)) >> 18)

#define UDPHS0_UDPHS_EPTCTLENB1_NAK_OUT_EPTCTLENB1(x)\
	(((x) << 15) & GENMASK(15, 15))
#define UDPHS0_UDPHS_EPTCTLENB1_NAK_OUT_EPTCTLENB1_M GENMASK(15, 15)
#define UDPHS0_UDPHS_EPTCTLENB1_NAK_OUT_EPTCTLENB1_X(x)\
	(((x) & GENMASK(15, 15)) >> 15)

#define UDPHS0_UDPHS_EPTCTLENB1_NAK_IN_EPTCTLENB1(x)\
	(((x) << 14) & GENMASK(14, 14))
#define UDPHS0_UDPHS_EPTCTLENB1_NAK_IN_EPTCTLENB1_M GENMASK(14, 14)
#define UDPHS0_UDPHS_EPTCTLENB1_NAK_IN_EPTCTLENB1_X(x)\
	(((x) & GENMASK(14, 14)) >> 14)

#define UDPHS0_UDPHS_EPTCTLENB1_STALL_SNT_EPTCTLENB1(x)\
	(((x) << 13) & GENMASK(13, 13))
#define UDPHS0_UDPHS_EPTCTLENB1_STALL_SNT_EPTCTLENB1_M GENMASK(13, 13)
#define UDPHS0_UDPHS_EPTCTLENB1_STALL_SNT_EPTCTLENB1_X(x)\
	(((x) & GENMASK(13, 13)) >> 13)

#define UDPHS0_UDPHS_EPTCTLENB1_RX_SETUP_EPTCTLENB1(x)\
	(((x) << 12) & GENMASK(12, 12))
#define UDPHS0_UDPHS_EPTCTLENB1_RX_SETUP_EPTCTLENB1_M GENMASK(12, 12)
#define UDPHS0_UDPHS_EPTCTLENB1_RX_SETUP_EPTCTLENB1_X(x)\
	(((x) & GENMASK(12, 12)) >> 12)

#define UDPHS0_UDPHS_EPTCTLENB1_TXRDY_EPTCTLENB1(x)\
	(((x) << 11) & GENMASK(11, 11))
#define UDPHS0_UDPHS_EPTCTLENB1_TXRDY_EPTCTLENB1_M GENMASK(11, 11)
#define UDPHS0_UDPHS_EPTCTLENB1_TXRDY_EPTCTLENB1_X(x)\
	(((x) & GENMASK(11, 11)) >> 11)

#define UDPHS0_UDPHS_EPTCTLENB1_TX_COMPLT_EPTCTLENB1(x)\
	(((x) << 10) & GENMASK(10, 10))
#define UDPHS0_UDPHS_EPTCTLENB1_TX_COMPLT_EPTCTLENB1_M GENMASK(10, 10)
#define UDPHS0_UDPHS_EPTCTLENB1_TX_COMPLT_EPTCTLENB1_X(x)\
	(((x) & GENMASK(10, 10)) >> 10)

#define UDPHS0_UDPHS_EPTCTLENB1_RXRDY_TXKL_EPTCTLENB1(x)\
	(((x) << 9) & GENMASK(9, 9))
#define UDPHS0_UDPHS_EPTCTLENB1_RXRDY_TXKL_EPTCTLENB1_M GENMASK(9, 9)
#define UDPHS0_UDPHS_EPTCTLENB1_RXRDY_TXKL_EPTCTLENB1_X(x)\
	(((x) & GENMASK(9, 9)) >> 9)

#define UDPHS0_UDPHS_EPTCTLENB1_ERR_OVFLW_EPTCTLENB1(x)\
	(((x) << 8) & GENMASK(8, 8))
#define UDPHS0_UDPHS_EPTCTLENB1_ERR_OVFLW_EPTCTLENB1_M GENMASK(8, 8)
#define UDPHS0_UDPHS_EPTCTLENB1_ERR_OVFLW_EPTCTLENB1_X(x)\
	(((x) & GENMASK(8, 8)) >> 8)

#define UDPHS0_UDPHS_EPTCTLENB1_NYET_DIS_EPTCTLENB1(x)\
	(((x) << 4) & GENMASK(4, 4))
#define UDPHS0_UDPHS_EPTCTLENB1_NYET_DIS_EPTCTLENB1_M GENMASK(4, 4)
#define UDPHS0_UDPHS_EPTCTLENB1_NYET_DIS_EPTCTLENB1_X(x)\
	(((x) & GENMASK(4, 4)) >> 4)

#define UDPHS0_UDPHS_EPTCTLENB1_INTDIS_DMA_EPTCTLENB1(x)\
	(((x) << 3) & GENMASK(3, 3))
#define UDPHS0_UDPHS_EPTCTLENB1_INTDIS_DMA_EPTCTLENB1_M GENMASK(3, 3)
#define UDPHS0_UDPHS_EPTCTLENB1_INTDIS_DMA_EPTCTLENB1_X(x)\
	(((x) & GENMASK(3, 3)) >> 3)

#define UDPHS0_UDPHS_EPTCTLENB1_AUTO_VALID_EPTCTLENB1(x)\
	(((x) << 1) & GENMASK(1, 1))
#define UDPHS0_UDPHS_EPTCTLENB1_AUTO_VALID_EPTCTLENB1_M GENMASK(1, 1)
#define UDPHS0_UDPHS_EPTCTLENB1_AUTO_VALID_EPTCTLENB1_X(x)\
	(((x) & GENMASK(1, 1)) >> 1)

#define UDPHS0_UDPHS_EPTCTLENB1_EPT_ENABL_EPTCTLENB1(x) ((x) & GENMASK(0, 0))
#define UDPHS0_UDPHS_EPTCTLENB1_EPT_ENABL_EPTCTLENB1_M GENMASK(0, 0)
#define UDPHS0_UDPHS_EPTCTLENB1_EPT_ENABL_EPTCTLENB1_X(x) ((x) & GENMASK(0, 0))

/*      UDPHS0:UDPHS_REGS:UDPHS_EPTCLRSTA1 */
#define UDPHS0_UDPHS_EPTCLRSTA1(t) (t + 0x138)

#define UDPHS0_UDPHS_EPTCLRSTA1_NAK_OUT_EPTCLRSTA1(x)\
	(((x) << 15) & GENMASK(15, 15))
#define UDPHS0_UDPHS_EPTCLRSTA1_NAK_OUT_EPTCLRSTA1_M GENMASK(15, 15)
#define UDPHS0_UDPHS_EPTCLRSTA1_NAK_OUT_EPTCLRSTA1_X(x)\
	(((x) & GENMASK(15, 15)) >> 15)

#define UDPHS0_UDPHS_EPTCLRSTA1_NAK_IN_EPTCLRSTA1(x)\
	(((x) << 14) & GENMASK(14, 14))
#define UDPHS0_UDPHS_EPTCLRSTA1_NAK_IN_EPTCLRSTA1_M GENMASK(14, 14)
#define UDPHS0_UDPHS_EPTCLRSTA1_NAK_IN_EPTCLRSTA1_X(x)\
	(((x) & GENMASK(14, 14)) >> 14)

#define UDPHS0_UDPHS_EPTCLRSTA1_STALL_SNT_EPTCLRSTA1(x)\
	(((x) << 13) & GENMASK(13, 13))
#define UDPHS0_UDPHS_EPTCLRSTA1_STALL_SNT_EPTCLRSTA1_M GENMASK(13, 13)
#define UDPHS0_UDPHS_EPTCLRSTA1_STALL_SNT_EPTCLRSTA1_X(x)\
	(((x) & GENMASK(13, 13)) >> 13)

#define UDPHS0_UDPHS_EPTCLRSTA1_RX_SETUP_EPTCLRSTA1(x)\
	(((x) << 12) & GENMASK(12, 12))
#define UDPHS0_UDPHS_EPTCLRSTA1_RX_SETUP_EPTCLRSTA1_M GENMASK(12, 12)
#define UDPHS0_UDPHS_EPTCLRSTA1_RX_SETUP_EPTCLRSTA1_X(x)\
	(((x) & GENMASK(12, 12)) >> 12)

#define UDPHS0_UDPHS_EPTCLRSTA1_TX_COMPLT_EPTCLRSTA1(x)\
	(((x) << 10) & GENMASK(10, 10))
#define UDPHS0_UDPHS_EPTCLRSTA1_TX_COMPLT_EPTCLRSTA1_M GENMASK(10, 10)
#define UDPHS0_UDPHS_EPTCLRSTA1_TX_COMPLT_EPTCLRSTA1_X(x)\
	(((x) & GENMASK(10, 10)) >> 10)

#define UDPHS0_UDPHS_EPTCLRSTA1_RXRDY_TXKL_EPTCLRSTA1(x)\
	(((x) << 9) & GENMASK(9, 9))
#define UDPHS0_UDPHS_EPTCLRSTA1_RXRDY_TXKL_EPTCLRSTA1_M GENMASK(9, 9)
#define UDPHS0_UDPHS_EPTCLRSTA1_RXRDY_TXKL_EPTCLRSTA1_X(x)\
	(((x) & GENMASK(9, 9)) >> 9)

#define UDPHS0_UDPHS_EPTCLRSTA1_TOGGLESQ_EPTCLRSTA1(x)\
	(((x) << 6) & GENMASK(6, 6))
#define UDPHS0_UDPHS_EPTCLRSTA1_TOGGLESQ_EPTCLRSTA1_M GENMASK(6, 6)
#define UDPHS0_UDPHS_EPTCLRSTA1_TOGGLESQ_EPTCLRSTA1_X(x)\
	(((x) & GENMASK(6, 6)) >> 6)

#define UDPHS0_UDPHS_EPTCLRSTA1_FRCESTALL_EPTCLRSTA1(x)\
	(((x) << 5) & GENMASK(5, 5))
#define UDPHS0_UDPHS_EPTCLRSTA1_FRCESTALL_EPTCLRSTA1_M GENMASK(5, 5)
#define UDPHS0_UDPHS_EPTCLRSTA1_FRCESTALL_EPTCLRSTA1_X(x)\
	(((x) & GENMASK(5, 5)) >> 5)

/*      UDPHS0:UDPHS_REGS:UDPHS_EPTSTA1 */
#define UDPHS0_UDPHS_EPTSTA1(t)   (t + 0x13c)

#define UDPHS0_UDPHS_EPTSTA1_SHRT_PCKT_EPTSTA1(x)\
	(((x) << 31) & GENMASK(31, 31))
#define UDPHS0_UDPHS_EPTSTA1_SHRT_PCKT_EPTSTA1_M GENMASK(31, 31)
#define UDPHS0_UDPHS_EPTSTA1_SHRT_PCKT_EPTSTA1_X(x)\
	(((x) & GENMASK(31, 31)) >> 31)

#define UDPHS0_UDPHS_EPTSTA1_BYTE_COUNT_EPTSTA1(x)\
	(((x) << 20) & GENMASK(30, 20))
#define UDPHS0_UDPHS_EPTSTA1_BYTE_COUNT_EPTSTA1_M GENMASK(30, 20)
#define UDPHS0_UDPHS_EPTSTA1_BYTE_COUNT_EPTSTA1_X(x)\
	(((x) & GENMASK(30, 20)) >> 20)

#define UDPHS0_UDPHS_EPTSTA1_BUSY_BANK_STA_EPTSTA1(x)\
	(((x) << 18) & GENMASK(19, 18))
#define UDPHS0_UDPHS_EPTSTA1_BUSY_BANK_STA_EPTSTA1_M GENMASK(19, 18)
#define UDPHS0_UDPHS_EPTSTA1_BUSY_BANK_STA_EPTSTA1_X(x)\
	(((x) & GENMASK(19, 18)) >> 18)

#define UDPHS0_UDPHS_EPTSTA1_CURBK_CTLDIR_EPTSTA1(x)\
	(((x) << 16) & GENMASK(17, 16))
#define UDPHS0_UDPHS_EPTSTA1_CURBK_CTLDIR_EPTSTA1_M GENMASK(17, 16)
#define UDPHS0_UDPHS_EPTSTA1_CURBK_CTLDIR_EPTSTA1_X(x)\
	(((x) & GENMASK(17, 16)) >> 16)

#define UDPHS0_UDPHS_EPTSTA1_NAK_OUT_EPTSTA1(x)  (((x) << 15) & GENMASK(15, 15))
#define UDPHS0_UDPHS_EPTSTA1_NAK_OUT_EPTSTA1_M   GENMASK(15, 15)
#define UDPHS0_UDPHS_EPTSTA1_NAK_OUT_EPTSTA1_X(x)\
	(((x) & GENMASK(15, 15)) >> 15)

#define UDPHS0_UDPHS_EPTSTA1_NAK_IN_EPTSTA1(x)   (((x) << 14) & GENMASK(14, 14))
#define UDPHS0_UDPHS_EPTSTA1_NAK_IN_EPTSTA1_M    GENMASK(14, 14)
#define UDPHS0_UDPHS_EPTSTA1_NAK_IN_EPTSTA1_X(x) (((x) & GENMASK(14, 14)) >> 14)

#define UDPHS0_UDPHS_EPTSTA1_STALL_SNT_EPTSTA1(x)\
	(((x) << 13) & GENMASK(13, 13))
#define UDPHS0_UDPHS_EPTSTA1_STALL_SNT_EPTSTA1_M GENMASK(13, 13)
#define UDPHS0_UDPHS_EPTSTA1_STALL_SNT_EPTSTA1_X(x)\
	(((x) & GENMASK(13, 13)) >> 13)

#define UDPHS0_UDPHS_EPTSTA1_RX_SETUP_EPTSTA1(x) (((x) << 12) & GENMASK(12, 12))
#define UDPHS0_UDPHS_EPTSTA1_RX_SETUP_EPTSTA1_M  GENMASK(12, 12)
#define UDPHS0_UDPHS_EPTSTA1_RX_SETUP_EPTSTA1_X(x)\
	(((x) & GENMASK(12, 12)) >> 12)

#define UDPHS0_UDPHS_EPTSTA1_TXRDY_EPTSTA1(x)    (((x) << 11) & GENMASK(11, 11))
#define UDPHS0_UDPHS_EPTSTA1_TXRDY_EPTSTA1_M     GENMASK(11, 11)
#define UDPHS0_UDPHS_EPTSTA1_TXRDY_EPTSTA1_X(x)  (((x) & GENMASK(11, 11)) >> 11)

#define UDPHS0_UDPHS_EPTSTA1_TX_COMPLT_EPTSTA1(x)\
	(((x) << 10) & GENMASK(10, 10))
#define UDPHS0_UDPHS_EPTSTA1_TX_COMPLT_EPTSTA1_M GENMASK(10, 10)
#define UDPHS0_UDPHS_EPTSTA1_TX_COMPLT_EPTSTA1_X(x)\
	(((x) & GENMASK(10, 10)) >> 10)

#define UDPHS0_UDPHS_EPTSTA1_RXRDY_TXKL_EPTSTA1(x) (((x) << 9) & GENMASK(9, 9))
#define UDPHS0_UDPHS_EPTSTA1_RXRDY_TXKL_EPTSTA1_M GENMASK(9, 9)
#define UDPHS0_UDPHS_EPTSTA1_RXRDY_TXKL_EPTSTA1_X(x)\
	(((x) & GENMASK(9, 9)) >> 9)

#define UDPHS0_UDPHS_EPTSTA1_ERR_OVFLW_EPTSTA1(x) (((x) << 8) & GENMASK(8, 8))
#define UDPHS0_UDPHS_EPTSTA1_ERR_OVFLW_EPTSTA1_M GENMASK(8, 8)
#define UDPHS0_UDPHS_EPTSTA1_ERR_OVFLW_EPTSTA1_X(x) (((x) & GENMASK(8, 8)) >> 8)

#define UDPHS0_UDPHS_EPTSTA1_TOGGLESQ_STA_EPTSTA1(x)\
	(((x) << 6) & GENMASK(7, 6))
#define UDPHS0_UDPHS_EPTSTA1_TOGGLESQ_STA_EPTSTA1_M GENMASK(7, 6)
#define UDPHS0_UDPHS_EPTSTA1_TOGGLESQ_STA_EPTSTA1_X(x)\
	(((x) & GENMASK(7, 6)) >> 6)

#define UDPHS0_UDPHS_EPTSTA1_FRCESTALL_EPTSTA1(x) (((x) << 5) & GENMASK(5, 5))
#define UDPHS0_UDPHS_EPTSTA1_FRCESTALL_EPTSTA1_M GENMASK(5, 5)
#define UDPHS0_UDPHS_EPTSTA1_FRCESTALL_EPTSTA1_X(x) (((x) & GENMASK(5, 5)) >> 5)

/*      UDPHS0:UDPHS_REGS:UDPHS_EPTCFG2 */
#define UDPHS0_UDPHS_EPTCFG2(t)   (t + 0x140)

#define UDPHS0_UDPHS_EPTCFG2_EPT_MAPD_EPTCFG2(x) (((x) << 31) & GENMASK(31, 31))
#define UDPHS0_UDPHS_EPTCFG2_EPT_MAPD_EPTCFG2_M  GENMASK(31, 31)
#define UDPHS0_UDPHS_EPTCFG2_EPT_MAPD_EPTCFG2_X(x)\
	(((x) & GENMASK(31, 31)) >> 31)

#define UDPHS0_UDPHS_EPTCFG2_NB_TRANS_EPTCFG2(x) (((x) << 8) & GENMASK(9, 8))
#define UDPHS0_UDPHS_EPTCFG2_NB_TRANS_EPTCFG2_M  GENMASK(9, 8)
#define UDPHS0_UDPHS_EPTCFG2_NB_TRANS_EPTCFG2_X(x) (((x) & GENMASK(9, 8)) >> 8)

#define UDPHS0_UDPHS_EPTCFG2_BK_NUMBER_EPTCFG2(x) (((x) << 6) & GENMASK(7, 6))
#define UDPHS0_UDPHS_EPTCFG2_BK_NUMBER_EPTCFG2_M GENMASK(7, 6)
#define UDPHS0_UDPHS_EPTCFG2_BK_NUMBER_EPTCFG2_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define UDPHS0_UDPHS_EPTCFG2_EPT_TYPE_EPTCFG2(x) (((x) << 4) & GENMASK(5, 4))
#define UDPHS0_UDPHS_EPTCFG2_EPT_TYPE_EPTCFG2_M  GENMASK(5, 4)
#define UDPHS0_UDPHS_EPTCFG2_EPT_TYPE_EPTCFG2_X(x) (((x) & GENMASK(5, 4)) >> 4)

#define UDPHS0_UDPHS_EPTCFG2_EPT_DIR_EPTCFG2(x)  (((x) << 3) & GENMASK(3, 3))
#define UDPHS0_UDPHS_EPTCFG2_EPT_DIR_EPTCFG2_M   GENMASK(3, 3)
#define UDPHS0_UDPHS_EPTCFG2_EPT_DIR_EPTCFG2_X(x) (((x) & GENMASK(3, 3)) >> 3)

#define UDPHS0_UDPHS_EPTCFG2_EPT_SIZE_EPTCFG2(x) ((x) & GENMASK(2, 0))
#define UDPHS0_UDPHS_EPTCFG2_EPT_SIZE_EPTCFG2_M  GENMASK(2, 0)
#define UDPHS0_UDPHS_EPTCFG2_EPT_SIZE_EPTCFG2_X(x) ((x) & GENMASK(2, 0))

/*      UDPHS0:UDPHS_REGS:UDPHS_EPTCTLENB2 */
#define UDPHS0_UDPHS_EPTCTLENB2(t) (t + 0x144)

#define UDPHS0_UDPHS_EPTCTLENB2_SHRT_PCKT_EPTCTLENB2(x)\
	(((x) << 31) & GENMASK(31, 31))
#define UDPHS0_UDPHS_EPTCTLENB2_SHRT_PCKT_EPTCTLENB2_M GENMASK(31, 31)
#define UDPHS0_UDPHS_EPTCTLENB2_SHRT_PCKT_EPTCTLENB2_X(x)\
	(((x) & GENMASK(31, 31)) >> 31)

#define UDPHS0_UDPHS_EPTCTLENB2_BUSY_BANK_EPTCTLENB2(x)\
	(((x) << 18) & GENMASK(18, 18))
#define UDPHS0_UDPHS_EPTCTLENB2_BUSY_BANK_EPTCTLENB2_M GENMASK(18, 18)
#define UDPHS0_UDPHS_EPTCTLENB2_BUSY_BANK_EPTCTLENB2_X(x)\
	(((x) & GENMASK(18, 18)) >> 18)

#define UDPHS0_UDPHS_EPTCTLENB2_NAK_OUT_EPTCTLENB2(x)\
	(((x) << 15) & GENMASK(15, 15))
#define UDPHS0_UDPHS_EPTCTLENB2_NAK_OUT_EPTCTLENB2_M GENMASK(15, 15)
#define UDPHS0_UDPHS_EPTCTLENB2_NAK_OUT_EPTCTLENB2_X(x)\
	(((x) & GENMASK(15, 15)) >> 15)

#define UDPHS0_UDPHS_EPTCTLENB2_NAK_IN_EPTCTLENB2(x)\
	(((x) << 14) & GENMASK(14, 14))
#define UDPHS0_UDPHS_EPTCTLENB2_NAK_IN_EPTCTLENB2_M GENMASK(14, 14)
#define UDPHS0_UDPHS_EPTCTLENB2_NAK_IN_EPTCTLENB2_X(x)\
	(((x) & GENMASK(14, 14)) >> 14)

#define UDPHS0_UDPHS_EPTCTLENB2_STALL_SNT_EPTCTLENB2(x)\
	(((x) << 13) & GENMASK(13, 13))
#define UDPHS0_UDPHS_EPTCTLENB2_STALL_SNT_EPTCTLENB2_M GENMASK(13, 13)
#define UDPHS0_UDPHS_EPTCTLENB2_STALL_SNT_EPTCTLENB2_X(x)\
	(((x) & GENMASK(13, 13)) >> 13)

#define UDPHS0_UDPHS_EPTCTLENB2_RX_SETUP_EPTCTLENB2(x)\
	(((x) << 12) & GENMASK(12, 12))
#define UDPHS0_UDPHS_EPTCTLENB2_RX_SETUP_EPTCTLENB2_M GENMASK(12, 12)
#define UDPHS0_UDPHS_EPTCTLENB2_RX_SETUP_EPTCTLENB2_X(x)\
	(((x) & GENMASK(12, 12)) >> 12)

#define UDPHS0_UDPHS_EPTCTLENB2_TXRDY_EPTCTLENB2(x)\
	(((x) << 11) & GENMASK(11, 11))
#define UDPHS0_UDPHS_EPTCTLENB2_TXRDY_EPTCTLENB2_M GENMASK(11, 11)
#define UDPHS0_UDPHS_EPTCTLENB2_TXRDY_EPTCTLENB2_X(x)\
	(((x) & GENMASK(11, 11)) >> 11)

#define UDPHS0_UDPHS_EPTCTLENB2_TX_COMPLT_EPTCTLENB2(x)\
	(((x) << 10) & GENMASK(10, 10))
#define UDPHS0_UDPHS_EPTCTLENB2_TX_COMPLT_EPTCTLENB2_M GENMASK(10, 10)
#define UDPHS0_UDPHS_EPTCTLENB2_TX_COMPLT_EPTCTLENB2_X(x)\
	(((x) & GENMASK(10, 10)) >> 10)

#define UDPHS0_UDPHS_EPTCTLENB2_RXRDY_TXKL_EPTCTLENB2(x)\
	(((x) << 9) & GENMASK(9, 9))
#define UDPHS0_UDPHS_EPTCTLENB2_RXRDY_TXKL_EPTCTLENB2_M GENMASK(9, 9)
#define UDPHS0_UDPHS_EPTCTLENB2_RXRDY_TXKL_EPTCTLENB2_X(x)\
	(((x) & GENMASK(9, 9)) >> 9)

#define UDPHS0_UDPHS_EPTCTLENB2_ERR_OVFLW_EPTCTLENB2(x)\
	(((x) << 8) & GENMASK(8, 8))
#define UDPHS0_UDPHS_EPTCTLENB2_ERR_OVFLW_EPTCTLENB2_M GENMASK(8, 8)
#define UDPHS0_UDPHS_EPTCTLENB2_ERR_OVFLW_EPTCTLENB2_X(x)\
	(((x) & GENMASK(8, 8)) >> 8)

#define UDPHS0_UDPHS_EPTCTLENB2_NYET_DIS_EPTCTLENB2(x)\
	(((x) << 4) & GENMASK(4, 4))
#define UDPHS0_UDPHS_EPTCTLENB2_NYET_DIS_EPTCTLENB2_M GENMASK(4, 4)
#define UDPHS0_UDPHS_EPTCTLENB2_NYET_DIS_EPTCTLENB2_X(x)\
	(((x) & GENMASK(4, 4)) >> 4)

#define UDPHS0_UDPHS_EPTCTLENB2_INTDIS_DMA_EPTCTLENB2(x)\
	(((x) << 3) & GENMASK(3, 3))
#define UDPHS0_UDPHS_EPTCTLENB2_INTDIS_DMA_EPTCTLENB2_M GENMASK(3, 3)
#define UDPHS0_UDPHS_EPTCTLENB2_INTDIS_DMA_EPTCTLENB2_X(x)\
	(((x) & GENMASK(3, 3)) >> 3)

#define UDPHS0_UDPHS_EPTCTLENB2_AUTO_VALID_EPTCTLENB2(x)\
	(((x) << 1) & GENMASK(1, 1))
#define UDPHS0_UDPHS_EPTCTLENB2_AUTO_VALID_EPTCTLENB2_M GENMASK(1, 1)
#define UDPHS0_UDPHS_EPTCTLENB2_AUTO_VALID_EPTCTLENB2_X(x)\
	(((x) & GENMASK(1, 1)) >> 1)

#define UDPHS0_UDPHS_EPTCTLENB2_EPT_ENABL_EPTCTLENB2(x) ((x) & GENMASK(0, 0))
#define UDPHS0_UDPHS_EPTCTLENB2_EPT_ENABL_EPTCTLENB2_M GENMASK(0, 0)
#define UDPHS0_UDPHS_EPTCTLENB2_EPT_ENABL_EPTCTLENB2_X(x) ((x) & GENMASK(0, 0))

/*      UDPHS0:UDPHS_REGS:UDPHS_EPTSETSTA2 */
#define UDPHS0_UDPHS_EPTSETSTA2(t) (t + 0x154)

#define UDPHS0_UDPHS_EPTSETSTA2_TXRDY_EPTSETSTA2(x)\
	(((x) << 11) & GENMASK(11, 11))
#define UDPHS0_UDPHS_EPTSETSTA2_TXRDY_EPTSETSTA2_M GENMASK(11, 11)
#define UDPHS0_UDPHS_EPTSETSTA2_TXRDY_EPTSETSTA2_X(x)\
	(((x) & GENMASK(11, 11)) >> 11)

#define UDPHS0_UDPHS_EPTSETSTA2_RXRDY_TXKL_EPTSETSTA2(x)\
	(((x) << 9) & GENMASK(9, 9))
#define UDPHS0_UDPHS_EPTSETSTA2_RXRDY_TXKL_EPTSETSTA2_M GENMASK(9, 9)
#define UDPHS0_UDPHS_EPTSETSTA2_RXRDY_TXKL_EPTSETSTA2_X(x)\
	(((x) & GENMASK(9, 9)) >> 9)

#define UDPHS0_UDPHS_EPTSETSTA2_FRCESTALL_EPTSETSTA2(x)\
	(((x) << 5) & GENMASK(5, 5))
#define UDPHS0_UDPHS_EPTSETSTA2_FRCESTALL_EPTSETSTA2_M GENMASK(5, 5)
#define UDPHS0_UDPHS_EPTSETSTA2_FRCESTALL_EPTSETSTA2_X(x)\
	(((x) & GENMASK(5, 5)) >> 5)

/*      UDPHS0:UDPHS_REGS:UDPHS_EPTSTA2 */
#define UDPHS0_UDPHS_EPTSTA2(t)   (t + 0x15c)

#define UDPHS0_UDPHS_EPTSTA2_SHRT_PCKT_EPTSTA2(x)\
	(((x) << 31) & GENMASK(31, 31))
#define UDPHS0_UDPHS_EPTSTA2_SHRT_PCKT_EPTSTA2_M GENMASK(31, 31)
#define UDPHS0_UDPHS_EPTSTA2_SHRT_PCKT_EPTSTA2_X(x)\
	(((x) & GENMASK(31, 31)) >> 31)

#define UDPHS0_UDPHS_EPTSTA2_BYTE_COUNT_EPTSTA2(x)\
	(((x) << 20) & GENMASK(30, 20))
#define UDPHS0_UDPHS_EPTSTA2_BYTE_COUNT_EPTSTA2_M GENMASK(30, 20)
#define UDPHS0_UDPHS_EPTSTA2_BYTE_COUNT_EPTSTA2_X(x)\
	(((x) & GENMASK(30, 20)) >> 20)

#define UDPHS0_UDPHS_EPTSTA2_BUSY_BANK_STA_EPTSTA2(x)\
	(((x) << 18) & GENMASK(19, 18))
#define UDPHS0_UDPHS_EPTSTA2_BUSY_BANK_STA_EPTSTA2_M GENMASK(19, 18)
#define UDPHS0_UDPHS_EPTSTA2_BUSY_BANK_STA_EPTSTA2_X(x)\
	(((x) & GENMASK(19, 18)) >> 18)

#define UDPHS0_UDPHS_EPTSTA2_CURBK_CTLDIR_EPTSTA2(x)\
	(((x) << 16) & GENMASK(17, 16))
#define UDPHS0_UDPHS_EPTSTA2_CURBK_CTLDIR_EPTSTA2_M GENMASK(17, 16)
#define UDPHS0_UDPHS_EPTSTA2_CURBK_CTLDIR_EPTSTA2_X(x)\
	(((x) & GENMASK(17, 16)) >> 16)

#define UDPHS0_UDPHS_EPTSTA2_NAK_OUT_EPTSTA2(x)  (((x) << 15) & GENMASK(15, 15))
#define UDPHS0_UDPHS_EPTSTA2_NAK_OUT_EPTSTA2_M   GENMASK(15, 15)
#define UDPHS0_UDPHS_EPTSTA2_NAK_OUT_EPTSTA2_X(x)\
	(((x) & GENMASK(15, 15)) >> 15)

#define UDPHS0_UDPHS_EPTSTA2_NAK_IN_EPTSTA2(x)   (((x) << 14) & GENMASK(14, 14))
#define UDPHS0_UDPHS_EPTSTA2_NAK_IN_EPTSTA2_M    GENMASK(14, 14)
#define UDPHS0_UDPHS_EPTSTA2_NAK_IN_EPTSTA2_X(x) (((x) & GENMASK(14, 14)) >> 14)

#define UDPHS0_UDPHS_EPTSTA2_STALL_SNT_EPTSTA2(x)\
	(((x) << 13) & GENMASK(13, 13))
#define UDPHS0_UDPHS_EPTSTA2_STALL_SNT_EPTSTA2_M GENMASK(13, 13)
#define UDPHS0_UDPHS_EPTSTA2_STALL_SNT_EPTSTA2_X(x)\
	(((x) & GENMASK(13, 13)) >> 13)

#define UDPHS0_UDPHS_EPTSTA2_RX_SETUP_EPTSTA2(x) (((x) << 12) & GENMASK(12, 12))
#define UDPHS0_UDPHS_EPTSTA2_RX_SETUP_EPTSTA2_M  GENMASK(12, 12)
#define UDPHS0_UDPHS_EPTSTA2_RX_SETUP_EPTSTA2_X(x)\
	(((x) & GENMASK(12, 12)) >> 12)

#define UDPHS0_UDPHS_EPTSTA2_TXRDY_EPTSTA2(x)    (((x) << 11) & GENMASK(11, 11))
#define UDPHS0_UDPHS_EPTSTA2_TXRDY_EPTSTA2_M     GENMASK(11, 11)
#define UDPHS0_UDPHS_EPTSTA2_TXRDY_EPTSTA2_X(x)  (((x) & GENMASK(11, 11)) >> 11)

#define UDPHS0_UDPHS_EPTSTA2_TX_COMPLT_EPTSTA2(x)\
	(((x) << 10) & GENMASK(10, 10))
#define UDPHS0_UDPHS_EPTSTA2_TX_COMPLT_EPTSTA2_M GENMASK(10, 10)
#define UDPHS0_UDPHS_EPTSTA2_TX_COMPLT_EPTSTA2_X(x)\
	(((x) & GENMASK(10, 10)) >> 10)

#define UDPHS0_UDPHS_EPTSTA2_RXRDY_TXKL_EPTSTA2(x) (((x) << 9) & GENMASK(9, 9))
#define UDPHS0_UDPHS_EPTSTA2_RXRDY_TXKL_EPTSTA2_M GENMASK(9, 9)
#define UDPHS0_UDPHS_EPTSTA2_RXRDY_TXKL_EPTSTA2_X(x)\
	(((x) & GENMASK(9, 9)) >> 9)

#define UDPHS0_UDPHS_EPTSTA2_ERR_OVFLW_EPTSTA2(x) (((x) << 8) & GENMASK(8, 8))
#define UDPHS0_UDPHS_EPTSTA2_ERR_OVFLW_EPTSTA2_M GENMASK(8, 8)
#define UDPHS0_UDPHS_EPTSTA2_ERR_OVFLW_EPTSTA2_X(x) (((x) & GENMASK(8, 8)) >> 8)

#define UDPHS0_UDPHS_EPTSTA2_TOGGLESQ_STA_EPTSTA2(x)\
	(((x) << 6) & GENMASK(7, 6))
#define UDPHS0_UDPHS_EPTSTA2_TOGGLESQ_STA_EPTSTA2_M GENMASK(7, 6)
#define UDPHS0_UDPHS_EPTSTA2_TOGGLESQ_STA_EPTSTA2_X(x)\
	(((x) & GENMASK(7, 6)) >> 6)

#define UDPHS0_UDPHS_EPTSTA2_FRCESTALL_EPTSTA2(x) (((x) << 5) & GENMASK(5, 5))
#define UDPHS0_UDPHS_EPTSTA2_FRCESTALL_EPTSTA2_M GENMASK(5, 5)
#define UDPHS0_UDPHS_EPTSTA2_FRCESTALL_EPTSTA2_X(x) (((x) & GENMASK(5, 5)) >> 5)

/*      UDPHS0:UDPHS_REGS:UDPHS_EPTCFG3 */
#define UDPHS0_UDPHS_EPTCFG3(t)   (t + 0x160)

#define UDPHS0_UDPHS_EPTCFG3_EPT_MAPD_EPTCFG3(x) (((x) << 31) & GENMASK(31, 31))
#define UDPHS0_UDPHS_EPTCFG3_EPT_MAPD_EPTCFG3_M  GENMASK(31, 31)
#define UDPHS0_UDPHS_EPTCFG3_EPT_MAPD_EPTCFG3_X(x)\
	(((x) & GENMASK(31, 31)) >> 31)

#define UDPHS0_UDPHS_EPTCFG3_NB_TRANS_EPTCFG3(x) (((x) << 8) & GENMASK(9, 8))
#define UDPHS0_UDPHS_EPTCFG3_NB_TRANS_EPTCFG3_M  GENMASK(9, 8)
#define UDPHS0_UDPHS_EPTCFG3_NB_TRANS_EPTCFG3_X(x) (((x) & GENMASK(9, 8)) >> 8)

#define UDPHS0_UDPHS_EPTCFG3_BK_NUMBER_EPTCFG3(x) (((x) << 6) & GENMASK(7, 6))
#define UDPHS0_UDPHS_EPTCFG3_BK_NUMBER_EPTCFG3_M GENMASK(7, 6)
#define UDPHS0_UDPHS_EPTCFG3_BK_NUMBER_EPTCFG3_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define UDPHS0_UDPHS_EPTCFG3_EPT_TYPE_EPTCFG3(x) (((x) << 4) & GENMASK(5, 4))
#define UDPHS0_UDPHS_EPTCFG3_EPT_TYPE_EPTCFG3_M  GENMASK(5, 4)
#define UDPHS0_UDPHS_EPTCFG3_EPT_TYPE_EPTCFG3_X(x) (((x) & GENMASK(5, 4)) >> 4)

#define UDPHS0_UDPHS_EPTCFG3_EPT_DIR_EPTCFG3(x)  (((x) << 3) & GENMASK(3, 3))
#define UDPHS0_UDPHS_EPTCFG3_EPT_DIR_EPTCFG3_M   GENMASK(3, 3)
#define UDPHS0_UDPHS_EPTCFG3_EPT_DIR_EPTCFG3_X(x) (((x) & GENMASK(3, 3)) >> 3)

#define UDPHS0_UDPHS_EPTCFG3_EPT_SIZE_EPTCFG3(x) ((x) & GENMASK(2, 0))
#define UDPHS0_UDPHS_EPTCFG3_EPT_SIZE_EPTCFG3_M  GENMASK(2, 0)
#define UDPHS0_UDPHS_EPTCFG3_EPT_SIZE_EPTCFG3_X(x) ((x) & GENMASK(2, 0))

/*      UDPHS0:UDPHS_REGS:UDPHS_EPTCTLENB3 */
#define UDPHS0_UDPHS_EPTCTLENB3(t) (t + 0x164)

#define UDPHS0_UDPHS_EPTCTLENB3_SHRT_PCKT_EPTCTLENB3(x)\
	(((x) << 31) & GENMASK(31, 31))
#define UDPHS0_UDPHS_EPTCTLENB3_SHRT_PCKT_EPTCTLENB3_M GENMASK(31, 31)
#define UDPHS0_UDPHS_EPTCTLENB3_SHRT_PCKT_EPTCTLENB3_X(x)\
	(((x) & GENMASK(31, 31)) >> 31)

#define UDPHS0_UDPHS_EPTCTLENB3_BUSY_BANK_EPTCTLENB3(x)\
	(((x) << 18) & GENMASK(18, 18))
#define UDPHS0_UDPHS_EPTCTLENB3_BUSY_BANK_EPTCTLENB3_M GENMASK(18, 18)
#define UDPHS0_UDPHS_EPTCTLENB3_BUSY_BANK_EPTCTLENB3_X(x)\
	(((x) & GENMASK(18, 18)) >> 18)

#define UDPHS0_UDPHS_EPTCTLENB3_NAK_OUT_EPTCTLENB3(x)\
	(((x) << 15) & GENMASK(15, 15))
#define UDPHS0_UDPHS_EPTCTLENB3_NAK_OUT_EPTCTLENB3_M GENMASK(15, 15)
#define UDPHS0_UDPHS_EPTCTLENB3_NAK_OUT_EPTCTLENB3_X(x)\
	(((x) & GENMASK(15, 15)) >> 15)

#define UDPHS0_UDPHS_EPTCTLENB3_NAK_IN_EPTCTLENB3(x)\
	(((x) << 14) & GENMASK(14, 14))
#define UDPHS0_UDPHS_EPTCTLENB3_NAK_IN_EPTCTLENB3_M GENMASK(14, 14)
#define UDPHS0_UDPHS_EPTCTLENB3_NAK_IN_EPTCTLENB3_X(x)\
	(((x) & GENMASK(14, 14)) >> 14)

#define UDPHS0_UDPHS_EPTCTLENB3_STALL_SNT_EPTCTLENB3(x)\
	(((x) << 13) & GENMASK(13, 13))
#define UDPHS0_UDPHS_EPTCTLENB3_STALL_SNT_EPTCTLENB3_M GENMASK(13, 13)
#define UDPHS0_UDPHS_EPTCTLENB3_STALL_SNT_EPTCTLENB3_X(x)\
	(((x) & GENMASK(13, 13)) >> 13)

#define UDPHS0_UDPHS_EPTCTLENB3_RX_SETUP_EPTCTLENB3(x)\
	(((x) << 12) & GENMASK(12, 12))
#define UDPHS0_UDPHS_EPTCTLENB3_RX_SETUP_EPTCTLENB3_M GENMASK(12, 12)
#define UDPHS0_UDPHS_EPTCTLENB3_RX_SETUP_EPTCTLENB3_X(x)\
	(((x) & GENMASK(12, 12)) >> 12)

#define UDPHS0_UDPHS_EPTCTLENB3_TXRDY_EPTCTLENB3(x)\
	(((x) << 11) & GENMASK(11, 11))
#define UDPHS0_UDPHS_EPTCTLENB3_TXRDY_EPTCTLENB3_M GENMASK(11, 11)
#define UDPHS0_UDPHS_EPTCTLENB3_TXRDY_EPTCTLENB3_X(x)\
	(((x) & GENMASK(11, 11)) >> 11)

#define UDPHS0_UDPHS_EPTCTLENB3_TX_COMPLT_EPTCTLENB3(x)\
	(((x) << 10) & GENMASK(10, 10))
#define UDPHS0_UDPHS_EPTCTLENB3_TX_COMPLT_EPTCTLENB3_M GENMASK(10, 10)
#define UDPHS0_UDPHS_EPTCTLENB3_TX_COMPLT_EPTCTLENB3_X(x)\
	(((x) & GENMASK(10, 10)) >> 10)

#define UDPHS0_UDPHS_EPTCTLENB3_RXRDY_TXKL_EPTCTLENB3(x)\
	(((x) << 9) & GENMASK(9, 9))
#define UDPHS0_UDPHS_EPTCTLENB3_RXRDY_TXKL_EPTCTLENB3_M GENMASK(9, 9)
#define UDPHS0_UDPHS_EPTCTLENB3_RXRDY_TXKL_EPTCTLENB3_X(x)\
	(((x) & GENMASK(9, 9)) >> 9)

#define UDPHS0_UDPHS_EPTCTLENB3_ERR_OVFLW_EPTCTLENB3(x)\
	(((x) << 8) & GENMASK(8, 8))
#define UDPHS0_UDPHS_EPTCTLENB3_ERR_OVFLW_EPTCTLENB3_M GENMASK(8, 8)
#define UDPHS0_UDPHS_EPTCTLENB3_ERR_OVFLW_EPTCTLENB3_X(x)\
	(((x) & GENMASK(8, 8)) >> 8)

#define UDPHS0_UDPHS_EPTCTLENB3_NYET_DIS_EPTCTLENB3(x)\
	(((x) << 4) & GENMASK(4, 4))
#define UDPHS0_UDPHS_EPTCTLENB3_NYET_DIS_EPTCTLENB3_M GENMASK(4, 4)
#define UDPHS0_UDPHS_EPTCTLENB3_NYET_DIS_EPTCTLENB3_X(x)\
	(((x) & GENMASK(4, 4)) >> 4)

#define UDPHS0_UDPHS_EPTCTLENB3_INTDIS_DMA_EPTCTLENB3(x)\
	(((x) << 3) & GENMASK(3, 3))
#define UDPHS0_UDPHS_EPTCTLENB3_INTDIS_DMA_EPTCTLENB3_M GENMASK(3, 3)
#define UDPHS0_UDPHS_EPTCTLENB3_INTDIS_DMA_EPTCTLENB3_X(x)\
	(((x) & GENMASK(3, 3)) >> 3)

#define UDPHS0_UDPHS_EPTCTLENB3_AUTO_VALID_EPTCTLENB3(x)\
	(((x) << 1) & GENMASK(1, 1))
#define UDPHS0_UDPHS_EPTCTLENB3_AUTO_VALID_EPTCTLENB3_M GENMASK(1, 1)
#define UDPHS0_UDPHS_EPTCTLENB3_AUTO_VALID_EPTCTLENB3_X(x)\
	(((x) & GENMASK(1, 1)) >> 1)

#define UDPHS0_UDPHS_EPTCTLENB3_EPT_ENABL_EPTCTLENB3(x) ((x) & GENMASK(0, 0))
#define UDPHS0_UDPHS_EPTCTLENB3_EPT_ENABL_EPTCTLENB3_M GENMASK(0, 0)
#define UDPHS0_UDPHS_EPTCTLENB3_EPT_ENABL_EPTCTLENB3_X(x) ((x) & GENMASK(0, 0))

/*      UVOV:UVOV_REGS:UVOV_CTL */
#define UVOV_UVOV_CTL(t)          (t + 0x00)

#define UVOV_UVOV_CTL_MST_OVR_DET_EN(x)          (((x) << 1) & GENMASK(1, 1))
#define UVOV_UVOV_CTL_MST_OVR_DET_EN_M           GENMASK(1, 1)
#define UVOV_UVOV_CTL_MST_OVR_DET_EN_X(x)        (((x) & GENMASK(1, 1)) >> 1)

#define UVOV_UVOV_CTL_MST_UVR_DET_EN(x)          ((x) & GENMASK(0, 0))
#define UVOV_UVOV_CTL_MST_UVR_DET_EN_M           GENMASK(0, 0)
#define UVOV_UVOV_CTL_MST_UVR_DET_EN_X(x)        ((x) & GENMASK(0, 0))

/*      UVOV:UVOV_REGS:UVOV_INT_STS */
#define UVOV_UVOV_INT_STS(t)      (t + 0x04)

#define UVOV_UVOV_INT_STS_TRIM_INT_STS(x)        (((x) << 16) & GENMASK(23, 16))
#define UVOV_UVOV_INT_STS_TRIM_INT_STS_M         GENMASK(23, 16)
#define UVOV_UVOV_INT_STS_TRIM_INT_STS_X(x)      (((x) & GENMASK(23, 16)) >> 16)

#define UVOV_UVOV_INT_STS_OVR_INT_STS(x)         (((x) << 8) & GENMASK(15, 8))
#define UVOV_UVOV_INT_STS_OVR_INT_STS_M          GENMASK(15, 8)
#define UVOV_UVOV_INT_STS_OVR_INT_STS_X(x)       (((x) & GENMASK(15, 8)) >> 8)

#define UVOV_UVOV_INT_STS_UVR_INT_STS(x)         ((x) & GENMASK(7, 0))
#define UVOV_UVOV_INT_STS_UVR_INT_STS_M          GENMASK(7, 0)
#define UVOV_UVOV_INT_STS_UVR_INT_STS_X(x)       ((x) & GENMASK(7, 0))

/*      UVOV:UVOV_REGS:UVOV_INT_EN */
#define UVOV_UVOV_INT_EN(t)       (t + 0x08)

#define UVOV_UVOV_INT_EN_TRIM_INT_EN(x)          (((x) << 16) & GENMASK(23, 16))
#define UVOV_UVOV_INT_EN_TRIM_INT_EN_M           GENMASK(23, 16)
#define UVOV_UVOV_INT_EN_TRIM_INT_EN_X(x)        (((x) & GENMASK(23, 16)) >> 16)

#define UVOV_UVOV_INT_EN_OVR_INT_EN(x)           (((x) << 8) & GENMASK(15, 8))
#define UVOV_UVOV_INT_EN_OVR_INT_EN_M            GENMASK(15, 8)
#define UVOV_UVOV_INT_EN_OVR_INT_EN_X(x)         (((x) & GENMASK(15, 8)) >> 8)

#define UVOV_UVOV_INT_EN_UVR_INT_EN(x)           ((x) & GENMASK(7, 0))
#define UVOV_UVOV_INT_EN_UVR_INT_EN_M            GENMASK(7, 0)
#define UVOV_UVOV_INT_EN_UVR_INT_EN_X(x)         ((x) & GENMASK(7, 0))

/*      UVOV:UVOV_REGS:UVOV_INT_DIS */
#define UVOV_UVOV_INT_DIS(t)      (t + 0x0c)

#define UVOV_UVOV_INT_DIS_TRIM_INT_DIS(x)        (((x) << 16) & GENMASK(23, 16))
#define UVOV_UVOV_INT_DIS_TRIM_INT_DIS_M         GENMASK(23, 16)
#define UVOV_UVOV_INT_DIS_TRIM_INT_DIS_X(x)      (((x) & GENMASK(23, 16)) >> 16)

#define UVOV_UVOV_INT_DIS_OVR_INT_DIS(x)         (((x) << 8) & GENMASK(15, 8))
#define UVOV_UVOV_INT_DIS_OVR_INT_DIS_M          GENMASK(15, 8)
#define UVOV_UVOV_INT_DIS_OVR_INT_DIS_X(x)       (((x) & GENMASK(15, 8)) >> 8)

#define UVOV_UVOV_INT_DIS_UVR_INT_DIS(x)         ((x) & GENMASK(7, 0))
#define UVOV_UVOV_INT_DIS_UVR_INT_DIS_M          GENMASK(7, 0)
#define UVOV_UVOV_INT_DIS_UVR_INT_DIS_X(x)       ((x) & GENMASK(7, 0))

/*      UVOV:UVOV_CFG:UVOV_CFG0 */
#define UVOV_UVOV_CFG0(t, g)      (t + (0x20 + ((g) * 16)))

#define UVOV_UVOV_CFG0_OV_SLEEP_EN(x)            (((x) << 30) & GENMASK(30, 30))
#define UVOV_UVOV_CFG0_OV_SLEEP_EN_M             GENMASK(30, 30)
#define UVOV_UVOV_CFG0_OV_SLEEP_EN_X(x)          (((x) & GENMASK(30, 30)) >> 30)

#define UVOV_UVOV_CFG0_UV_SLEEP_EN(x)            (((x) << 29) & GENMASK(29, 29))
#define UVOV_UVOV_CFG0_UV_SLEEP_EN_M             GENMASK(29, 29)
#define UVOV_UVOV_CFG0_UV_SLEEP_EN_X(x)          (((x) & GENMASK(29, 29)) >> 29)

#define UVOV_UVOV_CFG0_OV_DEB_EN(x)              (((x) << 28) & GENMASK(28, 28))
#define UVOV_UVOV_CFG0_OV_DEB_EN_M               GENMASK(28, 28)
#define UVOV_UVOV_CFG0_OV_DEB_EN_X(x)            (((x) & GENMASK(28, 28)) >> 28)

#define UVOV_UVOV_CFG0_UV_DEB_EN(x)              (((x) << 27) & GENMASK(27, 27))
#define UVOV_UVOV_CFG0_UV_DEB_EN_M               GENMASK(27, 27)
#define UVOV_UVOV_CFG0_UV_DEB_EN_X(x)            (((x) & GENMASK(27, 27)) >> 27)

#define UVOV_UVOV_CFG0_TUNE_CDR(x)               (((x) << 24) & GENMASK(26, 24))
#define UVOV_UVOV_CFG0_TUNE_CDR_M                GENMASK(26, 24)
#define UVOV_UVOV_CFG0_TUNE_CDR_X(x)             (((x) & GENMASK(26, 24)) >> 24)

#define UVOV_UVOV_CFG0_TUNE_M(x)                 (((x) << 18) & GENMASK(23, 18))
#define UVOV_UVOV_CFG0_TUNE_M_M                  GENMASK(23, 18)
#define UVOV_UVOV_CFG0_TUNE_M_X(x)               (((x) & GENMASK(23, 18)) >> 18)

#define UVOV_UVOV_CFG0_TUNE_MAG(x)               (((x) << 12) & GENMASK(17, 12))
#define UVOV_UVOV_CFG0_TUNE_MAG_M                GENMASK(17, 12)
#define UVOV_UVOV_CFG0_TUNE_MAG_X(x)             (((x) & GENMASK(17, 12)) >> 12)

#define UVOV_UVOV_CFG0_OV_RST_EN(x)              (((x) << 11) & GENMASK(11, 11))
#define UVOV_UVOV_CFG0_OV_RST_EN_M               GENMASK(11, 11)
#define UVOV_UVOV_CFG0_OV_RST_EN_X(x)            (((x) & GENMASK(11, 11)) >> 11)

#define UVOV_UVOV_CFG0_UV_RST_EN(x)              (((x) << 10) & GENMASK(10, 10))
#define UVOV_UVOV_CFG0_UV_RST_EN_M               GENMASK(10, 10)
#define UVOV_UVOV_CFG0_UV_RST_EN_X(x)            (((x) & GENMASK(10, 10)) >> 10)

#define UVOV_UVOV_CFG0_VDD_REF_SEL(x)            (((x) << 8) & GENMASK(9, 8))
#define UVOV_UVOV_CFG0_VDD_REF_SEL_M             GENMASK(9, 8)
#define UVOV_UVOV_CFG0_VDD_REF_SEL_X(x)          (((x) & GENMASK(9, 8)) >> 8)

#define UVOV_UVOV_CFG0_SUPLVL_DET(x)             (((x) << 7) & GENMASK(7, 7))
#define UVOV_UVOV_CFG0_SUPLVL_DET_M              GENMASK(7, 7)
#define UVOV_UVOV_CFG0_SUPLVL_DET_X(x)           (((x) & GENMASK(7, 7)) >> 7)

#define UVOV_UVOV_CFG0_TRIM_EN(x)                (((x) << 6) & GENMASK(6, 6))
#define UVOV_UVOV_CFG0_TRIM_EN_M                 GENMASK(6, 6)
#define UVOV_UVOV_CFG0_TRIM_EN_X(x)              (((x) & GENMASK(6, 6)) >> 6)

#define UVOV_UVOV_CFG0_OVR_RNG_SEL(x)            (((x) << 4) & GENMASK(5, 4))
#define UVOV_UVOV_CFG0_OVR_RNG_SEL_M             GENMASK(5, 4)
#define UVOV_UVOV_CFG0_OVR_RNG_SEL_X(x)          (((x) & GENMASK(5, 4)) >> 4)

#define UVOV_UVOV_CFG0_UVR_RNG_SEL(x)            (((x) << 2) & GENMASK(3, 2))
#define UVOV_UVOV_CFG0_UVR_RNG_SEL_M             GENMASK(3, 2)
#define UVOV_UVOV_CFG0_UVR_RNG_SEL_X(x)          (((x) & GENMASK(3, 2)) >> 2)

#define UVOV_UVOV_CFG0_OVR_DET_EN(x)             (((x) << 1) & GENMASK(1, 1))
#define UVOV_UVOV_CFG0_OVR_DET_EN_M              GENMASK(1, 1)
#define UVOV_UVOV_CFG0_OVR_DET_EN_X(x)           (((x) & GENMASK(1, 1)) >> 1)

#define UVOV_UVOV_CFG0_UVR_DET_EN(x)             ((x) & GENMASK(0, 0))
#define UVOV_UVOV_CFG0_UVR_DET_EN_M              GENMASK(0, 0)
#define UVOV_UVOV_CFG0_UVR_DET_EN_X(x)           ((x) & GENMASK(0, 0))

/*      UVOV:UVOV_CFG:UVOV_CFG1 */
#define UVOV_UVOV_CFG1(t, g)      (t + (0x24 + ((g) * 16)))

#define UVOV_UVOV_CFG1_UVOV_DEB(x)               (((x) << 8) & GENMASK(31, 8))
#define UVOV_UVOV_CFG1_UVOV_DEB_M                GENMASK(31, 8)
#define UVOV_UVOV_CFG1_UVOV_DEB_X(x)             (((x) & GENMASK(31, 8)) >> 8)

#define UVOV_UVOV_CFG1_V33_STS(x)                (((x) << 3) & GENMASK(3, 3))
#define UVOV_UVOV_CFG1_V33_STS_M                 GENMASK(3, 3)
#define UVOV_UVOV_CFG1_V33_STS_X(x)              (((x) & GENMASK(3, 3)) >> 3)

#define UVOV_UVOV_CFG1_V25_STS(x)                (((x) << 2) & GENMASK(2, 2))
#define UVOV_UVOV_CFG1_V25_STS_M                 GENMASK(2, 2)
#define UVOV_UVOV_CFG1_V25_STS_X(x)              (((x) & GENMASK(2, 2)) >> 2)

#define UVOV_UVOV_CFG1_OV_STS(x)                 (((x) << 1) & GENMASK(1, 1))
#define UVOV_UVOV_CFG1_OV_STS_M                  GENMASK(1, 1)
#define UVOV_UVOV_CFG1_OV_STS_X(x)               (((x) & GENMASK(1, 1)) >> 1)

#define UVOV_UVOV_CFG1_UV_STS(x)                 ((x) & GENMASK(0, 0))
#define UVOV_UVOV_CFG1_UV_STS_M                  GENMASK(0, 0)
#define UVOV_UVOV_CFG1_UV_STS_X(x)               ((x) & GENMASK(0, 0))

/*      XDMAC:XDMAC_REG:XDMAC_GTYPE */
#define XDMAC_XDMAC_GTYPE(t)      (t + 0x00)

#define XDMAC_XDMAC_GTYPE_NB_REQ(x)              (((x) << 16) & GENMASK(22, 16))
#define XDMAC_XDMAC_GTYPE_NB_REQ_M               GENMASK(22, 16)
#define XDMAC_XDMAC_GTYPE_NB_REQ_X(x)            (((x) & GENMASK(22, 16)) >> 16)

#define XDMAC_XDMAC_GTYPE_FIFO_SZ(x)             (((x) << 5) & GENMASK(15, 5))
#define XDMAC_XDMAC_GTYPE_FIFO_SZ_M              GENMASK(15, 5)
#define XDMAC_XDMAC_GTYPE_FIFO_SZ_X(x)           (((x) & GENMASK(15, 5)) >> 5)

#define XDMAC_XDMAC_GTYPE_NB_CH(x)               ((x) & GENMASK(4, 0))
#define XDMAC_XDMAC_GTYPE_NB_CH_M                GENMASK(4, 0)
#define XDMAC_XDMAC_GTYPE_NB_CH_X(x)             ((x) & GENMASK(4, 0))

/*      XDMAC:XDMAC_REG:XDMAC_GIE */
#define XDMAC_XDMAC_GIE(t)        (t + 0x0c)

#define XDMAC_XDMAC_GIE_IEx(x)                   ((x) & GENMASK(15, 0))
#define XDMAC_XDMAC_GIE_IEx_M                    GENMASK(15, 0)
#define XDMAC_XDMAC_GIE_IEx_X(x)                 ((x) & GENMASK(15, 0))

/*      XDMAC:XDMAC_REG:XDMAC_GE */
#define XDMAC_XDMAC_GE(t)         (t + 0x1c)

#define XDMAC_XDMAC_GE_ENx(x)                    ((x) & GENMASK(15, 0))
#define XDMAC_XDMAC_GE_ENx_M                     GENMASK(15, 0)
#define XDMAC_XDMAC_GE_ENx_X(x)                  ((x) & GENMASK(15, 0))

/*      XDMAC:XDMAC_REG:XDMAC_GD */
#define XDMAC_XDMAC_GD(t)         (t + 0x20)

#define XDMAC_XDMAC_GD_DIx(x)                    ((x) & GENMASK(15, 0))
#define XDMAC_XDMAC_GD_DIx_M                     GENMASK(15, 0)
#define XDMAC_XDMAC_GD_DIx_X(x)                  ((x) & GENMASK(15, 0))

/*      XDMAC:XDMAC_REG:XDMAC_GS */
#define XDMAC_XDMAC_GS(t)         (t + 0x24)

#define XDMAC_XDMAC_GS_STx(x)                    ((x) & GENMASK(15, 0))
#define XDMAC_XDMAC_GS_STx_M                     GENMASK(15, 0)
#define XDMAC_XDMAC_GS_STx_X(x)                  ((x) & GENMASK(15, 0))

/*      XDMAC:XDMAC_REG:XDMAC_CIE_CH0 */
#define XDMAC_XDMAC_CIE_CH0(t)    (t + 0x60)

#define XDMAC_XDMAC_CIE_CH0_TCIE_CH0(x)          (((x) << 7) & GENMASK(7, 7))
#define XDMAC_XDMAC_CIE_CH0_TCIE_CH0_M           GENMASK(7, 7)
#define XDMAC_XDMAC_CIE_CH0_TCIE_CH0_X(x)        (((x) & GENMASK(7, 7)) >> 7)

#define XDMAC_XDMAC_CIE_CH0_ROIE_CH0(x)          (((x) << 6) & GENMASK(6, 6))
#define XDMAC_XDMAC_CIE_CH0_ROIE_CH0_M           GENMASK(6, 6)
#define XDMAC_XDMAC_CIE_CH0_ROIE_CH0_X(x)        (((x) & GENMASK(6, 6)) >> 6)

#define XDMAC_XDMAC_CIE_CH0_WBIE_CH0(x)          (((x) << 5) & GENMASK(5, 5))
#define XDMAC_XDMAC_CIE_CH0_WBIE_CH0_M           GENMASK(5, 5)
#define XDMAC_XDMAC_CIE_CH0_WBIE_CH0_X(x)        (((x) & GENMASK(5, 5)) >> 5)

#define XDMAC_XDMAC_CIE_CH0_RBIE_CH0(x)          (((x) << 4) & GENMASK(4, 4))
#define XDMAC_XDMAC_CIE_CH0_RBIE_CH0_M           GENMASK(4, 4)
#define XDMAC_XDMAC_CIE_CH0_RBIE_CH0_X(x)        (((x) & GENMASK(4, 4)) >> 4)

#define XDMAC_XDMAC_CIE_CH0_FIE_CH0(x)           (((x) << 3) & GENMASK(3, 3))
#define XDMAC_XDMAC_CIE_CH0_FIE_CH0_M            GENMASK(3, 3)
#define XDMAC_XDMAC_CIE_CH0_FIE_CH0_X(x)         (((x) & GENMASK(3, 3)) >> 3)

#define XDMAC_XDMAC_CIE_CH0_DIE_CH0(x)           (((x) << 2) & GENMASK(2, 2))
#define XDMAC_XDMAC_CIE_CH0_DIE_CH0_M            GENMASK(2, 2)
#define XDMAC_XDMAC_CIE_CH0_DIE_CH0_X(x)         (((x) & GENMASK(2, 2)) >> 2)

#define XDMAC_XDMAC_CIE_CH0_LIE_CH0(x)           (((x) << 1) & GENMASK(1, 1))
#define XDMAC_XDMAC_CIE_CH0_LIE_CH0_M            GENMASK(1, 1)
#define XDMAC_XDMAC_CIE_CH0_LIE_CH0_X(x)         (((x) & GENMASK(1, 1)) >> 1)

#define XDMAC_XDMAC_CIE_CH0_BIE_CH0(x)           ((x) & GENMASK(0, 0))
#define XDMAC_XDMAC_CIE_CH0_BIE_CH0_M            GENMASK(0, 0)
#define XDMAC_XDMAC_CIE_CH0_BIE_CH0_X(x)         ((x) & GENMASK(0, 0))

/*      XDMAC:XDMAC_REG:XDMAC_CID_CH0 */
#define XDMAC_XDMAC_CID_CH0(t)    (t + 0x64)

#define XDMAC_XDMAC_CID_CH0_TCID_CH0(x)          (((x) << 7) & GENMASK(7, 7))
#define XDMAC_XDMAC_CID_CH0_TCID_CH0_M           GENMASK(7, 7)
#define XDMAC_XDMAC_CID_CH0_TCID_CH0_X(x)        (((x) & GENMASK(7, 7)) >> 7)

#define XDMAC_XDMAC_CID_CH0_ROID_CH0(x)          (((x) << 6) & GENMASK(6, 6))
#define XDMAC_XDMAC_CID_CH0_ROID_CH0_M           GENMASK(6, 6)
#define XDMAC_XDMAC_CID_CH0_ROID_CH0_X(x)        (((x) & GENMASK(6, 6)) >> 6)

#define XDMAC_XDMAC_CID_CH0_WBEID_CH0(x)         (((x) << 5) & GENMASK(5, 5))
#define XDMAC_XDMAC_CID_CH0_WBEID_CH0_M          GENMASK(5, 5)
#define XDMAC_XDMAC_CID_CH0_WBEID_CH0_X(x)       (((x) & GENMASK(5, 5)) >> 5)

#define XDMAC_XDMAC_CID_CH0_RBEID_CH0(x)         (((x) << 4) & GENMASK(4, 4))
#define XDMAC_XDMAC_CID_CH0_RBEID_CH0_M          GENMASK(4, 4)
#define XDMAC_XDMAC_CID_CH0_RBEID_CH0_X(x)       (((x) & GENMASK(4, 4)) >> 4)

#define XDMAC_XDMAC_CID_CH0_FID_CH0(x)           (((x) << 3) & GENMASK(3, 3))
#define XDMAC_XDMAC_CID_CH0_FID_CH0_M            GENMASK(3, 3)
#define XDMAC_XDMAC_CID_CH0_FID_CH0_X(x)         (((x) & GENMASK(3, 3)) >> 3)

#define XDMAC_XDMAC_CID_CH0_DID_CH0(x)           (((x) << 2) & GENMASK(2, 2))
#define XDMAC_XDMAC_CID_CH0_DID_CH0_M            GENMASK(2, 2)
#define XDMAC_XDMAC_CID_CH0_DID_CH0_X(x)         (((x) & GENMASK(2, 2)) >> 2)

#define XDMAC_XDMAC_CID_CH0_LID_CH0(x)           (((x) << 1) & GENMASK(1, 1))
#define XDMAC_XDMAC_CID_CH0_LID_CH0_M            GENMASK(1, 1)
#define XDMAC_XDMAC_CID_CH0_LID_CH0_X(x)         (((x) & GENMASK(1, 1)) >> 1)

#define XDMAC_XDMAC_CID_CH0_BID_CH0(x)           ((x) & GENMASK(0, 0))
#define XDMAC_XDMAC_CID_CH0_BID_CH0_M            GENMASK(0, 0)
#define XDMAC_XDMAC_CID_CH0_BID_CH0_X(x)         ((x) & GENMASK(0, 0))

/*      XDMAC:XDMAC_REG:XDMAC_CIM_CH0 */
#define XDMAC_XDMAC_CIM_CH0(t)    (t + 0x68)

#define XDMAC_XDMAC_CIM_CH0_TCIM_CH0(x)          (((x) << 7) & GENMASK(7, 7))
#define XDMAC_XDMAC_CIM_CH0_TCIM_CH0_M           GENMASK(7, 7)
#define XDMAC_XDMAC_CIM_CH0_TCIM_CH0_X(x)        (((x) & GENMASK(7, 7)) >> 7)

#define XDMAC_XDMAC_CIM_CH0_ROIM_CH0(x)          (((x) << 6) & GENMASK(6, 6))
#define XDMAC_XDMAC_CIM_CH0_ROIM_CH0_M           GENMASK(6, 6)
#define XDMAC_XDMAC_CIM_CH0_ROIM_CH0_X(x)        (((x) & GENMASK(6, 6)) >> 6)

#define XDMAC_XDMAC_CIM_CH0_WBEIM_CH0(x)         (((x) << 5) & GENMASK(5, 5))
#define XDMAC_XDMAC_CIM_CH0_WBEIM_CH0_M          GENMASK(5, 5)
#define XDMAC_XDMAC_CIM_CH0_WBEIM_CH0_X(x)       (((x) & GENMASK(5, 5)) >> 5)

#define XDMAC_XDMAC_CIM_CH0_RBEIM_CH0(x)         (((x) << 4) & GENMASK(4, 4))
#define XDMAC_XDMAC_CIM_CH0_RBEIM_CH0_M          GENMASK(4, 4)
#define XDMAC_XDMAC_CIM_CH0_RBEIM_CH0_X(x)       (((x) & GENMASK(4, 4)) >> 4)

#define XDMAC_XDMAC_CIM_CH0_FIM_CH0(x)           (((x) << 3) & GENMASK(3, 3))
#define XDMAC_XDMAC_CIM_CH0_FIM_CH0_M            GENMASK(3, 3)
#define XDMAC_XDMAC_CIM_CH0_FIM_CH0_X(x)         (((x) & GENMASK(3, 3)) >> 3)

#define XDMAC_XDMAC_CIM_CH0_DIM_CH0(x)           (((x) << 2) & GENMASK(2, 2))
#define XDMAC_XDMAC_CIM_CH0_DIM_CH0_M            GENMASK(2, 2)
#define XDMAC_XDMAC_CIM_CH0_DIM_CH0_X(x)         (((x) & GENMASK(2, 2)) >> 2)

#define XDMAC_XDMAC_CIM_CH0_LIM_CH0(x)           (((x) << 1) & GENMASK(1, 1))
#define XDMAC_XDMAC_CIM_CH0_LIM_CH0_M            GENMASK(1, 1)
#define XDMAC_XDMAC_CIM_CH0_LIM_CH0_X(x)         (((x) & GENMASK(1, 1)) >> 1)

#define XDMAC_XDMAC_CIM_CH0_BIM_CH0(x)           ((x) & GENMASK(0, 0))
#define XDMAC_XDMAC_CIM_CH0_BIM_CH0_M            GENMASK(0, 0)
#define XDMAC_XDMAC_CIM_CH0_BIM_CH0_X(x)         ((x) & GENMASK(0, 0))

/*      XDMAC:XDMAC_REG:XDMAC_CIS_CH0 */
#define XDMAC_XDMAC_CIS_CH0(t)    (t + 0x6c)

#define XDMAC_XDMAC_CIS_CH0_TCIS_CH0(x)          (((x) << 7) & GENMASK(7, 7))
#define XDMAC_XDMAC_CIS_CH0_TCIS_CH0_M           GENMASK(7, 7)
#define XDMAC_XDMAC_CIS_CH0_TCIS_CH0_X(x)        (((x) & GENMASK(7, 7)) >> 7)

#define XDMAC_XDMAC_CIS_CH0_ROIS_CH0(x)          (((x) << 6) & GENMASK(6, 6))
#define XDMAC_XDMAC_CIS_CH0_ROIS_CH0_M           GENMASK(6, 6)
#define XDMAC_XDMAC_CIS_CH0_ROIS_CH0_X(x)        (((x) & GENMASK(6, 6)) >> 6)

#define XDMAC_XDMAC_CIS_CH0_WBEIS_CH0(x)         (((x) << 5) & GENMASK(5, 5))
#define XDMAC_XDMAC_CIS_CH0_WBEIS_CH0_M          GENMASK(5, 5)
#define XDMAC_XDMAC_CIS_CH0_WBEIS_CH0_X(x)       (((x) & GENMASK(5, 5)) >> 5)

#define XDMAC_XDMAC_CIS_CH0_RBEIS_CH0(x)         (((x) << 4) & GENMASK(4, 4))
#define XDMAC_XDMAC_CIS_CH0_RBEIS_CH0_M          GENMASK(4, 4)
#define XDMAC_XDMAC_CIS_CH0_RBEIS_CH0_X(x)       (((x) & GENMASK(4, 4)) >> 4)

#define XDMAC_XDMAC_CIS_CH0_FIS_CH0(x)           (((x) << 3) & GENMASK(3, 3))
#define XDMAC_XDMAC_CIS_CH0_FIS_CH0_M            GENMASK(3, 3)
#define XDMAC_XDMAC_CIS_CH0_FIS_CH0_X(x)         (((x) & GENMASK(3, 3)) >> 3)

#define XDMAC_XDMAC_CIS_CH0_DIS_CH0(x)           (((x) << 2) & GENMASK(2, 2))
#define XDMAC_XDMAC_CIS_CH0_DIS_CH0_M            GENMASK(2, 2)
#define XDMAC_XDMAC_CIS_CH0_DIS_CH0_X(x)         (((x) & GENMASK(2, 2)) >> 2)

#define XDMAC_XDMAC_CIS_CH0_LIS_CH0(x)           (((x) << 1) & GENMASK(1, 1))
#define XDMAC_XDMAC_CIS_CH0_LIS_CH0_M            GENMASK(1, 1)
#define XDMAC_XDMAC_CIS_CH0_LIS_CH0_X(x)         (((x) & GENMASK(1, 1)) >> 1)

#define XDMAC_XDMAC_CIS_CH0_BIS_CH0(x)           ((x) & GENMASK(0, 0))
#define XDMAC_XDMAC_CIS_CH0_BIS_CH0_M            GENMASK(0, 0)
#define XDMAC_XDMAC_CIS_CH0_BIS_CH0_X(x)         ((x) & GENMASK(0, 0))

/*      XDMAC:XDMAC_REG:XDMAC_CSA_CH0 */
#define XDMAC_XDMAC_CSA_CH0(t)    (t + 0x70)

/*      XDMAC:XDMAC_REG:XDMAC_CDA_CH0 */
#define XDMAC_XDMAC_CDA_CH0(t)    (t + 0x74)

/*      XDMAC:XDMAC_REG:XDMAC_CNDA_CH0 */
#define XDMAC_XDMAC_CNDA_CH0(t)   (t + 0x78)

#define XDMAC_XDMAC_CNDA_CH0_NDA_CH0(x)          (((x) << 2) & GENMASK(31, 2))
#define XDMAC_XDMAC_CNDA_CH0_NDA_CH0_M           GENMASK(31, 2)
#define XDMAC_XDMAC_CNDA_CH0_NDA_CH0_X(x)        (((x) & GENMASK(31, 2)) >> 2)

/*      XDMAC:XDMAC_REG:XDMAC_CNDC_CH0 */
#define XDMAC_XDMAC_CNDC_CH0(t)   (t + 0x7c)

#define XDMAC_XDMAC_CNDC_CH0_QOS_CH0(x)          (((x) << 5) & GENMASK(6, 5))
#define XDMAC_XDMAC_CNDC_CH0_QOS_CH0_M           GENMASK(6, 5)
#define XDMAC_XDMAC_CNDC_CH0_QOS_CH0_X(x)        (((x) & GENMASK(6, 5)) >> 5)

#define XDMAC_XDMAC_CNDC_CH0_NDVIEW_CH0(x)       (((x) << 3) & GENMASK(4, 3))
#define XDMAC_XDMAC_CNDC_CH0_NDVIEW_CH0_M        GENMASK(4, 3)
#define XDMAC_XDMAC_CNDC_CH0_NDVIEW_CH0_X(x)     (((x) & GENMASK(4, 3)) >> 3)

#define XDMAC_XDMAC_CNDC_CH0_NDDUP_CH0(x)        (((x) << 2) & GENMASK(2, 2))
#define XDMAC_XDMAC_CNDC_CH0_NDDUP_CH0_M         GENMASK(2, 2)
#define XDMAC_XDMAC_CNDC_CH0_NDDUP_CH0_X(x)      (((x) & GENMASK(2, 2)) >> 2)

#define XDMAC_XDMAC_CNDC_CH0_NDSUP_CH0(x)        (((x) << 1) & GENMASK(1, 1))
#define XDMAC_XDMAC_CNDC_CH0_NDSUP_CH0_M         GENMASK(1, 1)
#define XDMAC_XDMAC_CNDC_CH0_NDSUP_CH0_X(x)      (((x) & GENMASK(1, 1)) >> 1)

#define XDMAC_XDMAC_CNDC_CH0_NDE_CH0(x)          ((x) & GENMASK(0, 0))
#define XDMAC_XDMAC_CNDC_CH0_NDE_CH0_M           GENMASK(0, 0)
#define XDMAC_XDMAC_CNDC_CH0_NDE_CH0_X(x)        ((x) & GENMASK(0, 0))

/*      XDMAC:XDMAC_REG:XDMAC_CUBC_CH0 */
#define XDMAC_XDMAC_CUBC_CH0(t)   (t + 0x80)

#define XDMAC_XDMAC_CUBC_CH0_UBLEN_CH0(x)        ((x) & GENMASK(23, 0))
#define XDMAC_XDMAC_CUBC_CH0_UBLEN_CH0_M         GENMASK(23, 0)
#define XDMAC_XDMAC_CUBC_CH0_UBLEN_CH0_X(x)      ((x) & GENMASK(23, 0))

/*      XDMAC:XDMAC_REG:XDMAC_CBC_CH0 */
#define XDMAC_XDMAC_CBC_CH0(t)    (t + 0x84)

#define XDMAC_XDMAC_CBC_CH0_BLEN_CH0(x)          ((x) & GENMASK(11, 0))
#define XDMAC_XDMAC_CBC_CH0_BLEN_CH0_M           GENMASK(11, 0)
#define XDMAC_XDMAC_CBC_CH0_BLEN_CH0_X(x)        ((x) & GENMASK(11, 0))

/*      XDMAC:XDMAC_REG:XDMAC_CC_CH0 */
#define XDMAC_XDMAC_CC_CH0(t)     (t + 0x88)

#define XDMAC_XDMAC_CC_CH0_PERID_CH0(x)          (((x) << 24) & GENMASK(30, 24))
#define XDMAC_XDMAC_CC_CH0_PERID_CH0_M           GENMASK(30, 24)
#define XDMAC_XDMAC_CC_CH0_PERID_CH0_X(x)        (((x) & GENMASK(30, 24)) >> 24)

#define XDMAC_XDMAC_CC_CH0_WRIP_CH0(x)           (((x) << 23) & GENMASK(23, 23))
#define XDMAC_XDMAC_CC_CH0_WRIP_CH0_M            GENMASK(23, 23)
#define XDMAC_XDMAC_CC_CH0_WRIP_CH0_X(x)         (((x) & GENMASK(23, 23)) >> 23)

#define XDMAC_XDMAC_CC_CH0_RDIP_CH0(x)           (((x) << 22) & GENMASK(22, 22))
#define XDMAC_XDMAC_CC_CH0_RDIP_CH0_M            GENMASK(22, 22)
#define XDMAC_XDMAC_CC_CH0_RDIP_CH0_X(x)         (((x) & GENMASK(22, 22)) >> 22)

#define XDMAC_XDMAC_CC_CH0_INITD_CH0(x)          (((x) << 21) & GENMASK(21, 21))
#define XDMAC_XDMAC_CC_CH0_INITD_CH0_M           GENMASK(21, 21)
#define XDMAC_XDMAC_CC_CH0_INITD_CH0_X(x)        (((x) & GENMASK(21, 21)) >> 21)

#define XDMAC_XDMAC_CC_CH0_DAM_CH0(x)            (((x) << 18) & GENMASK(19, 18))
#define XDMAC_XDMAC_CC_CH0_DAM_CH0_M             GENMASK(19, 18)
#define XDMAC_XDMAC_CC_CH0_DAM_CH0_X(x)          (((x) & GENMASK(19, 18)) >> 18)

#define XDMAC_XDMAC_CC_CH0_SAM_CH0(x)            (((x) << 16) & GENMASK(17, 16))
#define XDMAC_XDMAC_CC_CH0_SAM_CH0_M             GENMASK(17, 16)
#define XDMAC_XDMAC_CC_CH0_SAM_CH0_X(x)          (((x) & GENMASK(17, 16)) >> 16)

#define XDMAC_XDMAC_CC_CH0_DWIDTH_CH0(x)         (((x) << 11) & GENMASK(12, 11))
#define XDMAC_XDMAC_CC_CH0_DWIDTH_CH0_M          GENMASK(12, 11)
#define XDMAC_XDMAC_CC_CH0_DWIDTH_CH0_X(x)       (((x) & GENMASK(12, 11)) >> 11)

#define XDMAC_XDMAC_CC_CH0_CSIZE_CH0(x)          (((x) << 8) & GENMASK(10, 8))
#define XDMAC_XDMAC_CC_CH0_CSIZE_CH0_M           GENMASK(10, 8)
#define XDMAC_XDMAC_CC_CH0_CSIZE_CH0_X(x)        (((x) & GENMASK(10, 8)) >> 8)

#define XDMAC_XDMAC_CC_CH0_MEMSET_CH0(x)         (((x) << 7) & GENMASK(7, 7))
#define XDMAC_XDMAC_CC_CH0_MEMSET_CH0_M          GENMASK(7, 7)
#define XDMAC_XDMAC_CC_CH0_MEMSET_CH0_X(x)       (((x) & GENMASK(7, 7)) >> 7)

#define XDMAC_XDMAC_CC_CH0_SWREQ_CH0(x)          (((x) << 6) & GENMASK(6, 6))
#define XDMAC_XDMAC_CC_CH0_SWREQ_CH0_M           GENMASK(6, 6)
#define XDMAC_XDMAC_CC_CH0_SWREQ_CH0_X(x)        (((x) & GENMASK(6, 6)) >> 6)

#define XDMAC_XDMAC_CC_CH0_PROT_CH0(x)           (((x) << 5) & GENMASK(5, 5))
#define XDMAC_XDMAC_CC_CH0_PROT_CH0_M            GENMASK(5, 5)
#define XDMAC_XDMAC_CC_CH0_PROT_CH0_X(x)         (((x) & GENMASK(5, 5)) >> 5)

#define XDMAC_XDMAC_CC_CH0_DSYNC_CH0(x)          (((x) << 4) & GENMASK(4, 4))
#define XDMAC_XDMAC_CC_CH0_DSYNC_CH0_M           GENMASK(4, 4)
#define XDMAC_XDMAC_CC_CH0_DSYNC_CH0_X(x)        (((x) & GENMASK(4, 4)) >> 4)

#define XDMAC_XDMAC_CC_CH0_MBSIZE_CH0(x)         (((x) << 1) & GENMASK(2, 1))
#define XDMAC_XDMAC_CC_CH0_MBSIZE_CH0_M          GENMASK(2, 1)
#define XDMAC_XDMAC_CC_CH0_MBSIZE_CH0_X(x)       (((x) & GENMASK(2, 1)) >> 1)

#define XDMAC_XDMAC_CC_CH0_TYPE_CH0(x)           ((x) & GENMASK(0, 0))
#define XDMAC_XDMAC_CC_CH0_TYPE_CH0_M            GENMASK(0, 0)
#define XDMAC_XDMAC_CC_CH0_TYPE_CH0_X(x)         ((x) & GENMASK(0, 0))

/*      XDMAC:XDMAC_REG:XDMAC_CDS_MSP_CH0 */
#define XDMAC_XDMAC_CDS_MSP_CH0(t) (t + 0x8c)

#define XDMAC_XDMAC_CDS_MSP_CH0_DDS_MSP_CH0(x)   (((x) << 16) & GENMASK(31, 16))
#define XDMAC_XDMAC_CDS_MSP_CH0_DDS_MSP_CH0_M    GENMASK(31, 16)
#define XDMAC_XDMAC_CDS_MSP_CH0_DDS_MSP_CH0_X(x) (((x) & GENMASK(31, 16)) >> 16)

#define XDMAC_XDMAC_CDS_MSP_CH0_SDS_MSP_CH0(x)   ((x) & GENMASK(15, 0))
#define XDMAC_XDMAC_CDS_MSP_CH0_SDS_MSP_CH0_M    GENMASK(15, 0)
#define XDMAC_XDMAC_CDS_MSP_CH0_SDS_MSP_CH0_X(x) ((x) & GENMASK(15, 0))

/*      XDMAC:XDMAC_REG:XDMAC_CSUS_CH0 */
#define XDMAC_XDMAC_CSUS_CH0(t)   (t + 0x90)

#define XDMAC_XDMAC_CSUS_CH0_SUBS_CH0(x)         ((x) & GENMASK(23, 0))
#define XDMAC_XDMAC_CSUS_CH0_SUBS_CH0_M          GENMASK(23, 0)
#define XDMAC_XDMAC_CSUS_CH0_SUBS_CH0_X(x)       ((x) & GENMASK(23, 0))

/*      XDMAC:XDMAC_REG:XDMAC_CDUS_CH0 */
#define XDMAC_XDMAC_CDUS_CH0(t)   (t + 0x94)

#define XDMAC_XDMAC_CDUS_CH0_DUBS_CH0(x)         ((x) & GENMASK(23, 0))
#define XDMAC_XDMAC_CDUS_CH0_DUBS_CH0_M          GENMASK(23, 0)
#define XDMAC_XDMAC_CDUS_CH0_DUBS_CH0_X(x)       ((x) & GENMASK(23, 0))

/*      XDMAC:XDMAC_REG:XDMAC_CTCS_CH0 */
#define XDMAC_XDMAC_CTCS_CH0(t)   (t + 0x98)

#define XDMAC_XDMAC_CTCS_CH0_TC_CH0(x)           ((x) & GENMASK(23, 0))
#define XDMAC_XDMAC_CTCS_CH0_TC_CH0_M            GENMASK(23, 0)
#define XDMAC_XDMAC_CTCS_CH0_TC_CH0_X(x)         ((x) & GENMASK(23, 0))

/*      XDMAC:XDMAC_REG:XDMAC_CIE_CH1 */
#define XDMAC_XDMAC_CIE_CH1(t)    (t + 0xa0)

#define XDMAC_XDMAC_CIE_CH1_TCIE_CH1(x)          (((x) << 7) & GENMASK(7, 7))
#define XDMAC_XDMAC_CIE_CH1_TCIE_CH1_M           GENMASK(7, 7)
#define XDMAC_XDMAC_CIE_CH1_TCIE_CH1_X(x)        (((x) & GENMASK(7, 7)) >> 7)

#define XDMAC_XDMAC_CIE_CH1_ROIE_CH1(x)          (((x) << 6) & GENMASK(6, 6))
#define XDMAC_XDMAC_CIE_CH1_ROIE_CH1_M           GENMASK(6, 6)
#define XDMAC_XDMAC_CIE_CH1_ROIE_CH1_X(x)        (((x) & GENMASK(6, 6)) >> 6)

#define XDMAC_XDMAC_CIE_CH1_WBIE_CH1(x)          (((x) << 5) & GENMASK(5, 5))
#define XDMAC_XDMAC_CIE_CH1_WBIE_CH1_M           GENMASK(5, 5)
#define XDMAC_XDMAC_CIE_CH1_WBIE_CH1_X(x)        (((x) & GENMASK(5, 5)) >> 5)

#define XDMAC_XDMAC_CIE_CH1_RBIE_CH1(x)          (((x) << 4) & GENMASK(4, 4))
#define XDMAC_XDMAC_CIE_CH1_RBIE_CH1_M           GENMASK(4, 4)
#define XDMAC_XDMAC_CIE_CH1_RBIE_CH1_X(x)        (((x) & GENMASK(4, 4)) >> 4)

#define XDMAC_XDMAC_CIE_CH1_FIE_CH1(x)           (((x) << 3) & GENMASK(3, 3))
#define XDMAC_XDMAC_CIE_CH1_FIE_CH1_M            GENMASK(3, 3)
#define XDMAC_XDMAC_CIE_CH1_FIE_CH1_X(x)         (((x) & GENMASK(3, 3)) >> 3)

#define XDMAC_XDMAC_CIE_CH1_DIE_CH1(x)           (((x) << 2) & GENMASK(2, 2))
#define XDMAC_XDMAC_CIE_CH1_DIE_CH1_M            GENMASK(2, 2)
#define XDMAC_XDMAC_CIE_CH1_DIE_CH1_X(x)         (((x) & GENMASK(2, 2)) >> 2)

#define XDMAC_XDMAC_CIE_CH1_LIE_CH1(x)           (((x) << 1) & GENMASK(1, 1))
#define XDMAC_XDMAC_CIE_CH1_LIE_CH1_M            GENMASK(1, 1)
#define XDMAC_XDMAC_CIE_CH1_LIE_CH1_X(x)         (((x) & GENMASK(1, 1)) >> 1)

#define XDMAC_XDMAC_CIE_CH1_BIE_CH1(x)           ((x) & GENMASK(0, 0))
#define XDMAC_XDMAC_CIE_CH1_BIE_CH1_M            GENMASK(0, 0)
#define XDMAC_XDMAC_CIE_CH1_BIE_CH1_X(x)         ((x) & GENMASK(0, 0))

/*      XDMAC:XDMAC_REG:XDMAC_VERSION */
#define XDMAC_XDMAC_VERSION(t)    (t + 0xffc)

#define XDMAC_XDMAC_VERSION_MFN(x)               (((x) << 16) & GENMASK(18, 16))
#define XDMAC_XDMAC_VERSION_MFN_M                GENMASK(18, 16)
#define XDMAC_XDMAC_VERSION_MFN_X(x)             (((x) & GENMASK(18, 16)) >> 16)

#define XDMAC_XDMAC_VERSION_VERSION(x)           ((x) & GENMASK(11, 0))
#define XDMAC_XDMAC_VERSION_VERSION_M            GENMASK(11, 0)
#define XDMAC_XDMAC_VERSION_VERSION_X(x)         ((x) & GENMASK(11, 0))


#endif /* _LAN966X_REGS_SR_H_ */
