/*
 * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

/* This file is autogenerated by cml-utils 2022-09-21 12:22:06 +0200.
 * Commit ID: 83c9e9a057a7d46878acb7c7b3b3efd62878baf2
 */

/* LAN969X registers */

#ifndef _LAN969X_DDR_SR_H_
#define _LAN969X_DDR_SR_H_

/*      CPU:CPU_REGS:RESET */
#define CPU_RESET(t)              (t + 0x84)

#define CPU_RESET_VCORE_RST(x)                   (((x) << 7) & GENMASK(7, 7))
#define CPU_RESET_VCORE_RST_M                    GENMASK(7, 7)
#define CPU_RESET_VCORE_RST_X(x)                 (((x) & GENMASK(7, 7)) >> 7)

#define CPU_RESET_CPU_CORE_0_WARM_RST(x)         (((x) << 6) & GENMASK(6, 6))
#define CPU_RESET_CPU_CORE_0_WARM_RST_M          GENMASK(6, 6)
#define CPU_RESET_CPU_CORE_0_WARM_RST_X(x)       (((x) & GENMASK(6, 6)) >> 6)

#define CPU_RESET_PROC_DBG_RST(x)                (((x) << 5) & GENMASK(5, 5))
#define CPU_RESET_PROC_DBG_RST_M                 GENMASK(5, 5)
#define CPU_RESET_PROC_DBG_RST_X(x)              (((x) & GENMASK(5, 5)) >> 5)

#define CPU_RESET_JTAG_RST(x)                    (((x) << 4) & GENMASK(4, 4))
#define CPU_RESET_JTAG_RST_M                     GENMASK(4, 4)
#define CPU_RESET_JTAG_RST_X(x)                  (((x) & GENMASK(4, 4)) >> 4)

#define CPU_RESET_CPU_L2_RST(x)                  (((x) << 3) & GENMASK(3, 3))
#define CPU_RESET_CPU_L2_RST_M                   GENMASK(3, 3)
#define CPU_RESET_CPU_L2_RST_X(x)                (((x) & GENMASK(3, 3)) >> 3)

#define CPU_RESET_MEM_RST(x)                     (((x) << 2) & GENMASK(2, 2))
#define CPU_RESET_MEM_RST_M                      GENMASK(2, 2)
#define CPU_RESET_MEM_RST_X(x)                   (((x) & GENMASK(2, 2)) >> 2)

#define CPU_RESET_WDT_FORCE_RST(x)               (((x) << 1) & GENMASK(1, 1))
#define CPU_RESET_WDT_FORCE_RST_M                GENMASK(1, 1)
#define CPU_RESET_WDT_FORCE_RST_X(x)             (((x) & GENMASK(1, 1)) >> 1)

#define CPU_RESET_CPU_CORE_0_COLD_RST(x)         ((x) & GENMASK(0, 0))
#define CPU_RESET_CPU_CORE_0_COLD_RST_M          GENMASK(0, 0)
#define CPU_RESET_CPU_CORE_0_COLD_RST_X(x)       ((x) & GENMASK(0, 0))

/*      CPU:CPU_REGS:RESET_PROT_STAT */
#define CPU_RESET_PROT_STAT(t)    (t + 0x88)

#define CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE(x) (((x) << 5) & GENMASK(5, 5))
#define CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE_M GENMASK(5, 5)
#define CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE_X(x) (((x) & GENMASK(5, 5)) >> 5)

#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_AMBA(x) (((x) << 4) & GENMASK(4, 4))
#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_AMBA_M GENMASK(4, 4)
#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_AMBA_X(x)\
	(((x) & GENMASK(4, 4)) >> 4)

#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_WDT(x) (((x) << 3) & GENMASK(3, 3))
#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_WDT_M GENMASK(3, 3)
#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_WDT_X(x) (((x) & GENMASK(3, 3)) >> 3)

#define CPU_RESET_PROT_STAT_VCORE_WDT_RST_PROT_WDT(x)\
	(((x) << 2) & GENMASK(2, 2))
#define CPU_RESET_PROT_STAT_VCORE_WDT_RST_PROT_WDT_M GENMASK(2, 2)
#define CPU_RESET_PROT_STAT_VCORE_WDT_RST_PROT_WDT_X(x)\
	(((x) & GENMASK(2, 2)) >> 2)

#define CPU_RESET_PROT_STAT_VCORE_WDT_RST_STAT(x) (((x) << 1) & GENMASK(1, 1))
#define CPU_RESET_PROT_STAT_VCORE_WDT_RST_STAT_M GENMASK(1, 1)
#define CPU_RESET_PROT_STAT_VCORE_WDT_RST_STAT_X(x) (((x) & GENMASK(1, 1)) >> 1)

#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_PCIE(x) ((x) & GENMASK(0, 0))
#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_PCIE_M GENMASK(0, 0)
#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_PCIE_X(x) ((x) & GENMASK(0, 0))

/*      CPU:DDRCTRL:DDRCTRL_CLK */
#define CPU_DDRCTRL_CLK(t)        (t + 0x2ec)

#define CPU_DDRCTRL_CLK_DDR_CLK_ENA(x)           ((x) & GENMASK(0, 0))
#define CPU_DDRCTRL_CLK_DDR_CLK_ENA_M            GENMASK(0, 0)
#define CPU_DDRCTRL_CLK_DDR_CLK_ENA_X(x)         ((x) & GENMASK(0, 0))

#define CPU_DDRCTRL_CLK_DDR_AXI0_CLK_ENA(x)      (((x) << 1) & GENMASK(1, 1))
#define CPU_DDRCTRL_CLK_DDR_AXI0_CLK_ENA_M       GENMASK(1, 1)
#define CPU_DDRCTRL_CLK_DDR_AXI0_CLK_ENA_X(x)    (((x) & GENMASK(1, 1)) >> 1)

#define CPU_DDRCTRL_CLK_DDR_AXI1_CLK_ENA(x)      (((x) << 2) & GENMASK(2, 2))
#define CPU_DDRCTRL_CLK_DDR_AXI1_CLK_ENA_M       GENMASK(2, 2)
#define CPU_DDRCTRL_CLK_DDR_AXI1_CLK_ENA_X(x)    (((x) & GENMASK(2, 2)) >> 2)

#define CPU_DDRCTRL_CLK_DDR_AXI2_CLK_ENA(x)      (((x) << 3) & GENMASK(3, 3))
#define CPU_DDRCTRL_CLK_DDR_AXI2_CLK_ENA_M       GENMASK(3, 3)
#define CPU_DDRCTRL_CLK_DDR_AXI2_CLK_ENA_X(x)    (((x) & GENMASK(3, 3)) >> 3)

#define CPU_DDRCTRL_CLK_DDR_APB_CLK_ENA(x)       (((x) << 4) & GENMASK(4, 4))
#define CPU_DDRCTRL_CLK_DDR_APB_CLK_ENA_M        GENMASK(4, 4)
#define CPU_DDRCTRL_CLK_DDR_APB_CLK_ENA_X(x)     (((x) & GENMASK(4, 4)) >> 4)

#define CPU_DDRCTRL_CLK_DDRPHY_CTL_CLK_ENA(x)    (((x) << 5) & GENMASK(5, 5))
#define CPU_DDRCTRL_CLK_DDRPHY_CTL_CLK_ENA_M     GENMASK(5, 5)
#define CPU_DDRCTRL_CLK_DDRPHY_CTL_CLK_ENA_X(x)  (((x) & GENMASK(5, 5)) >> 5)

#define CPU_DDRCTRL_CLK_DDRPHY_APB_CLK_ENA(x)    (((x) << 6) & GENMASK(6, 6))
#define CPU_DDRCTRL_CLK_DDRPHY_APB_CLK_ENA_M     GENMASK(6, 6)
#define CPU_DDRCTRL_CLK_DDRPHY_APB_CLK_ENA_X(x)  (((x) & GENMASK(6, 6)) >> 6)

#define CPU_DDRCTRL_CLK_RAM_RING_ENA(x)          (((x) << 7) & GENMASK(7, 7))
#define CPU_DDRCTRL_CLK_RAM_RING_ENA_M           GENMASK(7, 7)
#define CPU_DDRCTRL_CLK_RAM_RING_ENA_X(x)        (((x) & GENMASK(7, 7)) >> 7)

/*      CPU:DDRCTRL:DDRCTRL_RST */
#define CPU_DDRCTRL_RST(t)        (t + 0x2f0)

#define CPU_DDRCTRL_RST_DDRC_RST(x)              ((x) & GENMASK(0, 0))
#define CPU_DDRCTRL_RST_DDRC_RST_M               GENMASK(0, 0)
#define CPU_DDRCTRL_RST_DDRC_RST_X(x)            ((x) & GENMASK(0, 0))

#define CPU_DDRCTRL_RST_DDR_AXI0_RST(x)          (((x) << 1) & GENMASK(1, 1))
#define CPU_DDRCTRL_RST_DDR_AXI0_RST_M           GENMASK(1, 1)
#define CPU_DDRCTRL_RST_DDR_AXI0_RST_X(x)        (((x) & GENMASK(1, 1)) >> 1)

#define CPU_DDRCTRL_RST_DDR_AXI1_RST(x)          (((x) << 2) & GENMASK(2, 2))
#define CPU_DDRCTRL_RST_DDR_AXI1_RST_M           GENMASK(2, 2)
#define CPU_DDRCTRL_RST_DDR_AXI1_RST_X(x)        (((x) & GENMASK(2, 2)) >> 2)

#define CPU_DDRCTRL_RST_DDR_AXI2_RST(x)          (((x) << 3) & GENMASK(3, 3))
#define CPU_DDRCTRL_RST_DDR_AXI2_RST_M           GENMASK(3, 3)
#define CPU_DDRCTRL_RST_DDR_AXI2_RST_X(x)        (((x) & GENMASK(3, 3)) >> 3)

#define CPU_DDRCTRL_RST_DDR_APB_RST(x)           (((x) << 4) & GENMASK(4, 4))
#define CPU_DDRCTRL_RST_DDR_APB_RST_M            GENMASK(4, 4)
#define CPU_DDRCTRL_RST_DDR_APB_RST_X(x)         (((x) & GENMASK(4, 4)) >> 4)

#define CPU_DDRCTRL_RST_DDRPHY_CTL_RST(x)        (((x) << 5) & GENMASK(5, 5))
#define CPU_DDRCTRL_RST_DDRPHY_CTL_RST_M         GENMASK(5, 5)
#define CPU_DDRCTRL_RST_DDRPHY_CTL_RST_X(x)      (((x) & GENMASK(5, 5)) >> 5)

#define CPU_DDRCTRL_RST_FPGA_DDRPHY_SOFT_RST(x)  (((x) << 6) & GENMASK(6, 6))
#define CPU_DDRCTRL_RST_FPGA_DDRPHY_SOFT_RST_M   GENMASK(6, 6)
#define CPU_DDRCTRL_RST_FPGA_DDRPHY_SOFT_RST_X(x) (((x) & GENMASK(6, 6)) >> 6)

#define CPU_DDRCTRL_RST_DDRPHY_APB_RST(x)        (((x) << 7) & GENMASK(7, 7))
#define CPU_DDRCTRL_RST_DDRPHY_APB_RST_M         GENMASK(7, 7)
#define CPU_DDRCTRL_RST_DDRPHY_APB_RST_X(x)      (((x) & GENMASK(7, 7)) >> 7)

/*      CPU:DDRCTRL:DDRC_INTR_RAW_STAT */
#define CPU_DDRC_INTR_RAW_STAT(t) (t + 0x2f4)

#define CPU_DDRC_INTR_RAW_STAT_SBR_DONE_INTR_RAW_STAT(x) ((x) & GENMASK(0, 0))
#define CPU_DDRC_INTR_RAW_STAT_SBR_DONE_INTR_RAW_STAT_M GENMASK(0, 0)
#define CPU_DDRC_INTR_RAW_STAT_SBR_DONE_INTR_RAW_STAT_X(x) ((x) & GENMASK(0, 0))

#define CPU_DDRC_INTR_RAW_STAT_ECC_CORRECTED_ERR_INTR_RAW_STAT(x)\
	(((x) << 1) & GENMASK(1, 1))
#define CPU_DDRC_INTR_RAW_STAT_ECC_CORRECTED_ERR_INTR_RAW_STAT_M GENMASK(1, 1)
#define CPU_DDRC_INTR_RAW_STAT_ECC_CORRECTED_ERR_INTR_RAW_STAT_X(x)\
	(((x) & GENMASK(1, 1)) >> 1)

#define CPU_DDRC_INTR_RAW_STAT_ECC_UNCORRECTED_ERR_INTR_RAW_STAT(x)\
	(((x) << 2) & GENMASK(2, 2))
#define CPU_DDRC_INTR_RAW_STAT_ECC_UNCORRECTED_ERR_INTR_RAW_STAT_M GENMASK(2, 2)
#define CPU_DDRC_INTR_RAW_STAT_ECC_UNCORRECTED_ERR_INTR_RAW_STAT_X(x)\
	(((x) & GENMASK(2, 2)) >> 2)

#define CPU_DDRC_INTR_RAW_STAT_ECC_AP_ERR_INTR_RAW_STAT(x)\
	(((x) << 3) & GENMASK(3, 3))
#define CPU_DDRC_INTR_RAW_STAT_ECC_AP_ERR_INTR_RAW_STAT_M GENMASK(3, 3)
#define CPU_DDRC_INTR_RAW_STAT_ECC_AP_ERR_INTR_RAW_STAT_X(x)\
	(((x) & GENMASK(3, 3)) >> 3)

#define CPU_DDRC_INTR_RAW_STAT_DFI_ALERT_ERR_INTR_RAW_STAT(x)\
	(((x) << 4) & GENMASK(4, 4))
#define CPU_DDRC_INTR_RAW_STAT_DFI_ALERT_ERR_INTR_RAW_STAT_M GENMASK(4, 4)
#define CPU_DDRC_INTR_RAW_STAT_DFI_ALERT_ERR_INTR_RAW_STAT_X(x)\
	(((x) & GENMASK(4, 4)) >> 4)

/*      CPU:DDRCTRL:DDRC_INTR_MASK */
#define CPU_DDRC_INTR_MASK(t)     (t + 0x2f8)

#define CPU_DDRC_INTR_MASK_SBR_DONE_INTR_MASK(x) ((x) & GENMASK(0, 0))
#define CPU_DDRC_INTR_MASK_SBR_DONE_INTR_MASK_M  GENMASK(0, 0)
#define CPU_DDRC_INTR_MASK_SBR_DONE_INTR_MASK_X(x) ((x) & GENMASK(0, 0))

#define CPU_DDRC_INTR_MASK_ECC_CORRECTED_ERR_INTR_MASK(x)\
	(((x) << 1) & GENMASK(1, 1))
#define CPU_DDRC_INTR_MASK_ECC_CORRECTED_ERR_INTR_MASK_M GENMASK(1, 1)
#define CPU_DDRC_INTR_MASK_ECC_CORRECTED_ERR_INTR_MASK_X(x)\
	(((x) & GENMASK(1, 1)) >> 1)

#define CPU_DDRC_INTR_MASK_ECC_UNCORRECTED_ERR_INTR_MASK(x)\
	(((x) << 2) & GENMASK(2, 2))
#define CPU_DDRC_INTR_MASK_ECC_UNCORRECTED_ERR_INTR_MASK_M GENMASK(2, 2)
#define CPU_DDRC_INTR_MASK_ECC_UNCORRECTED_ERR_INTR_MASK_X(x)\
	(((x) & GENMASK(2, 2)) >> 2)

#define CPU_DDRC_INTR_MASK_ECC_AP_ERR_INTR_MASK(x) (((x) << 3) & GENMASK(3, 3))
#define CPU_DDRC_INTR_MASK_ECC_AP_ERR_INTR_MASK_M GENMASK(3, 3)
#define CPU_DDRC_INTR_MASK_ECC_AP_ERR_INTR_MASK_X(x)\
	(((x) & GENMASK(3, 3)) >> 3)

#define CPU_DDRC_INTR_MASK_DFI_ALERT_ERR_INTR_MASK(x)\
	(((x) << 4) & GENMASK(4, 4))
#define CPU_DDRC_INTR_MASK_DFI_ALERT_ERR_INTR_MASK_M GENMASK(4, 4)
#define CPU_DDRC_INTR_MASK_DFI_ALERT_ERR_INTR_MASK_X(x)\
	(((x) & GENMASK(4, 4)) >> 4)

/*      CPU:DDRCTRL:DDRC_INTR_MASKED_STAT */
#define CPU_DDRC_INTR_MASKED_STAT(t) (t + 0x2fc)

#define CPU_DDRC_INTR_MASKED_STAT_SBR_DONE_INTR_STAT(x) ((x) & GENMASK(0, 0))
#define CPU_DDRC_INTR_MASKED_STAT_SBR_DONE_INTR_STAT_M GENMASK(0, 0)
#define CPU_DDRC_INTR_MASKED_STAT_SBR_DONE_INTR_STAT_X(x) ((x) & GENMASK(0, 0))

#define CPU_DDRC_INTR_MASKED_STAT_ECC_CORRECTED_ERR_INTR_STAT(x)\
	(((x) << 1) & GENMASK(1, 1))
#define CPU_DDRC_INTR_MASKED_STAT_ECC_CORRECTED_ERR_INTR_STAT_M GENMASK(1, 1)
#define CPU_DDRC_INTR_MASKED_STAT_ECC_CORRECTED_ERR_INTR_STAT_X(x)\
	(((x) & GENMASK(1, 1)) >> 1)

#define CPU_DDRC_INTR_MASKED_STAT_ECC_UNCORRECTED_ERR_INTR_STAT(x)\
	(((x) << 2) & GENMASK(2, 2))
#define CPU_DDRC_INTR_MASKED_STAT_ECC_UNCORRECTED_ERR_INTR_STAT_M GENMASK(2, 2)
#define CPU_DDRC_INTR_MASKED_STAT_ECC_UNCORRECTED_ERR_INTR_STAT_X(x)\
	(((x) & GENMASK(2, 2)) >> 2)

#define CPU_DDRC_INTR_MASKED_STAT_ECC_AP_ERR_INTR_STAT(x)\
	(((x) << 3) & GENMASK(3, 3))
#define CPU_DDRC_INTR_MASKED_STAT_ECC_AP_ERR_INTR_STAT_M GENMASK(3, 3)
#define CPU_DDRC_INTR_MASKED_STAT_ECC_AP_ERR_INTR_STAT_X(x)\
	(((x) & GENMASK(3, 3)) >> 3)

#define CPU_DDRC_INTR_MASKED_STAT_DFI_ALERT_ERR_INTR_STAT(x)\
	(((x) << 4) & GENMASK(4, 4))
#define CPU_DDRC_INTR_MASKED_STAT_DFI_ALERT_ERR_INTR_STAT_M GENMASK(4, 4)
#define CPU_DDRC_INTR_MASKED_STAT_DFI_ALERT_ERR_INTR_STAT_X(x)\
	(((x) & GENMASK(4, 4)) >> 4)

/*      CPU:DDRCTRL:DRAM0_MPR_PAGE_STAT */
#define CPU_DRAM0_MPR_PAGE_STAT(t) (t + 0x300)

/*      CPU:DDRCTRL:DRAM1_MPR_PAGE_STAT */
#define CPU_DRAM1_MPR_PAGE_STAT(t) (t + 0x304)

/*      DDR_PHY:DDR_MULTIPHY_REGS:GENERAL_SETUP */
#define DDR_PHY_GENERAL_SETUP(t)  (t + 0x00)

#define DDR_PHY_GENERAL_SETUP_FORMAT(x)          ((x) & GENMASK(1, 0))
#define DDR_PHY_GENERAL_SETUP_FORMAT_M           GENMASK(1, 0)
#define DDR_PHY_GENERAL_SETUP_FORMAT_X(x)        ((x) & GENMASK(1, 0))

#define DDR_PHY_GENERAL_SETUP_PHY_CHANNEL_EN(x)  (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_GENERAL_SETUP_PHY_CHANNEL_EN_M   GENMASK(3, 2)
#define DDR_PHY_GENERAL_SETUP_PHY_CHANNEL_EN_X(x) (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_GENERAL_SETUP_WRITE_DQS_ADJUST(x) (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_GENERAL_SETUP_WRITE_DQS_ADJUST_M GENMASK(4, 4)
#define DDR_PHY_GENERAL_SETUP_WRITE_DQS_ADJUST_X(x) (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_GENERAL_SETUP_AUTOTRAIN_EN(x)    (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_GENERAL_SETUP_AUTOTRAIN_EN_M     GENMASK(5, 5)
#define DDR_PHY_GENERAL_SETUP_AUTOTRAIN_EN_X(x)  (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_GENERAL_SETUP_PB_MUX_SEL(x)      (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_GENERAL_SETUP_PB_MUX_SEL_M       GENMASK(7, 6)
#define DDR_PHY_GENERAL_SETUP_PB_MUX_SEL_X(x)    (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_GENERAL_SETUP_TRAINING_BASE(x)   (((x) << 8) & GENMASK(12, 8))
#define DDR_PHY_GENERAL_SETUP_TRAINING_BASE_M    GENMASK(12, 8)
#define DDR_PHY_GENERAL_SETUP_TRAINING_BASE_X(x) (((x) & GENMASK(12, 8)) >> 8)

#define DDR_PHY_GENERAL_SETUP_CA_BUS_VAL_EDGE(x) (((x) << 13) & GENMASK(13, 13))
#define DDR_PHY_GENERAL_SETUP_CA_BUS_VAL_EDGE_M  GENMASK(13, 13)
#define DDR_PHY_GENERAL_SETUP_CA_BUS_VAL_EDGE_X(x)\
	(((x) & GENMASK(13, 13)) >> 13)

/*      DDR_PHY:DDR_MULTIPHY_REGS:PLAYBACK_ENABLE */
#define DDR_PHY_PLAYBACK_ENABLE(t) (t + 0x04)

#define DDR_PHY_PLAYBACK_ENABLE_PB_START(x)      ((x) & GENMASK(0, 0))
#define DDR_PHY_PLAYBACK_ENABLE_PB_START_M       GENMASK(0, 0)
#define DDR_PHY_PLAYBACK_ENABLE_PB_START_X(x)    ((x) & GENMASK(0, 0))

/*      DDR_PHY:DDR_MULTIPHY_REGS:PLAYBACK_STATUS */
#define DDR_PHY_PLAYBACK_STATUS(t) (t + 0x08)

#define DDR_PHY_PLAYBACK_STATUS_PLAYBACK_RUNNING(x) ((x) & GENMASK(0, 0))
#define DDR_PHY_PLAYBACK_STATUS_PLAYBACK_RUNNING_M GENMASK(0, 0)
#define DDR_PHY_PLAYBACK_STATUS_PLAYBACK_RUNNING_X(x) ((x) & GENMASK(0, 0))

#define DDR_PHY_PLAYBACK_STATUS_UNUSED_STS(x)    (((x) << 1) & GENMASK(3, 1))
#define DDR_PHY_PLAYBACK_STATUS_UNUSED_STS_M     GENMASK(3, 1)
#define DDR_PHY_PLAYBACK_STATUS_UNUSED_STS_X(x)  (((x) & GENMASK(3, 1)) >> 1)

#define DDR_PHY_PLAYBACK_STATUS_LAST_ADDR(x)     (((x) << 4) & GENMASK(9, 4))
#define DDR_PHY_PLAYBACK_STATUS_LAST_ADDR_M      GENMASK(9, 4)
#define DDR_PHY_PLAYBACK_STATUS_LAST_ADDR_X(x)   (((x) & GENMASK(9, 4)) >> 4)

/*      DDR_PHY:DDR_MULTIPHY_REGS:WRITE_PIPE_DELAY */
#define DDR_PHY_WRITE_PIPE_DELAY(t) (t + 0x0c)

#define DDR_PHY_WRITE_PIPE_DELAY_WR_PIPE_DELAY(x) ((x) & GENMASK(3, 0))
#define DDR_PHY_WRITE_PIPE_DELAY_WR_PIPE_DELAY_M GENMASK(3, 0)
#define DDR_PHY_WRITE_PIPE_DELAY_WR_PIPE_DELAY_X(x) ((x) & GENMASK(3, 0))

#define DDR_PHY_WRITE_PIPE_DELAY_MEMCLK_DLY_OFFSET(x)\
	(((x) << 4) & GENMASK(5, 4))
#define DDR_PHY_WRITE_PIPE_DELAY_MEMCLK_DLY_OFFSET_M GENMASK(5, 4)
#define DDR_PHY_WRITE_PIPE_DELAY_MEMCLK_DLY_OFFSET_X(x)\
	(((x) & GENMASK(5, 4)) >> 4)

/*      DDR_PHY:DDR_MULTIPHY_REGS:CA_PIPE_DELAY */
#define DDR_PHY_CA_PIPE_DELAY(t)  (t + 0x10)

#define DDR_PHY_CA_PIPE_DELAY_CA_PIPE_DELAY(x)   ((x) & GENMASK(4, 0))
#define DDR_PHY_CA_PIPE_DELAY_CA_PIPE_DELAY_M    GENMASK(4, 0)
#define DDR_PHY_CA_PIPE_DELAY_CA_PIPE_DELAY_X(x) ((x) & GENMASK(4, 0))

/*      DDR_PHY:DDR_MULTIPHY_REGS:DATA_BYTE_SEL */
#define DDR_PHY_DATA_BYTE_SEL(t)  (t + 0x14)

#define DDR_PHY_DATA_BYTE_SEL_BYTE_SEL(x)        ((x) & GENMASK(3, 0))
#define DDR_PHY_DATA_BYTE_SEL_BYTE_SEL_M         GENMASK(3, 0)
#define DDR_PHY_DATA_BYTE_SEL_BYTE_SEL_X(x)      ((x) & GENMASK(3, 0))

#define DDR_PHY_DATA_BYTE_SEL_RANK_SEL(x)        (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DATA_BYTE_SEL_RANK_SEL_M         GENMASK(4, 4)
#define DDR_PHY_DATA_BYTE_SEL_RANK_SEL_X(x)      (((x) & GENMASK(4, 4)) >> 4)

/*      DDR_PHY:DDR_MULTIPHY_REGS:CTRLUPD_CONFIG */
#define DDR_PHY_CTRLUPD_CONFIG(t) (t + 0x18)

#define DDR_PHY_CTRLUPD_CONFIG_REQ_TO_ACK_DLY(x) ((x) & GENMASK(5, 0))
#define DDR_PHY_CTRLUPD_CONFIG_REQ_TO_ACK_DLY_M  GENMASK(5, 0)
#define DDR_PHY_CTRLUPD_CONFIG_REQ_TO_ACK_DLY_X(x) ((x) & GENMASK(5, 0))

#define DDR_PHY_CTRLUPD_CONFIG_UNUSED(x)         (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_CTRLUPD_CONFIG_UNUSED_M          GENMASK(7, 6)
#define DDR_PHY_CTRLUPD_CONFIG_UNUSED_X(x)       (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_CTRLUPD_CONFIG_ACK_VLD_CLKS(x)   (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_CTRLUPD_CONFIG_ACK_VLD_CLKS_M    GENMASK(13, 8)
#define DDR_PHY_CTRLUPD_CONFIG_ACK_VLD_CLKS_X(x) (((x) & GENMASK(13, 8)) >> 8)

/*      DDR_PHY:DDR_MULTIPHY_REGS:DEBUG */
#define DDR_PHY_DEBUG(t)          (t + 0x1c)

#define DDR_PHY_DEBUG_IPR_RD_MUX(x)              ((x) & GENMASK(0, 0))
#define DDR_PHY_DEBUG_IPR_RD_MUX_M               GENMASK(0, 0)
#define DDR_PHY_DEBUG_IPR_RD_MUX_X(x)            ((x) & GENMASK(0, 0))

/*      DDR_PHY:DDR_MULTIPHY_REGS:INTERRUPT_MASK */
#define DDR_PHY_INTERRUPT_MASK(t) (t + 0x20)

#define DDR_PHY_INTERRUPT_MASK_PB_INTR_MASK(x)   ((x) & GENMASK(0, 0))
#define DDR_PHY_INTERRUPT_MASK_PB_INTR_MASK_M    GENMASK(0, 0)
#define DDR_PHY_INTERRUPT_MASK_PB_INTR_MASK_X(x) ((x) & GENMASK(0, 0))

#define DDR_PHY_INTERRUPT_MASK_DRQ_ERR_INTR_MASK(x) (((x) << 1) & GENMASK(9, 1))
#define DDR_PHY_INTERRUPT_MASK_DRQ_ERR_INTR_MASK_M GENMASK(9, 1)
#define DDR_PHY_INTERRUPT_MASK_DRQ_ERR_INTR_MASK_X(x)\
	(((x) & GENMASK(9, 1)) >> 1)

/*      DDR_PHY:DDR_MULTIPHY_REGS:INTERRUPT_ENABLE */
#define DDR_PHY_INTERRUPT_ENABLE(t) (t + 0x24)

#define DDR_PHY_INTERRUPT_ENABLE_PB_INTR_EN(x)   ((x) & GENMASK(0, 0))
#define DDR_PHY_INTERRUPT_ENABLE_PB_INTR_EN_M    GENMASK(0, 0)
#define DDR_PHY_INTERRUPT_ENABLE_PB_INTR_EN_X(x) ((x) & GENMASK(0, 0))

#define DDR_PHY_INTERRUPT_ENABLE_DQS_ERR_INTR_EN(x) (((x) << 1) & GENMASK(9, 1))
#define DDR_PHY_INTERRUPT_ENABLE_DQS_ERR_INTR_EN_M GENMASK(9, 1)
#define DDR_PHY_INTERRUPT_ENABLE_DQS_ERR_INTR_EN_X(x)\
	(((x) & GENMASK(9, 1)) >> 1)

/*      DDR_PHY:DDR_MULTIPHY_REGS:INTERRUPT_STATUS */
#define DDR_PHY_INTERRUPT_STATUS(t) (t + 0x28)

#define DDR_PHY_INTERRUPT_STATUS_PB_INTR_STS(x)  ((x) & GENMASK(0, 0))
#define DDR_PHY_INTERRUPT_STATUS_PB_INTR_STS_M   GENMASK(0, 0)
#define DDR_PHY_INTERRUPT_STATUS_PB_INTR_STS_X(x) ((x) & GENMASK(0, 0))

#define DDR_PHY_INTERRUPT_STATUS_DQS_ERR_INTR_STS(x)\
	(((x) << 1) & GENMASK(9, 1))
#define DDR_PHY_INTERRUPT_STATUS_DQS_ERR_INTR_STS_M GENMASK(9, 1)
#define DDR_PHY_INTERRUPT_STATUS_DQS_ERR_INTR_STS_X(x)\
	(((x) & GENMASK(9, 1)) >> 1)

/*      DDR_PHY:DDR_MULTIPHY_REGS:INTERRUPT_CLEAR */
#define DDR_PHY_INTERRUPT_CLEAR(t) (t + 0x2c)

#define DDR_PHY_INTERRUPT_CLEAR_INTR_CLR(x)      ((x) & GENMASK(0, 0))
#define DDR_PHY_INTERRUPT_CLEAR_INTR_CLR_M       GENMASK(0, 0)
#define DDR_PHY_INTERRUPT_CLEAR_INTR_CLR_X(x)    ((x) & GENMASK(0, 0))

/*      DDR_PHY:DDR_MULTIPHY_REGS:DFICLK_READ_DELAY_RANK_0 */
#define DDR_PHY_DFICLK_READ_DELAY_RANK_0(t) (t + 0x30)

#define DDR_PHY_DFICLK_READ_DELAY_RANK_0_RD_EN_VLD_DLY_0_R0(x)\
	((x) & GENMASK(1, 0))
#define DDR_PHY_DFICLK_READ_DELAY_RANK_0_RD_EN_VLD_DLY_0_R0_M GENMASK(1, 0)
#define DDR_PHY_DFICLK_READ_DELAY_RANK_0_RD_EN_VLD_DLY_0_R0_X(x)\
	((x) & GENMASK(1, 0))

#define DDR_PHY_DFICLK_READ_DELAY_RANK_0_RD_EN_VLD_DLY_1_R0(x)\
	(((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DFICLK_READ_DELAY_RANK_0_RD_EN_VLD_DLY_1_R0_M GENMASK(3, 2)
#define DDR_PHY_DFICLK_READ_DELAY_RANK_0_RD_EN_VLD_DLY_1_R0_X(x)\
	(((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DFICLK_READ_DELAY_RANK_0_RD_EN_VLD_DLY_2_R0(x)\
	(((x) << 4) & GENMASK(5, 4))
#define DDR_PHY_DFICLK_READ_DELAY_RANK_0_RD_EN_VLD_DLY_2_R0_M GENMASK(5, 4)
#define DDR_PHY_DFICLK_READ_DELAY_RANK_0_RD_EN_VLD_DLY_2_R0_X(x)\
	(((x) & GENMASK(5, 4)) >> 4)

#define DDR_PHY_DFICLK_READ_DELAY_RANK_0_RD_EN_VLD_DLY_3_R0(x)\
	(((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DFICLK_READ_DELAY_RANK_0_RD_EN_VLD_DLY_3_R0_M GENMASK(7, 6)
#define DDR_PHY_DFICLK_READ_DELAY_RANK_0_RD_EN_VLD_DLY_3_R0_X(x)\
	(((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DFICLK_READ_DELAY_RANK_0_RD_EN_VLD_DLY_4_R0(x)\
	(((x) << 8) & GENMASK(9, 8))
#define DDR_PHY_DFICLK_READ_DELAY_RANK_0_RD_EN_VLD_DLY_4_R0_M GENMASK(9, 8)
#define DDR_PHY_DFICLK_READ_DELAY_RANK_0_RD_EN_VLD_DLY_4_R0_X(x)\
	(((x) & GENMASK(9, 8)) >> 8)

#define DDR_PHY_DFICLK_READ_DELAY_RANK_0_RD_EN_VLD_DLY_5_R0(x)\
	(((x) << 10) & GENMASK(11, 10))
#define DDR_PHY_DFICLK_READ_DELAY_RANK_0_RD_EN_VLD_DLY_5_R0_M GENMASK(11, 10)
#define DDR_PHY_DFICLK_READ_DELAY_RANK_0_RD_EN_VLD_DLY_5_R0_X(x)\
	(((x) & GENMASK(11, 10)) >> 10)

#define DDR_PHY_DFICLK_READ_DELAY_RANK_0_RD_EN_VLD_DLY_6_R0(x)\
	(((x) << 12) & GENMASK(13, 12))
#define DDR_PHY_DFICLK_READ_DELAY_RANK_0_RD_EN_VLD_DLY_6_R0_M GENMASK(13, 12)
#define DDR_PHY_DFICLK_READ_DELAY_RANK_0_RD_EN_VLD_DLY_6_R0_X(x)\
	(((x) & GENMASK(13, 12)) >> 12)

#define DDR_PHY_DFICLK_READ_DELAY_RANK_0_RD_EN_VLD_DLY_7_R0(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DFICLK_READ_DELAY_RANK_0_RD_EN_VLD_DLY_7_R0_M GENMASK(15, 14)
#define DDR_PHY_DFICLK_READ_DELAY_RANK_0_RD_EN_VLD_DLY_7_R0_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DFICLK_READ_DELAY_RANK_0_RD_EN_VLD_DLY_8_R0(x)\
	(((x) << 16) & GENMASK(17, 16))
#define DDR_PHY_DFICLK_READ_DELAY_RANK_0_RD_EN_VLD_DLY_8_R0_M GENMASK(17, 16)
#define DDR_PHY_DFICLK_READ_DELAY_RANK_0_RD_EN_VLD_DLY_8_R0_X(x)\
	(((x) & GENMASK(17, 16)) >> 16)

/*      DDR_PHY:DDR_MULTIPHY_REGS:FCLK_READ_DELAY_RANK_0_BYTES_7_0 */
#define DDR_PHY_FCLK_READ_DELAY_RANK_0_BYTES_7_0(t) (t + 0x34)

#define DDR_PHY_FCLK_READ_DELAY_RANK_0_BYTES_7_0_RD_DATA_PIPE_0_R0(x)\
	((x) & GENMASK(3, 0))
#define DDR_PHY_FCLK_READ_DELAY_RANK_0_BYTES_7_0_RD_DATA_PIPE_0_R0_M\
	GENMASK(3, 0)
#define DDR_PHY_FCLK_READ_DELAY_RANK_0_BYTES_7_0_RD_DATA_PIPE_0_R0_X(x)\
	((x) & GENMASK(3, 0))

#define DDR_PHY_FCLK_READ_DELAY_RANK_0_BYTES_7_0_RD_DATA_PIPE_1_R0(x)\
	(((x) << 4) & GENMASK(7, 4))
#define DDR_PHY_FCLK_READ_DELAY_RANK_0_BYTES_7_0_RD_DATA_PIPE_1_R0_M\
	GENMASK(7, 4)
#define DDR_PHY_FCLK_READ_DELAY_RANK_0_BYTES_7_0_RD_DATA_PIPE_1_R0_X(x)\
	(((x) & GENMASK(7, 4)) >> 4)

#define DDR_PHY_FCLK_READ_DELAY_RANK_0_BYTES_7_0_RD_DATA_PIPE_2_R0(x)\
	(((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_FCLK_READ_DELAY_RANK_0_BYTES_7_0_RD_DATA_PIPE_2_R0_M\
	GENMASK(11, 8)
#define DDR_PHY_FCLK_READ_DELAY_RANK_0_BYTES_7_0_RD_DATA_PIPE_2_R0_X(x)\
	(((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_FCLK_READ_DELAY_RANK_0_BYTES_7_0_RD_DATA_PIPE_3_R0(x)\
	(((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_FCLK_READ_DELAY_RANK_0_BYTES_7_0_RD_DATA_PIPE_3_R0_M\
	GENMASK(15, 12)
#define DDR_PHY_FCLK_READ_DELAY_RANK_0_BYTES_7_0_RD_DATA_PIPE_3_R0_X(x)\
	(((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_FCLK_READ_DELAY_RANK_0_BYTES_7_0_RD_DATA_PIPE_4_R0(x)\
	(((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_FCLK_READ_DELAY_RANK_0_BYTES_7_0_RD_DATA_PIPE_4_R0_M\
	GENMASK(19, 16)
#define DDR_PHY_FCLK_READ_DELAY_RANK_0_BYTES_7_0_RD_DATA_PIPE_4_R0_X(x)\
	(((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_FCLK_READ_DELAY_RANK_0_BYTES_7_0_RD_DATA_PIPE_5_R0(x)\
	(((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_FCLK_READ_DELAY_RANK_0_BYTES_7_0_RD_DATA_PIPE_5_R0_M\
	GENMASK(23, 20)
#define DDR_PHY_FCLK_READ_DELAY_RANK_0_BYTES_7_0_RD_DATA_PIPE_5_R0_X(x)\
	(((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_FCLK_READ_DELAY_RANK_0_BYTES_7_0_RD_DATA_PIPE_6_R0(x)\
	(((x) << 24) & GENMASK(27, 24))
#define DDR_PHY_FCLK_READ_DELAY_RANK_0_BYTES_7_0_RD_DATA_PIPE_6_R0_M\
	GENMASK(27, 24)
#define DDR_PHY_FCLK_READ_DELAY_RANK_0_BYTES_7_0_RD_DATA_PIPE_6_R0_X(x)\
	(((x) & GENMASK(27, 24)) >> 24)

#define DDR_PHY_FCLK_READ_DELAY_RANK_0_BYTES_7_0_RD_DATA_PIPE_7_R0(x)\
	(((x) << 28) & GENMASK(31, 28))
#define DDR_PHY_FCLK_READ_DELAY_RANK_0_BYTES_7_0_RD_DATA_PIPE_7_R0_M\
	GENMASK(31, 28)
#define DDR_PHY_FCLK_READ_DELAY_RANK_0_BYTES_7_0_RD_DATA_PIPE_7_R0_X(x)\
	(((x) & GENMASK(31, 28)) >> 28)

/*      DDR_PHY:DDR_MULTIPHY_REGS:FCLK_READ_DELAY_RANK_0_BYTE_8 */
#define DDR_PHY_FCLK_READ_DELAY_RANK_0_BYTE_8(t) (t + 0x38)

#define DDR_PHY_FCLK_READ_DELAY_RANK_0_BYTE_8_RD_DATA_PIPE_8_R0(x)\
	((x) & GENMASK(3, 0))
#define DDR_PHY_FCLK_READ_DELAY_RANK_0_BYTE_8_RD_DATA_PIPE_8_R0_M GENMASK(3, 0)
#define DDR_PHY_FCLK_READ_DELAY_RANK_0_BYTE_8_RD_DATA_PIPE_8_R0_X(x)\
	((x) & GENMASK(3, 0))

/*      DDR_PHY:DDR_MULTIPHY_REGS:RESERVED_1 */
#define DDR_PHY_RESERVED_1(t)     (t + 0x3c)

/*      DDR_PHY:DDR_MULTIPHY_REGS:DFICLK_READ_DELAY_RANK_1 */
#define DDR_PHY_DFICLK_READ_DELAY_RANK_1(t) (t + 0x40)

#define DDR_PHY_DFICLK_READ_DELAY_RANK_1_RD_EN_VLD_DLY_0_R1(x)\
	((x) & GENMASK(1, 0))
#define DDR_PHY_DFICLK_READ_DELAY_RANK_1_RD_EN_VLD_DLY_0_R1_M GENMASK(1, 0)
#define DDR_PHY_DFICLK_READ_DELAY_RANK_1_RD_EN_VLD_DLY_0_R1_X(x)\
	((x) & GENMASK(1, 0))

#define DDR_PHY_DFICLK_READ_DELAY_RANK_1_RD_EN_VLD_DLY_1_R1(x)\
	(((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DFICLK_READ_DELAY_RANK_1_RD_EN_VLD_DLY_1_R1_M GENMASK(3, 2)
#define DDR_PHY_DFICLK_READ_DELAY_RANK_1_RD_EN_VLD_DLY_1_R1_X(x)\
	(((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DFICLK_READ_DELAY_RANK_1_RD_EN_VLD_DLY_2_R1(x)\
	(((x) << 4) & GENMASK(5, 4))
#define DDR_PHY_DFICLK_READ_DELAY_RANK_1_RD_EN_VLD_DLY_2_R1_M GENMASK(5, 4)
#define DDR_PHY_DFICLK_READ_DELAY_RANK_1_RD_EN_VLD_DLY_2_R1_X(x)\
	(((x) & GENMASK(5, 4)) >> 4)

#define DDR_PHY_DFICLK_READ_DELAY_RANK_1_RD_EN_VLD_DLY_3_R1(x)\
	(((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DFICLK_READ_DELAY_RANK_1_RD_EN_VLD_DLY_3_R1_M GENMASK(7, 6)
#define DDR_PHY_DFICLK_READ_DELAY_RANK_1_RD_EN_VLD_DLY_3_R1_X(x)\
	(((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DFICLK_READ_DELAY_RANK_1_RD_EN_VLD_DLY_4_R1(x)\
	(((x) << 8) & GENMASK(9, 8))
#define DDR_PHY_DFICLK_READ_DELAY_RANK_1_RD_EN_VLD_DLY_4_R1_M GENMASK(9, 8)
#define DDR_PHY_DFICLK_READ_DELAY_RANK_1_RD_EN_VLD_DLY_4_R1_X(x)\
	(((x) & GENMASK(9, 8)) >> 8)

#define DDR_PHY_DFICLK_READ_DELAY_RANK_1_RD_EN_VLD_DLY_5_R1(x)\
	(((x) << 10) & GENMASK(11, 10))
#define DDR_PHY_DFICLK_READ_DELAY_RANK_1_RD_EN_VLD_DLY_5_R1_M GENMASK(11, 10)
#define DDR_PHY_DFICLK_READ_DELAY_RANK_1_RD_EN_VLD_DLY_5_R1_X(x)\
	(((x) & GENMASK(11, 10)) >> 10)

#define DDR_PHY_DFICLK_READ_DELAY_RANK_1_RD_EN_VLD_DLY_6_R1(x)\
	(((x) << 12) & GENMASK(13, 12))
#define DDR_PHY_DFICLK_READ_DELAY_RANK_1_RD_EN_VLD_DLY_6_R1_M GENMASK(13, 12)
#define DDR_PHY_DFICLK_READ_DELAY_RANK_1_RD_EN_VLD_DLY_6_R1_X(x)\
	(((x) & GENMASK(13, 12)) >> 12)

#define DDR_PHY_DFICLK_READ_DELAY_RANK_1_RD_EN_VLD_DLY_7_R1(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DFICLK_READ_DELAY_RANK_1_RD_EN_VLD_DLY_7_R1_M GENMASK(15, 14)
#define DDR_PHY_DFICLK_READ_DELAY_RANK_1_RD_EN_VLD_DLY_7_R1_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DFICLK_READ_DELAY_RANK_1_RD_EN_VLD_DLY_8_R1(x)\
	(((x) << 16) & GENMASK(17, 16))
#define DDR_PHY_DFICLK_READ_DELAY_RANK_1_RD_EN_VLD_DLY_8_R1_M GENMASK(17, 16)
#define DDR_PHY_DFICLK_READ_DELAY_RANK_1_RD_EN_VLD_DLY_8_R1_X(x)\
	(((x) & GENMASK(17, 16)) >> 16)

/*      DDR_PHY:DDR_MULTIPHY_REGS:FCLK_READ_DELAY_RANK_1_BYTES_7_0 */
#define DDR_PHY_FCLK_READ_DELAY_RANK_1_BYTES_7_0(t) (t + 0x44)

#define DDR_PHY_FCLK_READ_DELAY_RANK_1_BYTES_7_0_RD_DATA_PIPE_0_R1(x)\
	((x) & GENMASK(3, 0))
#define DDR_PHY_FCLK_READ_DELAY_RANK_1_BYTES_7_0_RD_DATA_PIPE_0_R1_M\
	GENMASK(3, 0)
#define DDR_PHY_FCLK_READ_DELAY_RANK_1_BYTES_7_0_RD_DATA_PIPE_0_R1_X(x)\
	((x) & GENMASK(3, 0))

#define DDR_PHY_FCLK_READ_DELAY_RANK_1_BYTES_7_0_RD_DATA_PIPE_1_R1(x)\
	(((x) << 4) & GENMASK(7, 4))
#define DDR_PHY_FCLK_READ_DELAY_RANK_1_BYTES_7_0_RD_DATA_PIPE_1_R1_M\
	GENMASK(7, 4)
#define DDR_PHY_FCLK_READ_DELAY_RANK_1_BYTES_7_0_RD_DATA_PIPE_1_R1_X(x)\
	(((x) & GENMASK(7, 4)) >> 4)

#define DDR_PHY_FCLK_READ_DELAY_RANK_1_BYTES_7_0_RD_DATA_PIPE_2_R1(x)\
	(((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_FCLK_READ_DELAY_RANK_1_BYTES_7_0_RD_DATA_PIPE_2_R1_M\
	GENMASK(11, 8)
#define DDR_PHY_FCLK_READ_DELAY_RANK_1_BYTES_7_0_RD_DATA_PIPE_2_R1_X(x)\
	(((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_FCLK_READ_DELAY_RANK_1_BYTES_7_0_RD_DATA_PIPE_3_R1(x)\
	(((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_FCLK_READ_DELAY_RANK_1_BYTES_7_0_RD_DATA_PIPE_3_R1_M\
	GENMASK(15, 12)
#define DDR_PHY_FCLK_READ_DELAY_RANK_1_BYTES_7_0_RD_DATA_PIPE_3_R1_X(x)\
	(((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_FCLK_READ_DELAY_RANK_1_BYTES_7_0_RD_DATA_PIPE_4_R1(x)\
	(((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_FCLK_READ_DELAY_RANK_1_BYTES_7_0_RD_DATA_PIPE_4_R1_M\
	GENMASK(19, 16)
#define DDR_PHY_FCLK_READ_DELAY_RANK_1_BYTES_7_0_RD_DATA_PIPE_4_R1_X(x)\
	(((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_FCLK_READ_DELAY_RANK_1_BYTES_7_0_RD_DATA_PIPE_5_R1(x)\
	(((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_FCLK_READ_DELAY_RANK_1_BYTES_7_0_RD_DATA_PIPE_5_R1_M\
	GENMASK(23, 20)
#define DDR_PHY_FCLK_READ_DELAY_RANK_1_BYTES_7_0_RD_DATA_PIPE_5_R1_X(x)\
	(((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_FCLK_READ_DELAY_RANK_1_BYTES_7_0_RD_DATA_PIPE_6_R1(x)\
	(((x) << 24) & GENMASK(27, 24))
#define DDR_PHY_FCLK_READ_DELAY_RANK_1_BYTES_7_0_RD_DATA_PIPE_6_R1_M\
	GENMASK(27, 24)
#define DDR_PHY_FCLK_READ_DELAY_RANK_1_BYTES_7_0_RD_DATA_PIPE_6_R1_X(x)\
	(((x) & GENMASK(27, 24)) >> 24)

#define DDR_PHY_FCLK_READ_DELAY_RANK_1_BYTES_7_0_RD_DATA_PIPE_7_R1(x)\
	(((x) << 28) & GENMASK(31, 28))
#define DDR_PHY_FCLK_READ_DELAY_RANK_1_BYTES_7_0_RD_DATA_PIPE_7_R1_M\
	GENMASK(31, 28)
#define DDR_PHY_FCLK_READ_DELAY_RANK_1_BYTES_7_0_RD_DATA_PIPE_7_R1_X(x)\
	(((x) & GENMASK(31, 28)) >> 28)

/*      DDR_PHY:DDR_MULTIPHY_REGS:FCLK_READ_DELAY_RANK_1_BYTE_8 */
#define DDR_PHY_FCLK_READ_DELAY_RANK_1_BYTE_8(t) (t + 0x48)

#define DDR_PHY_FCLK_READ_DELAY_RANK_1_BYTE_8_RD_DATA_PIPE_8_R1(x)\
	((x) & GENMASK(3, 0))
#define DDR_PHY_FCLK_READ_DELAY_RANK_1_BYTE_8_RD_DATA_PIPE_8_R1_M GENMASK(3, 0)
#define DDR_PHY_FCLK_READ_DELAY_RANK_1_BYTE_8_RD_DATA_PIPE_8_R1_X(x)\
	((x) & GENMASK(3, 0))

/*      DDR_PHY:DDR_MULTIPHY_REGS:RESERVED_2 */
#define DDR_PHY_RESERVED_2(t)     (t + 0x4c)

/*      DDR_PHY:DDR_MULTIPHY_REGS:FCLK_READ_OFFSET_RANK_0_BYTES_7_0 */
#define DDR_PHY_FCLK_READ_OFFSET_RANK_0_BYTES_7_0(t) (t + 0x50)

#define DDR_PHY_FCLK_READ_OFFSET_RANK_0_BYTES_7_0_READ_OFFSET_0_R0(x)\
	((x) & GENMASK(3, 0))
#define DDR_PHY_FCLK_READ_OFFSET_RANK_0_BYTES_7_0_READ_OFFSET_0_R0_M\
	GENMASK(3, 0)
#define DDR_PHY_FCLK_READ_OFFSET_RANK_0_BYTES_7_0_READ_OFFSET_0_R0_X(x)\
	((x) & GENMASK(3, 0))

#define DDR_PHY_FCLK_READ_OFFSET_RANK_0_BYTES_7_0_READ_OFFSET_1_R0(x)\
	(((x) << 4) & GENMASK(7, 4))
#define DDR_PHY_FCLK_READ_OFFSET_RANK_0_BYTES_7_0_READ_OFFSET_1_R0_M\
	GENMASK(7, 4)
#define DDR_PHY_FCLK_READ_OFFSET_RANK_0_BYTES_7_0_READ_OFFSET_1_R0_X(x)\
	(((x) & GENMASK(7, 4)) >> 4)

#define DDR_PHY_FCLK_READ_OFFSET_RANK_0_BYTES_7_0_READ_OFFSET_2_R0(x)\
	(((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_FCLK_READ_OFFSET_RANK_0_BYTES_7_0_READ_OFFSET_2_R0_M\
	GENMASK(11, 8)
#define DDR_PHY_FCLK_READ_OFFSET_RANK_0_BYTES_7_0_READ_OFFSET_2_R0_X(x)\
	(((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_FCLK_READ_OFFSET_RANK_0_BYTES_7_0_READ_OFFSET_3_R0(x)\
	(((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_FCLK_READ_OFFSET_RANK_0_BYTES_7_0_READ_OFFSET_3_R0_M\
	GENMASK(15, 12)
#define DDR_PHY_FCLK_READ_OFFSET_RANK_0_BYTES_7_0_READ_OFFSET_3_R0_X(x)\
	(((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_FCLK_READ_OFFSET_RANK_0_BYTES_7_0_READ_OFFSET_4_R0(x)\
	(((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_FCLK_READ_OFFSET_RANK_0_BYTES_7_0_READ_OFFSET_4_R0_M\
	GENMASK(19, 16)
#define DDR_PHY_FCLK_READ_OFFSET_RANK_0_BYTES_7_0_READ_OFFSET_4_R0_X(x)\
	(((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_FCLK_READ_OFFSET_RANK_0_BYTES_7_0_READ_OFFSET_5_R0(x)\
	(((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_FCLK_READ_OFFSET_RANK_0_BYTES_7_0_READ_OFFSET_5_R0_M\
	GENMASK(23, 20)
#define DDR_PHY_FCLK_READ_OFFSET_RANK_0_BYTES_7_0_READ_OFFSET_5_R0_X(x)\
	(((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_FCLK_READ_OFFSET_RANK_0_BYTES_7_0_READ_OFFSET_6_R0(x)\
	(((x) << 24) & GENMASK(27, 24))
#define DDR_PHY_FCLK_READ_OFFSET_RANK_0_BYTES_7_0_READ_OFFSET_6_R0_M\
	GENMASK(27, 24)
#define DDR_PHY_FCLK_READ_OFFSET_RANK_0_BYTES_7_0_READ_OFFSET_6_R0_X(x)\
	(((x) & GENMASK(27, 24)) >> 24)

#define DDR_PHY_FCLK_READ_OFFSET_RANK_0_BYTES_7_0_READ_OFFSET_7_R0(x)\
	(((x) << 28) & GENMASK(31, 28))
#define DDR_PHY_FCLK_READ_OFFSET_RANK_0_BYTES_7_0_READ_OFFSET_7_R0_M\
	GENMASK(31, 28)
#define DDR_PHY_FCLK_READ_OFFSET_RANK_0_BYTES_7_0_READ_OFFSET_7_R0_X(x)\
	(((x) & GENMASK(31, 28)) >> 28)

/*      DDR_PHY:DDR_MULTIPHY_REGS:FCLK_READ_OFFSET_RANK_0_BYTE_8 */
#define DDR_PHY_FCLK_READ_OFFSET_RANK_0_BYTE_8(t) (t + 0x54)

#define DDR_PHY_FCLK_READ_OFFSET_RANK_0_BYTE_8_READ_OFFSET_8_R0(x)\
	((x) & GENMASK(3, 0))
#define DDR_PHY_FCLK_READ_OFFSET_RANK_0_BYTE_8_READ_OFFSET_8_R0_M GENMASK(3, 0)
#define DDR_PHY_FCLK_READ_OFFSET_RANK_0_BYTE_8_READ_OFFSET_8_R0_X(x)\
	((x) & GENMASK(3, 0))

/*      DDR_PHY:DDR_MULTIPHY_REGS:FCLK_READ_OFFSET_RANK_1_BYTES_7_0 */
#define DDR_PHY_FCLK_READ_OFFSET_RANK_1_BYTES_7_0(t) (t + 0x58)

#define DDR_PHY_FCLK_READ_OFFSET_RANK_1_BYTES_7_0_READ_OFFSET_0_R1(x)\
	((x) & GENMASK(3, 0))
#define DDR_PHY_FCLK_READ_OFFSET_RANK_1_BYTES_7_0_READ_OFFSET_0_R1_M\
	GENMASK(3, 0)
#define DDR_PHY_FCLK_READ_OFFSET_RANK_1_BYTES_7_0_READ_OFFSET_0_R1_X(x)\
	((x) & GENMASK(3, 0))

#define DDR_PHY_FCLK_READ_OFFSET_RANK_1_BYTES_7_0_READ_OFFSET_1_R1(x)\
	(((x) << 4) & GENMASK(7, 4))
#define DDR_PHY_FCLK_READ_OFFSET_RANK_1_BYTES_7_0_READ_OFFSET_1_R1_M\
	GENMASK(7, 4)
#define DDR_PHY_FCLK_READ_OFFSET_RANK_1_BYTES_7_0_READ_OFFSET_1_R1_X(x)\
	(((x) & GENMASK(7, 4)) >> 4)

#define DDR_PHY_FCLK_READ_OFFSET_RANK_1_BYTES_7_0_READ_OFFSET_2_R1(x)\
	(((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_FCLK_READ_OFFSET_RANK_1_BYTES_7_0_READ_OFFSET_2_R1_M\
	GENMASK(11, 8)
#define DDR_PHY_FCLK_READ_OFFSET_RANK_1_BYTES_7_0_READ_OFFSET_2_R1_X(x)\
	(((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_FCLK_READ_OFFSET_RANK_1_BYTES_7_0_READ_OFFSET_3_R1(x)\
	(((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_FCLK_READ_OFFSET_RANK_1_BYTES_7_0_READ_OFFSET_3_R1_M\
	GENMASK(15, 12)
#define DDR_PHY_FCLK_READ_OFFSET_RANK_1_BYTES_7_0_READ_OFFSET_3_R1_X(x)\
	(((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_FCLK_READ_OFFSET_RANK_1_BYTES_7_0_READ_OFFSET_4_R1(x)\
	(((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_FCLK_READ_OFFSET_RANK_1_BYTES_7_0_READ_OFFSET_4_R1_M\
	GENMASK(19, 16)
#define DDR_PHY_FCLK_READ_OFFSET_RANK_1_BYTES_7_0_READ_OFFSET_4_R1_X(x)\
	(((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_FCLK_READ_OFFSET_RANK_1_BYTES_7_0_READ_OFFSET_5_R1(x)\
	(((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_FCLK_READ_OFFSET_RANK_1_BYTES_7_0_READ_OFFSET_5_R1_M\
	GENMASK(23, 20)
#define DDR_PHY_FCLK_READ_OFFSET_RANK_1_BYTES_7_0_READ_OFFSET_5_R1_X(x)\
	(((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_FCLK_READ_OFFSET_RANK_1_BYTES_7_0_READ_OFFSET_6_R1(x)\
	(((x) << 24) & GENMASK(27, 24))
#define DDR_PHY_FCLK_READ_OFFSET_RANK_1_BYTES_7_0_READ_OFFSET_6_R1_M\
	GENMASK(27, 24)
#define DDR_PHY_FCLK_READ_OFFSET_RANK_1_BYTES_7_0_READ_OFFSET_6_R1_X(x)\
	(((x) & GENMASK(27, 24)) >> 24)

#define DDR_PHY_FCLK_READ_OFFSET_RANK_1_BYTES_7_0_READ_OFFSET_7_R1(x)\
	(((x) << 28) & GENMASK(31, 28))
#define DDR_PHY_FCLK_READ_OFFSET_RANK_1_BYTES_7_0_READ_OFFSET_7_R1_M\
	GENMASK(31, 28)
#define DDR_PHY_FCLK_READ_OFFSET_RANK_1_BYTES_7_0_READ_OFFSET_7_R1_X(x)\
	(((x) & GENMASK(31, 28)) >> 28)

/*      DDR_PHY:DDR_MULTIPHY_REGS:FCLK_READ_OFFSET_RANK_1_BYTE_8 */
#define DDR_PHY_FCLK_READ_OFFSET_RANK_1_BYTE_8(t) (t + 0x5c)

#define DDR_PHY_FCLK_READ_OFFSET_RANK_1_BYTE_8_READ_OFFSET_8_R1(x)\
	((x) & GENMASK(3, 0))
#define DDR_PHY_FCLK_READ_OFFSET_RANK_1_BYTE_8_READ_OFFSET_8_R1_M GENMASK(3, 0)
#define DDR_PHY_FCLK_READ_OFFSET_RANK_1_BYTE_8_READ_OFFSET_8_R1_X(x)\
	((x) & GENMASK(3, 0))

/*      DDR_PHY:DDR_MULTIPHY_REGS:AUTOTRAIN_LOOP_ADDR */
#define DDR_PHY_AUTOTRAIN_LOOP_ADDR(t) (t + 0x60)

#define DDR_PHY_AUTOTRAIN_LOOP_ADDR_START_ADDR(x) ((x) & GENMASK(4, 0))
#define DDR_PHY_AUTOTRAIN_LOOP_ADDR_START_ADDR_M GENMASK(4, 0)
#define DDR_PHY_AUTOTRAIN_LOOP_ADDR_START_ADDR_X(x) ((x) & GENMASK(4, 0))

/*      DDR_PHY:DDR_MULTIPHY_REGS:TRAIN_STATUS */
#define DDR_PHY_TRAIN_STATUS(t)   (t + 0x64)

#define DDR_PHY_TRAIN_STATUS_SUCCESS_STS(x)      ((x) & GENMASK(0, 0))
#define DDR_PHY_TRAIN_STATUS_SUCCESS_STS_M       GENMASK(0, 0)
#define DDR_PHY_TRAIN_STATUS_SUCCESS_STS_X(x)    ((x) & GENMASK(0, 0))

#define DDR_PHY_TRAIN_STATUS_OFFSET_STS(x)       (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_TRAIN_STATUS_OFFSET_STS_M        GENMASK(1, 1)
#define DDR_PHY_TRAIN_STATUS_OFFSET_STS_X(x)     (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_TRAIN_STATUS_FAIL_STS(x)         (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_TRAIN_STATUS_FAIL_STS_M          GENMASK(2, 2)
#define DDR_PHY_TRAIN_STATUS_FAIL_STS_X(x)       (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_TRAIN_STATUS_AUTOTRAIN_STS(x)    (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_TRAIN_STATUS_AUTOTRAIN_STS_M     GENMASK(3, 3)
#define DDR_PHY_TRAIN_STATUS_AUTOTRAIN_STS_X(x)  (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_TRAIN_STATUS_AUTOLAST_BYTE(x)    (((x) << 4) & GENMASK(7, 4))
#define DDR_PHY_TRAIN_STATUS_AUTOLAST_BYTE_M     GENMASK(7, 4)
#define DDR_PHY_TRAIN_STATUS_AUTOLAST_BYTE_X(x)  (((x) & GENMASK(7, 4)) >> 4)

#define DDR_PHY_TRAIN_STATUS_AUTOLAST_RANK(x)    (((x) << 8) & GENMASK(8, 8))
#define DDR_PHY_TRAIN_STATUS_AUTOLAST_RANK_M     GENMASK(8, 8)
#define DDR_PHY_TRAIN_STATUS_AUTOLAST_RANK_X(x)  (((x) & GENMASK(8, 8)) >> 8)

/*      DDR_PHY:DDR_MULTIPHY_REGS:READ_TRAINING_CAPTURE0 */
#define DDR_PHY_READ_TRAINING_CAPTURE0(t) (t + 0x68)

/*      DDR_PHY:DDR_MULTIPHY_REGS:READ_TRAINING_CAPTURE1 */
#define DDR_PHY_READ_TRAINING_CAPTURE1(t) (t + 0x6c)

/*      DDR_PHY:DDR_MULTIPHY_REGS:REVISION_REGISTER */
#define DDR_PHY_REVISION_REGISTER(t) (t + 0x70)

#define DDR_PHY_REVISION_REGISTER_MINOR_REV(x)   ((x) & GENMASK(7, 0))
#define DDR_PHY_REVISION_REGISTER_MINOR_REV_M    GENMASK(7, 0)
#define DDR_PHY_REVISION_REGISTER_MINOR_REV_X(x) ((x) & GENMASK(7, 0))

#define DDR_PHY_REVISION_REGISTER_MAJOR_REV(x)   (((x) << 8) & GENMASK(15, 8))
#define DDR_PHY_REVISION_REGISTER_MAJOR_REV_M    GENMASK(15, 8)
#define DDR_PHY_REVISION_REGISTER_MAJOR_REV_X(x) (((x) & GENMASK(15, 8)) >> 8)

/*      DDR_PHY:DDR_MULTIPHY_REGS:RESERVED_3 */
#define DDR_PHY_RESERVED_3(t, r)  (t + (0x74 + ((r) * 4)))

/*      DDR_PHY:DDR_MULTIPHY_REGS:PLAYBACK_ENGINE_CODE */
#define DDR_PHY_PLAYBACK_ENGINE_CODE(t, r) (t + (0x800 + ((r) * 4)))

/*      DDR_UMCTL2:UMCTL2_REGS:MSTR */
#define DDR_UMCTL2_MSTR(t)        (t + 0x00)

#define DDR_UMCTL2_MSTR_DDR3ENA(x)               ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_MSTR_DDR3ENA_M                GENMASK(0, 0)
#define DDR_UMCTL2_MSTR_DDR3ENA_X(x)             ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_MSTR_BURSTCHOP(x)             (((x) << 9) & GENMASK(9, 9))
#define DDR_UMCTL2_MSTR_BURSTCHOP_M              GENMASK(9, 9)
#define DDR_UMCTL2_MSTR_BURSTCHOP_X(x)           (((x) & GENMASK(9, 9)) >> 9)

#define DDR_UMCTL2_MSTR_EN_2T_TIMING_MODE(x)     (((x) << 10) & GENMASK(10, 10))
#define DDR_UMCTL2_MSTR_EN_2T_TIMING_MODE_M      GENMASK(10, 10)
#define DDR_UMCTL2_MSTR_EN_2T_TIMING_MODE_X(x)   (((x) & GENMASK(10, 10)) >> 10)

#define DDR_UMCTL2_MSTR_DATA_BUS_WIDTH(x)        (((x) << 12) & GENMASK(13, 12))
#define DDR_UMCTL2_MSTR_DATA_BUS_WIDTH_M         GENMASK(13, 12)
#define DDR_UMCTL2_MSTR_DATA_BUS_WIDTH_X(x)      (((x) & GENMASK(13, 12)) >> 12)

#define DDR_UMCTL2_MSTR_DLL_OFF_MODE(x)          (((x) << 15) & GENMASK(15, 15))
#define DDR_UMCTL2_MSTR_DLL_OFF_MODE_M           GENMASK(15, 15)
#define DDR_UMCTL2_MSTR_DLL_OFF_MODE_X(x)        (((x) & GENMASK(15, 15)) >> 15)

#define DDR_UMCTL2_MSTR_BURST_RDWR(x)            (((x) << 16) & GENMASK(19, 16))
#define DDR_UMCTL2_MSTR_BURST_RDWR_M             GENMASK(19, 16)
#define DDR_UMCTL2_MSTR_BURST_RDWR_X(x)          (((x) & GENMASK(19, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_REGS:STAT */
#define DDR_UMCTL2_STAT(t)        (t + 0x04)

#define DDR_UMCTL2_STAT_OPERATING_MODE(x)        ((x) & GENMASK(1, 0))
#define DDR_UMCTL2_STAT_OPERATING_MODE_M         GENMASK(1, 0)
#define DDR_UMCTL2_STAT_OPERATING_MODE_X(x)      ((x) & GENMASK(1, 0))

#define DDR_UMCTL2_STAT_SELFREF_TYPE(x)          (((x) << 4) & GENMASK(5, 4))
#define DDR_UMCTL2_STAT_SELFREF_TYPE_M           GENMASK(5, 4)
#define DDR_UMCTL2_STAT_SELFREF_TYPE_X(x)        (((x) & GENMASK(5, 4)) >> 4)

#define DDR_UMCTL2_STAT_SELFREF_CAM_NOT_EMPTY(x) (((x) << 12) & GENMASK(12, 12))
#define DDR_UMCTL2_STAT_SELFREF_CAM_NOT_EMPTY_M  GENMASK(12, 12)
#define DDR_UMCTL2_STAT_SELFREF_CAM_NOT_EMPTY_X(x)\
	(((x) & GENMASK(12, 12)) >> 12)

/*      DDR_UMCTL2:UMCTL2_REGS:MRCTRL0 */
#define DDR_UMCTL2_MRCTRL0(t)     (t + 0x10)

#define DDR_UMCTL2_MRCTRL0_MR_RANK(x)            (((x) << 4) & GENMASK(4, 4))
#define DDR_UMCTL2_MRCTRL0_MR_RANK_M             GENMASK(4, 4)
#define DDR_UMCTL2_MRCTRL0_MR_RANK_X(x)          (((x) & GENMASK(4, 4)) >> 4)

#define DDR_UMCTL2_MRCTRL0_MR_ADDR(x)            (((x) << 12) & GENMASK(15, 12))
#define DDR_UMCTL2_MRCTRL0_MR_ADDR_M             GENMASK(15, 12)
#define DDR_UMCTL2_MRCTRL0_MR_ADDR_X(x)          (((x) & GENMASK(15, 12)) >> 12)

#define DDR_UMCTL2_MRCTRL0_MR_WR(x)              (((x) << 31) & GENMASK(31, 31))
#define DDR_UMCTL2_MRCTRL0_MR_WR_M               GENMASK(31, 31)
#define DDR_UMCTL2_MRCTRL0_MR_WR_X(x)            (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_UMCTL2:UMCTL2_REGS:MRCTRL1 */
#define DDR_UMCTL2_MRCTRL1(t)     (t + 0x14)

#define DDR_UMCTL2_MRCTRL1_MR_DATA(x)            ((x) & GENMASK(15, 0))
#define DDR_UMCTL2_MRCTRL1_MR_DATA_M             GENMASK(15, 0)
#define DDR_UMCTL2_MRCTRL1_MR_DATA_X(x)          ((x) & GENMASK(15, 0))

/*      DDR_UMCTL2:UMCTL2_REGS:MRSTAT */
#define DDR_UMCTL2_MRSTAT(t)      (t + 0x18)

#define DDR_UMCTL2_MRSTAT_MR_WR_BUSY(x)          ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_MRSTAT_MR_WR_BUSY_M           GENMASK(0, 0)
#define DDR_UMCTL2_MRSTAT_MR_WR_BUSY_X(x)        ((x) & GENMASK(0, 0))

/*      DDR_UMCTL2:UMCTL2_REGS:PWRCTL */
#define DDR_UMCTL2_PWRCTL(t)      (t + 0x30)

#define DDR_UMCTL2_PWRCTL_SELFREF_EN(x)          ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_PWRCTL_SELFREF_EN_M           GENMASK(0, 0)
#define DDR_UMCTL2_PWRCTL_SELFREF_EN_X(x)        ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_PWRCTL_POWERDOWN_EN(x)        (((x) << 1) & GENMASK(1, 1))
#define DDR_UMCTL2_PWRCTL_POWERDOWN_EN_M         GENMASK(1, 1)
#define DDR_UMCTL2_PWRCTL_POWERDOWN_EN_X(x)      (((x) & GENMASK(1, 1)) >> 1)

#define DDR_UMCTL2_PWRCTL_EN_DFI_DRAM_CLK_DISABLE(x)\
	(((x) << 3) & GENMASK(3, 3))
#define DDR_UMCTL2_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_M GENMASK(3, 3)
#define DDR_UMCTL2_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_X(x)\
	(((x) & GENMASK(3, 3)) >> 3)

#define DDR_UMCTL2_PWRCTL_SELFREF_SW(x)          (((x) << 5) & GENMASK(5, 5))
#define DDR_UMCTL2_PWRCTL_SELFREF_SW_M           GENMASK(5, 5)
#define DDR_UMCTL2_PWRCTL_SELFREF_SW_X(x)        (((x) & GENMASK(5, 5)) >> 5)

#define DDR_UMCTL2_PWRCTL_DIS_CAM_DRAIN_SELFREF(x) (((x) << 7) & GENMASK(7, 7))
#define DDR_UMCTL2_PWRCTL_DIS_CAM_DRAIN_SELFREF_M GENMASK(7, 7)
#define DDR_UMCTL2_PWRCTL_DIS_CAM_DRAIN_SELFREF_X(x)\
	(((x) & GENMASK(7, 7)) >> 7)

/*      DDR_UMCTL2:UMCTL2_REGS:PWRTMG */
#define DDR_UMCTL2_PWRTMG(t)      (t + 0x34)

#define DDR_UMCTL2_PWRTMG_POWERDOWN_TO_X32(x)    ((x) & GENMASK(4, 0))
#define DDR_UMCTL2_PWRTMG_POWERDOWN_TO_X32_M     GENMASK(4, 0)
#define DDR_UMCTL2_PWRTMG_POWERDOWN_TO_X32_X(x)  ((x) & GENMASK(4, 0))

#define DDR_UMCTL2_PWRTMG_SELFREF_TO_X32(x)      (((x) << 16) & GENMASK(23, 16))
#define DDR_UMCTL2_PWRTMG_SELFREF_TO_X32_M       GENMASK(23, 16)
#define DDR_UMCTL2_PWRTMG_SELFREF_TO_X32_X(x)    (((x) & GENMASK(23, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_REGS:HWLPCTL */
#define DDR_UMCTL2_HWLPCTL(t)     (t + 0x38)

#define DDR_UMCTL2_HWLPCTL_HW_LP_EN(x)           ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_HWLPCTL_HW_LP_EN_M            GENMASK(0, 0)
#define DDR_UMCTL2_HWLPCTL_HW_LP_EN_X(x)         ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_HWLPCTL_HW_LP_EXIT_IDLE_EN(x) (((x) << 1) & GENMASK(1, 1))
#define DDR_UMCTL2_HWLPCTL_HW_LP_EXIT_IDLE_EN_M  GENMASK(1, 1)
#define DDR_UMCTL2_HWLPCTL_HW_LP_EXIT_IDLE_EN_X(x) (((x) & GENMASK(1, 1)) >> 1)

#define DDR_UMCTL2_HWLPCTL_HW_LP_IDLE_X32(x)     (((x) << 16) & GENMASK(27, 16))
#define DDR_UMCTL2_HWLPCTL_HW_LP_IDLE_X32_M      GENMASK(27, 16)
#define DDR_UMCTL2_HWLPCTL_HW_LP_IDLE_X32_X(x)   (((x) & GENMASK(27, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_REGS:RFSHCTL0 */
#define DDR_UMCTL2_RFSHCTL0(t)    (t + 0x50)

#define DDR_UMCTL2_RFSHCTL0_REFRESH_BURST(x)     (((x) << 4) & GENMASK(8, 4))
#define DDR_UMCTL2_RFSHCTL0_REFRESH_BURST_M      GENMASK(8, 4)
#define DDR_UMCTL2_RFSHCTL0_REFRESH_BURST_X(x)   (((x) & GENMASK(8, 4)) >> 4)

#define DDR_UMCTL2_RFSHCTL0_REFRESH_TO_X32(x)    (((x) << 12) & GENMASK(16, 12))
#define DDR_UMCTL2_RFSHCTL0_REFRESH_TO_X32_M     GENMASK(16, 12)
#define DDR_UMCTL2_RFSHCTL0_REFRESH_TO_X32_X(x)  (((x) & GENMASK(16, 12)) >> 12)

#define DDR_UMCTL2_RFSHCTL0_REFRESH_MARGIN(x)    (((x) << 20) & GENMASK(23, 20))
#define DDR_UMCTL2_RFSHCTL0_REFRESH_MARGIN_M     GENMASK(23, 20)
#define DDR_UMCTL2_RFSHCTL0_REFRESH_MARGIN_X(x)  (((x) & GENMASK(23, 20)) >> 20)

/*      DDR_UMCTL2:UMCTL2_REGS:RFSHCTL3 */
#define DDR_UMCTL2_RFSHCTL3(t)    (t + 0x60)

#define DDR_UMCTL2_RFSHCTL3_DIS_AUTO_REFRESH(x)  ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_RFSHCTL3_DIS_AUTO_REFRESH_M   GENMASK(0, 0)
#define DDR_UMCTL2_RFSHCTL3_DIS_AUTO_REFRESH_X(x) ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_RFSHCTL3_REFRESH_UPDATE_LEVEL(x) (((x) << 1) & GENMASK(1, 1))
#define DDR_UMCTL2_RFSHCTL3_REFRESH_UPDATE_LEVEL_M GENMASK(1, 1)
#define DDR_UMCTL2_RFSHCTL3_REFRESH_UPDATE_LEVEL_X(x)\
	(((x) & GENMASK(1, 1)) >> 1)

/*      DDR_UMCTL2:UMCTL2_REGS:RFSHTMG */
#define DDR_UMCTL2_RFSHTMG(t)     (t + 0x64)

#define DDR_UMCTL2_RFSHTMG_T_RFC_MIN(x)          ((x) & GENMASK(9, 0))
#define DDR_UMCTL2_RFSHTMG_T_RFC_MIN_M           GENMASK(9, 0)
#define DDR_UMCTL2_RFSHTMG_T_RFC_MIN_X(x)        ((x) & GENMASK(9, 0))

#define DDR_UMCTL2_RFSHTMG_T_RFC_NOM_X1_X32(x)   (((x) << 16) & GENMASK(27, 16))
#define DDR_UMCTL2_RFSHTMG_T_RFC_NOM_X1_X32_M    GENMASK(27, 16)
#define DDR_UMCTL2_RFSHTMG_T_RFC_NOM_X1_X32_X(x) (((x) & GENMASK(27, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_REGS:CRCPARCTL0 */
#define DDR_UMCTL2_CRCPARCTL0(t)  (t + 0xc0)

#define DDR_UMCTL2_CRCPARCTL0_DFI_ALERT_ERR_INT_EN(x) ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_M GENMASK(0, 0)
#define DDR_UMCTL2_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_X(x) ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR(x)\
	(((x) << 1) & GENMASK(1, 1))
#define DDR_UMCTL2_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_M GENMASK(1, 1)
#define DDR_UMCTL2_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_X(x)\
	(((x) & GENMASK(1, 1)) >> 1)

#define DDR_UMCTL2_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR(x)\
	(((x) << 2) & GENMASK(2, 2))
#define DDR_UMCTL2_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_M GENMASK(2, 2)
#define DDR_UMCTL2_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_X(x)\
	(((x) & GENMASK(2, 2)) >> 2)

/*      DDR_UMCTL2:UMCTL2_REGS:CRCPARSTAT */
#define DDR_UMCTL2_CRCPARSTAT(t)  (t + 0xcc)

#define DDR_UMCTL2_CRCPARSTAT_DFI_ALERT_ERR_CNT(x) ((x) & GENMASK(15, 0))
#define DDR_UMCTL2_CRCPARSTAT_DFI_ALERT_ERR_CNT_M GENMASK(15, 0)
#define DDR_UMCTL2_CRCPARSTAT_DFI_ALERT_ERR_CNT_X(x) ((x) & GENMASK(15, 0))

#define DDR_UMCTL2_CRCPARSTAT_DFI_ALERT_ERR_INT(x)\
	(((x) << 16) & GENMASK(16, 16))
#define DDR_UMCTL2_CRCPARSTAT_DFI_ALERT_ERR_INT_M GENMASK(16, 16)
#define DDR_UMCTL2_CRCPARSTAT_DFI_ALERT_ERR_INT_X(x)\
	(((x) & GENMASK(16, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_REGS:INIT0 */
#define DDR_UMCTL2_INIT0(t)       (t + 0xd0)

#define DDR_UMCTL2_INIT0_PRE_CKE_X1024(x)        ((x) & GENMASK(11, 0))
#define DDR_UMCTL2_INIT0_PRE_CKE_X1024_M         GENMASK(11, 0)
#define DDR_UMCTL2_INIT0_PRE_CKE_X1024_X(x)      ((x) & GENMASK(11, 0))

#define DDR_UMCTL2_INIT0_POST_CKE_X1024(x)       (((x) << 16) & GENMASK(25, 16))
#define DDR_UMCTL2_INIT0_POST_CKE_X1024_M        GENMASK(25, 16)
#define DDR_UMCTL2_INIT0_POST_CKE_X1024_X(x)     (((x) & GENMASK(25, 16)) >> 16)

#define DDR_UMCTL2_INIT0_SKIP_DRAM_INIT(x)       (((x) << 30) & GENMASK(31, 30))
#define DDR_UMCTL2_INIT0_SKIP_DRAM_INIT_M        GENMASK(31, 30)
#define DDR_UMCTL2_INIT0_SKIP_DRAM_INIT_X(x)     (((x) & GENMASK(31, 30)) >> 30)

/*      DDR_UMCTL2:UMCTL2_REGS:INIT1 */
#define DDR_UMCTL2_INIT1(t)       (t + 0xd4)

#define DDR_UMCTL2_INIT1_PRE_OCD_X32(x)          ((x) & GENMASK(3, 0))
#define DDR_UMCTL2_INIT1_PRE_OCD_X32_M           GENMASK(3, 0)
#define DDR_UMCTL2_INIT1_PRE_OCD_X32_X(x)        ((x) & GENMASK(3, 0))

#define DDR_UMCTL2_INIT1_DRAM_RSTN_X1024(x)      (((x) << 16) & GENMASK(24, 16))
#define DDR_UMCTL2_INIT1_DRAM_RSTN_X1024_M       GENMASK(24, 16)
#define DDR_UMCTL2_INIT1_DRAM_RSTN_X1024_X(x)    (((x) & GENMASK(24, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_REGS:INIT3 */
#define DDR_UMCTL2_INIT3(t)       (t + 0xdc)

#define DDR_UMCTL2_INIT3_EMR(x)                  ((x) & GENMASK(15, 0))
#define DDR_UMCTL2_INIT3_EMR_M                   GENMASK(15, 0)
#define DDR_UMCTL2_INIT3_EMR_X(x)                ((x) & GENMASK(15, 0))

#define DDR_UMCTL2_INIT3_MR(x)                   (((x) << 16) & GENMASK(31, 16))
#define DDR_UMCTL2_INIT3_MR_M                    GENMASK(31, 16)
#define DDR_UMCTL2_INIT3_MR_X(x)                 (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_REGS:INIT4 */
#define DDR_UMCTL2_INIT4(t)       (t + 0xe0)

#define DDR_UMCTL2_INIT4_EMR3(x)                 ((x) & GENMASK(15, 0))
#define DDR_UMCTL2_INIT4_EMR3_M                  GENMASK(15, 0)
#define DDR_UMCTL2_INIT4_EMR3_X(x)               ((x) & GENMASK(15, 0))

#define DDR_UMCTL2_INIT4_EMR2(x)                 (((x) << 16) & GENMASK(31, 16))
#define DDR_UMCTL2_INIT4_EMR2_M                  GENMASK(31, 16)
#define DDR_UMCTL2_INIT4_EMR2_X(x)               (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_REGS:INIT5 */
#define DDR_UMCTL2_INIT5(t)       (t + 0xe4)

#define DDR_UMCTL2_INIT5_DEV_ZQINIT_X32(x)       (((x) << 16) & GENMASK(23, 16))
#define DDR_UMCTL2_INIT5_DEV_ZQINIT_X32_M        GENMASK(23, 16)
#define DDR_UMCTL2_INIT5_DEV_ZQINIT_X32_X(x)     (((x) & GENMASK(23, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_REGS:DIMMCTL */
#define DDR_UMCTL2_DIMMCTL(t)     (t + 0xf0)

#define DDR_UMCTL2_DIMMCTL_DIMM_STAGGER_CS_EN(x) ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_DIMMCTL_DIMM_STAGGER_CS_EN_M  GENMASK(0, 0)
#define DDR_UMCTL2_DIMMCTL_DIMM_STAGGER_CS_EN_X(x) ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_DIMMCTL_DIMM_ADDR_MIRR_EN(x)  (((x) << 1) & GENMASK(1, 1))
#define DDR_UMCTL2_DIMMCTL_DIMM_ADDR_MIRR_EN_M   GENMASK(1, 1)
#define DDR_UMCTL2_DIMMCTL_DIMM_ADDR_MIRR_EN_X(x) (((x) & GENMASK(1, 1)) >> 1)

/*      DDR_UMCTL2:UMCTL2_REGS:DRAMTMG0 */
#define DDR_UMCTL2_DRAMTMG0(t)    (t + 0x100)

#define DDR_UMCTL2_DRAMTMG0_T_RAS_MIN(x)         ((x) & GENMASK(5, 0))
#define DDR_UMCTL2_DRAMTMG0_T_RAS_MIN_M          GENMASK(5, 0)
#define DDR_UMCTL2_DRAMTMG0_T_RAS_MIN_X(x)       ((x) & GENMASK(5, 0))

#define DDR_UMCTL2_DRAMTMG0_T_RAS_MAX(x)         (((x) << 8) & GENMASK(14, 8))
#define DDR_UMCTL2_DRAMTMG0_T_RAS_MAX_M          GENMASK(14, 8)
#define DDR_UMCTL2_DRAMTMG0_T_RAS_MAX_X(x)       (((x) & GENMASK(14, 8)) >> 8)

#define DDR_UMCTL2_DRAMTMG0_T_FAW(x)             (((x) << 16) & GENMASK(21, 16))
#define DDR_UMCTL2_DRAMTMG0_T_FAW_M              GENMASK(21, 16)
#define DDR_UMCTL2_DRAMTMG0_T_FAW_X(x)           (((x) & GENMASK(21, 16)) >> 16)

#define DDR_UMCTL2_DRAMTMG0_WR2PRE(x)            (((x) << 24) & GENMASK(30, 24))
#define DDR_UMCTL2_DRAMTMG0_WR2PRE_M             GENMASK(30, 24)
#define DDR_UMCTL2_DRAMTMG0_WR2PRE_X(x)          (((x) & GENMASK(30, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:DRAMTMG1 */
#define DDR_UMCTL2_DRAMTMG1(t)    (t + 0x104)

#define DDR_UMCTL2_DRAMTMG1_T_RC(x)              ((x) & GENMASK(6, 0))
#define DDR_UMCTL2_DRAMTMG1_T_RC_M               GENMASK(6, 0)
#define DDR_UMCTL2_DRAMTMG1_T_RC_X(x)            ((x) & GENMASK(6, 0))

#define DDR_UMCTL2_DRAMTMG1_RD2PRE(x)            (((x) << 8) & GENMASK(13, 8))
#define DDR_UMCTL2_DRAMTMG1_RD2PRE_M             GENMASK(13, 8)
#define DDR_UMCTL2_DRAMTMG1_RD2PRE_X(x)          (((x) & GENMASK(13, 8)) >> 8)

#define DDR_UMCTL2_DRAMTMG1_T_XP(x)              (((x) << 16) & GENMASK(20, 16))
#define DDR_UMCTL2_DRAMTMG1_T_XP_M               GENMASK(20, 16)
#define DDR_UMCTL2_DRAMTMG1_T_XP_X(x)            (((x) & GENMASK(20, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_REGS:DRAMTMG2 */
#define DDR_UMCTL2_DRAMTMG2(t)    (t + 0x108)

#define DDR_UMCTL2_DRAMTMG2_WR2RD(x)             ((x) & GENMASK(5, 0))
#define DDR_UMCTL2_DRAMTMG2_WR2RD_M              GENMASK(5, 0)
#define DDR_UMCTL2_DRAMTMG2_WR2RD_X(x)           ((x) & GENMASK(5, 0))

#define DDR_UMCTL2_DRAMTMG2_RD2WR(x)             (((x) << 8) & GENMASK(13, 8))
#define DDR_UMCTL2_DRAMTMG2_RD2WR_M              GENMASK(13, 8)
#define DDR_UMCTL2_DRAMTMG2_RD2WR_X(x)           (((x) & GENMASK(13, 8)) >> 8)

/*      DDR_UMCTL2:UMCTL2_REGS:DRAMTMG3 */
#define DDR_UMCTL2_DRAMTMG3(t)    (t + 0x10c)

#define DDR_UMCTL2_DRAMTMG3_T_MOD(x)             ((x) & GENMASK(9, 0))
#define DDR_UMCTL2_DRAMTMG3_T_MOD_M              GENMASK(9, 0)
#define DDR_UMCTL2_DRAMTMG3_T_MOD_X(x)           ((x) & GENMASK(9, 0))

#define DDR_UMCTL2_DRAMTMG3_T_MRD(x)             (((x) << 12) & GENMASK(17, 12))
#define DDR_UMCTL2_DRAMTMG3_T_MRD_M              GENMASK(17, 12)
#define DDR_UMCTL2_DRAMTMG3_T_MRD_X(x)           (((x) & GENMASK(17, 12)) >> 12)

/*      DDR_UMCTL2:UMCTL2_REGS:DRAMTMG4 */
#define DDR_UMCTL2_DRAMTMG4(t)    (t + 0x110)

#define DDR_UMCTL2_DRAMTMG4_T_RP(x)              ((x) & GENMASK(4, 0))
#define DDR_UMCTL2_DRAMTMG4_T_RP_M               GENMASK(4, 0)
#define DDR_UMCTL2_DRAMTMG4_T_RP_X(x)            ((x) & GENMASK(4, 0))

#define DDR_UMCTL2_DRAMTMG4_T_RRD(x)             (((x) << 8) & GENMASK(11, 8))
#define DDR_UMCTL2_DRAMTMG4_T_RRD_M              GENMASK(11, 8)
#define DDR_UMCTL2_DRAMTMG4_T_RRD_X(x)           (((x) & GENMASK(11, 8)) >> 8)

#define DDR_UMCTL2_DRAMTMG4_T_CCD(x)             (((x) << 16) & GENMASK(19, 16))
#define DDR_UMCTL2_DRAMTMG4_T_CCD_M              GENMASK(19, 16)
#define DDR_UMCTL2_DRAMTMG4_T_CCD_X(x)           (((x) & GENMASK(19, 16)) >> 16)

#define DDR_UMCTL2_DRAMTMG4_T_RCD(x)             (((x) << 24) & GENMASK(28, 24))
#define DDR_UMCTL2_DRAMTMG4_T_RCD_M              GENMASK(28, 24)
#define DDR_UMCTL2_DRAMTMG4_T_RCD_X(x)           (((x) & GENMASK(28, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:DRAMTMG5 */
#define DDR_UMCTL2_DRAMTMG5(t)    (t + 0x114)

#define DDR_UMCTL2_DRAMTMG5_T_CKE(x)             ((x) & GENMASK(4, 0))
#define DDR_UMCTL2_DRAMTMG5_T_CKE_M              GENMASK(4, 0)
#define DDR_UMCTL2_DRAMTMG5_T_CKE_X(x)           ((x) & GENMASK(4, 0))

#define DDR_UMCTL2_DRAMTMG5_T_CKESR(x)           (((x) << 8) & GENMASK(13, 8))
#define DDR_UMCTL2_DRAMTMG5_T_CKESR_M            GENMASK(13, 8)
#define DDR_UMCTL2_DRAMTMG5_T_CKESR_X(x)         (((x) & GENMASK(13, 8)) >> 8)

#define DDR_UMCTL2_DRAMTMG5_T_CKSRE(x)           (((x) << 16) & GENMASK(19, 16))
#define DDR_UMCTL2_DRAMTMG5_T_CKSRE_M            GENMASK(19, 16)
#define DDR_UMCTL2_DRAMTMG5_T_CKSRE_X(x)         (((x) & GENMASK(19, 16)) >> 16)

#define DDR_UMCTL2_DRAMTMG5_T_CKSRX(x)           (((x) << 24) & GENMASK(27, 24))
#define DDR_UMCTL2_DRAMTMG5_T_CKSRX_M            GENMASK(27, 24)
#define DDR_UMCTL2_DRAMTMG5_T_CKSRX_X(x)         (((x) & GENMASK(27, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:DRAMTMG8 */
#define DDR_UMCTL2_DRAMTMG8(t)    (t + 0x120)

#define DDR_UMCTL2_DRAMTMG8_T_XS_X32(x)          ((x) & GENMASK(6, 0))
#define DDR_UMCTL2_DRAMTMG8_T_XS_X32_M           GENMASK(6, 0)
#define DDR_UMCTL2_DRAMTMG8_T_XS_X32_X(x)        ((x) & GENMASK(6, 0))

#define DDR_UMCTL2_DRAMTMG8_T_XS_DLL_X32(x)      (((x) << 8) & GENMASK(14, 8))
#define DDR_UMCTL2_DRAMTMG8_T_XS_DLL_X32_M       GENMASK(14, 8)
#define DDR_UMCTL2_DRAMTMG8_T_XS_DLL_X32_X(x)    (((x) & GENMASK(14, 8)) >> 8)

/*      DDR_UMCTL2:UMCTL2_REGS:DRAMTMG15 */
#define DDR_UMCTL2_DRAMTMG15(t)   (t + 0x13c)

#define DDR_UMCTL2_DRAMTMG15_T_STAB_X32(x)       ((x) & GENMASK(7, 0))
#define DDR_UMCTL2_DRAMTMG15_T_STAB_X32_M        GENMASK(7, 0)
#define DDR_UMCTL2_DRAMTMG15_T_STAB_X32_X(x)     ((x) & GENMASK(7, 0))

#define DDR_UMCTL2_DRAMTMG15_EN_DFI_LP_T_STAB(x) (((x) << 31) & GENMASK(31, 31))
#define DDR_UMCTL2_DRAMTMG15_EN_DFI_LP_T_STAB_M  GENMASK(31, 31)
#define DDR_UMCTL2_DRAMTMG15_EN_DFI_LP_T_STAB_X(x)\
	(((x) & GENMASK(31, 31)) >> 31)

/*      DDR_UMCTL2:UMCTL2_REGS:ZQCTL0 */
#define DDR_UMCTL2_ZQCTL0(t)      (t + 0x180)

#define DDR_UMCTL2_ZQCTL0_T_ZQ_SHORT_NOP(x)      ((x) & GENMASK(9, 0))
#define DDR_UMCTL2_ZQCTL0_T_ZQ_SHORT_NOP_M       GENMASK(9, 0)
#define DDR_UMCTL2_ZQCTL0_T_ZQ_SHORT_NOP_X(x)    ((x) & GENMASK(9, 0))

#define DDR_UMCTL2_ZQCTL0_T_ZQ_LONG_NOP(x)       (((x) << 16) & GENMASK(26, 16))
#define DDR_UMCTL2_ZQCTL0_T_ZQ_LONG_NOP_M        GENMASK(26, 16)
#define DDR_UMCTL2_ZQCTL0_T_ZQ_LONG_NOP_X(x)     (((x) & GENMASK(26, 16)) >> 16)

#define DDR_UMCTL2_ZQCTL0_ZQ_RESISTOR_SHARED(x)  (((x) << 29) & GENMASK(29, 29))
#define DDR_UMCTL2_ZQCTL0_ZQ_RESISTOR_SHARED_M   GENMASK(29, 29)
#define DDR_UMCTL2_ZQCTL0_ZQ_RESISTOR_SHARED_X(x)\
	(((x) & GENMASK(29, 29)) >> 29)

#define DDR_UMCTL2_ZQCTL0_DIS_SRX_ZQCL(x)        (((x) << 30) & GENMASK(30, 30))
#define DDR_UMCTL2_ZQCTL0_DIS_SRX_ZQCL_M         GENMASK(30, 30)
#define DDR_UMCTL2_ZQCTL0_DIS_SRX_ZQCL_X(x)      (((x) & GENMASK(30, 30)) >> 30)

#define DDR_UMCTL2_ZQCTL0_DIS_AUTO_ZQ(x)         (((x) << 31) & GENMASK(31, 31))
#define DDR_UMCTL2_ZQCTL0_DIS_AUTO_ZQ_M          GENMASK(31, 31)
#define DDR_UMCTL2_ZQCTL0_DIS_AUTO_ZQ_X(x)       (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_UMCTL2:UMCTL2_REGS:ZQCTL1 */
#define DDR_UMCTL2_ZQCTL1(t)      (t + 0x184)

#define DDR_UMCTL2_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024(x) ((x) & GENMASK(19, 0))
#define DDR_UMCTL2_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_M GENMASK(19, 0)
#define DDR_UMCTL2_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_X(x) ((x) & GENMASK(19, 0))

/*      DDR_UMCTL2:UMCTL2_REGS:DFITMG0 */
#define DDR_UMCTL2_DFITMG0(t)     (t + 0x190)

#define DDR_UMCTL2_DFITMG0_DFI_TPHY_WRLAT(x)     ((x) & GENMASK(5, 0))
#define DDR_UMCTL2_DFITMG0_DFI_TPHY_WRLAT_M      GENMASK(5, 0)
#define DDR_UMCTL2_DFITMG0_DFI_TPHY_WRLAT_X(x)   ((x) & GENMASK(5, 0))

#define DDR_UMCTL2_DFITMG0_DFI_TPHY_WRDATA(x)    (((x) << 8) & GENMASK(13, 8))
#define DDR_UMCTL2_DFITMG0_DFI_TPHY_WRDATA_M     GENMASK(13, 8)
#define DDR_UMCTL2_DFITMG0_DFI_TPHY_WRDATA_X(x)  (((x) & GENMASK(13, 8)) >> 8)

#define DDR_UMCTL2_DFITMG0_DFI_WRDATA_USE_DFI_PHY_CLK(x)\
	(((x) << 15) & GENMASK(15, 15))
#define DDR_UMCTL2_DFITMG0_DFI_WRDATA_USE_DFI_PHY_CLK_M GENMASK(15, 15)
#define DDR_UMCTL2_DFITMG0_DFI_WRDATA_USE_DFI_PHY_CLK_X(x)\
	(((x) & GENMASK(15, 15)) >> 15)

#define DDR_UMCTL2_DFITMG0_DFI_T_RDDATA_EN(x)    (((x) << 16) & GENMASK(22, 16))
#define DDR_UMCTL2_DFITMG0_DFI_T_RDDATA_EN_M     GENMASK(22, 16)
#define DDR_UMCTL2_DFITMG0_DFI_T_RDDATA_EN_X(x)  (((x) & GENMASK(22, 16)) >> 16)

#define DDR_UMCTL2_DFITMG0_DFI_RDDATA_USE_DFI_PHY_CLK(x)\
	(((x) << 23) & GENMASK(23, 23))
#define DDR_UMCTL2_DFITMG0_DFI_RDDATA_USE_DFI_PHY_CLK_M GENMASK(23, 23)
#define DDR_UMCTL2_DFITMG0_DFI_RDDATA_USE_DFI_PHY_CLK_X(x)\
	(((x) & GENMASK(23, 23)) >> 23)

#define DDR_UMCTL2_DFITMG0_DFI_T_CTRL_DELAY(x)   (((x) << 24) & GENMASK(28, 24))
#define DDR_UMCTL2_DFITMG0_DFI_T_CTRL_DELAY_M    GENMASK(28, 24)
#define DDR_UMCTL2_DFITMG0_DFI_T_CTRL_DELAY_X(x) (((x) & GENMASK(28, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:DFITMG1 */
#define DDR_UMCTL2_DFITMG1(t)     (t + 0x194)

#define DDR_UMCTL2_DFITMG1_DFI_T_DRAM_CLK_ENABLE(x) ((x) & GENMASK(4, 0))
#define DDR_UMCTL2_DFITMG1_DFI_T_DRAM_CLK_ENABLE_M GENMASK(4, 0)
#define DDR_UMCTL2_DFITMG1_DFI_T_DRAM_CLK_ENABLE_X(x) ((x) & GENMASK(4, 0))

#define DDR_UMCTL2_DFITMG1_DFI_T_DRAM_CLK_DISABLE(x)\
	(((x) << 8) & GENMASK(12, 8))
#define DDR_UMCTL2_DFITMG1_DFI_T_DRAM_CLK_DISABLE_M GENMASK(12, 8)
#define DDR_UMCTL2_DFITMG1_DFI_T_DRAM_CLK_DISABLE_X(x)\
	(((x) & GENMASK(12, 8)) >> 8)

#define DDR_UMCTL2_DFITMG1_DFI_T_WRDATA_DELAY(x) (((x) << 16) & GENMASK(20, 16))
#define DDR_UMCTL2_DFITMG1_DFI_T_WRDATA_DELAY_M  GENMASK(20, 16)
#define DDR_UMCTL2_DFITMG1_DFI_T_WRDATA_DELAY_X(x)\
	(((x) & GENMASK(20, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_REGS:DFILPCFG0 */
#define DDR_UMCTL2_DFILPCFG0(t)   (t + 0x198)

#define DDR_UMCTL2_DFILPCFG0_DFI_LP_EN_PD(x)     ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_DFILPCFG0_DFI_LP_EN_PD_M      GENMASK(0, 0)
#define DDR_UMCTL2_DFILPCFG0_DFI_LP_EN_PD_X(x)   ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_DFILPCFG0_DFI_LP_WAKEUP_PD(x) (((x) << 4) & GENMASK(7, 4))
#define DDR_UMCTL2_DFILPCFG0_DFI_LP_WAKEUP_PD_M  GENMASK(7, 4)
#define DDR_UMCTL2_DFILPCFG0_DFI_LP_WAKEUP_PD_X(x) (((x) & GENMASK(7, 4)) >> 4)

#define DDR_UMCTL2_DFILPCFG0_DFI_LP_EN_SR(x)     (((x) << 8) & GENMASK(8, 8))
#define DDR_UMCTL2_DFILPCFG0_DFI_LP_EN_SR_M      GENMASK(8, 8)
#define DDR_UMCTL2_DFILPCFG0_DFI_LP_EN_SR_X(x)   (((x) & GENMASK(8, 8)) >> 8)

#define DDR_UMCTL2_DFILPCFG0_DFI_LP_WAKEUP_SR(x) (((x) << 12) & GENMASK(15, 12))
#define DDR_UMCTL2_DFILPCFG0_DFI_LP_WAKEUP_SR_M  GENMASK(15, 12)
#define DDR_UMCTL2_DFILPCFG0_DFI_LP_WAKEUP_SR_X(x)\
	(((x) & GENMASK(15, 12)) >> 12)

#define DDR_UMCTL2_DFILPCFG0_DFI_TLP_RESP(x)     (((x) << 24) & GENMASK(28, 24))
#define DDR_UMCTL2_DFILPCFG0_DFI_TLP_RESP_M      GENMASK(28, 24)
#define DDR_UMCTL2_DFILPCFG0_DFI_TLP_RESP_X(x)   (((x) & GENMASK(28, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:DFIUPD0 */
#define DDR_UMCTL2_DFIUPD0(t)     (t + 0x1a0)

#define DDR_UMCTL2_DFIUPD0_DFI_T_CTRLUP_MIN(x)   ((x) & GENMASK(9, 0))
#define DDR_UMCTL2_DFIUPD0_DFI_T_CTRLUP_MIN_M    GENMASK(9, 0)
#define DDR_UMCTL2_DFIUPD0_DFI_T_CTRLUP_MIN_X(x) ((x) & GENMASK(9, 0))

#define DDR_UMCTL2_DFIUPD0_DFI_T_CTRLUP_MAX(x)   (((x) << 16) & GENMASK(25, 16))
#define DDR_UMCTL2_DFIUPD0_DFI_T_CTRLUP_MAX_M    GENMASK(25, 16)
#define DDR_UMCTL2_DFIUPD0_DFI_T_CTRLUP_MAX_X(x) (((x) & GENMASK(25, 16)) >> 16)

#define DDR_UMCTL2_DFIUPD0_CTRLUPD_PRE_SRX(x)    (((x) << 29) & GENMASK(29, 29))
#define DDR_UMCTL2_DFIUPD0_CTRLUPD_PRE_SRX_M     GENMASK(29, 29)
#define DDR_UMCTL2_DFIUPD0_CTRLUPD_PRE_SRX_X(x)  (((x) & GENMASK(29, 29)) >> 29)

#define DDR_UMCTL2_DFIUPD0_DIS_AUTO_CTRLUPD_SRX(x)\
	(((x) << 30) & GENMASK(30, 30))
#define DDR_UMCTL2_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_M GENMASK(30, 30)
#define DDR_UMCTL2_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_X(x)\
	(((x) & GENMASK(30, 30)) >> 30)

#define DDR_UMCTL2_DFIUPD0_DIS_AUTO_CTRLUPD(x)   (((x) << 31) & GENMASK(31, 31))
#define DDR_UMCTL2_DFIUPD0_DIS_AUTO_CTRLUPD_M    GENMASK(31, 31)
#define DDR_UMCTL2_DFIUPD0_DIS_AUTO_CTRLUPD_X(x) (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_UMCTL2:UMCTL2_REGS:DFIUPD1 */
#define DDR_UMCTL2_DFIUPD1(t)     (t + 0x1a4)

#define DDR_UMCTL2_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024(x)\
	((x) & GENMASK(7, 0))
#define DDR_UMCTL2_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_M GENMASK(7, 0)
#define DDR_UMCTL2_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_X(x)\
	((x) & GENMASK(7, 0))

#define DDR_UMCTL2_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024(x)\
	(((x) << 16) & GENMASK(23, 16))
#define DDR_UMCTL2_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_M GENMASK(23, 16)
#define DDR_UMCTL2_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_X(x)\
	(((x) & GENMASK(23, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_REGS:DFIUPD2 */
#define DDR_UMCTL2_DFIUPD2(t)     (t + 0x1a8)

#define DDR_UMCTL2_DFIUPD2_DFI_PHYUPD_EN(x)      (((x) << 31) & GENMASK(31, 31))
#define DDR_UMCTL2_DFIUPD2_DFI_PHYUPD_EN_M       GENMASK(31, 31)
#define DDR_UMCTL2_DFIUPD2_DFI_PHYUPD_EN_X(x)    (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_UMCTL2:UMCTL2_REGS:DFIMISC */
#define DDR_UMCTL2_DFIMISC(t)     (t + 0x1b0)

#define DDR_UMCTL2_DFIMISC_DFI_INIT_COMPLETE_EN(x) ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_DFIMISC_DFI_INIT_COMPLETE_EN_M GENMASK(0, 0)
#define DDR_UMCTL2_DFIMISC_DFI_INIT_COMPLETE_EN_X(x) ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_DFIMISC_DFI_DATA_CS_POLARITY(x) (((x) << 2) & GENMASK(2, 2))
#define DDR_UMCTL2_DFIMISC_DFI_DATA_CS_POLARITY_M GENMASK(2, 2)
#define DDR_UMCTL2_DFIMISC_DFI_DATA_CS_POLARITY_X(x)\
	(((x) & GENMASK(2, 2)) >> 2)

#define DDR_UMCTL2_DFIMISC_CTL_IDLE_EN(x)        (((x) << 4) & GENMASK(4, 4))
#define DDR_UMCTL2_DFIMISC_CTL_IDLE_EN_M         GENMASK(4, 4)
#define DDR_UMCTL2_DFIMISC_CTL_IDLE_EN_X(x)      (((x) & GENMASK(4, 4)) >> 4)

#define DDR_UMCTL2_DFIMISC_DFI_INIT_START(x)     (((x) << 5) & GENMASK(5, 5))
#define DDR_UMCTL2_DFIMISC_DFI_INIT_START_M      GENMASK(5, 5)
#define DDR_UMCTL2_DFIMISC_DFI_INIT_START_X(x)   (((x) & GENMASK(5, 5)) >> 5)

#define DDR_UMCTL2_DFIMISC_DFI_FREQUENCY(x)      (((x) << 8) & GENMASK(12, 8))
#define DDR_UMCTL2_DFIMISC_DFI_FREQUENCY_M       GENMASK(12, 8)
#define DDR_UMCTL2_DFIMISC_DFI_FREQUENCY_X(x)    (((x) & GENMASK(12, 8)) >> 8)

/*      DDR_UMCTL2:UMCTL2_REGS:DFITMG2 */
#define DDR_UMCTL2_DFITMG2(t)     (t + 0x1b4)

#define DDR_UMCTL2_DFITMG2_DFI_TPHY_WRCSLAT(x)   ((x) & GENMASK(5, 0))
#define DDR_UMCTL2_DFITMG2_DFI_TPHY_WRCSLAT_M    GENMASK(5, 0)
#define DDR_UMCTL2_DFITMG2_DFI_TPHY_WRCSLAT_X(x) ((x) & GENMASK(5, 0))

#define DDR_UMCTL2_DFITMG2_DFI_TPHY_RDCSLAT(x)   (((x) << 8) & GENMASK(14, 8))
#define DDR_UMCTL2_DFITMG2_DFI_TPHY_RDCSLAT_M    GENMASK(14, 8)
#define DDR_UMCTL2_DFITMG2_DFI_TPHY_RDCSLAT_X(x) (((x) & GENMASK(14, 8)) >> 8)

/*      DDR_UMCTL2:UMCTL2_REGS:DFISTAT */
#define DDR_UMCTL2_DFISTAT(t)     (t + 0x1bc)

#define DDR_UMCTL2_DFISTAT_DFI_INIT_COMPLETE(x)  ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_DFISTAT_DFI_INIT_COMPLETE_M   GENMASK(0, 0)
#define DDR_UMCTL2_DFISTAT_DFI_INIT_COMPLETE_X(x) ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_DFISTAT_DFI_LP_ACK(x)         (((x) << 1) & GENMASK(1, 1))
#define DDR_UMCTL2_DFISTAT_DFI_LP_ACK_M          GENMASK(1, 1)
#define DDR_UMCTL2_DFISTAT_DFI_LP_ACK_X(x)       (((x) & GENMASK(1, 1)) >> 1)

/*      DDR_UMCTL2:UMCTL2_REGS:DFIPHYMSTR */
#define DDR_UMCTL2_DFIPHYMSTR(t)  (t + 0x1c4)

#define DDR_UMCTL2_DFIPHYMSTR_DFI_PHYMSTR_EN(x)  ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_DFIPHYMSTR_DFI_PHYMSTR_EN_M   GENMASK(0, 0)
#define DDR_UMCTL2_DFIPHYMSTR_DFI_PHYMSTR_EN_X(x) ((x) & GENMASK(0, 0))

/*      DDR_UMCTL2:UMCTL2_REGS:ADDRMAP1 */
#define DDR_UMCTL2_ADDRMAP1(t)    (t + 0x204)

#define DDR_UMCTL2_ADDRMAP1_ADDRMAP_BANK_B0(x)   ((x) & GENMASK(5, 0))
#define DDR_UMCTL2_ADDRMAP1_ADDRMAP_BANK_B0_M    GENMASK(5, 0)
#define DDR_UMCTL2_ADDRMAP1_ADDRMAP_BANK_B0_X(x) ((x) & GENMASK(5, 0))

#define DDR_UMCTL2_ADDRMAP1_ADDRMAP_BANK_B1(x)   (((x) << 8) & GENMASK(13, 8))
#define DDR_UMCTL2_ADDRMAP1_ADDRMAP_BANK_B1_M    GENMASK(13, 8)
#define DDR_UMCTL2_ADDRMAP1_ADDRMAP_BANK_B1_X(x) (((x) & GENMASK(13, 8)) >> 8)

#define DDR_UMCTL2_ADDRMAP1_ADDRMAP_BANK_B2(x)   (((x) << 16) & GENMASK(21, 16))
#define DDR_UMCTL2_ADDRMAP1_ADDRMAP_BANK_B2_M    GENMASK(21, 16)
#define DDR_UMCTL2_ADDRMAP1_ADDRMAP_BANK_B2_X(x) (((x) & GENMASK(21, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_REGS:ADDRMAP2 */
#define DDR_UMCTL2_ADDRMAP2(t)    (t + 0x208)

#define DDR_UMCTL2_ADDRMAP2_ADDRMAP_COL_B2(x)    ((x) & GENMASK(3, 0))
#define DDR_UMCTL2_ADDRMAP2_ADDRMAP_COL_B2_M     GENMASK(3, 0)
#define DDR_UMCTL2_ADDRMAP2_ADDRMAP_COL_B2_X(x)  ((x) & GENMASK(3, 0))

#define DDR_UMCTL2_ADDRMAP2_ADDRMAP_COL_B3(x)    (((x) << 8) & GENMASK(11, 8))
#define DDR_UMCTL2_ADDRMAP2_ADDRMAP_COL_B3_M     GENMASK(11, 8)
#define DDR_UMCTL2_ADDRMAP2_ADDRMAP_COL_B3_X(x)  (((x) & GENMASK(11, 8)) >> 8)

#define DDR_UMCTL2_ADDRMAP2_ADDRMAP_COL_B4(x)    (((x) << 16) & GENMASK(19, 16))
#define DDR_UMCTL2_ADDRMAP2_ADDRMAP_COL_B4_M     GENMASK(19, 16)
#define DDR_UMCTL2_ADDRMAP2_ADDRMAP_COL_B4_X(x)  (((x) & GENMASK(19, 16)) >> 16)

#define DDR_UMCTL2_ADDRMAP2_ADDRMAP_COL_B5(x)    (((x) << 24) & GENMASK(27, 24))
#define DDR_UMCTL2_ADDRMAP2_ADDRMAP_COL_B5_M     GENMASK(27, 24)
#define DDR_UMCTL2_ADDRMAP2_ADDRMAP_COL_B5_X(x)  (((x) & GENMASK(27, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:ADDRMAP3 */
#define DDR_UMCTL2_ADDRMAP3(t)    (t + 0x20c)

#define DDR_UMCTL2_ADDRMAP3_ADDRMAP_COL_B6(x)    ((x) & GENMASK(3, 0))
#define DDR_UMCTL2_ADDRMAP3_ADDRMAP_COL_B6_M     GENMASK(3, 0)
#define DDR_UMCTL2_ADDRMAP3_ADDRMAP_COL_B6_X(x)  ((x) & GENMASK(3, 0))

#define DDR_UMCTL2_ADDRMAP3_ADDRMAP_COL_B7(x)    (((x) << 8) & GENMASK(12, 8))
#define DDR_UMCTL2_ADDRMAP3_ADDRMAP_COL_B7_M     GENMASK(12, 8)
#define DDR_UMCTL2_ADDRMAP3_ADDRMAP_COL_B7_X(x)  (((x) & GENMASK(12, 8)) >> 8)

#define DDR_UMCTL2_ADDRMAP3_ADDRMAP_COL_B8(x)    (((x) << 16) & GENMASK(20, 16))
#define DDR_UMCTL2_ADDRMAP3_ADDRMAP_COL_B8_M     GENMASK(20, 16)
#define DDR_UMCTL2_ADDRMAP3_ADDRMAP_COL_B8_X(x)  (((x) & GENMASK(20, 16)) >> 16)

#define DDR_UMCTL2_ADDRMAP3_ADDRMAP_COL_B9(x)    (((x) << 24) & GENMASK(28, 24))
#define DDR_UMCTL2_ADDRMAP3_ADDRMAP_COL_B9_M     GENMASK(28, 24)
#define DDR_UMCTL2_ADDRMAP3_ADDRMAP_COL_B9_X(x)  (((x) & GENMASK(28, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:ADDRMAP4 */
#define DDR_UMCTL2_ADDRMAP4(t)    (t + 0x210)

#define DDR_UMCTL2_ADDRMAP4_ADDRMAP_COL_B10(x)   ((x) & GENMASK(4, 0))
#define DDR_UMCTL2_ADDRMAP4_ADDRMAP_COL_B10_M    GENMASK(4, 0)
#define DDR_UMCTL2_ADDRMAP4_ADDRMAP_COL_B10_X(x) ((x) & GENMASK(4, 0))

#define DDR_UMCTL2_ADDRMAP4_ADDRMAP_COL_B11(x)   (((x) << 8) & GENMASK(12, 8))
#define DDR_UMCTL2_ADDRMAP4_ADDRMAP_COL_B11_M    GENMASK(12, 8)
#define DDR_UMCTL2_ADDRMAP4_ADDRMAP_COL_B11_X(x) (((x) & GENMASK(12, 8)) >> 8)

/*      DDR_UMCTL2:UMCTL2_REGS:ADDRMAP5 */
#define DDR_UMCTL2_ADDRMAP5(t)    (t + 0x214)

#define DDR_UMCTL2_ADDRMAP5_ADDRMAP_ROW_B0(x)    ((x) & GENMASK(3, 0))
#define DDR_UMCTL2_ADDRMAP5_ADDRMAP_ROW_B0_M     GENMASK(3, 0)
#define DDR_UMCTL2_ADDRMAP5_ADDRMAP_ROW_B0_X(x)  ((x) & GENMASK(3, 0))

#define DDR_UMCTL2_ADDRMAP5_ADDRMAP_ROW_B1(x)    (((x) << 8) & GENMASK(11, 8))
#define DDR_UMCTL2_ADDRMAP5_ADDRMAP_ROW_B1_M     GENMASK(11, 8)
#define DDR_UMCTL2_ADDRMAP5_ADDRMAP_ROW_B1_X(x)  (((x) & GENMASK(11, 8)) >> 8)

#define DDR_UMCTL2_ADDRMAP5_ADDRMAP_ROW_B2_10(x) (((x) << 16) & GENMASK(19, 16))
#define DDR_UMCTL2_ADDRMAP5_ADDRMAP_ROW_B2_10_M  GENMASK(19, 16)
#define DDR_UMCTL2_ADDRMAP5_ADDRMAP_ROW_B2_10_X(x)\
	(((x) & GENMASK(19, 16)) >> 16)

#define DDR_UMCTL2_ADDRMAP5_ADDRMAP_ROW_B11(x)   (((x) << 24) & GENMASK(27, 24))
#define DDR_UMCTL2_ADDRMAP5_ADDRMAP_ROW_B11_M    GENMASK(27, 24)
#define DDR_UMCTL2_ADDRMAP5_ADDRMAP_ROW_B11_X(x) (((x) & GENMASK(27, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:ADDRMAP6 */
#define DDR_UMCTL2_ADDRMAP6(t)    (t + 0x218)

#define DDR_UMCTL2_ADDRMAP6_ADDRMAP_ROW_B12(x)   ((x) & GENMASK(3, 0))
#define DDR_UMCTL2_ADDRMAP6_ADDRMAP_ROW_B12_M    GENMASK(3, 0)
#define DDR_UMCTL2_ADDRMAP6_ADDRMAP_ROW_B12_X(x) ((x) & GENMASK(3, 0))

#define DDR_UMCTL2_ADDRMAP6_ADDRMAP_ROW_B13(x)   (((x) << 8) & GENMASK(11, 8))
#define DDR_UMCTL2_ADDRMAP6_ADDRMAP_ROW_B13_M    GENMASK(11, 8)
#define DDR_UMCTL2_ADDRMAP6_ADDRMAP_ROW_B13_X(x) (((x) & GENMASK(11, 8)) >> 8)

#define DDR_UMCTL2_ADDRMAP6_ADDRMAP_ROW_B14(x)   (((x) << 16) & GENMASK(19, 16))
#define DDR_UMCTL2_ADDRMAP6_ADDRMAP_ROW_B14_M    GENMASK(19, 16)
#define DDR_UMCTL2_ADDRMAP6_ADDRMAP_ROW_B14_X(x) (((x) & GENMASK(19, 16)) >> 16)

#define DDR_UMCTL2_ADDRMAP6_ADDRMAP_ROW_B15(x)   (((x) << 24) & GENMASK(27, 24))
#define DDR_UMCTL2_ADDRMAP6_ADDRMAP_ROW_B15_M    GENMASK(27, 24)
#define DDR_UMCTL2_ADDRMAP6_ADDRMAP_ROW_B15_X(x) (((x) & GENMASK(27, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:ADDRMAP9 */
#define DDR_UMCTL2_ADDRMAP9(t)    (t + 0x224)

#define DDR_UMCTL2_ADDRMAP9_ADDRMAP_ROW_B2(x)    ((x) & GENMASK(3, 0))
#define DDR_UMCTL2_ADDRMAP9_ADDRMAP_ROW_B2_M     GENMASK(3, 0)
#define DDR_UMCTL2_ADDRMAP9_ADDRMAP_ROW_B2_X(x)  ((x) & GENMASK(3, 0))

#define DDR_UMCTL2_ADDRMAP9_ADDRMAP_ROW_B3(x)    (((x) << 8) & GENMASK(11, 8))
#define DDR_UMCTL2_ADDRMAP9_ADDRMAP_ROW_B3_M     GENMASK(11, 8)
#define DDR_UMCTL2_ADDRMAP9_ADDRMAP_ROW_B3_X(x)  (((x) & GENMASK(11, 8)) >> 8)

#define DDR_UMCTL2_ADDRMAP9_ADDRMAP_ROW_B4(x)    (((x) << 16) & GENMASK(19, 16))
#define DDR_UMCTL2_ADDRMAP9_ADDRMAP_ROW_B4_M     GENMASK(19, 16)
#define DDR_UMCTL2_ADDRMAP9_ADDRMAP_ROW_B4_X(x)  (((x) & GENMASK(19, 16)) >> 16)

#define DDR_UMCTL2_ADDRMAP9_ADDRMAP_ROW_B5(x)    (((x) << 24) & GENMASK(27, 24))
#define DDR_UMCTL2_ADDRMAP9_ADDRMAP_ROW_B5_M     GENMASK(27, 24)
#define DDR_UMCTL2_ADDRMAP9_ADDRMAP_ROW_B5_X(x)  (((x) & GENMASK(27, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:ADDRMAP10 */
#define DDR_UMCTL2_ADDRMAP10(t)   (t + 0x228)

#define DDR_UMCTL2_ADDRMAP10_ADDRMAP_ROW_B6(x)   ((x) & GENMASK(3, 0))
#define DDR_UMCTL2_ADDRMAP10_ADDRMAP_ROW_B6_M    GENMASK(3, 0)
#define DDR_UMCTL2_ADDRMAP10_ADDRMAP_ROW_B6_X(x) ((x) & GENMASK(3, 0))

#define DDR_UMCTL2_ADDRMAP10_ADDRMAP_ROW_B7(x)   (((x) << 8) & GENMASK(11, 8))
#define DDR_UMCTL2_ADDRMAP10_ADDRMAP_ROW_B7_M    GENMASK(11, 8)
#define DDR_UMCTL2_ADDRMAP10_ADDRMAP_ROW_B7_X(x) (((x) & GENMASK(11, 8)) >> 8)

#define DDR_UMCTL2_ADDRMAP10_ADDRMAP_ROW_B8(x)   (((x) << 16) & GENMASK(19, 16))
#define DDR_UMCTL2_ADDRMAP10_ADDRMAP_ROW_B8_M    GENMASK(19, 16)
#define DDR_UMCTL2_ADDRMAP10_ADDRMAP_ROW_B8_X(x) (((x) & GENMASK(19, 16)) >> 16)

#define DDR_UMCTL2_ADDRMAP10_ADDRMAP_ROW_B9(x)   (((x) << 24) & GENMASK(27, 24))
#define DDR_UMCTL2_ADDRMAP10_ADDRMAP_ROW_B9_M    GENMASK(27, 24)
#define DDR_UMCTL2_ADDRMAP10_ADDRMAP_ROW_B9_X(x) (((x) & GENMASK(27, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:ADDRMAP11 */
#define DDR_UMCTL2_ADDRMAP11(t)   (t + 0x22c)

#define DDR_UMCTL2_ADDRMAP11_ADDRMAP_ROW_B10(x)  ((x) & GENMASK(3, 0))
#define DDR_UMCTL2_ADDRMAP11_ADDRMAP_ROW_B10_M   GENMASK(3, 0)
#define DDR_UMCTL2_ADDRMAP11_ADDRMAP_ROW_B10_X(x) ((x) & GENMASK(3, 0))

/*      DDR_UMCTL2:UMCTL2_REGS:ODTCFG */
#define DDR_UMCTL2_ODTCFG(t)      (t + 0x240)

#define DDR_UMCTL2_ODTCFG_RD_ODT_DELAY(x)        (((x) << 2) & GENMASK(6, 2))
#define DDR_UMCTL2_ODTCFG_RD_ODT_DELAY_M         GENMASK(6, 2)
#define DDR_UMCTL2_ODTCFG_RD_ODT_DELAY_X(x)      (((x) & GENMASK(6, 2)) >> 2)

#define DDR_UMCTL2_ODTCFG_RD_ODT_HOLD(x)         (((x) << 8) & GENMASK(11, 8))
#define DDR_UMCTL2_ODTCFG_RD_ODT_HOLD_M          GENMASK(11, 8)
#define DDR_UMCTL2_ODTCFG_RD_ODT_HOLD_X(x)       (((x) & GENMASK(11, 8)) >> 8)

#define DDR_UMCTL2_ODTCFG_WR_ODT_DELAY(x)        (((x) << 16) & GENMASK(20, 16))
#define DDR_UMCTL2_ODTCFG_WR_ODT_DELAY_M         GENMASK(20, 16)
#define DDR_UMCTL2_ODTCFG_WR_ODT_DELAY_X(x)      (((x) & GENMASK(20, 16)) >> 16)

#define DDR_UMCTL2_ODTCFG_WR_ODT_HOLD(x)         (((x) << 24) & GENMASK(27, 24))
#define DDR_UMCTL2_ODTCFG_WR_ODT_HOLD_M          GENMASK(27, 24)
#define DDR_UMCTL2_ODTCFG_WR_ODT_HOLD_X(x)       (((x) & GENMASK(27, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:ODTMAP */
#define DDR_UMCTL2_ODTMAP(t)      (t + 0x244)

#define DDR_UMCTL2_ODTMAP_RANK0_WR_ODT(x)        ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_ODTMAP_RANK0_WR_ODT_M         GENMASK(0, 0)
#define DDR_UMCTL2_ODTMAP_RANK0_WR_ODT_X(x)      ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_ODTMAP_RANK0_RD_ODT(x)        (((x) << 4) & GENMASK(4, 4))
#define DDR_UMCTL2_ODTMAP_RANK0_RD_ODT_M         GENMASK(4, 4)
#define DDR_UMCTL2_ODTMAP_RANK0_RD_ODT_X(x)      (((x) & GENMASK(4, 4)) >> 4)

/*      DDR_UMCTL2:UMCTL2_REGS:SCHED */
#define DDR_UMCTL2_SCHED(t)       (t + 0x250)

#define DDR_UMCTL2_SCHED_FORCE_LOW_PRI_N(x)      ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_SCHED_FORCE_LOW_PRI_N_M       GENMASK(0, 0)
#define DDR_UMCTL2_SCHED_FORCE_LOW_PRI_N_X(x)    ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_SCHED_PREFER_WRITE(x)         (((x) << 1) & GENMASK(1, 1))
#define DDR_UMCTL2_SCHED_PREFER_WRITE_M          GENMASK(1, 1)
#define DDR_UMCTL2_SCHED_PREFER_WRITE_X(x)       (((x) & GENMASK(1, 1)) >> 1)

#define DDR_UMCTL2_SCHED_PAGECLOSE(x)            (((x) << 2) & GENMASK(2, 2))
#define DDR_UMCTL2_SCHED_PAGECLOSE_M             GENMASK(2, 2)
#define DDR_UMCTL2_SCHED_PAGECLOSE_X(x)          (((x) & GENMASK(2, 2)) >> 2)

#define DDR_UMCTL2_SCHED_LPR_NUM_ENTRIES(x)      (((x) << 8) & GENMASK(12, 8))
#define DDR_UMCTL2_SCHED_LPR_NUM_ENTRIES_M       GENMASK(12, 8)
#define DDR_UMCTL2_SCHED_LPR_NUM_ENTRIES_X(x)    (((x) & GENMASK(12, 8)) >> 8)

#define DDR_UMCTL2_SCHED_GO2CRITICAL_HYSTERESIS(x)\
	(((x) << 16) & GENMASK(23, 16))
#define DDR_UMCTL2_SCHED_GO2CRITICAL_HYSTERESIS_M GENMASK(23, 16)
#define DDR_UMCTL2_SCHED_GO2CRITICAL_HYSTERESIS_X(x)\
	(((x) & GENMASK(23, 16)) >> 16)

#define DDR_UMCTL2_SCHED_RDWR_IDLE_GAP(x)        (((x) << 24) & GENMASK(30, 24))
#define DDR_UMCTL2_SCHED_RDWR_IDLE_GAP_M         GENMASK(30, 24)
#define DDR_UMCTL2_SCHED_RDWR_IDLE_GAP_X(x)      (((x) & GENMASK(30, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:SCHED1 */
#define DDR_UMCTL2_SCHED1(t)      (t + 0x254)

#define DDR_UMCTL2_SCHED1_PAGECLOSE_TIMER(x)     ((x) & GENMASK(7, 0))
#define DDR_UMCTL2_SCHED1_PAGECLOSE_TIMER_M      GENMASK(7, 0)
#define DDR_UMCTL2_SCHED1_PAGECLOSE_TIMER_X(x)   ((x) & GENMASK(7, 0))

/*      DDR_UMCTL2:UMCTL2_REGS:PERFHPR1 */
#define DDR_UMCTL2_PERFHPR1(t)    (t + 0x25c)

#define DDR_UMCTL2_PERFHPR1_HPR_MAX_STARVE(x)    ((x) & GENMASK(15, 0))
#define DDR_UMCTL2_PERFHPR1_HPR_MAX_STARVE_M     GENMASK(15, 0)
#define DDR_UMCTL2_PERFHPR1_HPR_MAX_STARVE_X(x)  ((x) & GENMASK(15, 0))

#define DDR_UMCTL2_PERFHPR1_HPR_XACT_RUN_LENGTH(x)\
	(((x) << 24) & GENMASK(31, 24))
#define DDR_UMCTL2_PERFHPR1_HPR_XACT_RUN_LENGTH_M GENMASK(31, 24)
#define DDR_UMCTL2_PERFHPR1_HPR_XACT_RUN_LENGTH_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:PERFLPR1 */
#define DDR_UMCTL2_PERFLPR1(t)    (t + 0x264)

#define DDR_UMCTL2_PERFLPR1_LPR_MAX_STARVE(x)    ((x) & GENMASK(15, 0))
#define DDR_UMCTL2_PERFLPR1_LPR_MAX_STARVE_M     GENMASK(15, 0)
#define DDR_UMCTL2_PERFLPR1_LPR_MAX_STARVE_X(x)  ((x) & GENMASK(15, 0))

#define DDR_UMCTL2_PERFLPR1_LPR_XACT_RUN_LENGTH(x)\
	(((x) << 24) & GENMASK(31, 24))
#define DDR_UMCTL2_PERFLPR1_LPR_XACT_RUN_LENGTH_M GENMASK(31, 24)
#define DDR_UMCTL2_PERFLPR1_LPR_XACT_RUN_LENGTH_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:PERFWR1 */
#define DDR_UMCTL2_PERFWR1(t)     (t + 0x26c)

#define DDR_UMCTL2_PERFWR1_W_MAX_STARVE(x)       ((x) & GENMASK(15, 0))
#define DDR_UMCTL2_PERFWR1_W_MAX_STARVE_M        GENMASK(15, 0)
#define DDR_UMCTL2_PERFWR1_W_MAX_STARVE_X(x)     ((x) & GENMASK(15, 0))

#define DDR_UMCTL2_PERFWR1_W_XACT_RUN_LENGTH(x)  (((x) << 24) & GENMASK(31, 24))
#define DDR_UMCTL2_PERFWR1_W_XACT_RUN_LENGTH_M   GENMASK(31, 24)
#define DDR_UMCTL2_PERFWR1_W_XACT_RUN_LENGTH_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:DBG0 */
#define DDR_UMCTL2_DBG0(t)        (t + 0x300)

#define DDR_UMCTL2_DBG0_DIS_WC(x)                ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_DBG0_DIS_WC_M                 GENMASK(0, 0)
#define DDR_UMCTL2_DBG0_DIS_WC_X(x)              ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_DBG0_DIS_COLLISION_PAGE_OPT(x) (((x) << 4) & GENMASK(4, 4))
#define DDR_UMCTL2_DBG0_DIS_COLLISION_PAGE_OPT_M GENMASK(4, 4)
#define DDR_UMCTL2_DBG0_DIS_COLLISION_PAGE_OPT_X(x) (((x) & GENMASK(4, 4)) >> 4)

/*      DDR_UMCTL2:UMCTL2_REGS:DBG1 */
#define DDR_UMCTL2_DBG1(t)        (t + 0x304)

#define DDR_UMCTL2_DBG1_DIS_DQ(x)                ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_DBG1_DIS_DQ_M                 GENMASK(0, 0)
#define DDR_UMCTL2_DBG1_DIS_DQ_X(x)              ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_DBG1_DIS_HIF(x)               (((x) << 1) & GENMASK(1, 1))
#define DDR_UMCTL2_DBG1_DIS_HIF_M                GENMASK(1, 1)
#define DDR_UMCTL2_DBG1_DIS_HIF_X(x)             (((x) & GENMASK(1, 1)) >> 1)

/*      DDR_UMCTL2:UMCTL2_REGS:DBGCAM */
#define DDR_UMCTL2_DBGCAM(t)      (t + 0x308)

#define DDR_UMCTL2_DBGCAM_DBG_HPR_Q_DEPTH(x)     ((x) & GENMASK(5, 0))
#define DDR_UMCTL2_DBGCAM_DBG_HPR_Q_DEPTH_M      GENMASK(5, 0)
#define DDR_UMCTL2_DBGCAM_DBG_HPR_Q_DEPTH_X(x)   ((x) & GENMASK(5, 0))

#define DDR_UMCTL2_DBGCAM_DBG_LPR_Q_DEPTH(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_UMCTL2_DBGCAM_DBG_LPR_Q_DEPTH_M      GENMASK(13, 8)
#define DDR_UMCTL2_DBGCAM_DBG_LPR_Q_DEPTH_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_UMCTL2_DBGCAM_DBG_W_Q_DEPTH(x)       (((x) << 16) & GENMASK(21, 16))
#define DDR_UMCTL2_DBGCAM_DBG_W_Q_DEPTH_M        GENMASK(21, 16)
#define DDR_UMCTL2_DBGCAM_DBG_W_Q_DEPTH_X(x)     (((x) & GENMASK(21, 16)) >> 16)

#define DDR_UMCTL2_DBGCAM_DBG_STALL(x)           (((x) << 24) & GENMASK(24, 24))
#define DDR_UMCTL2_DBGCAM_DBG_STALL_M            GENMASK(24, 24)
#define DDR_UMCTL2_DBGCAM_DBG_STALL_X(x)         (((x) & GENMASK(24, 24)) >> 24)

#define DDR_UMCTL2_DBGCAM_DBG_RD_Q_EMPTY(x)      (((x) << 25) & GENMASK(25, 25))
#define DDR_UMCTL2_DBGCAM_DBG_RD_Q_EMPTY_M       GENMASK(25, 25)
#define DDR_UMCTL2_DBGCAM_DBG_RD_Q_EMPTY_X(x)    (((x) & GENMASK(25, 25)) >> 25)

#define DDR_UMCTL2_DBGCAM_DBG_WR_Q_EMPTY(x)      (((x) << 26) & GENMASK(26, 26))
#define DDR_UMCTL2_DBGCAM_DBG_WR_Q_EMPTY_M       GENMASK(26, 26)
#define DDR_UMCTL2_DBGCAM_DBG_WR_Q_EMPTY_X(x)    (((x) & GENMASK(26, 26)) >> 26)

#define DDR_UMCTL2_DBGCAM_RD_DATA_PIPELINE_EMPTY(x)\
	(((x) << 28) & GENMASK(28, 28))
#define DDR_UMCTL2_DBGCAM_RD_DATA_PIPELINE_EMPTY_M GENMASK(28, 28)
#define DDR_UMCTL2_DBGCAM_RD_DATA_PIPELINE_EMPTY_X(x)\
	(((x) & GENMASK(28, 28)) >> 28)

#define DDR_UMCTL2_DBGCAM_WR_DATA_PIPELINE_EMPTY(x)\
	(((x) << 29) & GENMASK(29, 29))
#define DDR_UMCTL2_DBGCAM_WR_DATA_PIPELINE_EMPTY_M GENMASK(29, 29)
#define DDR_UMCTL2_DBGCAM_WR_DATA_PIPELINE_EMPTY_X(x)\
	(((x) & GENMASK(29, 29)) >> 29)

/*      DDR_UMCTL2:UMCTL2_REGS:DBGCMD */
#define DDR_UMCTL2_DBGCMD(t)      (t + 0x30c)

#define DDR_UMCTL2_DBGCMD_RANK0_REFRESH(x)       ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_DBGCMD_RANK0_REFRESH_M        GENMASK(0, 0)
#define DDR_UMCTL2_DBGCMD_RANK0_REFRESH_X(x)     ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_DBGCMD_ZQ_CALIB_SHORT(x)      (((x) << 4) & GENMASK(4, 4))
#define DDR_UMCTL2_DBGCMD_ZQ_CALIB_SHORT_M       GENMASK(4, 4)
#define DDR_UMCTL2_DBGCMD_ZQ_CALIB_SHORT_X(x)    (((x) & GENMASK(4, 4)) >> 4)

#define DDR_UMCTL2_DBGCMD_CTRLUPD(x)             (((x) << 5) & GENMASK(5, 5))
#define DDR_UMCTL2_DBGCMD_CTRLUPD_M              GENMASK(5, 5)
#define DDR_UMCTL2_DBGCMD_CTRLUPD_X(x)           (((x) & GENMASK(5, 5)) >> 5)

/*      DDR_UMCTL2:UMCTL2_REGS:DBGSTAT */
#define DDR_UMCTL2_DBGSTAT(t)     (t + 0x310)

#define DDR_UMCTL2_DBGSTAT_RANK0_REFRESH_BUSY(x) ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_DBGSTAT_RANK0_REFRESH_BUSY_M  GENMASK(0, 0)
#define DDR_UMCTL2_DBGSTAT_RANK0_REFRESH_BUSY_X(x) ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_DBGSTAT_ZQ_CALIB_SHORT_BUSY(x) (((x) << 4) & GENMASK(4, 4))
#define DDR_UMCTL2_DBGSTAT_ZQ_CALIB_SHORT_BUSY_M GENMASK(4, 4)
#define DDR_UMCTL2_DBGSTAT_ZQ_CALIB_SHORT_BUSY_X(x) (((x) & GENMASK(4, 4)) >> 4)

#define DDR_UMCTL2_DBGSTAT_CTRLUPD_BUSY(x)       (((x) << 5) & GENMASK(5, 5))
#define DDR_UMCTL2_DBGSTAT_CTRLUPD_BUSY_M        GENMASK(5, 5)
#define DDR_UMCTL2_DBGSTAT_CTRLUPD_BUSY_X(x)     (((x) & GENMASK(5, 5)) >> 5)

/*      DDR_UMCTL2:UMCTL2_REGS:SWCTL */
#define DDR_UMCTL2_SWCTL(t)       (t + 0x320)

#define DDR_UMCTL2_SWCTL_SW_DONE(x)              ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_SWCTL_SW_DONE_M               GENMASK(0, 0)
#define DDR_UMCTL2_SWCTL_SW_DONE_X(x)            ((x) & GENMASK(0, 0))

/*      DDR_UMCTL2:UMCTL2_REGS:SWSTAT */
#define DDR_UMCTL2_SWSTAT(t)      (t + 0x324)

#define DDR_UMCTL2_SWSTAT_SW_DONE_ACK(x)         ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_SWSTAT_SW_DONE_ACK_M          GENMASK(0, 0)
#define DDR_UMCTL2_SWSTAT_SW_DONE_ACK_X(x)       ((x) & GENMASK(0, 0))

/*      DDR_UMCTL2:UMCTL2_REGS:POISONCFG */
#define DDR_UMCTL2_POISONCFG(t)   (t + 0x36c)

#define DDR_UMCTL2_POISONCFG_WR_POISON_SLVERR_EN(x) ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_POISONCFG_WR_POISON_SLVERR_EN_M GENMASK(0, 0)
#define DDR_UMCTL2_POISONCFG_WR_POISON_SLVERR_EN_X(x) ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_POISONCFG_WR_POISON_INTR_EN(x) (((x) << 4) & GENMASK(4, 4))
#define DDR_UMCTL2_POISONCFG_WR_POISON_INTR_EN_M GENMASK(4, 4)
#define DDR_UMCTL2_POISONCFG_WR_POISON_INTR_EN_X(x) (((x) & GENMASK(4, 4)) >> 4)

#define DDR_UMCTL2_POISONCFG_WR_POISON_INTR_CLR(x) (((x) << 8) & GENMASK(8, 8))
#define DDR_UMCTL2_POISONCFG_WR_POISON_INTR_CLR_M GENMASK(8, 8)
#define DDR_UMCTL2_POISONCFG_WR_POISON_INTR_CLR_X(x)\
	(((x) & GENMASK(8, 8)) >> 8)

#define DDR_UMCTL2_POISONCFG_RD_POISON_SLVERR_EN(x)\
	(((x) << 16) & GENMASK(16, 16))
#define DDR_UMCTL2_POISONCFG_RD_POISON_SLVERR_EN_M GENMASK(16, 16)
#define DDR_UMCTL2_POISONCFG_RD_POISON_SLVERR_EN_X(x)\
	(((x) & GENMASK(16, 16)) >> 16)

#define DDR_UMCTL2_POISONCFG_RD_POISON_INTR_EN(x)\
	(((x) << 20) & GENMASK(20, 20))
#define DDR_UMCTL2_POISONCFG_RD_POISON_INTR_EN_M GENMASK(20, 20)
#define DDR_UMCTL2_POISONCFG_RD_POISON_INTR_EN_X(x)\
	(((x) & GENMASK(20, 20)) >> 20)

#define DDR_UMCTL2_POISONCFG_RD_POISON_INTR_CLR(x)\
	(((x) << 24) & GENMASK(24, 24))
#define DDR_UMCTL2_POISONCFG_RD_POISON_INTR_CLR_M GENMASK(24, 24)
#define DDR_UMCTL2_POISONCFG_RD_POISON_INTR_CLR_X(x)\
	(((x) & GENMASK(24, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:POISONSTAT */
#define DDR_UMCTL2_POISONSTAT(t)  (t + 0x370)

#define DDR_UMCTL2_POISONSTAT_WR_POISON_INTR_0(x) ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_POISONSTAT_WR_POISON_INTR_0_M GENMASK(0, 0)
#define DDR_UMCTL2_POISONSTAT_WR_POISON_INTR_0_X(x) ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_POISONSTAT_WR_POISON_INTR_1(x) (((x) << 1) & GENMASK(1, 1))
#define DDR_UMCTL2_POISONSTAT_WR_POISON_INTR_1_M GENMASK(1, 1)
#define DDR_UMCTL2_POISONSTAT_WR_POISON_INTR_1_X(x) (((x) & GENMASK(1, 1)) >> 1)

#define DDR_UMCTL2_POISONSTAT_WR_POISON_INTR_2(x) (((x) << 2) & GENMASK(2, 2))
#define DDR_UMCTL2_POISONSTAT_WR_POISON_INTR_2_M GENMASK(2, 2)
#define DDR_UMCTL2_POISONSTAT_WR_POISON_INTR_2_X(x) (((x) & GENMASK(2, 2)) >> 2)

#define DDR_UMCTL2_POISONSTAT_RD_POISON_INTR_0(x)\
	(((x) << 16) & GENMASK(16, 16))
#define DDR_UMCTL2_POISONSTAT_RD_POISON_INTR_0_M GENMASK(16, 16)
#define DDR_UMCTL2_POISONSTAT_RD_POISON_INTR_0_X(x)\
	(((x) & GENMASK(16, 16)) >> 16)

#define DDR_UMCTL2_POISONSTAT_RD_POISON_INTR_1(x)\
	(((x) << 17) & GENMASK(17, 17))
#define DDR_UMCTL2_POISONSTAT_RD_POISON_INTR_1_M GENMASK(17, 17)
#define DDR_UMCTL2_POISONSTAT_RD_POISON_INTR_1_X(x)\
	(((x) & GENMASK(17, 17)) >> 17)

#define DDR_UMCTL2_POISONSTAT_RD_POISON_INTR_2(x)\
	(((x) << 18) & GENMASK(18, 18))
#define DDR_UMCTL2_POISONSTAT_RD_POISON_INTR_2_M GENMASK(18, 18)
#define DDR_UMCTL2_POISONSTAT_RD_POISON_INTR_2_X(x)\
	(((x) & GENMASK(18, 18)) >> 18)

/*      DDR_UMCTL2:UMCTL2_MP:PSTAT */
#define DDR_UMCTL2_PSTAT(t)       (t + 0x3fc)

#define DDR_UMCTL2_PSTAT_RD_PORT_BUSY_0(x)       ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_PSTAT_RD_PORT_BUSY_0_M        GENMASK(0, 0)
#define DDR_UMCTL2_PSTAT_RD_PORT_BUSY_0_X(x)     ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_PSTAT_RD_PORT_BUSY_1(x)       (((x) << 1) & GENMASK(1, 1))
#define DDR_UMCTL2_PSTAT_RD_PORT_BUSY_1_M        GENMASK(1, 1)
#define DDR_UMCTL2_PSTAT_RD_PORT_BUSY_1_X(x)     (((x) & GENMASK(1, 1)) >> 1)

#define DDR_UMCTL2_PSTAT_RD_PORT_BUSY_2(x)       (((x) << 2) & GENMASK(2, 2))
#define DDR_UMCTL2_PSTAT_RD_PORT_BUSY_2_M        GENMASK(2, 2)
#define DDR_UMCTL2_PSTAT_RD_PORT_BUSY_2_X(x)     (((x) & GENMASK(2, 2)) >> 2)

#define DDR_UMCTL2_PSTAT_WR_PORT_BUSY_0(x)       (((x) << 16) & GENMASK(16, 16))
#define DDR_UMCTL2_PSTAT_WR_PORT_BUSY_0_M        GENMASK(16, 16)
#define DDR_UMCTL2_PSTAT_WR_PORT_BUSY_0_X(x)     (((x) & GENMASK(16, 16)) >> 16)

#define DDR_UMCTL2_PSTAT_WR_PORT_BUSY_1(x)       (((x) << 17) & GENMASK(17, 17))
#define DDR_UMCTL2_PSTAT_WR_PORT_BUSY_1_M        GENMASK(17, 17)
#define DDR_UMCTL2_PSTAT_WR_PORT_BUSY_1_X(x)     (((x) & GENMASK(17, 17)) >> 17)

#define DDR_UMCTL2_PSTAT_WR_PORT_BUSY_2(x)       (((x) << 18) & GENMASK(18, 18))
#define DDR_UMCTL2_PSTAT_WR_PORT_BUSY_2_M        GENMASK(18, 18)
#define DDR_UMCTL2_PSTAT_WR_PORT_BUSY_2_X(x)     (((x) & GENMASK(18, 18)) >> 18)

/*      DDR_UMCTL2:UMCTL2_MP:PCCFG */
#define DDR_UMCTL2_PCCFG(t)       (t + 0x400)

#define DDR_UMCTL2_PCCFG_GO2CRITICAL_EN(x)       ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_PCCFG_GO2CRITICAL_EN_M        GENMASK(0, 0)
#define DDR_UMCTL2_PCCFG_GO2CRITICAL_EN_X(x)     ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_PCCFG_PAGEMATCH_LIMIT(x)      (((x) << 4) & GENMASK(4, 4))
#define DDR_UMCTL2_PCCFG_PAGEMATCH_LIMIT_M       GENMASK(4, 4)
#define DDR_UMCTL2_PCCFG_PAGEMATCH_LIMIT_X(x)    (((x) & GENMASK(4, 4)) >> 4)

#define DDR_UMCTL2_PCCFG_BL_EXP_MODE(x)          (((x) << 8) & GENMASK(8, 8))
#define DDR_UMCTL2_PCCFG_BL_EXP_MODE_M           GENMASK(8, 8)
#define DDR_UMCTL2_PCCFG_BL_EXP_MODE_X(x)        (((x) & GENMASK(8, 8)) >> 8)

/*      DDR_UMCTL2:UMCTL2_MP:PCFGR_0 */
#define DDR_UMCTL2_PCFGR_0(t)     (t + 0x404)

#define DDR_UMCTL2_PCFGR_0_PCFGR_0_RD_PORT_PRIORITY(x) ((x) & GENMASK(9, 0))
#define DDR_UMCTL2_PCFGR_0_PCFGR_0_RD_PORT_PRIORITY_M GENMASK(9, 0)
#define DDR_UMCTL2_PCFGR_0_PCFGR_0_RD_PORT_PRIORITY_X(x) ((x) & GENMASK(9, 0))

#define DDR_UMCTL2_PCFGR_0_PCFGR_0_RD_PORT_AGING_EN(x)\
	(((x) << 12) & GENMASK(12, 12))
#define DDR_UMCTL2_PCFGR_0_PCFGR_0_RD_PORT_AGING_EN_M GENMASK(12, 12)
#define DDR_UMCTL2_PCFGR_0_PCFGR_0_RD_PORT_AGING_EN_X(x)\
	(((x) & GENMASK(12, 12)) >> 12)

#define DDR_UMCTL2_PCFGR_0_PCFGR_0_RD_PORT_URGENT_EN(x)\
	(((x) << 13) & GENMASK(13, 13))
#define DDR_UMCTL2_PCFGR_0_PCFGR_0_RD_PORT_URGENT_EN_M GENMASK(13, 13)
#define DDR_UMCTL2_PCFGR_0_PCFGR_0_RD_PORT_URGENT_EN_X(x)\
	(((x) & GENMASK(13, 13)) >> 13)

#define DDR_UMCTL2_PCFGR_0_PCFGR_0_RD_PORT_PAGEMATCH_EN(x)\
	(((x) << 14) & GENMASK(14, 14))
#define DDR_UMCTL2_PCFGR_0_PCFGR_0_RD_PORT_PAGEMATCH_EN_M GENMASK(14, 14)
#define DDR_UMCTL2_PCFGR_0_PCFGR_0_RD_PORT_PAGEMATCH_EN_X(x)\
	(((x) & GENMASK(14, 14)) >> 14)

/*      DDR_UMCTL2:UMCTL2_MP:PCFGW_0 */
#define DDR_UMCTL2_PCFGW_0(t)     (t + 0x408)

#define DDR_UMCTL2_PCFGW_0_PCFGW_0_WR_PORT_PRIORITY(x) ((x) & GENMASK(9, 0))
#define DDR_UMCTL2_PCFGW_0_PCFGW_0_WR_PORT_PRIORITY_M GENMASK(9, 0)
#define DDR_UMCTL2_PCFGW_0_PCFGW_0_WR_PORT_PRIORITY_X(x) ((x) & GENMASK(9, 0))

#define DDR_UMCTL2_PCFGW_0_PCFGW_0_WR_PORT_AGING_EN(x)\
	(((x) << 12) & GENMASK(12, 12))
#define DDR_UMCTL2_PCFGW_0_PCFGW_0_WR_PORT_AGING_EN_M GENMASK(12, 12)
#define DDR_UMCTL2_PCFGW_0_PCFGW_0_WR_PORT_AGING_EN_X(x)\
	(((x) & GENMASK(12, 12)) >> 12)

#define DDR_UMCTL2_PCFGW_0_PCFGW_0_WR_PORT_URGENT_EN(x)\
	(((x) << 13) & GENMASK(13, 13))
#define DDR_UMCTL2_PCFGW_0_PCFGW_0_WR_PORT_URGENT_EN_M GENMASK(13, 13)
#define DDR_UMCTL2_PCFGW_0_PCFGW_0_WR_PORT_URGENT_EN_X(x)\
	(((x) & GENMASK(13, 13)) >> 13)

#define DDR_UMCTL2_PCFGW_0_PCFGW_0_WR_PORT_PAGEMATCH_EN(x)\
	(((x) << 14) & GENMASK(14, 14))
#define DDR_UMCTL2_PCFGW_0_PCFGW_0_WR_PORT_PAGEMATCH_EN_M GENMASK(14, 14)
#define DDR_UMCTL2_PCFGW_0_PCFGW_0_WR_PORT_PAGEMATCH_EN_X(x)\
	(((x) & GENMASK(14, 14)) >> 14)

/*      DDR_UMCTL2:UMCTL2_MP:PCTRL_0 */
#define DDR_UMCTL2_PCTRL_0(t)     (t + 0x490)

#define DDR_UMCTL2_PCTRL_0_PCTRL_0_PORT_EN(x)    ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_PCTRL_0_PCTRL_0_PORT_EN_M     GENMASK(0, 0)
#define DDR_UMCTL2_PCTRL_0_PCTRL_0_PORT_EN_X(x)  ((x) & GENMASK(0, 0))

/*      DDR_UMCTL2:UMCTL2_MP:PCFGQOS0_0 */
#define DDR_UMCTL2_PCFGQOS0_0(t)  (t + 0x494)

#define DDR_UMCTL2_PCFGQOS0_0_PCFGQOS0_0_RQOS_MAP_LEVEL1(x)\
	((x) & GENMASK(3, 0))
#define DDR_UMCTL2_PCFGQOS0_0_PCFGQOS0_0_RQOS_MAP_LEVEL1_M GENMASK(3, 0)
#define DDR_UMCTL2_PCFGQOS0_0_PCFGQOS0_0_RQOS_MAP_LEVEL1_X(x)\
	((x) & GENMASK(3, 0))

#define DDR_UMCTL2_PCFGQOS0_0_PCFGQOS0_0_RQOS_MAP_REGION0(x)\
	(((x) << 16) & GENMASK(17, 16))
#define DDR_UMCTL2_PCFGQOS0_0_PCFGQOS0_0_RQOS_MAP_REGION0_M GENMASK(17, 16)
#define DDR_UMCTL2_PCFGQOS0_0_PCFGQOS0_0_RQOS_MAP_REGION0_X(x)\
	(((x) & GENMASK(17, 16)) >> 16)

#define DDR_UMCTL2_PCFGQOS0_0_PCFGQOS0_0_RQOS_MAP_REGION1(x)\
	(((x) << 20) & GENMASK(21, 20))
#define DDR_UMCTL2_PCFGQOS0_0_PCFGQOS0_0_RQOS_MAP_REGION1_M GENMASK(21, 20)
#define DDR_UMCTL2_PCFGQOS0_0_PCFGQOS0_0_RQOS_MAP_REGION1_X(x)\
	(((x) & GENMASK(21, 20)) >> 20)

/*      DDR_UMCTL2:UMCTL2_MP:PCFGR_1 */
#define DDR_UMCTL2_PCFGR_1(t)     (t + 0x4b4)

#define DDR_UMCTL2_PCFGR_1_PCFGR_1_RD_PORT_PRIORITY(x) ((x) & GENMASK(9, 0))
#define DDR_UMCTL2_PCFGR_1_PCFGR_1_RD_PORT_PRIORITY_M GENMASK(9, 0)
#define DDR_UMCTL2_PCFGR_1_PCFGR_1_RD_PORT_PRIORITY_X(x) ((x) & GENMASK(9, 0))

#define DDR_UMCTL2_PCFGR_1_PCFGR_1_RD_PORT_AGING_EN(x)\
	(((x) << 12) & GENMASK(12, 12))
#define DDR_UMCTL2_PCFGR_1_PCFGR_1_RD_PORT_AGING_EN_M GENMASK(12, 12)
#define DDR_UMCTL2_PCFGR_1_PCFGR_1_RD_PORT_AGING_EN_X(x)\
	(((x) & GENMASK(12, 12)) >> 12)

#define DDR_UMCTL2_PCFGR_1_PCFGR_1_RD_PORT_URGENT_EN(x)\
	(((x) << 13) & GENMASK(13, 13))
#define DDR_UMCTL2_PCFGR_1_PCFGR_1_RD_PORT_URGENT_EN_M GENMASK(13, 13)
#define DDR_UMCTL2_PCFGR_1_PCFGR_1_RD_PORT_URGENT_EN_X(x)\
	(((x) & GENMASK(13, 13)) >> 13)

#define DDR_UMCTL2_PCFGR_1_PCFGR_1_RD_PORT_PAGEMATCH_EN(x)\
	(((x) << 14) & GENMASK(14, 14))
#define DDR_UMCTL2_PCFGR_1_PCFGR_1_RD_PORT_PAGEMATCH_EN_M GENMASK(14, 14)
#define DDR_UMCTL2_PCFGR_1_PCFGR_1_RD_PORT_PAGEMATCH_EN_X(x)\
	(((x) & GENMASK(14, 14)) >> 14)

/*      DDR_UMCTL2:UMCTL2_MP:PCFGW_1 */
#define DDR_UMCTL2_PCFGW_1(t)     (t + 0x4b8)

#define DDR_UMCTL2_PCFGW_1_PCFGW_1_WR_PORT_PRIORITY(x) ((x) & GENMASK(9, 0))
#define DDR_UMCTL2_PCFGW_1_PCFGW_1_WR_PORT_PRIORITY_M GENMASK(9, 0)
#define DDR_UMCTL2_PCFGW_1_PCFGW_1_WR_PORT_PRIORITY_X(x) ((x) & GENMASK(9, 0))

#define DDR_UMCTL2_PCFGW_1_PCFGW_1_WR_PORT_AGING_EN(x)\
	(((x) << 12) & GENMASK(12, 12))
#define DDR_UMCTL2_PCFGW_1_PCFGW_1_WR_PORT_AGING_EN_M GENMASK(12, 12)
#define DDR_UMCTL2_PCFGW_1_PCFGW_1_WR_PORT_AGING_EN_X(x)\
	(((x) & GENMASK(12, 12)) >> 12)

#define DDR_UMCTL2_PCFGW_1_PCFGW_1_WR_PORT_URGENT_EN(x)\
	(((x) << 13) & GENMASK(13, 13))
#define DDR_UMCTL2_PCFGW_1_PCFGW_1_WR_PORT_URGENT_EN_M GENMASK(13, 13)
#define DDR_UMCTL2_PCFGW_1_PCFGW_1_WR_PORT_URGENT_EN_X(x)\
	(((x) & GENMASK(13, 13)) >> 13)

#define DDR_UMCTL2_PCFGW_1_PCFGW_1_WR_PORT_PAGEMATCH_EN(x)\
	(((x) << 14) & GENMASK(14, 14))
#define DDR_UMCTL2_PCFGW_1_PCFGW_1_WR_PORT_PAGEMATCH_EN_M GENMASK(14, 14)
#define DDR_UMCTL2_PCFGW_1_PCFGW_1_WR_PORT_PAGEMATCH_EN_X(x)\
	(((x) & GENMASK(14, 14)) >> 14)

/*      DDR_UMCTL2:UMCTL2_MP:PCTRL_1 */
#define DDR_UMCTL2_PCTRL_1(t)     (t + 0x540)

#define DDR_UMCTL2_PCTRL_1_PCTRL_1_PORT_EN(x)    ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_PCTRL_1_PCTRL_1_PORT_EN_M     GENMASK(0, 0)
#define DDR_UMCTL2_PCTRL_1_PCTRL_1_PORT_EN_X(x)  ((x) & GENMASK(0, 0))

/*      DDR_UMCTL2:UMCTL2_MP:PCFGQOS0_1 */
#define DDR_UMCTL2_PCFGQOS0_1(t)  (t + 0x544)

#define DDR_UMCTL2_PCFGQOS0_1_PCFGQOS0_1_RQOS_MAP_LEVEL1(x)\
	((x) & GENMASK(3, 0))
#define DDR_UMCTL2_PCFGQOS0_1_PCFGQOS0_1_RQOS_MAP_LEVEL1_M GENMASK(3, 0)
#define DDR_UMCTL2_PCFGQOS0_1_PCFGQOS0_1_RQOS_MAP_LEVEL1_X(x)\
	((x) & GENMASK(3, 0))

#define DDR_UMCTL2_PCFGQOS0_1_PCFGQOS0_1_RQOS_MAP_REGION0(x)\
	(((x) << 16) & GENMASK(17, 16))
#define DDR_UMCTL2_PCFGQOS0_1_PCFGQOS0_1_RQOS_MAP_REGION0_M GENMASK(17, 16)
#define DDR_UMCTL2_PCFGQOS0_1_PCFGQOS0_1_RQOS_MAP_REGION0_X(x)\
	(((x) & GENMASK(17, 16)) >> 16)

#define DDR_UMCTL2_PCFGQOS0_1_PCFGQOS0_1_RQOS_MAP_REGION1(x)\
	(((x) << 20) & GENMASK(21, 20))
#define DDR_UMCTL2_PCFGQOS0_1_PCFGQOS0_1_RQOS_MAP_REGION1_M GENMASK(21, 20)
#define DDR_UMCTL2_PCFGQOS0_1_PCFGQOS0_1_RQOS_MAP_REGION1_X(x)\
	(((x) & GENMASK(21, 20)) >> 20)

/*      DDR_UMCTL2:UMCTL2_MP:PCFGR_2 */
#define DDR_UMCTL2_PCFGR_2(t)     (t + 0x564)

#define DDR_UMCTL2_PCFGR_2_PCFGR_2_RD_PORT_PRIORITY(x) ((x) & GENMASK(9, 0))
#define DDR_UMCTL2_PCFGR_2_PCFGR_2_RD_PORT_PRIORITY_M GENMASK(9, 0)
#define DDR_UMCTL2_PCFGR_2_PCFGR_2_RD_PORT_PRIORITY_X(x) ((x) & GENMASK(9, 0))

#define DDR_UMCTL2_PCFGR_2_PCFGR_2_RD_PORT_AGING_EN(x)\
	(((x) << 12) & GENMASK(12, 12))
#define DDR_UMCTL2_PCFGR_2_PCFGR_2_RD_PORT_AGING_EN_M GENMASK(12, 12)
#define DDR_UMCTL2_PCFGR_2_PCFGR_2_RD_PORT_AGING_EN_X(x)\
	(((x) & GENMASK(12, 12)) >> 12)

#define DDR_UMCTL2_PCFGR_2_PCFGR_2_RD_PORT_URGENT_EN(x)\
	(((x) << 13) & GENMASK(13, 13))
#define DDR_UMCTL2_PCFGR_2_PCFGR_2_RD_PORT_URGENT_EN_M GENMASK(13, 13)
#define DDR_UMCTL2_PCFGR_2_PCFGR_2_RD_PORT_URGENT_EN_X(x)\
	(((x) & GENMASK(13, 13)) >> 13)

#define DDR_UMCTL2_PCFGR_2_PCFGR_2_RD_PORT_PAGEMATCH_EN(x)\
	(((x) << 14) & GENMASK(14, 14))
#define DDR_UMCTL2_PCFGR_2_PCFGR_2_RD_PORT_PAGEMATCH_EN_M GENMASK(14, 14)
#define DDR_UMCTL2_PCFGR_2_PCFGR_2_RD_PORT_PAGEMATCH_EN_X(x)\
	(((x) & GENMASK(14, 14)) >> 14)

/*      DDR_UMCTL2:UMCTL2_MP:PCFGW_2 */
#define DDR_UMCTL2_PCFGW_2(t)     (t + 0x568)

#define DDR_UMCTL2_PCFGW_2_PCFGW_2_WR_PORT_PRIORITY(x) ((x) & GENMASK(9, 0))
#define DDR_UMCTL2_PCFGW_2_PCFGW_2_WR_PORT_PRIORITY_M GENMASK(9, 0)
#define DDR_UMCTL2_PCFGW_2_PCFGW_2_WR_PORT_PRIORITY_X(x) ((x) & GENMASK(9, 0))

#define DDR_UMCTL2_PCFGW_2_PCFGW_2_WR_PORT_AGING_EN(x)\
	(((x) << 12) & GENMASK(12, 12))
#define DDR_UMCTL2_PCFGW_2_PCFGW_2_WR_PORT_AGING_EN_M GENMASK(12, 12)
#define DDR_UMCTL2_PCFGW_2_PCFGW_2_WR_PORT_AGING_EN_X(x)\
	(((x) & GENMASK(12, 12)) >> 12)

#define DDR_UMCTL2_PCFGW_2_PCFGW_2_WR_PORT_URGENT_EN(x)\
	(((x) << 13) & GENMASK(13, 13))
#define DDR_UMCTL2_PCFGW_2_PCFGW_2_WR_PORT_URGENT_EN_M GENMASK(13, 13)
#define DDR_UMCTL2_PCFGW_2_PCFGW_2_WR_PORT_URGENT_EN_X(x)\
	(((x) & GENMASK(13, 13)) >> 13)

#define DDR_UMCTL2_PCFGW_2_PCFGW_2_WR_PORT_PAGEMATCH_EN(x)\
	(((x) << 14) & GENMASK(14, 14))
#define DDR_UMCTL2_PCFGW_2_PCFGW_2_WR_PORT_PAGEMATCH_EN_M GENMASK(14, 14)
#define DDR_UMCTL2_PCFGW_2_PCFGW_2_WR_PORT_PAGEMATCH_EN_X(x)\
	(((x) & GENMASK(14, 14)) >> 14)

/*      DDR_UMCTL2:UMCTL2_MP:PCTRL_2 */
#define DDR_UMCTL2_PCTRL_2(t)     (t + 0x5f0)

#define DDR_UMCTL2_PCTRL_2_PCTRL_2_PORT_EN(x)    ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_PCTRL_2_PCTRL_2_PORT_EN_M     GENMASK(0, 0)
#define DDR_UMCTL2_PCTRL_2_PCTRL_2_PORT_EN_X(x)  ((x) & GENMASK(0, 0))

/*      DDR_UMCTL2:UMCTL2_MP:PCFGQOS0_2 */
#define DDR_UMCTL2_PCFGQOS0_2(t)  (t + 0x5f4)

#define DDR_UMCTL2_PCFGQOS0_2_PCFGQOS0_2_RQOS_MAP_LEVEL1(x)\
	((x) & GENMASK(3, 0))
#define DDR_UMCTL2_PCFGQOS0_2_PCFGQOS0_2_RQOS_MAP_LEVEL1_M GENMASK(3, 0)
#define DDR_UMCTL2_PCFGQOS0_2_PCFGQOS0_2_RQOS_MAP_LEVEL1_X(x)\
	((x) & GENMASK(3, 0))

#define DDR_UMCTL2_PCFGQOS0_2_PCFGQOS0_2_RQOS_MAP_REGION0(x)\
	(((x) << 16) & GENMASK(17, 16))
#define DDR_UMCTL2_PCFGQOS0_2_PCFGQOS0_2_RQOS_MAP_REGION0_M GENMASK(17, 16)
#define DDR_UMCTL2_PCFGQOS0_2_PCFGQOS0_2_RQOS_MAP_REGION0_X(x)\
	(((x) & GENMASK(17, 16)) >> 16)

#define DDR_UMCTL2_PCFGQOS0_2_PCFGQOS0_2_RQOS_MAP_REGION1(x)\
	(((x) << 20) & GENMASK(21, 20))
#define DDR_UMCTL2_PCFGQOS0_2_PCFGQOS0_2_RQOS_MAP_REGION1_M GENMASK(21, 20)
#define DDR_UMCTL2_PCFGQOS0_2_PCFGQOS0_2_RQOS_MAP_REGION1_X(x)\
	(((x) & GENMASK(21, 20)) >> 20)

/*      DDR_UMCTL2:UMCTL2_MP:SARBASE0 */
#define DDR_UMCTL2_SARBASE0(t)    (t + 0xf04)

#define DDR_UMCTL2_SARBASE0_BASE_ADDR(x)         ((x) & GENMASK(2, 0))
#define DDR_UMCTL2_SARBASE0_BASE_ADDR_M          GENMASK(2, 0)
#define DDR_UMCTL2_SARBASE0_BASE_ADDR_X(x)       ((x) & GENMASK(2, 0))

/*      DDR_UMCTL2:UMCTL2_MP:SARSIZE0 */
#define DDR_UMCTL2_SARSIZE0(t)    (t + 0xf08)

#define DDR_UMCTL2_SARSIZE0_NBLOCKS(x)           ((x) & GENMASK(7, 0))
#define DDR_UMCTL2_SARSIZE0_NBLOCKS_M            GENMASK(7, 0)
#define DDR_UMCTL2_SARSIZE0_NBLOCKS_X(x)         ((x) & GENMASK(7, 0))


#endif /* _LAN969X_DDR_SR_H_ */
