/*
 * Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

/* LAN66X compatibility file */

#ifndef _LAN966X_REGS_H_
#define _LAN966X_REGS_H_

#include <lan969x_regs.h>
#include <lan969x_targets.h>

#define LAN966X_AES_BASE	LAN969X_AES_BASE
#define LAN966X_CPU_BASE	LAN969X_CPU_BASE
#define LAN966X_HMATRIX2_BASE	LAN969X_HMATRIX2_BASE
#define LAN966X_OTP_BASE	LAN969X_OTP_BASE
#define LAN966X_QSPI_0_BASE	LAN969X_QSPI_0_BASE
#define LAN966X_SHA_BASE	LAN969X_SHA_BASE
#define LAN966X_SJTAG_BASE	LAN969X_SJTAG_BASE
#define LAN966X_TRNG_BASE	LAN969X_TRNG_BASE
#define LAN966X_GCB_BASE	LAN969X_GCB_BASE
#define LAN966X_QSPI0_MMAP	LAN969X_QSPI0_MMAP
#define LAN966X_DDR_BASE	LAN969X_DDR_BASE
#define LAN966X_DDR_ATF_SIZE	LAN969X_DDR_ATF_SIZE
#define LAN966X_DDR_MAX_SIZE	LAN969X_DDR_MAX_SIZE
#define LAN966X_SDMMC_BASE	LAN969X_SDMMC_0_BASE
#define LAN966X_SRAM_BASE	LAN969X_SRAM_BASE
#define LAN966X_SRAM_SIZE	LAN969X_SRAM_SIZE
#define LAN966X_PCIE_DBI_BASE	LAN969X_PCIE_DBI_BASE
#define LAN966X_PCIE_CFG_BASE	LAN969X_PCIE_CFG_BASE

#endif /* _LAN966X_REGS_H_ */
