/*
 * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

/* This file is autogenerated by cml-utils 2022-09-26 15:09:28 +0200.
 * Commit ID: 43604b17e9ce7c6bf23ab9cae71afa74b5d8091d
 */

/* LAN969X registers */

#ifndef _LAN969X_DDR_A0_H_
#define _LAN969X_DDR_A0_H_

/*      CPU:CPU_REGS:RESET */
#define CPU_RESET(t)              (t + 0x84)

#define CPU_RESET_VCORE_RST(x)                   (((x) << 7) & GENMASK(7, 7))
#define CPU_RESET_VCORE_RST_M                    GENMASK(7, 7)
#define CPU_RESET_VCORE_RST_X(x)                 (((x) & GENMASK(7, 7)) >> 7)

#define CPU_RESET_CPU_CORE_0_WARM_RST(x)         (((x) << 6) & GENMASK(6, 6))
#define CPU_RESET_CPU_CORE_0_WARM_RST_M          GENMASK(6, 6)
#define CPU_RESET_CPU_CORE_0_WARM_RST_X(x)       (((x) & GENMASK(6, 6)) >> 6)

#define CPU_RESET_PROC_DBG_RST(x)                (((x) << 5) & GENMASK(5, 5))
#define CPU_RESET_PROC_DBG_RST_M                 GENMASK(5, 5)
#define CPU_RESET_PROC_DBG_RST_X(x)              (((x) & GENMASK(5, 5)) >> 5)

#define CPU_RESET_JTAG_RST(x)                    (((x) << 4) & GENMASK(4, 4))
#define CPU_RESET_JTAG_RST_M                     GENMASK(4, 4)
#define CPU_RESET_JTAG_RST_X(x)                  (((x) & GENMASK(4, 4)) >> 4)

#define CPU_RESET_CPU_L2_RST(x)                  (((x) << 3) & GENMASK(3, 3))
#define CPU_RESET_CPU_L2_RST_M                   GENMASK(3, 3)
#define CPU_RESET_CPU_L2_RST_X(x)                (((x) & GENMASK(3, 3)) >> 3)

#define CPU_RESET_MEM_RST(x)                     (((x) << 2) & GENMASK(2, 2))
#define CPU_RESET_MEM_RST_M                      GENMASK(2, 2)
#define CPU_RESET_MEM_RST_X(x)                   (((x) & GENMASK(2, 2)) >> 2)

#define CPU_RESET_WDT_FORCE_RST(x)               (((x) << 1) & GENMASK(1, 1))
#define CPU_RESET_WDT_FORCE_RST_M                GENMASK(1, 1)
#define CPU_RESET_WDT_FORCE_RST_X(x)             (((x) & GENMASK(1, 1)) >> 1)

#define CPU_RESET_CPU_CORE_0_COLD_RST(x)         ((x) & GENMASK(0, 0))
#define CPU_RESET_CPU_CORE_0_COLD_RST_M          GENMASK(0, 0)
#define CPU_RESET_CPU_CORE_0_COLD_RST_X(x)       ((x) & GENMASK(0, 0))

/*      CPU:CPU_REGS:RESET_PROT_STAT */
#define CPU_RESET_PROT_STAT(t)    (t + 0x88)

#define CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE(x) (((x) << 5) & GENMASK(5, 5))
#define CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE_M GENMASK(5, 5)
#define CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE_X(x) (((x) & GENMASK(5, 5)) >> 5)

#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_AMBA(x) (((x) << 4) & GENMASK(4, 4))
#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_AMBA_M GENMASK(4, 4)
#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_AMBA_X(x)\
	(((x) & GENMASK(4, 4)) >> 4)

#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_WDT(x) (((x) << 3) & GENMASK(3, 3))
#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_WDT_M GENMASK(3, 3)
#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_WDT_X(x) (((x) & GENMASK(3, 3)) >> 3)

#define CPU_RESET_PROT_STAT_VCORE_WDT_RST_PROT_WDT(x)\
	(((x) << 2) & GENMASK(2, 2))
#define CPU_RESET_PROT_STAT_VCORE_WDT_RST_PROT_WDT_M GENMASK(2, 2)
#define CPU_RESET_PROT_STAT_VCORE_WDT_RST_PROT_WDT_X(x)\
	(((x) & GENMASK(2, 2)) >> 2)

#define CPU_RESET_PROT_STAT_VCORE_WDT_RST_STAT(x) (((x) << 1) & GENMASK(1, 1))
#define CPU_RESET_PROT_STAT_VCORE_WDT_RST_STAT_M GENMASK(1, 1)
#define CPU_RESET_PROT_STAT_VCORE_WDT_RST_STAT_X(x) (((x) & GENMASK(1, 1)) >> 1)

#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_PCIE(x) ((x) & GENMASK(0, 0))
#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_PCIE_M GENMASK(0, 0)
#define CPU_RESET_PROT_STAT_VCORE_RST_PROT_PCIE_X(x) ((x) & GENMASK(0, 0))

/*      CPU:DDRCTRL:DDRCTRL_CLK */
#define CPU_DDRCTRL_CLK(t)        (t + 0x2ec)

#define CPU_DDRCTRL_CLK_DDR_CLK_ENA(x)           ((x) & GENMASK(0, 0))
#define CPU_DDRCTRL_CLK_DDR_CLK_ENA_M            GENMASK(0, 0)
#define CPU_DDRCTRL_CLK_DDR_CLK_ENA_X(x)         ((x) & GENMASK(0, 0))

#define CPU_DDRCTRL_CLK_DDR_AXI0_CLK_ENA(x)      (((x) << 1) & GENMASK(1, 1))
#define CPU_DDRCTRL_CLK_DDR_AXI0_CLK_ENA_M       GENMASK(1, 1)
#define CPU_DDRCTRL_CLK_DDR_AXI0_CLK_ENA_X(x)    (((x) & GENMASK(1, 1)) >> 1)

#define CPU_DDRCTRL_CLK_DDR_AXI1_CLK_ENA(x)      (((x) << 2) & GENMASK(2, 2))
#define CPU_DDRCTRL_CLK_DDR_AXI1_CLK_ENA_M       GENMASK(2, 2)
#define CPU_DDRCTRL_CLK_DDR_AXI1_CLK_ENA_X(x)    (((x) & GENMASK(2, 2)) >> 2)

#define CPU_DDRCTRL_CLK_DDR_AXI2_CLK_ENA(x)      (((x) << 3) & GENMASK(3, 3))
#define CPU_DDRCTRL_CLK_DDR_AXI2_CLK_ENA_M       GENMASK(3, 3)
#define CPU_DDRCTRL_CLK_DDR_AXI2_CLK_ENA_X(x)    (((x) & GENMASK(3, 3)) >> 3)

#define CPU_DDRCTRL_CLK_DDR_APB_CLK_ENA(x)       (((x) << 4) & GENMASK(4, 4))
#define CPU_DDRCTRL_CLK_DDR_APB_CLK_ENA_M        GENMASK(4, 4)
#define CPU_DDRCTRL_CLK_DDR_APB_CLK_ENA_X(x)     (((x) & GENMASK(4, 4)) >> 4)

#define CPU_DDRCTRL_CLK_DDRPHY_CTL_CLK_ENA(x)    (((x) << 5) & GENMASK(5, 5))
#define CPU_DDRCTRL_CLK_DDRPHY_CTL_CLK_ENA_M     GENMASK(5, 5)
#define CPU_DDRCTRL_CLK_DDRPHY_CTL_CLK_ENA_X(x)  (((x) & GENMASK(5, 5)) >> 5)

#define CPU_DDRCTRL_CLK_DDRPHY_APB_CLK_ENA(x)    (((x) << 6) & GENMASK(6, 6))
#define CPU_DDRCTRL_CLK_DDRPHY_APB_CLK_ENA_M     GENMASK(6, 6)
#define CPU_DDRCTRL_CLK_DDRPHY_APB_CLK_ENA_X(x)  (((x) & GENMASK(6, 6)) >> 6)

#define CPU_DDRCTRL_CLK_RAM_RING_ENA(x)          (((x) << 7) & GENMASK(7, 7))
#define CPU_DDRCTRL_CLK_RAM_RING_ENA_M           GENMASK(7, 7)
#define CPU_DDRCTRL_CLK_RAM_RING_ENA_X(x)        (((x) & GENMASK(7, 7)) >> 7)

/*      CPU:DDRCTRL:DDRCTRL_RST */
#define CPU_DDRCTRL_RST(t)        (t + 0x2f0)

#define CPU_DDRCTRL_RST_DDRC_RST(x)              ((x) & GENMASK(0, 0))
#define CPU_DDRCTRL_RST_DDRC_RST_M               GENMASK(0, 0)
#define CPU_DDRCTRL_RST_DDRC_RST_X(x)            ((x) & GENMASK(0, 0))

#define CPU_DDRCTRL_RST_DDR_AXI0_RST(x)          (((x) << 1) & GENMASK(1, 1))
#define CPU_DDRCTRL_RST_DDR_AXI0_RST_M           GENMASK(1, 1)
#define CPU_DDRCTRL_RST_DDR_AXI0_RST_X(x)        (((x) & GENMASK(1, 1)) >> 1)

#define CPU_DDRCTRL_RST_DDR_AXI1_RST(x)          (((x) << 2) & GENMASK(2, 2))
#define CPU_DDRCTRL_RST_DDR_AXI1_RST_M           GENMASK(2, 2)
#define CPU_DDRCTRL_RST_DDR_AXI1_RST_X(x)        (((x) & GENMASK(2, 2)) >> 2)

#define CPU_DDRCTRL_RST_DDR_AXI2_RST(x)          (((x) << 3) & GENMASK(3, 3))
#define CPU_DDRCTRL_RST_DDR_AXI2_RST_M           GENMASK(3, 3)
#define CPU_DDRCTRL_RST_DDR_AXI2_RST_X(x)        (((x) & GENMASK(3, 3)) >> 3)

#define CPU_DDRCTRL_RST_DDR_APB_RST(x)           (((x) << 4) & GENMASK(4, 4))
#define CPU_DDRCTRL_RST_DDR_APB_RST_M            GENMASK(4, 4)
#define CPU_DDRCTRL_RST_DDR_APB_RST_X(x)         (((x) & GENMASK(4, 4)) >> 4)

#define CPU_DDRCTRL_RST_DDRPHY_CTL_RST(x)        (((x) << 5) & GENMASK(5, 5))
#define CPU_DDRCTRL_RST_DDRPHY_CTL_RST_M         GENMASK(5, 5)
#define CPU_DDRCTRL_RST_DDRPHY_CTL_RST_X(x)      (((x) & GENMASK(5, 5)) >> 5)

#define CPU_DDRCTRL_RST_FPGA_DDRPHY_SOFT_RST(x)  (((x) << 6) & GENMASK(6, 6))
#define CPU_DDRCTRL_RST_FPGA_DDRPHY_SOFT_RST_M   GENMASK(6, 6)
#define CPU_DDRCTRL_RST_FPGA_DDRPHY_SOFT_RST_X(x) (((x) & GENMASK(6, 6)) >> 6)

#define CPU_DDRCTRL_RST_DDRPHY_APB_RST(x)        (((x) << 7) & GENMASK(7, 7))
#define CPU_DDRCTRL_RST_DDRPHY_APB_RST_M         GENMASK(7, 7)
#define CPU_DDRCTRL_RST_DDRPHY_APB_RST_X(x)      (((x) & GENMASK(7, 7)) >> 7)

/*      CPU:DDRCTRL:DDRC_INTR_RAW_STAT */
#define CPU_DDRC_INTR_RAW_STAT(t) (t + 0x2f4)

#define CPU_DDRC_INTR_RAW_STAT_SBR_DONE_INTR_RAW_STAT(x) ((x) & GENMASK(0, 0))
#define CPU_DDRC_INTR_RAW_STAT_SBR_DONE_INTR_RAW_STAT_M GENMASK(0, 0)
#define CPU_DDRC_INTR_RAW_STAT_SBR_DONE_INTR_RAW_STAT_X(x) ((x) & GENMASK(0, 0))

#define CPU_DDRC_INTR_RAW_STAT_ECC_CORRECTED_ERR_INTR_RAW_STAT(x)\
	(((x) << 1) & GENMASK(1, 1))
#define CPU_DDRC_INTR_RAW_STAT_ECC_CORRECTED_ERR_INTR_RAW_STAT_M GENMASK(1, 1)
#define CPU_DDRC_INTR_RAW_STAT_ECC_CORRECTED_ERR_INTR_RAW_STAT_X(x)\
	(((x) & GENMASK(1, 1)) >> 1)

#define CPU_DDRC_INTR_RAW_STAT_ECC_UNCORRECTED_ERR_INTR_RAW_STAT(x)\
	(((x) << 2) & GENMASK(2, 2))
#define CPU_DDRC_INTR_RAW_STAT_ECC_UNCORRECTED_ERR_INTR_RAW_STAT_M GENMASK(2, 2)
#define CPU_DDRC_INTR_RAW_STAT_ECC_UNCORRECTED_ERR_INTR_RAW_STAT_X(x)\
	(((x) & GENMASK(2, 2)) >> 2)

#define CPU_DDRC_INTR_RAW_STAT_ECC_AP_ERR_INTR_RAW_STAT(x)\
	(((x) << 3) & GENMASK(3, 3))
#define CPU_DDRC_INTR_RAW_STAT_ECC_AP_ERR_INTR_RAW_STAT_M GENMASK(3, 3)
#define CPU_DDRC_INTR_RAW_STAT_ECC_AP_ERR_INTR_RAW_STAT_X(x)\
	(((x) & GENMASK(3, 3)) >> 3)

#define CPU_DDRC_INTR_RAW_STAT_DFI_ALERT_ERR_INTR_RAW_STAT(x)\
	(((x) << 4) & GENMASK(4, 4))
#define CPU_DDRC_INTR_RAW_STAT_DFI_ALERT_ERR_INTR_RAW_STAT_M GENMASK(4, 4)
#define CPU_DDRC_INTR_RAW_STAT_DFI_ALERT_ERR_INTR_RAW_STAT_X(x)\
	(((x) & GENMASK(4, 4)) >> 4)

/*      CPU:DDRCTRL:DDRC_INTR_MASK */
#define CPU_DDRC_INTR_MASK(t)     (t + 0x2f8)

#define CPU_DDRC_INTR_MASK_SBR_DONE_INTR_MASK(x) ((x) & GENMASK(0, 0))
#define CPU_DDRC_INTR_MASK_SBR_DONE_INTR_MASK_M  GENMASK(0, 0)
#define CPU_DDRC_INTR_MASK_SBR_DONE_INTR_MASK_X(x) ((x) & GENMASK(0, 0))

#define CPU_DDRC_INTR_MASK_ECC_CORRECTED_ERR_INTR_MASK(x)\
	(((x) << 1) & GENMASK(1, 1))
#define CPU_DDRC_INTR_MASK_ECC_CORRECTED_ERR_INTR_MASK_M GENMASK(1, 1)
#define CPU_DDRC_INTR_MASK_ECC_CORRECTED_ERR_INTR_MASK_X(x)\
	(((x) & GENMASK(1, 1)) >> 1)

#define CPU_DDRC_INTR_MASK_ECC_UNCORRECTED_ERR_INTR_MASK(x)\
	(((x) << 2) & GENMASK(2, 2))
#define CPU_DDRC_INTR_MASK_ECC_UNCORRECTED_ERR_INTR_MASK_M GENMASK(2, 2)
#define CPU_DDRC_INTR_MASK_ECC_UNCORRECTED_ERR_INTR_MASK_X(x)\
	(((x) & GENMASK(2, 2)) >> 2)

#define CPU_DDRC_INTR_MASK_ECC_AP_ERR_INTR_MASK(x) (((x) << 3) & GENMASK(3, 3))
#define CPU_DDRC_INTR_MASK_ECC_AP_ERR_INTR_MASK_M GENMASK(3, 3)
#define CPU_DDRC_INTR_MASK_ECC_AP_ERR_INTR_MASK_X(x)\
	(((x) & GENMASK(3, 3)) >> 3)

#define CPU_DDRC_INTR_MASK_DFI_ALERT_ERR_INTR_MASK(x)\
	(((x) << 4) & GENMASK(4, 4))
#define CPU_DDRC_INTR_MASK_DFI_ALERT_ERR_INTR_MASK_M GENMASK(4, 4)
#define CPU_DDRC_INTR_MASK_DFI_ALERT_ERR_INTR_MASK_X(x)\
	(((x) & GENMASK(4, 4)) >> 4)

/*      CPU:DDRCTRL:DDRC_INTR_MASKED_STAT */
#define CPU_DDRC_INTR_MASKED_STAT(t) (t + 0x2fc)

#define CPU_DDRC_INTR_MASKED_STAT_SBR_DONE_INTR_STAT(x) ((x) & GENMASK(0, 0))
#define CPU_DDRC_INTR_MASKED_STAT_SBR_DONE_INTR_STAT_M GENMASK(0, 0)
#define CPU_DDRC_INTR_MASKED_STAT_SBR_DONE_INTR_STAT_X(x) ((x) & GENMASK(0, 0))

#define CPU_DDRC_INTR_MASKED_STAT_ECC_CORRECTED_ERR_INTR_STAT(x)\
	(((x) << 1) & GENMASK(1, 1))
#define CPU_DDRC_INTR_MASKED_STAT_ECC_CORRECTED_ERR_INTR_STAT_M GENMASK(1, 1)
#define CPU_DDRC_INTR_MASKED_STAT_ECC_CORRECTED_ERR_INTR_STAT_X(x)\
	(((x) & GENMASK(1, 1)) >> 1)

#define CPU_DDRC_INTR_MASKED_STAT_ECC_UNCORRECTED_ERR_INTR_STAT(x)\
	(((x) << 2) & GENMASK(2, 2))
#define CPU_DDRC_INTR_MASKED_STAT_ECC_UNCORRECTED_ERR_INTR_STAT_M GENMASK(2, 2)
#define CPU_DDRC_INTR_MASKED_STAT_ECC_UNCORRECTED_ERR_INTR_STAT_X(x)\
	(((x) & GENMASK(2, 2)) >> 2)

#define CPU_DDRC_INTR_MASKED_STAT_ECC_AP_ERR_INTR_STAT(x)\
	(((x) << 3) & GENMASK(3, 3))
#define CPU_DDRC_INTR_MASKED_STAT_ECC_AP_ERR_INTR_STAT_M GENMASK(3, 3)
#define CPU_DDRC_INTR_MASKED_STAT_ECC_AP_ERR_INTR_STAT_X(x)\
	(((x) & GENMASK(3, 3)) >> 3)

#define CPU_DDRC_INTR_MASKED_STAT_DFI_ALERT_ERR_INTR_STAT(x)\
	(((x) << 4) & GENMASK(4, 4))
#define CPU_DDRC_INTR_MASKED_STAT_DFI_ALERT_ERR_INTR_STAT_M GENMASK(4, 4)
#define CPU_DDRC_INTR_MASKED_STAT_DFI_ALERT_ERR_INTR_STAT_X(x)\
	(((x) & GENMASK(4, 4)) >> 4)

/*      CPU:DDRCTRL:DRAM0_MPR_PAGE_STAT */
#define CPU_DRAM0_MPR_PAGE_STAT(t) (t + 0x300)

/*      CPU:DDRCTRL:DRAM1_MPR_PAGE_STAT */
#define CPU_DRAM1_MPR_PAGE_STAT(t) (t + 0x304)

/*      DDR_PHY:DWC_DDRPHY_PUB:RIDR */
#define DDR_PHY_RIDR(t)           (t + 0x00)

#define DDR_PHY_RIDR_PUBID(x)                    ((x) & GENMASK(11, 0))
#define DDR_PHY_RIDR_PUBID_M                     GENMASK(11, 0)
#define DDR_PHY_RIDR_PUBID_X(x)                  ((x) & GENMASK(11, 0))

#define DDR_PHY_RIDR_PHYID(x)                    (((x) << 12) & GENMASK(23, 12))
#define DDR_PHY_RIDR_PHYID_M                     GENMASK(23, 12)
#define DDR_PHY_RIDR_PHYID_X(x)                  (((x) & GENMASK(23, 12)) >> 12)

#define DDR_PHY_RIDR_UDRID(x)                    (((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_RIDR_UDRID_M                     GENMASK(31, 24)
#define DDR_PHY_RIDR_UDRID_X(x)                  (((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:PIR */
#define DDR_PHY_PIR(t)            (t + 0x04)

#define DDR_PHY_PIR_INIT(x)                      ((x) & GENMASK(0, 0))
#define DDR_PHY_PIR_INIT_M                       GENMASK(0, 0)
#define DDR_PHY_PIR_INIT_X(x)                    ((x) & GENMASK(0, 0))

#define DDR_PHY_PIR_ZCAL(x)                      (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_PIR_ZCAL_M                       GENMASK(1, 1)
#define DDR_PHY_PIR_ZCAL_X(x)                    (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_PIR_CA(x)                        (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_PIR_CA_M                         GENMASK(2, 2)
#define DDR_PHY_PIR_CA_X(x)                      (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_PIR_PIR_RESERVED_3(x)            (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_PIR_PIR_RESERVED_3_M             GENMASK(3, 3)
#define DDR_PHY_PIR_PIR_RESERVED_3_X(x)          (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_PIR_PLLINIT(x)                   (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_PIR_PLLINIT_M                    GENMASK(4, 4)
#define DDR_PHY_PIR_PLLINIT_X(x)                 (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_PIR_DCAL(x)                      (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_PIR_DCAL_M                       GENMASK(5, 5)
#define DDR_PHY_PIR_DCAL_X(x)                    (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_PIR_PHYRST(x)                    (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_PIR_PHYRST_M                     GENMASK(6, 6)
#define DDR_PHY_PIR_PHYRST_X(x)                  (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_PIR_DRAMRST(x)                   (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_PIR_DRAMRST_M                    GENMASK(7, 7)
#define DDR_PHY_PIR_DRAMRST_X(x)                 (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_PIR_DRAMINIT(x)                  (((x) << 8) & GENMASK(8, 8))
#define DDR_PHY_PIR_DRAMINIT_M                   GENMASK(8, 8)
#define DDR_PHY_PIR_DRAMINIT_X(x)                (((x) & GENMASK(8, 8)) >> 8)

#define DDR_PHY_PIR_WL(x)                        (((x) << 9) & GENMASK(9, 9))
#define DDR_PHY_PIR_WL_M                         GENMASK(9, 9)
#define DDR_PHY_PIR_WL_X(x)                      (((x) & GENMASK(9, 9)) >> 9)

#define DDR_PHY_PIR_QSGATE(x)                    (((x) << 10) & GENMASK(10, 10))
#define DDR_PHY_PIR_QSGATE_M                     GENMASK(10, 10)
#define DDR_PHY_PIR_QSGATE_X(x)                  (((x) & GENMASK(10, 10)) >> 10)

#define DDR_PHY_PIR_WLADJ(x)                     (((x) << 11) & GENMASK(11, 11))
#define DDR_PHY_PIR_WLADJ_M                      GENMASK(11, 11)
#define DDR_PHY_PIR_WLADJ_X(x)                   (((x) & GENMASK(11, 11)) >> 11)

#define DDR_PHY_PIR_RDDSKW(x)                    (((x) << 12) & GENMASK(12, 12))
#define DDR_PHY_PIR_RDDSKW_M                     GENMASK(12, 12)
#define DDR_PHY_PIR_RDDSKW_X(x)                  (((x) & GENMASK(12, 12)) >> 12)

#define DDR_PHY_PIR_WRDSKW(x)                    (((x) << 13) & GENMASK(13, 13))
#define DDR_PHY_PIR_WRDSKW_M                     GENMASK(13, 13)
#define DDR_PHY_PIR_WRDSKW_X(x)                  (((x) & GENMASK(13, 13)) >> 13)

#define DDR_PHY_PIR_RDEYE(x)                     (((x) << 14) & GENMASK(14, 14))
#define DDR_PHY_PIR_RDEYE_M                      GENMASK(14, 14)
#define DDR_PHY_PIR_RDEYE_X(x)                   (((x) & GENMASK(14, 14)) >> 14)

#define DDR_PHY_PIR_WREYE(x)                     (((x) << 15) & GENMASK(15, 15))
#define DDR_PHY_PIR_WREYE_M                      GENMASK(15, 15)
#define DDR_PHY_PIR_WREYE_X(x)                   (((x) & GENMASK(15, 15)) >> 15)

#define DDR_PHY_PIR_SRD(x)                       (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_PIR_SRD_M                        GENMASK(16, 16)
#define DDR_PHY_PIR_SRD_X(x)                     (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_PIR_VREF(x)                      (((x) << 17) & GENMASK(17, 17))
#define DDR_PHY_PIR_VREF_M                       GENMASK(17, 17)
#define DDR_PHY_PIR_VREF_X(x)                    (((x) & GENMASK(17, 17)) >> 17)

#define DDR_PHY_PIR_CTLDINIT(x)                  (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_PIR_CTLDINIT_M                   GENMASK(18, 18)
#define DDR_PHY_PIR_CTLDINIT_X(x)                (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_PIR_RDIMMINIT(x)                 (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_PIR_RDIMMINIT_M                  GENMASK(19, 19)
#define DDR_PHY_PIR_RDIMMINIT_X(x)               (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_PIR_RESERVED_28_20(x)            (((x) << 20) & GENMASK(28, 20))
#define DDR_PHY_PIR_RESERVED_28_20_M             GENMASK(28, 20)
#define DDR_PHY_PIR_RESERVED_28_20_X(x)          (((x) & GENMASK(28, 20)) >> 20)

#define DDR_PHY_PIR_DCALPSE(x)                   (((x) << 29) & GENMASK(29, 29))
#define DDR_PHY_PIR_DCALPSE_M                    GENMASK(29, 29)
#define DDR_PHY_PIR_DCALPSE_X(x)                 (((x) & GENMASK(29, 29)) >> 29)

#define DDR_PHY_PIR_ZCALBYP(x)                   (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_PIR_ZCALBYP_M                    GENMASK(30, 30)
#define DDR_PHY_PIR_ZCALBYP_X(x)                 (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_PIR_PIR_RESERVED_31(x)           (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_PIR_PIR_RESERVED_31_M            GENMASK(31, 31)
#define DDR_PHY_PIR_PIR_RESERVED_31_X(x)         (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:CGCR */
#define DDR_PHY_CGCR(t)           (t + 0x08)

#define DDR_PHY_CGCR_GICGEN(x)                   ((x) & GENMASK(0, 0))
#define DDR_PHY_CGCR_GICGEN_M                    GENMASK(0, 0)
#define DDR_PHY_CGCR_GICGEN_X(x)                 ((x) & GENMASK(0, 0))

#define DDR_PHY_CGCR_CFGICGEN(x)                 (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_CGCR_CFGICGEN_M                  GENMASK(1, 1)
#define DDR_PHY_CGCR_CFGICGEN_X(x)               (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_CGCR_INITICGEN(x)                (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_CGCR_INITICGEN_M                 GENMASK(2, 2)
#define DDR_PHY_CGCR_INITICGEN_X(x)              (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_CGCR_TRAINICGEN(x)               (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_CGCR_TRAINICGEN_M                GENMASK(3, 3)
#define DDR_PHY_CGCR_TRAINICGEN_X(x)             (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_CGCR_BISTICGEN(x)                (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_CGCR_BISTICGEN_M                 GENMASK(4, 4)
#define DDR_PHY_CGCR_BISTICGEN_X(x)              (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_CGCR_DCUICGEN(x)                 (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_CGCR_DCUICGEN_M                  GENMASK(5, 5)
#define DDR_PHY_CGCR_DCUICGEN_X(x)               (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_CGCR_SCHICGEN(x)                 (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_CGCR_SCHICGEN_M                  GENMASK(6, 6)
#define DDR_PHY_CGCR_SCHICGEN_X(x)               (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_CGCR_DFIICGEN(x)                 (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_CGCR_DFIICGEN_M                  GENMASK(7, 7)
#define DDR_PHY_CGCR_DFIICGEN_X(x)               (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_CGCR_CGCR_RESERVED_31_8(x)       (((x) << 8) & GENMASK(31, 8))
#define DDR_PHY_CGCR_CGCR_RESERVED_31_8_M        GENMASK(31, 8)
#define DDR_PHY_CGCR_CGCR_RESERVED_31_8_X(x)     (((x) & GENMASK(31, 8)) >> 8)

/*      DDR_PHY:DWC_DDRPHY_PUB:CGCR1 */
#define DDR_PHY_CGCR1(t)          (t + 0x0c)

#define DDR_PHY_CGCR1_GATEACCTLCLK(x)            ((x) & GENMASK(0, 0))
#define DDR_PHY_CGCR1_GATEACCTLCLK_M             GENMASK(0, 0)
#define DDR_PHY_CGCR1_GATEACCTLCLK_X(x)          ((x) & GENMASK(0, 0))

#define DDR_PHY_CGCR1_GATEACDDRCLK(x)            (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_CGCR1_GATEACDDRCLK_M             GENMASK(1, 1)
#define DDR_PHY_CGCR1_GATEACDDRCLK_X(x)          (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_CGCR1_GATEACRDCLK(x)             (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_CGCR1_GATEACRDCLK_M              GENMASK(2, 2)
#define DDR_PHY_CGCR1_GATEACRDCLK_X(x)           (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_CGCR1_GATEDXCTLCLK(x)            (((x) << 3) & GENMASK(11, 3))
#define DDR_PHY_CGCR1_GATEDXCTLCLK_M             GENMASK(11, 3)
#define DDR_PHY_CGCR1_GATEDXCTLCLK_X(x)          (((x) & GENMASK(11, 3)) >> 3)

#define DDR_PHY_CGCR1_GATEDXDDRCLK(x)            (((x) << 12) & GENMASK(20, 12))
#define DDR_PHY_CGCR1_GATEDXDDRCLK_M             GENMASK(20, 12)
#define DDR_PHY_CGCR1_GATEDXDDRCLK_X(x)          (((x) & GENMASK(20, 12)) >> 12)

#define DDR_PHY_CGCR1_GATEDXRDCLK(x)             (((x) << 21) & GENMASK(29, 21))
#define DDR_PHY_CGCR1_GATEDXRDCLK_M              GENMASK(29, 21)
#define DDR_PHY_CGCR1_GATEDXRDCLK_X(x)           (((x) & GENMASK(29, 21)) >> 21)

#define DDR_PHY_CGCR1_CGCR1_RESERVED_31_30(x)    (((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_CGCR1_CGCR1_RESERVED_31_30_M     GENMASK(31, 30)
#define DDR_PHY_CGCR1_CGCR1_RESERVED_31_30_X(x)  (((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:PGCR0 */
#define DDR_PHY_PGCR0(t)          (t + 0x10)

#define DDR_PHY_PGCR0_ICPC(x)                    ((x) & GENMASK(0, 0))
#define DDR_PHY_PGCR0_ICPC_M                     GENMASK(0, 0)
#define DDR_PHY_PGCR0_ICPC_X(x)                  ((x) & GENMASK(0, 0))

#define DDR_PHY_PGCR0_CLRZCAL(x)                 (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_PGCR0_CLRZCAL_M                  GENMASK(1, 1)
#define DDR_PHY_PGCR0_CLRZCAL_X(x)               (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_PGCR0_PLLFSMBYP(x)               (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_PGCR0_PLLFSMBYP_M                GENMASK(2, 2)
#define DDR_PHY_PGCR0_PLLFSMBYP_X(x)             (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_PGCR0_INITFSMBYP(x)              (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_PGCR0_INITFSMBYP_M               GENMASK(3, 3)
#define DDR_PHY_PGCR0_INITFSMBYP_X(x)            (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_PGCR0_CLRPERR(x)                 (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_PGCR0_CLRPERR_M                  GENMASK(4, 4)
#define DDR_PHY_PGCR0_CLRPERR_X(x)               (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_PGCR0_CLRTSTAT(x)                (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_PGCR0_CLRTSTAT_M                 GENMASK(5, 5)
#define DDR_PHY_PGCR0_CLRTSTAT_X(x)              (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_PGCR0_DLTMODE(x)                 (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_PGCR0_DLTMODE_M                  GENMASK(6, 6)
#define DDR_PHY_PGCR0_DLTMODE_X(x)               (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_PGCR0_DLTST(x)                   (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_PGCR0_DLTST_M                    GENMASK(7, 7)
#define DDR_PHY_PGCR0_DLTST_X(x)                 (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_PGCR0_OSCEN(x)                   (((x) << 8) & GENMASK(8, 8))
#define DDR_PHY_PGCR0_OSCEN_M                    GENMASK(8, 8)
#define DDR_PHY_PGCR0_OSCEN_X(x)                 (((x) & GENMASK(8, 8)) >> 8)

#define DDR_PHY_PGCR0_OSCDIV(x)                  (((x) << 9) & GENMASK(12, 9))
#define DDR_PHY_PGCR0_OSCDIV_M                   GENMASK(12, 9)
#define DDR_PHY_PGCR0_OSCDIV_X(x)                (((x) & GENMASK(12, 9)) >> 9)

#define DDR_PHY_PGCR0_ACWLPON(x)                 (((x) << 13) & GENMASK(13, 13))
#define DDR_PHY_PGCR0_ACWLPON_M                  GENMASK(13, 13)
#define DDR_PHY_PGCR0_ACWLPON_X(x)               (((x) & GENMASK(13, 13)) >> 13)

#define DDR_PHY_PGCR0_DTOSEL(x)                  (((x) << 14) & GENMASK(18, 14))
#define DDR_PHY_PGCR0_DTOSEL_M                   GENMASK(18, 14)
#define DDR_PHY_PGCR0_DTOSEL_X(x)                (((x) & GENMASK(18, 14)) >> 14)

#define DDR_PHY_PGCR0_OSCWDL(x)                  (((x) << 19) & GENMASK(20, 19))
#define DDR_PHY_PGCR0_OSCWDL_M                   GENMASK(20, 19)
#define DDR_PHY_PGCR0_OSCWDL_X(x)                (((x) & GENMASK(20, 19)) >> 19)

#define DDR_PHY_PGCR0_PGCR0_RESERVED_21(x)       (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_PGCR0_PGCR0_RESERVED_21_M        GENMASK(21, 21)
#define DDR_PHY_PGCR0_PGCR0_RESERVED_21_X(x)     (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_PGCR0_OSCWDDL(x)                 (((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_PGCR0_OSCWDDL_M                  GENMASK(23, 22)
#define DDR_PHY_PGCR0_OSCWDDL_X(x)               (((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_PGCR0_OSCACDL(x)                 (((x) << 24) & GENMASK(25, 24))
#define DDR_PHY_PGCR0_OSCACDL_M                  GENMASK(25, 24)
#define DDR_PHY_PGCR0_OSCACDL_X(x)               (((x) & GENMASK(25, 24)) >> 24)

#define DDR_PHY_PGCR0_PHYFRST(x)                 (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_PGCR0_PHYFRST_M                  GENMASK(26, 26)
#define DDR_PHY_PGCR0_PHYFRST_X(x)               (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_PGCR0_X4OSCWDL(x)                (((x) << 27) & GENMASK(28, 27))
#define DDR_PHY_PGCR0_X4OSCWDL_M                 GENMASK(28, 27)
#define DDR_PHY_PGCR0_X4OSCWDL_X(x)              (((x) & GENMASK(28, 27)) >> 27)

#define DDR_PHY_PGCR0_X4OSCWDDL(x)               (((x) << 29) & GENMASK(30, 29))
#define DDR_PHY_PGCR0_X4OSCWDDL_M                GENMASK(30, 29)
#define DDR_PHY_PGCR0_X4OSCWDDL_X(x)             (((x) & GENMASK(30, 29)) >> 29)

#define DDR_PHY_PGCR0_ADCP(x)                    (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_PGCR0_ADCP_M                     GENMASK(31, 31)
#define DDR_PHY_PGCR0_ADCP_X(x)                  (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:PGCR1 */
#define DDR_PHY_PGCR1(t)          (t + 0x14)

#define DDR_PHY_PGCR1_DTOMODE(x)                 ((x) & GENMASK(0, 0))
#define DDR_PHY_PGCR1_DTOMODE_M                  GENMASK(0, 0)
#define DDR_PHY_PGCR1_DTOMODE_X(x)               ((x) & GENMASK(0, 0))

#define DDR_PHY_PGCR1_WLMODE(x)                  (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_PGCR1_WLMODE_M                   GENMASK(1, 1)
#define DDR_PHY_PGCR1_WLMODE_X(x)                (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_PGCR1_WLSTEP(x)                  (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_PGCR1_WLSTEP_M                   GENMASK(2, 2)
#define DDR_PHY_PGCR1_WLSTEP_X(x)                (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_PGCR1_WLUNCRT(x)                 (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_PGCR1_WLUNCRT_M                  GENMASK(3, 3)
#define DDR_PHY_PGCR1_WLUNCRT_X(x)               (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_PGCR1_DDLBYPMODE(x)              (((x) << 4) & GENMASK(5, 4))
#define DDR_PHY_PGCR1_DDLBYPMODE_M               GENMASK(5, 4)
#define DDR_PHY_PGCR1_DDLBYPMODE_X(x)            (((x) & GENMASK(5, 4)) >> 4)

#define DDR_PHY_PGCR1_PUBMODE(x)                 (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_PGCR1_PUBMODE_M                  GENMASK(6, 6)
#define DDR_PHY_PGCR1_PUBMODE_X(x)               (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_PGCR1_IODDRM(x)                  (((x) << 7) & GENMASK(8, 7))
#define DDR_PHY_PGCR1_IODDRM_M                   GENMASK(8, 7)
#define DDR_PHY_PGCR1_IODDRM_X(x)                (((x) & GENMASK(8, 7)) >> 7)

#define DDR_PHY_PGCR1_PGCR1_MDLEN(x)             (((x) << 9) & GENMASK(9, 9))
#define DDR_PHY_PGCR1_PGCR1_MDLEN_M              GENMASK(9, 9)
#define DDR_PHY_PGCR1_PGCR1_MDLEN_X(x)           (((x) & GENMASK(9, 9)) >> 9)

#define DDR_PHY_PGCR1_LPFEN(x)                   (((x) << 10) & GENMASK(10, 10))
#define DDR_PHY_PGCR1_LPFEN_M                    GENMASK(10, 10)
#define DDR_PHY_PGCR1_LPFEN_X(x)                 (((x) & GENMASK(10, 10)) >> 10)

#define DDR_PHY_PGCR1_LPFDEPTH(x)                (((x) << 11) & GENMASK(12, 11))
#define DDR_PHY_PGCR1_LPFDEPTH_M                 GENMASK(12, 11)
#define DDR_PHY_PGCR1_LPFDEPTH_X(x)              (((x) & GENMASK(12, 11)) >> 11)

#define DDR_PHY_PGCR1_FDEPTH(x)                  (((x) << 13) & GENMASK(14, 13))
#define DDR_PHY_PGCR1_FDEPTH_M                   GENMASK(14, 13)
#define DDR_PHY_PGCR1_FDEPTH_X(x)                (((x) & GENMASK(14, 13)) >> 13)

#define DDR_PHY_PGCR1_DUALCHN(x)                 (((x) << 15) & GENMASK(15, 15))
#define DDR_PHY_PGCR1_DUALCHN_M                  GENMASK(15, 15)
#define DDR_PHY_PGCR1_DUALCHN_X(x)               (((x) & GENMASK(15, 15)) >> 15)

#define DDR_PHY_PGCR1_ACPDDC(x)                  (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_PGCR1_ACPDDC_M                   GENMASK(16, 16)
#define DDR_PHY_PGCR1_ACPDDC_X(x)                (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_PGCR1_LPMSTRC0(x)                (((x) << 17) & GENMASK(17, 17))
#define DDR_PHY_PGCR1_LPMSTRC0_M                 GENMASK(17, 17)
#define DDR_PHY_PGCR1_LPMSTRC0_X(x)              (((x) & GENMASK(17, 17)) >> 17)

#define DDR_PHY_PGCR1_UPDMSTRC0(x)               (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_PGCR1_UPDMSTRC0_M                GENMASK(18, 18)
#define DDR_PHY_PGCR1_UPDMSTRC0_X(x)             (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_PGCR1_PRCFG_EN(x)                (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_PGCR1_PRCFG_EN_M                 GENMASK(19, 19)
#define DDR_PHY_PGCR1_PRCFG_EN_X(x)              (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_PGCR1_LRDIMMST(x)                (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_PGCR1_LRDIMMST_M                 GENMASK(20, 20)
#define DDR_PHY_PGCR1_LRDIMMST_X(x)              (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_PGCR1_ACVLDDLY(x)                (((x) << 21) & GENMASK(23, 21))
#define DDR_PHY_PGCR1_ACVLDDLY_M                 GENMASK(23, 21)
#define DDR_PHY_PGCR1_ACVLDDLY_X(x)              (((x) & GENMASK(23, 21)) >> 21)

#define DDR_PHY_PGCR1_ACVLDTRN(x)                (((x) << 24) & GENMASK(24, 24))
#define DDR_PHY_PGCR1_ACVLDTRN_M                 GENMASK(24, 24)
#define DDR_PHY_PGCR1_ACVLDTRN_X(x)              (((x) & GENMASK(24, 24)) >> 24)

#define DDR_PHY_PGCR1_PHYHRST(x)                 (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_PGCR1_PHYHRST_M                  GENMASK(25, 25)
#define DDR_PHY_PGCR1_PHYHRST_X(x)               (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_PGCR1_DLYLDTM(x)                 (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_PGCR1_DLYLDTM_M                  GENMASK(26, 26)
#define DDR_PHY_PGCR1_DLYLDTM_X(x)               (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_PGCR1_IOLB(x)                    (((x) << 27) & GENMASK(27, 27))
#define DDR_PHY_PGCR1_IOLB_M                     GENMASK(27, 27)
#define DDR_PHY_PGCR1_IOLB_X(x)                  (((x) & GENMASK(27, 27)) >> 27)

#define DDR_PHY_PGCR1_LBDQSS(x)                  (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_PGCR1_LBDQSS_M                   GENMASK(28, 28)
#define DDR_PHY_PGCR1_LBDQSS_X(x)                (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_PGCR1_LBGDQS(x)                  (((x) << 29) & GENMASK(30, 29))
#define DDR_PHY_PGCR1_LBGDQS_M                   GENMASK(30, 29)
#define DDR_PHY_PGCR1_LBGDQS_X(x)                (((x) & GENMASK(30, 29)) >> 29)

#define DDR_PHY_PGCR1_LBMODE(x)                  (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_PGCR1_LBMODE_M                   GENMASK(31, 31)
#define DDR_PHY_PGCR1_LBMODE_X(x)                (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:PGCR2 */
#define DDR_PHY_PGCR2(t)          (t + 0x18)

#define DDR_PHY_PGCR2_TREFPRD(x)                 ((x) & GENMASK(17, 0))
#define DDR_PHY_PGCR2_TREFPRD_M                  GENMASK(17, 0)
#define DDR_PHY_PGCR2_TREFPRD_X(x)               ((x) & GENMASK(17, 0))

#define DDR_PHY_PGCR2_CSNCIDMUX(x)               (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_PGCR2_CSNCIDMUX_M                GENMASK(18, 18)
#define DDR_PHY_PGCR2_CSNCIDMUX_X(x)             (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_PGCR2_FXDLAT(x)                  (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_PGCR2_FXDLAT_M                   GENMASK(19, 19)
#define DDR_PHY_PGCR2_FXDLAT_X(x)                (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_PGCR2_DTPMXTMR(x)                (((x) << 20) & GENMASK(27, 20))
#define DDR_PHY_PGCR2_DTPMXTMR_M                 GENMASK(27, 20)
#define DDR_PHY_PGCR2_DTPMXTMR_X(x)              (((x) & GENMASK(27, 20)) >> 20)

#define DDR_PHY_PGCR2_FXDLATINCR(x)              (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_PGCR2_FXDLATINCR_M               GENMASK(28, 28)
#define DDR_PHY_PGCR2_FXDLATINCR_X(x)            (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_PGCR2_RFSHMODE(x)                (((x) << 29) & GENMASK(30, 29))
#define DDR_PHY_PGCR2_RFSHMODE_M                 GENMASK(30, 29)
#define DDR_PHY_PGCR2_RFSHMODE_X(x)              (((x) & GENMASK(30, 29)) >> 29)

#define DDR_PHY_PGCR2_PGCR2_RESERVED_31(x)       (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_PGCR2_PGCR2_RESERVED_31_M        GENMASK(31, 31)
#define DDR_PHY_PGCR2_PGCR2_RESERVED_31_X(x)     (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:PGCR3 */
#define DDR_PHY_PGCR3(t)          (t + 0x1c)

#define DDR_PHY_PGCR3_CLKLEVEL(x)                ((x) & GENMASK(1, 0))
#define DDR_PHY_PGCR3_CLKLEVEL_M                 GENMASK(1, 0)
#define DDR_PHY_PGCR3_CLKLEVEL_X(x)              ((x) & GENMASK(1, 0))

#define DDR_PHY_PGCR3_DISRST(x)                  (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_PGCR3_DISRST_M                   GENMASK(2, 2)
#define DDR_PHY_PGCR3_DISRST_X(x)                (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_PGCR3_RDMODE(x)                  (((x) << 3) & GENMASK(4, 3))
#define DDR_PHY_PGCR3_RDMODE_M                   GENMASK(4, 3)
#define DDR_PHY_PGCR3_RDMODE_X(x)                (((x) & GENMASK(4, 3)) >> 3)

#define DDR_PHY_PGCR3_RDBICL(x)                  (((x) << 5) & GENMASK(7, 5))
#define DDR_PHY_PGCR3_RDBICL_M                   GENMASK(7, 5)
#define DDR_PHY_PGCR3_RDBICL_X(x)                (((x) & GENMASK(7, 5)) >> 5)

#define DDR_PHY_PGCR3_RESERVED_8(x)              (((x) << 8) & GENMASK(8, 8))
#define DDR_PHY_PGCR3_RESERVED_8_M               GENMASK(8, 8)
#define DDR_PHY_PGCR3_RESERVED_8_X(x)            (((x) & GENMASK(8, 8)) >> 8)

#define DDR_PHY_PGCR3_LPACCTLCLKGEN(x)           (((x) << 9) & GENMASK(9, 9))
#define DDR_PHY_PGCR3_LPACCTLCLKGEN_M            GENMASK(9, 9)
#define DDR_PHY_PGCR3_LPACCTLCLKGEN_X(x)         (((x) & GENMASK(9, 9)) >> 9)

#define DDR_PHY_PGCR3_LPACDDRCLKGEN(x)           (((x) << 10) & GENMASK(10, 10))
#define DDR_PHY_PGCR3_LPACDDRCLKGEN_M            GENMASK(10, 10)
#define DDR_PHY_PGCR3_LPACDDRCLKGEN_X(x)         (((x) & GENMASK(10, 10)) >> 10)

#define DDR_PHY_PGCR3_LPACRDCLKGEN(x)            (((x) << 11) & GENMASK(11, 11))
#define DDR_PHY_PGCR3_LPACRDCLKGEN_M             GENMASK(11, 11)
#define DDR_PHY_PGCR3_LPACRDCLKGEN_X(x)          (((x) & GENMASK(11, 11)) >> 11)

#define DDR_PHY_PGCR3_DISACOE(x)                 (((x) << 12) & GENMASK(12, 12))
#define DDR_PHY_PGCR3_DISACOE_M                  GENMASK(12, 12)
#define DDR_PHY_PGCR3_DISACOE_X(x)               (((x) & GENMASK(12, 12)) >> 12)

#define DDR_PHY_PGCR3_LPDXCTLCLKGEN(x)           (((x) << 13) & GENMASK(13, 13))
#define DDR_PHY_PGCR3_LPDXCTLCLKGEN_M            GENMASK(13, 13)
#define DDR_PHY_PGCR3_LPDXCTLCLKGEN_X(x)         (((x) & GENMASK(13, 13)) >> 13)

#define DDR_PHY_PGCR3_LPDXDDRCLKGEN(x)           (((x) << 14) & GENMASK(14, 14))
#define DDR_PHY_PGCR3_LPDXDDRCLKGEN_M            GENMASK(14, 14)
#define DDR_PHY_PGCR3_LPDXDDRCLKGEN_X(x)         (((x) & GENMASK(14, 14)) >> 14)

#define DDR_PHY_PGCR3_LPDXRDCLKGEN(x)            (((x) << 15) & GENMASK(15, 15))
#define DDR_PHY_PGCR3_LPDXRDCLKGEN_M             GENMASK(15, 15)
#define DDR_PHY_PGCR3_LPDXRDCLKGEN_X(x)          (((x) & GENMASK(15, 15)) >> 15)

#define DDR_PHY_PGCR3_CKEN(x)                    (((x) << 16) & GENMASK(23, 16))
#define DDR_PHY_PGCR3_CKEN_M                     GENMASK(23, 16)
#define DDR_PHY_PGCR3_CKEN_X(x)                  (((x) & GENMASK(23, 16)) >> 16)

#define DDR_PHY_PGCR3_PRFBYP(x)                  (((x) << 24) & GENMASK(24, 24))
#define DDR_PHY_PGCR3_PRFBYP_M                   GENMASK(24, 24)
#define DDR_PHY_PGCR3_PRFBYP_X(x)                (((x) & GENMASK(24, 24)) >> 24)

#define DDR_PHY_PGCR3_PGCR3_WDBI(x)              (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_PGCR3_PGCR3_WDBI_M               GENMASK(25, 25)
#define DDR_PHY_PGCR3_PGCR3_WDBI_X(x)            (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_PGCR3_PGCR3_RDBI(x)              (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_PGCR3_PGCR3_RDBI_M               GENMASK(26, 26)
#define DDR_PHY_PGCR3_PGCR3_RDBI_X(x)            (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_PGCR3_RDBICLSEL(x)               (((x) << 27) & GENMASK(27, 27))
#define DDR_PHY_PGCR3_RDBICLSEL_M                GENMASK(27, 27)
#define DDR_PHY_PGCR3_RDBICLSEL_X(x)             (((x) & GENMASK(27, 27)) >> 27)

#define DDR_PHY_PGCR3_LPWAKEUP_THRSH(x)          (((x) << 28) & GENMASK(31, 28))
#define DDR_PHY_PGCR3_LPWAKEUP_THRSH_M           GENMASK(31, 28)
#define DDR_PHY_PGCR3_LPWAKEUP_THRSH_X(x)        (((x) & GENMASK(31, 28)) >> 28)

/*      DDR_PHY:DWC_DDRPHY_PUB:PGCR4 */
#define DDR_PHY_PGCR4(t)          (t + 0x20)

#define DDR_PHY_PGCR4_DXDDLBYP(x)                ((x) & GENMASK(15, 0))
#define DDR_PHY_PGCR4_DXDDLBYP_M                 GENMASK(15, 0)
#define DDR_PHY_PGCR4_DXDDLBYP_X(x)              ((x) & GENMASK(15, 0))

#define DDR_PHY_PGCR4_DXDDLLD(x)                 (((x) << 16) & GENMASK(20, 16))
#define DDR_PHY_PGCR4_DXDDLLD_M                  GENMASK(20, 16)
#define DDR_PHY_PGCR4_DXDDLLD_X(x)               (((x) & GENMASK(20, 16)) >> 16)

#define DDR_PHY_PGCR4_RESERVED_22_21(x)          (((x) << 21) & GENMASK(22, 21))
#define DDR_PHY_PGCR4_RESERVED_22_21_M           GENMASK(22, 21)
#define DDR_PHY_PGCR4_RESERVED_22_21_X(x)        (((x) & GENMASK(22, 21)) >> 21)

#define DDR_PHY_PGCR4_ACVLDTRNP(x)               (((x) << 23) & GENMASK(23, 23))
#define DDR_PHY_PGCR4_ACVLDTRNP_M                GENMASK(23, 23)
#define DDR_PHY_PGCR4_ACVLDTRNP_X(x)             (((x) & GENMASK(23, 23)) >> 23)

#define DDR_PHY_PGCR4_ACDDLBYP(x)                (((x) << 24) & GENMASK(28, 24))
#define DDR_PHY_PGCR4_ACDDLBYP_M                 GENMASK(28, 24)
#define DDR_PHY_PGCR4_ACDDLBYP_X(x)              (((x) & GENMASK(28, 24)) >> 24)

#define DDR_PHY_PGCR4_ACDDLLD(x)                 (((x) << 29) & GENMASK(29, 29))
#define DDR_PHY_PGCR4_ACDDLLD_M                  GENMASK(29, 29)
#define DDR_PHY_PGCR4_ACDDLLD_X(x)               (((x) & GENMASK(29, 29)) >> 29)

#define DDR_PHY_PGCR4_ACDCCBYP(x)                (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_PGCR4_ACDCCBYP_M                 GENMASK(30, 30)
#define DDR_PHY_PGCR4_ACDCCBYP_X(x)              (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_PGCR4_ACRDMODE(x)                (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_PGCR4_ACRDMODE_M                 GENMASK(31, 31)
#define DDR_PHY_PGCR4_ACRDMODE_X(x)              (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:PGCR5 */
#define DDR_PHY_PGCR5(t)          (t + 0x24)

#define DDR_PHY_PGCR5_FRQCHANGE(x)               ((x) & GENMASK(0, 0))
#define DDR_PHY_PGCR5_FRQCHANGE_M                GENMASK(0, 0)
#define DDR_PHY_PGCR5_FRQCHANGE_X(x)             ((x) & GENMASK(0, 0))

#define DDR_PHY_PGCR5_FRQACT(x)                  (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_PGCR5_FRQACT_M                   GENMASK(1, 1)
#define DDR_PHY_PGCR5_FRQACT_X(x)                (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_PGCR5_FFCDCAL(x)                 (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_PGCR5_FFCDCAL_M                  GENMASK(2, 2)
#define DDR_PHY_PGCR5_FFCDCAL_X(x)               (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_PGCR5_FFCDFIEN(x)                (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_PGCR5_FFCDFIEN_M                 GENMASK(3, 3)
#define DDR_PHY_PGCR5_FFCDFIEN_X(x)              (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_PGCR5_RESERVED_11_4(x)           (((x) << 4) & GENMASK(11, 4))
#define DDR_PHY_PGCR5_RESERVED_11_4_M            GENMASK(11, 4)
#define DDR_PHY_PGCR5_RESERVED_11_4_X(x)         (((x) & GENMASK(11, 4)) >> 4)

#define DDR_PHY_PGCR5_FRQBSEL(x)                 (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_PGCR5_FRQBSEL_M                  GENMASK(15, 12)
#define DDR_PHY_PGCR5_FRQBSEL_X(x)               (((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_PGCR5_FRQAT(x)                   (((x) << 16) & GENMASK(23, 16))
#define DDR_PHY_PGCR5_FRQAT_M                    GENMASK(23, 16)
#define DDR_PHY_PGCR5_FRQAT_X(x)                 (((x) & GENMASK(23, 16)) >> 16)

#define DDR_PHY_PGCR5_FRQBT(x)                   (((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_PGCR5_FRQBT_M                    GENMASK(31, 24)
#define DDR_PHY_PGCR5_FRQBT_X(x)                 (((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:PGCR6 */
#define DDR_PHY_PGCR6(t)          (t + 0x28)

#define DDR_PHY_PGCR6_INHVT(x)                   ((x) & GENMASK(0, 0))
#define DDR_PHY_PGCR6_INHVT_M                    GENMASK(0, 0)
#define DDR_PHY_PGCR6_INHVT_X(x)                 ((x) & GENMASK(0, 0))

#define DDR_PHY_PGCR6_FVT(x)                     (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_PGCR6_FVT_M                      GENMASK(1, 1)
#define DDR_PHY_PGCR6_FVT_X(x)                   (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_PGCR6_RESERVED_2(x)              (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_PGCR6_RESERVED_2_M               GENMASK(2, 2)
#define DDR_PHY_PGCR6_RESERVED_2_X(x)            (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_PGCR6_PARBVT(x)                  (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_PGCR6_PARBVT_M                   GENMASK(3, 3)
#define DDR_PHY_PGCR6_PARBVT_X(x)                (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_PGCR6_ACTNBVT(x)                 (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_PGCR6_ACTNBVT_M                  GENMASK(4, 4)
#define DDR_PHY_PGCR6_ACTNBVT_X(x)               (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_PGCR6_A17BVT(x)                  (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_PGCR6_A17BVT_M                   GENMASK(5, 5)
#define DDR_PHY_PGCR6_A17BVT_X(x)                (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_PGCR6_A16BVT(x)                  (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_PGCR6_A16BVT_M                   GENMASK(6, 6)
#define DDR_PHY_PGCR6_A16BVT_X(x)                (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_PGCR6_CIDBVT(x)                  (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_PGCR6_CIDBVT_M                   GENMASK(7, 7)
#define DDR_PHY_PGCR6_CIDBVT_X(x)                (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_PGCR6_CKBVT(x)                   (((x) << 8) & GENMASK(8, 8))
#define DDR_PHY_PGCR6_CKBVT_M                    GENMASK(8, 8)
#define DDR_PHY_PGCR6_CKBVT_X(x)                 (((x) & GENMASK(8, 8)) >> 8)

#define DDR_PHY_PGCR6_CSNBVT(x)                  (((x) << 9) & GENMASK(9, 9))
#define DDR_PHY_PGCR6_CSNBVT_M                   GENMASK(9, 9)
#define DDR_PHY_PGCR6_CSNBVT_X(x)                (((x) & GENMASK(9, 9)) >> 9)

#define DDR_PHY_PGCR6_CKEBVT(x)                  (((x) << 10) & GENMASK(10, 10))
#define DDR_PHY_PGCR6_CKEBVT_M                   GENMASK(10, 10)
#define DDR_PHY_PGCR6_CKEBVT_X(x)                (((x) & GENMASK(10, 10)) >> 10)

#define DDR_PHY_PGCR6_ODTBVT(x)                  (((x) << 11) & GENMASK(11, 11))
#define DDR_PHY_PGCR6_ODTBVT_M                   GENMASK(11, 11)
#define DDR_PHY_PGCR6_ODTBVT_X(x)                (((x) & GENMASK(11, 11)) >> 11)

#define DDR_PHY_PGCR6_A9_0BVT(x)                 (((x) << 12) & GENMASK(12, 12))
#define DDR_PHY_PGCR6_A9_0BVT_M                  GENMASK(12, 12)
#define DDR_PHY_PGCR6_A9_0BVT_X(x)               (((x) & GENMASK(12, 12)) >> 12)

#define DDR_PHY_PGCR6_ACDLVT(x)                  (((x) << 13) & GENMASK(13, 13))
#define DDR_PHY_PGCR6_ACDLVT_M                   GENMASK(13, 13)
#define DDR_PHY_PGCR6_ACDLVT_X(x)                (((x) & GENMASK(13, 13)) >> 13)

#define DDR_PHY_PGCR6_A15_10BVT(x)               (((x) << 14) & GENMASK(14, 14))
#define DDR_PHY_PGCR6_A15_10BVT_M                GENMASK(14, 14)
#define DDR_PHY_PGCR6_A15_10BVT_X(x)             (((x) & GENMASK(14, 14)) >> 14)

#define DDR_PHY_PGCR6_BABVT(x)                   (((x) << 15) & GENMASK(15, 15))
#define DDR_PHY_PGCR6_BABVT_M                    GENMASK(15, 15)
#define DDR_PHY_PGCR6_BABVT_X(x)                 (((x) & GENMASK(15, 15)) >> 15)

#define DDR_PHY_PGCR6_DLDLMT(x)                  (((x) << 16) & GENMASK(23, 16))
#define DDR_PHY_PGCR6_DLDLMT_M                   GENMASK(23, 16)
#define DDR_PHY_PGCR6_DLDLMT_X(x)                (((x) & GENMASK(23, 16)) >> 16)

#define DDR_PHY_PGCR6_PGCR6_RESERVED_31_24(x)    (((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_PGCR6_PGCR6_RESERVED_31_24_M     GENMASK(31, 24)
#define DDR_PHY_PGCR6_PGCR6_RESERVED_31_24_X(x)  (((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:PGCR7 */
#define DDR_PHY_PGCR7(t)          (t + 0x2c)

#define DDR_PHY_PGCR7_ACTMODE(x)                 ((x) & GENMASK(0, 0))
#define DDR_PHY_PGCR7_ACTMODE_M                  GENMASK(0, 0)
#define DDR_PHY_PGCR7_ACTMODE_X(x)               ((x) & GENMASK(0, 0))

#define DDR_PHY_PGCR7_ACDTOSEL(x)                (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_PGCR7_ACDTOSEL_M                 GENMASK(1, 1)
#define DDR_PHY_PGCR7_ACDTOSEL_X(x)              (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_PGCR7_ACRSVD_2(x)                (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_PGCR7_ACRSVD_2_M                 GENMASK(2, 2)
#define DDR_PHY_PGCR7_ACRSVD_2_X(x)              (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_PGCR7_ACDLDT(x)                  (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_PGCR7_ACDLDT_M                   GENMASK(3, 3)
#define DDR_PHY_PGCR7_ACDLDT_X(x)                (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_PGCR7_ACRCLKMD(x)                (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_PGCR7_ACRCLKMD_M                 GENMASK(4, 4)
#define DDR_PHY_PGCR7_ACRCLKMD_X(x)              (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_PGCR7_ACCALCLK(x)                (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_PGCR7_ACCALCLK_M                 GENMASK(5, 5)
#define DDR_PHY_PGCR7_ACCALCLK_X(x)              (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_PGCR7_ACDTOMUX(x)                (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_PGCR7_ACDTOMUX_M                 GENMASK(6, 6)
#define DDR_PHY_PGCR7_ACDTOMUX_X(x)              (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_PGCR7_CKNSTOPL(x)                (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_PGCR7_CKNSTOPL_M                 GENMASK(7, 7)
#define DDR_PHY_PGCR7_CKNSTOPL_X(x)              (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_PGCR7_PGCR7_RESERVED_15_8(x)     (((x) << 8) & GENMASK(15, 8))
#define DDR_PHY_PGCR7_PGCR7_RESERVED_15_8_M      GENMASK(15, 8)
#define DDR_PHY_PGCR7_PGCR7_RESERVED_15_8_X(x)   (((x) & GENMASK(15, 8)) >> 8)

#define DDR_PHY_PGCR7_DXTMODE(x)                 (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_PGCR7_DXTMODE_M                  GENMASK(16, 16)
#define DDR_PHY_PGCR7_DXTMODE_X(x)               (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_PGCR7_DXGDBYP(x)                 (((x) << 17) & GENMASK(17, 17))
#define DDR_PHY_PGCR7_DXGDBYP_M                  GENMASK(17, 17)
#define DDR_PHY_PGCR7_DXGDBYP_X(x)               (((x) & GENMASK(17, 17)) >> 17)

#define DDR_PHY_PGCR7_DXQSDBYP(x)                (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_PGCR7_DXQSDBYP_M                 GENMASK(18, 18)
#define DDR_PHY_PGCR7_DXQSDBYP_X(x)              (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_PGCR7_DXDDLLDT(x)                (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_PGCR7_DXDDLLDT_M                 GENMASK(19, 19)
#define DDR_PHY_PGCR7_DXDDLLDT_X(x)              (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_PGCR7_DXGSMD(x)                  (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_PGCR7_DXGSMD_M                   GENMASK(20, 20)
#define DDR_PHY_PGCR7_DXGSMD_X(x)                (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_PGCR7_DXDTOSEL(x)                (((x) << 21) & GENMASK(22, 21))
#define DDR_PHY_PGCR7_DXDTOSEL_M                 GENMASK(22, 21)
#define DDR_PHY_PGCR7_DXDTOSEL_X(x)              (((x) & GENMASK(22, 21)) >> 21)

#define DDR_PHY_PGCR7_DXQSGSEL(x)                (((x) << 23) & GENMASK(23, 23))
#define DDR_PHY_PGCR7_DXQSGSEL_M                 GENMASK(23, 23)
#define DDR_PHY_PGCR7_DXQSGSEL_X(x)              (((x) & GENMASK(23, 23)) >> 23)

#define DDR_PHY_PGCR7_DXRCLKMD(x)                (((x) << 24) & GENMASK(24, 24))
#define DDR_PHY_PGCR7_DXRCLKMD_M                 GENMASK(24, 24)
#define DDR_PHY_PGCR7_DXRCLKMD_X(x)              (((x) & GENMASK(24, 24)) >> 24)

#define DDR_PHY_PGCR7_DXCALCLK(x)                (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_PGCR7_DXCALCLK_M                 GENMASK(25, 25)
#define DDR_PHY_PGCR7_DXCALCLK_X(x)              (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_PGCR7_DXDTOMUX(x)                (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_PGCR7_DXDTOMUX_M                 GENMASK(26, 26)
#define DDR_PHY_PGCR7_DXDTOMUX_X(x)              (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_PGCR7_DXRSVD(x)                  (((x) << 27) & GENMASK(30, 27))
#define DDR_PHY_PGCR7_DXRSVD_M                   GENMASK(30, 27)
#define DDR_PHY_PGCR7_DXRSVD_X(x)                (((x) & GENMASK(30, 27)) >> 27)

#define DDR_PHY_PGCR7_WRPSTEX(x)                 (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_PGCR7_WRPSTEX_M                  GENMASK(31, 31)
#define DDR_PHY_PGCR7_WRPSTEX_X(x)               (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:PGCR8 */
#define DDR_PHY_PGCR8(t)          (t + 0x30)

#define DDR_PHY_PGCR8_DCALSVAL(x)                ((x) & GENMASK(8, 0))
#define DDR_PHY_PGCR8_DCALSVAL_M                 GENMASK(8, 0)
#define DDR_PHY_PGCR8_DCALSVAL_X(x)              ((x) & GENMASK(8, 0))

#define DDR_PHY_PGCR8_DCALTYPE(x)                (((x) << 9) & GENMASK(9, 9))
#define DDR_PHY_PGCR8_DCALTYPE_M                 GENMASK(9, 9)
#define DDR_PHY_PGCR8_DCALTYPE_X(x)              (((x) & GENMASK(9, 9)) >> 9)

#define DDR_PHY_PGCR8_PGCR8_RESERVED_31_10(x)    (((x) << 10) & GENMASK(31, 10))
#define DDR_PHY_PGCR8_PGCR8_RESERVED_31_10_M     GENMASK(31, 10)
#define DDR_PHY_PGCR8_PGCR8_RESERVED_31_10_X(x)  (((x) & GENMASK(31, 10)) >> 10)

/*      DDR_PHY:DWC_DDRPHY_PUB:PGSR0 */
#define DDR_PHY_PGSR0(t)          (t + 0x34)

#define DDR_PHY_PGSR0_IDONE(x)                   ((x) & GENMASK(0, 0))
#define DDR_PHY_PGSR0_IDONE_M                    GENMASK(0, 0)
#define DDR_PHY_PGSR0_IDONE_X(x)                 ((x) & GENMASK(0, 0))

#define DDR_PHY_PGSR0_PLDONE(x)                  (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_PGSR0_PLDONE_M                   GENMASK(1, 1)
#define DDR_PHY_PGSR0_PLDONE_X(x)                (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_PGSR0_DCDONE(x)                  (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_PGSR0_DCDONE_M                   GENMASK(2, 2)
#define DDR_PHY_PGSR0_DCDONE_X(x)                (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_PGSR0_ZCDONE(x)                  (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_PGSR0_ZCDONE_M                   GENMASK(3, 3)
#define DDR_PHY_PGSR0_ZCDONE_X(x)                (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_PGSR0_DIDONE(x)                  (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_PGSR0_DIDONE_M                   GENMASK(4, 4)
#define DDR_PHY_PGSR0_DIDONE_X(x)                (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_PGSR0_PGSR0_WLDONE(x)            (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_PGSR0_PGSR0_WLDONE_M             GENMASK(5, 5)
#define DDR_PHY_PGSR0_PGSR0_WLDONE_X(x)          (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_PGSR0_QSGDONE(x)                 (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_PGSR0_QSGDONE_M                  GENMASK(6, 6)
#define DDR_PHY_PGSR0_QSGDONE_X(x)               (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_PGSR0_WLADONE(x)                 (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_PGSR0_WLADONE_M                  GENMASK(7, 7)
#define DDR_PHY_PGSR0_WLADONE_X(x)               (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_PGSR0_RDDONE(x)                  (((x) << 8) & GENMASK(8, 8))
#define DDR_PHY_PGSR0_RDDONE_M                   GENMASK(8, 8)
#define DDR_PHY_PGSR0_RDDONE_X(x)                (((x) & GENMASK(8, 8)) >> 8)

#define DDR_PHY_PGSR0_WDDONE(x)                  (((x) << 9) & GENMASK(9, 9))
#define DDR_PHY_PGSR0_WDDONE_M                   GENMASK(9, 9)
#define DDR_PHY_PGSR0_WDDONE_X(x)                (((x) & GENMASK(9, 9)) >> 9)

#define DDR_PHY_PGSR0_REDONE(x)                  (((x) << 10) & GENMASK(10, 10))
#define DDR_PHY_PGSR0_REDONE_M                   GENMASK(10, 10)
#define DDR_PHY_PGSR0_REDONE_X(x)                (((x) & GENMASK(10, 10)) >> 10)

#define DDR_PHY_PGSR0_WEDONE(x)                  (((x) << 11) & GENMASK(11, 11))
#define DDR_PHY_PGSR0_WEDONE_M                   GENMASK(11, 11)
#define DDR_PHY_PGSR0_WEDONE_X(x)                (((x) & GENMASK(11, 11)) >> 11)

#define DDR_PHY_PGSR0_CADONE(x)                  (((x) << 12) & GENMASK(12, 12))
#define DDR_PHY_PGSR0_CADONE_M                   GENMASK(12, 12)
#define DDR_PHY_PGSR0_CADONE_X(x)                (((x) & GENMASK(12, 12)) >> 12)

#define DDR_PHY_PGSR0_SRDDONE(x)                 (((x) << 13) & GENMASK(13, 13))
#define DDR_PHY_PGSR0_SRDDONE_M                  GENMASK(13, 13)
#define DDR_PHY_PGSR0_SRDDONE_X(x)               (((x) & GENMASK(13, 13)) >> 13)

#define DDR_PHY_PGSR0_VDONE(x)                   (((x) << 14) & GENMASK(14, 14))
#define DDR_PHY_PGSR0_VDONE_M                    GENMASK(14, 14)
#define DDR_PHY_PGSR0_VDONE_X(x)                 (((x) & GENMASK(14, 14)) >> 14)

#define DDR_PHY_PGSR0_RESERVED_18_15(x)          (((x) << 15) & GENMASK(18, 15))
#define DDR_PHY_PGSR0_RESERVED_18_15_M           GENMASK(18, 15)
#define DDR_PHY_PGSR0_RESERVED_18_15_X(x)        (((x) & GENMASK(18, 15)) >> 15)

#define DDR_PHY_PGSR0_VERR(x)                    (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_PGSR0_VERR_M                     GENMASK(19, 19)
#define DDR_PHY_PGSR0_VERR_X(x)                  (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_PGSR0_ZCERR(x)                   (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_PGSR0_ZCERR_M                    GENMASK(20, 20)
#define DDR_PHY_PGSR0_ZCERR_X(x)                 (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_PGSR0_PGSR0_WLERR(x)             (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_PGSR0_PGSR0_WLERR_M              GENMASK(21, 21)
#define DDR_PHY_PGSR0_PGSR0_WLERR_X(x)           (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_PGSR0_PGSR0_QSGERR(x)            (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_PGSR0_PGSR0_QSGERR_M             GENMASK(22, 22)
#define DDR_PHY_PGSR0_PGSR0_QSGERR_X(x)          (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_PGSR0_PGSR0_WLAERR(x)            (((x) << 23) & GENMASK(23, 23))
#define DDR_PHY_PGSR0_PGSR0_WLAERR_M             GENMASK(23, 23)
#define DDR_PHY_PGSR0_PGSR0_WLAERR_X(x)          (((x) & GENMASK(23, 23)) >> 23)

#define DDR_PHY_PGSR0_PGSR0_RDERR(x)             (((x) << 24) & GENMASK(24, 24))
#define DDR_PHY_PGSR0_PGSR0_RDERR_M              GENMASK(24, 24)
#define DDR_PHY_PGSR0_PGSR0_RDERR_X(x)           (((x) & GENMASK(24, 24)) >> 24)

#define DDR_PHY_PGSR0_PGSR0_WDERR(x)             (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_PGSR0_PGSR0_WDERR_M              GENMASK(25, 25)
#define DDR_PHY_PGSR0_PGSR0_WDERR_X(x)           (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_PGSR0_PGSR0_REERR(x)             (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_PGSR0_PGSR0_REERR_M              GENMASK(26, 26)
#define DDR_PHY_PGSR0_PGSR0_REERR_X(x)           (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_PGSR0_PGSR0_WEERR(x)             (((x) << 27) & GENMASK(27, 27))
#define DDR_PHY_PGSR0_PGSR0_WEERR_M              GENMASK(27, 27)
#define DDR_PHY_PGSR0_PGSR0_WEERR_X(x)           (((x) & GENMASK(27, 27)) >> 27)

#define DDR_PHY_PGSR0_CAERR(x)                   (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_PGSR0_CAERR_M                    GENMASK(28, 28)
#define DDR_PHY_PGSR0_CAERR_X(x)                 (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_PGSR0_CAWRN(x)                   (((x) << 29) & GENMASK(29, 29))
#define DDR_PHY_PGSR0_CAWRN_M                    GENMASK(29, 29)
#define DDR_PHY_PGSR0_CAWRN_X(x)                 (((x) & GENMASK(29, 29)) >> 29)

#define DDR_PHY_PGSR0_PGSR0_SRDERR(x)            (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_PGSR0_PGSR0_SRDERR_M             GENMASK(30, 30)
#define DDR_PHY_PGSR0_PGSR0_SRDERR_X(x)          (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_PGSR0_APLOCK(x)                  (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_PGSR0_APLOCK_M                   GENMASK(31, 31)
#define DDR_PHY_PGSR0_APLOCK_X(x)                (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:PGSR1 */
#define DDR_PHY_PGSR1(t)          (t + 0x38)

#define DDR_PHY_PGSR1_PGSR1_DLTDONE(x)           ((x) & GENMASK(0, 0))
#define DDR_PHY_PGSR1_PGSR1_DLTDONE_M            GENMASK(0, 0)
#define DDR_PHY_PGSR1_PGSR1_DLTDONE_X(x)         ((x) & GENMASK(0, 0))

#define DDR_PHY_PGSR1_PGSR1_DLTCODE(x)           (((x) << 1) & GENMASK(24, 1))
#define DDR_PHY_PGSR1_PGSR1_DLTCODE_M            GENMASK(24, 1)
#define DDR_PHY_PGSR1_PGSR1_DLTCODE_X(x)         (((x) & GENMASK(24, 1)) >> 1)

#define DDR_PHY_PGSR1_PGSR1_RESERVED_28_25(x)    (((x) << 25) & GENMASK(28, 25))
#define DDR_PHY_PGSR1_PGSR1_RESERVED_28_25_M     GENMASK(28, 25)
#define DDR_PHY_PGSR1_PGSR1_RESERVED_28_25_X(x)  (((x) & GENMASK(28, 25)) >> 25)

#define DDR_PHY_PGSR1_FFCDONE(x)                 (((x) << 29) & GENMASK(29, 29))
#define DDR_PHY_PGSR1_FFCDONE_M                  GENMASK(29, 29)
#define DDR_PHY_PGSR1_FFCDONE_X(x)               (((x) & GENMASK(29, 29)) >> 29)

#define DDR_PHY_PGSR1_VTSTOP(x)                  (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_PGSR1_VTSTOP_M                   GENMASK(30, 30)
#define DDR_PHY_PGSR1_VTSTOP_X(x)                (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_PGSR1_PARERR(x)                  (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_PGSR1_PARERR_M                   GENMASK(31, 31)
#define DDR_PHY_PGSR1_PARERR_X(x)                (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:PTR0 */
#define DDR_PHY_PTR0(t)           (t + 0x40)

#define DDR_PHY_PTR0_TPHYRST(x)                  ((x) & GENMASK(5, 0))
#define DDR_PHY_PTR0_TPHYRST_M                   GENMASK(5, 0)
#define DDR_PHY_PTR0_TPHYRST_X(x)                ((x) & GENMASK(5, 0))

#define DDR_PHY_PTR0_TPLLGS(x)                   (((x) << 6) & GENMASK(20, 6))
#define DDR_PHY_PTR0_TPLLGS_M                    GENMASK(20, 6)
#define DDR_PHY_PTR0_TPLLGS_X(x)                 (((x) & GENMASK(20, 6)) >> 6)

#define DDR_PHY_PTR0_TPLLPD(x)                   (((x) << 21) & GENMASK(31, 21))
#define DDR_PHY_PTR0_TPLLPD_M                    GENMASK(31, 21)
#define DDR_PHY_PTR0_TPLLPD_X(x)                 (((x) & GENMASK(31, 21)) >> 21)

/*      DDR_PHY:DWC_DDRPHY_PUB:PTR1 */
#define DDR_PHY_PTR1(t)           (t + 0x44)

#define DDR_PHY_PTR1_TPLLRST(x)                  ((x) & GENMASK(12, 0))
#define DDR_PHY_PTR1_TPLLRST_M                   GENMASK(12, 0)
#define DDR_PHY_PTR1_TPLLRST_X(x)                ((x) & GENMASK(12, 0))

#define DDR_PHY_PTR1_RESERVED_14_13(x)           (((x) << 13) & GENMASK(14, 13))
#define DDR_PHY_PTR1_RESERVED_14_13_M            GENMASK(14, 13)
#define DDR_PHY_PTR1_RESERVED_14_13_X(x)         (((x) & GENMASK(14, 13)) >> 13)

#define DDR_PHY_PTR1_TPLLLOCK(x)                 (((x) << 15) & GENMASK(31, 15))
#define DDR_PHY_PTR1_TPLLLOCK_M                  GENMASK(31, 15)
#define DDR_PHY_PTR1_TPLLLOCK_X(x)               (((x) & GENMASK(31, 15)) >> 15)

/*      DDR_PHY:DWC_DDRPHY_PUB:PTR2 */
#define DDR_PHY_PTR2(t)           (t + 0x48)

#define DDR_PHY_PTR2_TCALON(x)                   ((x) & GENMASK(4, 0))
#define DDR_PHY_PTR2_TCALON_M                    GENMASK(4, 0)
#define DDR_PHY_PTR2_TCALON_X(x)                 ((x) & GENMASK(4, 0))

#define DDR_PHY_PTR2_TCALS(x)                    (((x) << 5) & GENMASK(9, 5))
#define DDR_PHY_PTR2_TCALS_M                     GENMASK(9, 5)
#define DDR_PHY_PTR2_TCALS_X(x)                  (((x) & GENMASK(9, 5)) >> 5)

#define DDR_PHY_PTR2_TCALH(x)                    (((x) << 10) & GENMASK(14, 10))
#define DDR_PHY_PTR2_TCALH_M                     GENMASK(14, 10)
#define DDR_PHY_PTR2_TCALH_X(x)                  (((x) & GENMASK(14, 10)) >> 10)

#define DDR_PHY_PTR2_TWLDLYS(x)                  (((x) << 15) & GENMASK(19, 15))
#define DDR_PHY_PTR2_TWLDLYS_M                   GENMASK(19, 15)
#define DDR_PHY_PTR2_TWLDLYS_X(x)                (((x) & GENMASK(19, 15)) >> 15)

#define DDR_PHY_PTR2_PTR2_RESERVED_31_20(x)      (((x) << 20) & GENMASK(31, 20))
#define DDR_PHY_PTR2_PTR2_RESERVED_31_20_M       GENMASK(31, 20)
#define DDR_PHY_PTR2_PTR2_RESERVED_31_20_X(x)    (((x) & GENMASK(31, 20)) >> 20)

/*      DDR_PHY:DWC_DDRPHY_PUB:PTR3 */
#define DDR_PHY_PTR3(t)           (t + 0x4c)

#define DDR_PHY_PTR3_TDINIT0(x)                  ((x) & GENMASK(19, 0))
#define DDR_PHY_PTR3_TDINIT0_M                   GENMASK(19, 0)
#define DDR_PHY_PTR3_TDINIT0_X(x)                ((x) & GENMASK(19, 0))

#define DDR_PHY_PTR3_TDINIT1(x)                  (((x) << 20) & GENMASK(29, 20))
#define DDR_PHY_PTR3_TDINIT1_M                   GENMASK(29, 20)
#define DDR_PHY_PTR3_TDINIT1_X(x)                (((x) & GENMASK(29, 20)) >> 20)

#define DDR_PHY_PTR3_PTR3_RESERVED_31_30(x)      (((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_PTR3_PTR3_RESERVED_31_30_M       GENMASK(31, 30)
#define DDR_PHY_PTR3_PTR3_RESERVED_31_30_X(x)    (((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:PTR4 */
#define DDR_PHY_PTR4(t)           (t + 0x50)

#define DDR_PHY_PTR4_TDINIT2(x)                  ((x) & GENMASK(17, 0))
#define DDR_PHY_PTR4_TDINIT2_M                   GENMASK(17, 0)
#define DDR_PHY_PTR4_TDINIT2_X(x)                ((x) & GENMASK(17, 0))

#define DDR_PHY_PTR4_TDINIT3(x)                  (((x) << 18) & GENMASK(28, 18))
#define DDR_PHY_PTR4_TDINIT3_M                   GENMASK(28, 18)
#define DDR_PHY_PTR4_TDINIT3_X(x)                (((x) & GENMASK(28, 18)) >> 18)

#define DDR_PHY_PTR4_PTR4_RESERVED_31_29(x)      (((x) << 29) & GENMASK(31, 29))
#define DDR_PHY_PTR4_PTR4_RESERVED_31_29_M       GENMASK(31, 29)
#define DDR_PHY_PTR4_PTR4_RESERVED_31_29_X(x)    (((x) & GENMASK(31, 29)) >> 29)

/*      DDR_PHY:DWC_DDRPHY_PUB:PTR5 */
#define DDR_PHY_PTR5(t)           (t + 0x54)

#define DDR_PHY_PTR5_TPLLFFCGS(x)                ((x) & GENMASK(11, 0))
#define DDR_PHY_PTR5_TPLLFFCGS_M                 GENMASK(11, 0)
#define DDR_PHY_PTR5_TPLLFFCGS_X(x)              ((x) & GENMASK(11, 0))

#define DDR_PHY_PTR5_PTR5_RESERVED_13_12(x)      (((x) << 12) & GENMASK(13, 12))
#define DDR_PHY_PTR5_PTR5_RESERVED_13_12_M       GENMASK(13, 12)
#define DDR_PHY_PTR5_PTR5_RESERVED_13_12_X(x)    (((x) & GENMASK(13, 12)) >> 12)

#define DDR_PHY_PTR5_TPLLFFCRGS(x)               (((x) << 14) & GENMASK(23, 14))
#define DDR_PHY_PTR5_TPLLFFCRGS_M                GENMASK(23, 14)
#define DDR_PHY_PTR5_TPLLFFCRGS_X(x)             (((x) & GENMASK(23, 14)) >> 14)

#define DDR_PHY_PTR5_RESERVED_25_24(x)           (((x) << 24) & GENMASK(25, 24))
#define DDR_PHY_PTR5_RESERVED_25_24_M            GENMASK(25, 24)
#define DDR_PHY_PTR5_RESERVED_25_24_X(x)         (((x) & GENMASK(25, 24)) >> 24)

#define DDR_PHY_PTR5_TPLLFRQSEL(x)               (((x) << 26) & GENMASK(31, 26))
#define DDR_PHY_PTR5_TPLLFRQSEL_M                GENMASK(31, 26)
#define DDR_PHY_PTR5_TPLLFRQSEL_X(x)             (((x) & GENMASK(31, 26)) >> 26)

/*      DDR_PHY:DWC_DDRPHY_PUB:PTR6 */
#define DDR_PHY_PTR6(t)           (t + 0x58)

#define DDR_PHY_PTR6_TPLLRLCK1(x)                ((x) & GENMASK(13, 0))
#define DDR_PHY_PTR6_TPLLRLCK1_M                 GENMASK(13, 0)
#define DDR_PHY_PTR6_TPLLRLCK1_X(x)              ((x) & GENMASK(13, 0))

#define DDR_PHY_PTR6_RESERVED_31_14(x)           (((x) << 14) & GENMASK(31, 14))
#define DDR_PHY_PTR6_RESERVED_31_14_M            GENMASK(31, 14)
#define DDR_PHY_PTR6_RESERVED_31_14_X(x)         (((x) & GENMASK(31, 14)) >> 14)

/*      DDR_PHY:DWC_DDRPHY_PUB:PLLCR0 */
#define DDR_PHY_PLLCR0(t)         (t + 0x68)

#define DDR_PHY_PLLCR0_PLLCR0_DTC(x)             ((x) & GENMASK(3, 0))
#define DDR_PHY_PLLCR0_PLLCR0_DTC_M              GENMASK(3, 0)
#define DDR_PHY_PLLCR0_PLLCR0_DTC_X(x)           ((x) & GENMASK(3, 0))

#define DDR_PHY_PLLCR0_PLLCR0_ATC(x)             (((x) << 4) & GENMASK(7, 4))
#define DDR_PHY_PLLCR0_PLLCR0_ATC_M              GENMASK(7, 4)
#define DDR_PHY_PLLCR0_PLLCR0_ATC_X(x)           (((x) & GENMASK(7, 4)) >> 4)

#define DDR_PHY_PLLCR0_PLLCR0_ATOEN(x)           (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_PLLCR0_PLLCR0_ATOEN_M            GENMASK(11, 8)
#define DDR_PHY_PLLCR0_PLLCR0_ATOEN_X(x)         (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_PLLCR0_PLLCR0_GSHIFT(x)          (((x) << 12) & GENMASK(12, 12))
#define DDR_PHY_PLLCR0_PLLCR0_GSHIFT_M           GENMASK(12, 12)
#define DDR_PHY_PLLCR0_PLLCR0_GSHIFT_X(x)        (((x) & GENMASK(12, 12)) >> 12)

#define DDR_PHY_PLLCR0_PLLCR0_CPIC(x)            (((x) << 13) & GENMASK(16, 13))
#define DDR_PHY_PLLCR0_PLLCR0_CPIC_M             GENMASK(16, 13)
#define DDR_PHY_PLLCR0_PLLCR0_CPIC_X(x)          (((x) & GENMASK(16, 13)) >> 13)

#define DDR_PHY_PLLCR0_PLLCR0_CPPC(x)            (((x) << 17) & GENMASK(22, 17))
#define DDR_PHY_PLLCR0_PLLCR0_CPPC_M             GENMASK(22, 17)
#define DDR_PHY_PLLCR0_PLLCR0_CPPC_X(x)          (((x) & GENMASK(22, 17)) >> 17)

#define DDR_PHY_PLLCR0_RLOCKM(x)                 (((x) << 23) & GENMASK(23, 23))
#define DDR_PHY_PLLCR0_RLOCKM_M                  GENMASK(23, 23)
#define DDR_PHY_PLLCR0_RLOCKM_X(x)               (((x) & GENMASK(23, 23)) >> 23)

#define DDR_PHY_PLLCR0_PLLCR0_FRQSEL(x)          (((x) << 24) & GENMASK(27, 24))
#define DDR_PHY_PLLCR0_PLLCR0_FRQSEL_M           GENMASK(27, 24)
#define DDR_PHY_PLLCR0_PLLCR0_FRQSEL_X(x)        (((x) & GENMASK(27, 24)) >> 24)

#define DDR_PHY_PLLCR0_RSTOPM(x)                 (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_PLLCR0_RSTOPM_M                  GENMASK(28, 28)
#define DDR_PHY_PLLCR0_RSTOPM_X(x)               (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_PLLCR0_PLLCR0_PLLPD(x)           (((x) << 29) & GENMASK(29, 29))
#define DDR_PHY_PLLCR0_PLLCR0_PLLPD_M            GENMASK(29, 29)
#define DDR_PHY_PLLCR0_PLLCR0_PLLPD_X(x)         (((x) & GENMASK(29, 29)) >> 29)

#define DDR_PHY_PLLCR0_PLLCR0_PLLRST(x)          (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_PLLCR0_PLLCR0_PLLRST_M           GENMASK(30, 30)
#define DDR_PHY_PLLCR0_PLLCR0_PLLRST_X(x)        (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_PLLCR0_PLLCR0_PLLBYP(x)          (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_PLLCR0_PLLCR0_PLLBYP_M           GENMASK(31, 31)
#define DDR_PHY_PLLCR0_PLLCR0_PLLBYP_X(x)        (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:PLLCR1 */
#define DDR_PHY_PLLCR1(t)         (t + 0x6c)

#define DDR_PHY_PLLCR1_PLLCR1_LOCKDS(x)          ((x) & GENMASK(0, 0))
#define DDR_PHY_PLLCR1_PLLCR1_LOCKDS_M           GENMASK(0, 0)
#define DDR_PHY_PLLCR1_PLLCR1_LOCKDS_X(x)        ((x) & GENMASK(0, 0))

#define DDR_PHY_PLLCR1_PLLCR1_LOCKCS(x)          (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_PLLCR1_PLLCR1_LOCKCS_M           GENMASK(1, 1)
#define DDR_PHY_PLLCR1_PLLCR1_LOCKCS_X(x)        (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_PLLCR1_PLLCR1_LOCKPS(x)          (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_PLLCR1_PLLCR1_LOCKPS_M           GENMASK(2, 2)
#define DDR_PHY_PLLCR1_PLLCR1_LOCKPS_X(x)        (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_PLLCR1_BYPVDD(x)                 (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_PLLCR1_BYPVDD_M                  GENMASK(3, 3)
#define DDR_PHY_PLLCR1_BYPVDD_X(x)               (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_PLLCR1_BYPVREGDIG(x)             (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_PLLCR1_BYPVREGDIG_M              GENMASK(4, 4)
#define DDR_PHY_PLLCR1_BYPVREGDIG_X(x)           (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_PLLCR1_BYPVREGCP(x)              (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_PLLCR1_BYPVREGCP_M               GENMASK(5, 5)
#define DDR_PHY_PLLCR1_BYPVREGCP_X(x)            (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_PLLCR1_RESERVED_15_6(x)          (((x) << 6) & GENMASK(15, 6))
#define DDR_PHY_PLLCR1_RESERVED_15_6_M           GENMASK(15, 6)
#define DDR_PHY_PLLCR1_RESERVED_15_6_X(x)        (((x) & GENMASK(15, 6)) >> 6)

#define DDR_PHY_PLLCR1_PLLPROG(x)                (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_PLLCR1_PLLPROG_M                 GENMASK(31, 16)
#define DDR_PHY_PLLCR1_PLLPROG_X(x)              (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:PLLCR2 */
#define DDR_PHY_PLLCR2(t)         (t + 0x70)

/*      DDR_PHY:DWC_DDRPHY_PUB:PLLCR3 */
#define DDR_PHY_PLLCR3(t)         (t + 0x74)

/*      DDR_PHY:DWC_DDRPHY_PUB:PLLCR4 */
#define DDR_PHY_PLLCR4(t)         (t + 0x78)

/*      DDR_PHY:DWC_DDRPHY_PUB:PLLCR5 */
#define DDR_PHY_PLLCR5(t)         (t + 0x7c)

#define DDR_PHY_PLLCR5_PLLCTRL_103_96(x)         ((x) & GENMASK(7, 0))
#define DDR_PHY_PLLCR5_PLLCTRL_103_96_M          GENMASK(7, 0)
#define DDR_PHY_PLLCR5_PLLCTRL_103_96_X(x)       ((x) & GENMASK(7, 0))

#define DDR_PHY_PLLCR5_PLLCR5_RESERVED_31_8(x)   (((x) << 8) & GENMASK(31, 8))
#define DDR_PHY_PLLCR5_PLLCR5_RESERVED_31_8_M    GENMASK(31, 8)
#define DDR_PHY_PLLCR5_PLLCR5_RESERVED_31_8_X(x) (((x) & GENMASK(31, 8)) >> 8)

/*      DDR_PHY:DWC_DDRPHY_PUB:PLLCR */
#define DDR_PHY_PLLCR(t)          (t + 0x80)

#define DDR_PHY_PLLCR_PLLCR_DTC(x)               ((x) & GENMASK(2, 0))
#define DDR_PHY_PLLCR_PLLCR_DTC_M                GENMASK(2, 0)
#define DDR_PHY_PLLCR_PLLCR_DTC_X(x)             ((x) & GENMASK(2, 0))

#define DDR_PHY_PLLCR_PLLCR_ATC(x)               (((x) << 3) & GENMASK(6, 3))
#define DDR_PHY_PLLCR_PLLCR_ATC_M                GENMASK(6, 3)
#define DDR_PHY_PLLCR_PLLCR_ATC_X(x)             (((x) & GENMASK(6, 3)) >> 3)

#define DDR_PHY_PLLCR_PLLCR_ATOEN(x)             (((x) << 7) & GENMASK(10, 7))
#define DDR_PHY_PLLCR_PLLCR_ATOEN_M              GENMASK(10, 7)
#define DDR_PHY_PLLCR_PLLCR_ATOEN_X(x)           (((x) & GENMASK(10, 7)) >> 7)

#define DDR_PHY_PLLCR_PLLCR_GSHIFT(x)            (((x) << 11) & GENMASK(11, 11))
#define DDR_PHY_PLLCR_PLLCR_GSHIFT_M             GENMASK(11, 11)
#define DDR_PHY_PLLCR_PLLCR_GSHIFT_X(x)          (((x) & GENMASK(11, 11)) >> 11)

#define DDR_PHY_PLLCR_PLLCR_CPIC(x)              (((x) << 12) & GENMASK(13, 12))
#define DDR_PHY_PLLCR_PLLCR_CPIC_M               GENMASK(13, 12)
#define DDR_PHY_PLLCR_PLLCR_CPIC_X(x)            (((x) & GENMASK(13, 12)) >> 12)

#define DDR_PHY_PLLCR_PLLCR_CPPC(x)              (((x) << 14) & GENMASK(17, 14))
#define DDR_PHY_PLLCR_PLLCR_CPPC_M               GENMASK(17, 14)
#define DDR_PHY_PLLCR_PLLCR_CPPC_X(x)            (((x) & GENMASK(17, 14)) >> 14)

#define DDR_PHY_PLLCR_RGSHIFT(x)                 (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_PLLCR_RGSHIFT_M                  GENMASK(18, 18)
#define DDR_PHY_PLLCR_RGSHIFT_X(x)               (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_PLLCR_PLLCR_FRQSEL(x)            (((x) << 19) & GENMASK(20, 19))
#define DDR_PHY_PLLCR_PLLCR_FRQSEL_M             GENMASK(20, 19)
#define DDR_PHY_PLLCR_PLLCR_FRQSEL_X(x)          (((x) & GENMASK(20, 19)) >> 19)

#define DDR_PHY_PLLCR_RGVINT(x)                  (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_PLLCR_RGVINT_M                   GENMASK(21, 21)
#define DDR_PHY_PLLCR_RGVINT_X(x)                (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_PLLCR_PLLCR_LOCKDS(x)            (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_PLLCR_PLLCR_LOCKDS_M             GENMASK(22, 22)
#define DDR_PHY_PLLCR_PLLCR_LOCKDS_X(x)          (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_PLLCR_PLLCR_LOCKCS(x)            (((x) << 23) & GENMASK(23, 23))
#define DDR_PHY_PLLCR_PLLCR_LOCKCS_M             GENMASK(23, 23)
#define DDR_PHY_PLLCR_PLLCR_LOCKCS_X(x)          (((x) & GENMASK(23, 23)) >> 23)

#define DDR_PHY_PLLCR_PLLCR_LOCKPS(x)            (((x) << 24) & GENMASK(24, 24))
#define DDR_PHY_PLLCR_PLLCR_LOCKPS_M             GENMASK(24, 24)
#define DDR_PHY_PLLCR_PLLCR_LOCKPS_X(x)          (((x) & GENMASK(24, 24)) >> 24)

#define DDR_PHY_PLLCR_PLLCR_RESERVED_28_25(x)    (((x) << 25) & GENMASK(28, 25))
#define DDR_PHY_PLLCR_PLLCR_RESERVED_28_25_M     GENMASK(28, 25)
#define DDR_PHY_PLLCR_PLLCR_RESERVED_28_25_X(x)  (((x) & GENMASK(28, 25)) >> 25)

#define DDR_PHY_PLLCR_PLLCR_PLLPD(x)             (((x) << 29) & GENMASK(29, 29))
#define DDR_PHY_PLLCR_PLLCR_PLLPD_M              GENMASK(29, 29)
#define DDR_PHY_PLLCR_PLLCR_PLLPD_X(x)           (((x) & GENMASK(29, 29)) >> 29)

#define DDR_PHY_PLLCR_PLLCR_PLLRST(x)            (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_PLLCR_PLLCR_PLLRST_M             GENMASK(30, 30)
#define DDR_PHY_PLLCR_PLLCR_PLLRST_X(x)          (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_PLLCR_PLLCR_PLLBYP(x)            (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_PLLCR_PLLCR_PLLBYP_M             GENMASK(31, 31)
#define DDR_PHY_PLLCR_PLLCR_PLLBYP_X(x)          (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DXCCR */
#define DDR_PHY_DXCCR(t)          (t + 0x88)

#define DDR_PHY_DXCCR_DXODT(x)                   ((x) & GENMASK(0, 0))
#define DDR_PHY_DXCCR_DXODT_M                    GENMASK(0, 0)
#define DDR_PHY_DXCCR_DXODT_X(x)                 ((x) & GENMASK(0, 0))

#define DDR_PHY_DXCCR_DXCCR_DXIOM(x)             (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DXCCR_DXCCR_DXIOM_M              GENMASK(1, 1)
#define DDR_PHY_DXCCR_DXCCR_DXIOM_X(x)           (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DXCCR_DXCCR_MDLEN(x)             (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DXCCR_DXCCR_MDLEN_M              GENMASK(2, 2)
#define DDR_PHY_DXCCR_DXCCR_MDLEN_X(x)           (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DXCCR_DQSGLB(x)                  (((x) << 3) & GENMASK(4, 3))
#define DDR_PHY_DXCCR_DQSGLB_M                   GENMASK(4, 3)
#define DDR_PHY_DXCCR_DQSGLB_X(x)                (((x) & GENMASK(4, 3)) >> 3)

#define DDR_PHY_DXCCR_DQSRES(x)                  (((x) << 5) & GENMASK(8, 5))
#define DDR_PHY_DXCCR_DQSRES_M                   GENMASK(8, 5)
#define DDR_PHY_DXCCR_DQSRES_X(x)                (((x) & GENMASK(8, 5)) >> 5)

#define DDR_PHY_DXCCR_DQSNRES(x)                 (((x) << 9) & GENMASK(12, 9))
#define DDR_PHY_DXCCR_DQSNRES_M                  GENMASK(12, 9)
#define DDR_PHY_DXCCR_DQSNRES_X(x)               (((x) & GENMASK(12, 9)) >> 9)

#define DDR_PHY_DXCCR_DXSR(x)                    (((x) << 13) & GENMASK(14, 13))
#define DDR_PHY_DXCCR_DXSR_M                     GENMASK(14, 13)
#define DDR_PHY_DXCCR_DXSR_X(x)                  (((x) & GENMASK(14, 13)) >> 13)

#define DDR_PHY_DXCCR_MSBUDQ(x)                  (((x) << 15) & GENMASK(17, 15))
#define DDR_PHY_DXCCR_MSBUDQ_M                   GENMASK(17, 15)
#define DDR_PHY_DXCCR_MSBUDQ_X(x)                (((x) & GENMASK(17, 15)) >> 15)

#define DDR_PHY_DXCCR_DXCCR_RESERVED_19_18(x)    (((x) << 18) & GENMASK(19, 18))
#define DDR_PHY_DXCCR_DXCCR_RESERVED_19_18_M     GENMASK(19, 18)
#define DDR_PHY_DXCCR_DXCCR_RESERVED_19_18_X(x)  (((x) & GENMASK(19, 18)) >> 18)

#define DDR_PHY_DXCCR_QSCNTENCTL(x)              (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DXCCR_QSCNTENCTL_M               GENMASK(20, 20)
#define DDR_PHY_DXCCR_QSCNTENCTL_X(x)            (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DXCCR_UDQIOM(x)                  (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DXCCR_UDQIOM_M                   GENMASK(21, 21)
#define DDR_PHY_DXCCR_UDQIOM_X(x)                (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DXCCR_QSCNTEN(x)                 (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DXCCR_QSCNTEN_M                  GENMASK(22, 22)
#define DDR_PHY_DXCCR_QSCNTEN_X(x)               (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DXCCR_DXDCCBYP(x)                (((x) << 23) & GENMASK(23, 23))
#define DDR_PHY_DXCCR_DXDCCBYP_M                 GENMASK(23, 23)
#define DDR_PHY_DXCCR_DXDCCBYP_X(x)              (((x) & GENMASK(23, 23)) >> 23)

#define DDR_PHY_DXCCR_RESERVED_28_24(x)          (((x) << 24) & GENMASK(28, 24))
#define DDR_PHY_DXCCR_RESERVED_28_24_M           GENMASK(28, 24)
#define DDR_PHY_DXCCR_RESERVED_28_24_X(x)        (((x) & GENMASK(28, 24)) >> 24)

#define DDR_PHY_DXCCR_RKLOOP(x)                  (((x) << 29) & GENMASK(29, 29))
#define DDR_PHY_DXCCR_RKLOOP_M                   GENMASK(29, 29)
#define DDR_PHY_DXCCR_RKLOOP_X(x)                (((x) & GENMASK(29, 29)) >> 29)

#define DDR_PHY_DXCCR_X4DQSMD(x)                 (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DXCCR_X4DQSMD_M                  GENMASK(30, 30)
#define DDR_PHY_DXCCR_X4DQSMD_X(x)               (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DXCCR_X4MODE(x)                  (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DXCCR_X4MODE_M                   GENMASK(31, 31)
#define DDR_PHY_DXCCR_X4MODE_X(x)                (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DSGCR */
#define DDR_PHY_DSGCR(t)          (t + 0x90)

#define DDR_PHY_DSGCR_PUREN(x)                   ((x) & GENMASK(0, 0))
#define DDR_PHY_DSGCR_PUREN_M                    GENMASK(0, 0)
#define DDR_PHY_DSGCR_PUREN_X(x)                 ((x) & GENMASK(0, 0))

#define DDR_PHY_DSGCR_BDISEN(x)                  (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DSGCR_BDISEN_M                   GENMASK(1, 1)
#define DDR_PHY_DSGCR_BDISEN_X(x)                (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DSGCR_CTLZUEN(x)                 (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DSGCR_CTLZUEN_M                  GENMASK(2, 2)
#define DDR_PHY_DSGCR_CTLZUEN_X(x)               (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DSGCR_LPIOPD(x)                  (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DSGCR_LPIOPD_M                   GENMASK(3, 3)
#define DDR_PHY_DSGCR_LPIOPD_X(x)                (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DSGCR_LPPLLPD(x)                 (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DSGCR_LPPLLPD_M                  GENMASK(4, 4)
#define DDR_PHY_DSGCR_LPPLLPD_X(x)               (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DSGCR_CUAEN(x)                   (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DSGCR_CUAEN_M                    GENMASK(5, 5)
#define DDR_PHY_DSGCR_CUAEN_X(x)                 (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DSGCR_DQSGX(x)                   (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DSGCR_DQSGX_M                    GENMASK(7, 6)
#define DDR_PHY_DSGCR_DQSGX_X(x)                 (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DSGCR_PUAD(x)                    (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DSGCR_PUAD_M                     GENMASK(11, 8)
#define DDR_PHY_DSGCR_PUAD_X(x)                  (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DSGCR_DTOODT(x)                  (((x) << 12) & GENMASK(12, 12))
#define DDR_PHY_DSGCR_DTOODT_M                   GENMASK(12, 12)
#define DDR_PHY_DSGCR_DTOODT_X(x)                (((x) & GENMASK(12, 12)) >> 12)

#define DDR_PHY_DSGCR_RESERVED_13(x)             (((x) << 13) & GENMASK(13, 13))
#define DDR_PHY_DSGCR_RESERVED_13_M              GENMASK(13, 13)
#define DDR_PHY_DSGCR_RESERVED_13_X(x)           (((x) & GENMASK(13, 13)) >> 13)

#define DDR_PHY_DSGCR_DTOPDR(x)                  (((x) << 14) & GENMASK(14, 14))
#define DDR_PHY_DSGCR_DTOPDR_M                   GENMASK(14, 14)
#define DDR_PHY_DSGCR_DTOPDR_X(x)                (((x) & GENMASK(14, 14)) >> 14)

#define DDR_PHY_DSGCR_DTOIOM(x)                  (((x) << 15) & GENMASK(15, 15))
#define DDR_PHY_DSGCR_DTOIOM_M                   GENMASK(15, 15)
#define DDR_PHY_DSGCR_DTOIOM_X(x)                (((x) & GENMASK(15, 15)) >> 15)

#define DDR_PHY_DSGCR_DTOOE(x)                   (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DSGCR_DTOOE_M                    GENMASK(16, 16)
#define DDR_PHY_DSGCR_DTOOE_X(x)                 (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DSGCR_ATOAE(x)                   (((x) << 17) & GENMASK(17, 17))
#define DDR_PHY_DSGCR_ATOAE_M                    GENMASK(17, 17)
#define DDR_PHY_DSGCR_ATOAE_X(x)                 (((x) & GENMASK(17, 17)) >> 17)

#define DDR_PHY_DSGCR_WRRMODE(x)                 (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_DSGCR_WRRMODE_M                  GENMASK(18, 18)
#define DDR_PHY_DSGCR_WRRMODE_X(x)               (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_DSGCR_SDRMODE(x)                 (((x) << 19) & GENMASK(20, 19))
#define DDR_PHY_DSGCR_SDRMODE_M                  GENMASK(20, 19)
#define DDR_PHY_DSGCR_SDRMODE_X(x)               (((x) & GENMASK(20, 19)) >> 19)

#define DDR_PHY_DSGCR_RSTOE(x)                   (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DSGCR_RSTOE_M                    GENMASK(21, 21)
#define DDR_PHY_DSGCR_RSTOE_X(x)                 (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DSGCR_RRRMODE(x)                 (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DSGCR_RRRMODE_M                  GENMASK(22, 22)
#define DDR_PHY_DSGCR_RRRMODE_X(x)               (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DSGCR_PHYZUEN(x)                 (((x) << 23) & GENMASK(23, 23))
#define DDR_PHY_DSGCR_PHYZUEN_M                  GENMASK(23, 23)
#define DDR_PHY_DSGCR_PHYZUEN_X(x)               (((x) & GENMASK(23, 23)) >> 23)

#define DDR_PHY_DSGCR_LPACIOPD(x)                (((x) << 24) & GENMASK(24, 24))
#define DDR_PHY_DSGCR_LPACIOPD_M                 GENMASK(24, 24)
#define DDR_PHY_DSGCR_LPACIOPD_X(x)              (((x) & GENMASK(24, 24)) >> 24)

#define DDR_PHY_DSGCR_DSGCR_RESERVED_31_25(x)    (((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DSGCR_DSGCR_RESERVED_31_25_M     GENMASK(31, 25)
#define DDR_PHY_DSGCR_DSGCR_RESERVED_31_25_X(x)  (((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:ODTCR */
#define DDR_PHY_ODTCR(t)          (t + 0x98)

#define DDR_PHY_ODTCR_RDODT(x)                   ((x) & GENMASK(1, 0))
#define DDR_PHY_ODTCR_RDODT_M                    GENMASK(1, 0)
#define DDR_PHY_ODTCR_RDODT_X(x)                 ((x) & GENMASK(1, 0))

#define DDR_PHY_ODTCR_RDODT_RSVD(x)              (((x) << 2) & GENMASK(11, 2))
#define DDR_PHY_ODTCR_RDODT_RSVD_M               GENMASK(11, 2)
#define DDR_PHY_ODTCR_RDODT_RSVD_X(x)            (((x) & GENMASK(11, 2)) >> 2)

#define DDR_PHY_ODTCR_ODTCR_RESERVED_15_12(x)    (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_ODTCR_ODTCR_RESERVED_15_12_M     GENMASK(15, 12)
#define DDR_PHY_ODTCR_ODTCR_RESERVED_15_12_X(x)  (((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_ODTCR_WRODT(x)                   (((x) << 16) & GENMASK(17, 16))
#define DDR_PHY_ODTCR_WRODT_M                    GENMASK(17, 16)
#define DDR_PHY_ODTCR_WRODT_X(x)                 (((x) & GENMASK(17, 16)) >> 16)

#define DDR_PHY_ODTCR_WRODT_RSVD(x)              (((x) << 18) & GENMASK(27, 18))
#define DDR_PHY_ODTCR_WRODT_RSVD_M               GENMASK(27, 18)
#define DDR_PHY_ODTCR_WRODT_RSVD_X(x)            (((x) & GENMASK(27, 18)) >> 18)

#define DDR_PHY_ODTCR_ODTCR_RESERVED_31_28(x)    (((x) << 28) & GENMASK(31, 28))
#define DDR_PHY_ODTCR_ODTCR_RESERVED_31_28_M     GENMASK(31, 28)
#define DDR_PHY_ODTCR_ODTCR_RESERVED_31_28_X(x)  (((x) & GENMASK(31, 28)) >> 28)

/*      DDR_PHY:DWC_DDRPHY_PUB:AACR */
#define DDR_PHY_AACR(t)           (t + 0xa0)

#define DDR_PHY_AACR_AATR(x)                     ((x) & GENMASK(29, 0))
#define DDR_PHY_AACR_AATR_M                      GENMASK(29, 0)
#define DDR_PHY_AACR_AATR_X(x)                   ((x) & GENMASK(29, 0))

#define DDR_PHY_AACR_AAENC(x)                    (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_AACR_AAENC_M                     GENMASK(30, 30)
#define DDR_PHY_AACR_AAENC_X(x)                  (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_AACR_AAOENC(x)                   (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_AACR_AAOENC_M                    GENMASK(31, 31)
#define DDR_PHY_AACR_AAOENC_X(x)                 (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:GPR0 */
#define DDR_PHY_GPR0(t)           (t + 0xc0)

/*      DDR_PHY:DWC_DDRPHY_PUB:GPR1 */
#define DDR_PHY_GPR1(t)           (t + 0xc4)

/*      DDR_PHY:DWC_DDRPHY_PUB:DCR */
#define DDR_PHY_DCR(t)            (t + 0x100)

#define DDR_PHY_DCR_DDRMD(x)                     ((x) & GENMASK(2, 0))
#define DDR_PHY_DCR_DDRMD_M                      GENMASK(2, 0)
#define DDR_PHY_DCR_DDRMD_X(x)                   ((x) & GENMASK(2, 0))

#define DDR_PHY_DCR_DDR8BNK(x)                   (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DCR_DDR8BNK_M                    GENMASK(3, 3)
#define DDR_PHY_DCR_DDR8BNK_X(x)                 (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DCR_PDQ(x)                       (((x) << 4) & GENMASK(6, 4))
#define DDR_PHY_DCR_PDQ_M                        GENMASK(6, 4)
#define DDR_PHY_DCR_PDQ_X(x)                     (((x) & GENMASK(6, 4)) >> 4)

#define DDR_PHY_DCR_MPRDQ(x)                     (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_DCR_MPRDQ_M                      GENMASK(7, 7)
#define DDR_PHY_DCR_MPRDQ_X(x)                   (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_DCR_DDRTYPE(x)                   (((x) << 8) & GENMASK(9, 8))
#define DDR_PHY_DCR_DDRTYPE_M                    GENMASK(9, 8)
#define DDR_PHY_DCR_DDRTYPE_X(x)                 (((x) & GENMASK(9, 8)) >> 8)

#define DDR_PHY_DCR_BYTEMASK(x)                  (((x) << 10) & GENMASK(17, 10))
#define DDR_PHY_DCR_BYTEMASK_M                   GENMASK(17, 10)
#define DDR_PHY_DCR_BYTEMASK_X(x)                (((x) & GENMASK(17, 10)) >> 10)

#define DDR_PHY_DCR_RESERVED_26_18(x)            (((x) << 18) & GENMASK(26, 18))
#define DDR_PHY_DCR_RESERVED_26_18_M             GENMASK(26, 18)
#define DDR_PHY_DCR_RESERVED_26_18_X(x)          (((x) & GENMASK(26, 18)) >> 18)

#define DDR_PHY_DCR_NOSRA(x)                     (((x) << 27) & GENMASK(27, 27))
#define DDR_PHY_DCR_NOSRA_M                      GENMASK(27, 27)
#define DDR_PHY_DCR_NOSRA_X(x)                   (((x) & GENMASK(27, 27)) >> 27)

#define DDR_PHY_DCR_DDR2T(x)                     (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_DCR_DDR2T_M                      GENMASK(28, 28)
#define DDR_PHY_DCR_DDR2T_X(x)                   (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_DCR_UDIMM(x)                     (((x) << 29) & GENMASK(29, 29))
#define DDR_PHY_DCR_UDIMM_M                      GENMASK(29, 29)
#define DDR_PHY_DCR_UDIMM_X(x)                   (((x) & GENMASK(29, 29)) >> 29)

#define DDR_PHY_DCR_UBG(x)                       (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DCR_UBG_M                        GENMASK(30, 30)
#define DDR_PHY_DCR_UBG_X(x)                     (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DCR_DCR_RESERVED_31(x)           (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DCR_DCR_RESERVED_31_M            GENMASK(31, 31)
#define DDR_PHY_DCR_DCR_RESERVED_31_X(x)         (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DTPR0 */
#define DDR_PHY_DTPR0(t)          (t + 0x110)

#define DDR_PHY_DTPR0_TRTP(x)                    ((x) & GENMASK(3, 0))
#define DDR_PHY_DTPR0_TRTP_M                     GENMASK(3, 0)
#define DDR_PHY_DTPR0_TRTP_X(x)                  ((x) & GENMASK(3, 0))

#define DDR_PHY_DTPR0_DTPR0_RESERVED_7_4(x)      (((x) << 4) & GENMASK(7, 4))
#define DDR_PHY_DTPR0_DTPR0_RESERVED_7_4_M       GENMASK(7, 4)
#define DDR_PHY_DTPR0_DTPR0_RESERVED_7_4_X(x)    (((x) & GENMASK(7, 4)) >> 4)

#define DDR_PHY_DTPR0_TRP(x)                     (((x) << 8) & GENMASK(14, 8))
#define DDR_PHY_DTPR0_TRP_M                      GENMASK(14, 8)
#define DDR_PHY_DTPR0_TRP_X(x)                   (((x) & GENMASK(14, 8)) >> 8)

#define DDR_PHY_DTPR0_DTPR0_RESERVED_15(x)       (((x) << 15) & GENMASK(15, 15))
#define DDR_PHY_DTPR0_DTPR0_RESERVED_15_M        GENMASK(15, 15)
#define DDR_PHY_DTPR0_DTPR0_RESERVED_15_X(x)     (((x) & GENMASK(15, 15)) >> 15)

#define DDR_PHY_DTPR0_TRAS(x)                    (((x) << 16) & GENMASK(22, 16))
#define DDR_PHY_DTPR0_TRAS_M                     GENMASK(22, 16)
#define DDR_PHY_DTPR0_TRAS_X(x)                  (((x) & GENMASK(22, 16)) >> 16)

#define DDR_PHY_DTPR0_DTPR0_RESERVED_23(x)       (((x) << 23) & GENMASK(23, 23))
#define DDR_PHY_DTPR0_DTPR0_RESERVED_23_M        GENMASK(23, 23)
#define DDR_PHY_DTPR0_DTPR0_RESERVED_23_X(x)     (((x) & GENMASK(23, 23)) >> 23)

#define DDR_PHY_DTPR0_TRRD(x)                    (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DTPR0_TRRD_M                     GENMASK(29, 24)
#define DDR_PHY_DTPR0_TRRD_X(x)                  (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DTPR0_DTPR0_RESERVED_31_30(x)    (((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DTPR0_DTPR0_RESERVED_31_30_M     GENMASK(31, 30)
#define DDR_PHY_DTPR0_DTPR0_RESERVED_31_30_X(x)  (((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DTPR1 */
#define DDR_PHY_DTPR1(t)          (t + 0x114)

#define DDR_PHY_DTPR1_TMRD(x)                    ((x) & GENMASK(4, 0))
#define DDR_PHY_DTPR1_TMRD_M                     GENMASK(4, 0)
#define DDR_PHY_DTPR1_TMRD_X(x)                  ((x) & GENMASK(4, 0))

#define DDR_PHY_DTPR1_DTPR1_RESERVED_7_5(x)      (((x) << 5) & GENMASK(7, 5))
#define DDR_PHY_DTPR1_DTPR1_RESERVED_7_5_M       GENMASK(7, 5)
#define DDR_PHY_DTPR1_DTPR1_RESERVED_7_5_X(x)    (((x) & GENMASK(7, 5)) >> 5)

#define DDR_PHY_DTPR1_TMOD(x)                    (((x) << 8) & GENMASK(10, 8))
#define DDR_PHY_DTPR1_TMOD_M                     GENMASK(10, 8)
#define DDR_PHY_DTPR1_TMOD_X(x)                  (((x) & GENMASK(10, 8)) >> 8)

#define DDR_PHY_DTPR1_DTPR1_RESERVED_15_11(x)    (((x) << 11) & GENMASK(15, 11))
#define DDR_PHY_DTPR1_DTPR1_RESERVED_15_11_M     GENMASK(15, 11)
#define DDR_PHY_DTPR1_DTPR1_RESERVED_15_11_X(x)  (((x) & GENMASK(15, 11)) >> 11)

#define DDR_PHY_DTPR1_TFAW(x)                    (((x) << 16) & GENMASK(23, 16))
#define DDR_PHY_DTPR1_TFAW_M                     GENMASK(23, 16)
#define DDR_PHY_DTPR1_TFAW_X(x)                  (((x) & GENMASK(23, 16)) >> 16)

#define DDR_PHY_DTPR1_TWLMRD(x)                  (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DTPR1_TWLMRD_M                   GENMASK(29, 24)
#define DDR_PHY_DTPR1_TWLMRD_X(x)                (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DTPR1_DTPR1_RESERVED_31_30(x)    (((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DTPR1_DTPR1_RESERVED_31_30_M     GENMASK(31, 30)
#define DDR_PHY_DTPR1_DTPR1_RESERVED_31_30_X(x)  (((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DTPR2 */
#define DDR_PHY_DTPR2(t)          (t + 0x118)

#define DDR_PHY_DTPR2_TXS(x)                     ((x) & GENMASK(9, 0))
#define DDR_PHY_DTPR2_TXS_M                      GENMASK(9, 0)
#define DDR_PHY_DTPR2_TXS_X(x)                   ((x) & GENMASK(9, 0))

#define DDR_PHY_DTPR2_RESERVED_15_10(x)          (((x) << 10) & GENMASK(15, 10))
#define DDR_PHY_DTPR2_RESERVED_15_10_M           GENMASK(15, 10)
#define DDR_PHY_DTPR2_RESERVED_15_10_X(x)        (((x) & GENMASK(15, 10)) >> 10)

#define DDR_PHY_DTPR2_TCKE(x)                    (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DTPR2_TCKE_M                     GENMASK(19, 16)
#define DDR_PHY_DTPR2_TCKE_X(x)                  (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DTPR2_RESERVED_23_20(x)          (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DTPR2_RESERVED_23_20_M           GENMASK(23, 20)
#define DDR_PHY_DTPR2_RESERVED_23_20_X(x)        (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DTPR2_TRTODT(x)                  (((x) << 24) & GENMASK(24, 24))
#define DDR_PHY_DTPR2_TRTODT_M                   GENMASK(24, 24)
#define DDR_PHY_DTPR2_TRTODT_X(x)                (((x) & GENMASK(24, 24)) >> 24)

#define DDR_PHY_DTPR2_RESERVED_27_25(x)          (((x) << 25) & GENMASK(27, 25))
#define DDR_PHY_DTPR2_RESERVED_27_25_M           GENMASK(27, 25)
#define DDR_PHY_DTPR2_RESERVED_27_25_X(x)        (((x) & GENMASK(27, 25)) >> 25)

#define DDR_PHY_DTPR2_TRTW(x)                    (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_DTPR2_TRTW_M                     GENMASK(28, 28)
#define DDR_PHY_DTPR2_TRTW_X(x)                  (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_DTPR2_DTPR2_RESERVED_31_29(x)    (((x) << 29) & GENMASK(31, 29))
#define DDR_PHY_DTPR2_DTPR2_RESERVED_31_29_M     GENMASK(31, 29)
#define DDR_PHY_DTPR2_DTPR2_RESERVED_31_29_X(x)  (((x) & GENMASK(31, 29)) >> 29)

/*      DDR_PHY:DWC_DDRPHY_PUB:DTPR3 */
#define DDR_PHY_DTPR3(t)          (t + 0x11c)

#define DDR_PHY_DTPR3_TDQSCK(x)                  ((x) & GENMASK(2, 0))
#define DDR_PHY_DTPR3_TDQSCK_M                   GENMASK(2, 0)
#define DDR_PHY_DTPR3_TDQSCK_X(x)                ((x) & GENMASK(2, 0))

#define DDR_PHY_DTPR3_DTPR3_RESERVED_7_3(x)      (((x) << 3) & GENMASK(7, 3))
#define DDR_PHY_DTPR3_DTPR3_RESERVED_7_3_M       GENMASK(7, 3)
#define DDR_PHY_DTPR3_DTPR3_RESERVED_7_3_X(x)    (((x) & GENMASK(7, 3)) >> 3)

#define DDR_PHY_DTPR3_TDQSCKMAX(x)               (((x) << 8) & GENMASK(10, 8))
#define DDR_PHY_DTPR3_TDQSCKMAX_M                GENMASK(10, 8)
#define DDR_PHY_DTPR3_TDQSCKMAX_X(x)             (((x) & GENMASK(10, 8)) >> 8)

#define DDR_PHY_DTPR3_DTPR3_RESERVED_15_11(x)    (((x) << 11) & GENMASK(15, 11))
#define DDR_PHY_DTPR3_DTPR3_RESERVED_15_11_M     GENMASK(15, 11)
#define DDR_PHY_DTPR3_DTPR3_RESERVED_15_11_X(x)  (((x) & GENMASK(15, 11)) >> 11)

#define DDR_PHY_DTPR3_TDLLK(x)                   (((x) << 16) & GENMASK(25, 16))
#define DDR_PHY_DTPR3_TDLLK_M                    GENMASK(25, 16)
#define DDR_PHY_DTPR3_TDLLK_X(x)                 (((x) & GENMASK(25, 16)) >> 16)

#define DDR_PHY_DTPR3_TCCD(x)                    (((x) << 26) & GENMASK(28, 26))
#define DDR_PHY_DTPR3_TCCD_M                     GENMASK(28, 26)
#define DDR_PHY_DTPR3_TCCD_X(x)                  (((x) & GENMASK(28, 26)) >> 26)

#define DDR_PHY_DTPR3_TOFDX(x)                   (((x) << 29) & GENMASK(31, 29))
#define DDR_PHY_DTPR3_TOFDX_M                    GENMASK(31, 29)
#define DDR_PHY_DTPR3_TOFDX_X(x)                 (((x) & GENMASK(31, 29)) >> 29)

/*      DDR_PHY:DWC_DDRPHY_PUB:DTPR4 */
#define DDR_PHY_DTPR4(t)          (t + 0x120)

#define DDR_PHY_DTPR4_TXP(x)                     ((x) & GENMASK(4, 0))
#define DDR_PHY_DTPR4_TXP_M                      GENMASK(4, 0)
#define DDR_PHY_DTPR4_TXP_X(x)                   ((x) & GENMASK(4, 0))

#define DDR_PHY_DTPR4_DTPR4_RESERVED_7_5(x)      (((x) << 5) & GENMASK(7, 5))
#define DDR_PHY_DTPR4_DTPR4_RESERVED_7_5_M       GENMASK(7, 5)
#define DDR_PHY_DTPR4_DTPR4_RESERVED_7_5_X(x)    (((x) & GENMASK(7, 5)) >> 5)

#define DDR_PHY_DTPR4_TWLO(x)                    (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DTPR4_TWLO_M                     GENMASK(11, 8)
#define DDR_PHY_DTPR4_TWLO_X(x)                  (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DTPR4_DTPR4_RESERVED_15_12(x)    (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_DTPR4_DTPR4_RESERVED_15_12_M     GENMASK(15, 12)
#define DDR_PHY_DTPR4_DTPR4_RESERVED_15_12_X(x)  (((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_DTPR4_TRFC(x)                    (((x) << 16) & GENMASK(25, 16))
#define DDR_PHY_DTPR4_TRFC_M                     GENMASK(25, 16)
#define DDR_PHY_DTPR4_TRFC_X(x)                  (((x) & GENMASK(25, 16)) >> 16)

#define DDR_PHY_DTPR4_DTPR4_RESERVED_27_26(x)    (((x) << 26) & GENMASK(27, 26))
#define DDR_PHY_DTPR4_DTPR4_RESERVED_27_26_M     GENMASK(27, 26)
#define DDR_PHY_DTPR4_DTPR4_RESERVED_27_26_X(x)  (((x) & GENMASK(27, 26)) >> 26)

#define DDR_PHY_DTPR4_TAOND_TAOFD(x)             (((x) << 28) & GENMASK(29, 28))
#define DDR_PHY_DTPR4_TAOND_TAOFD_M              GENMASK(29, 28)
#define DDR_PHY_DTPR4_TAOND_TAOFD_X(x)           (((x) & GENMASK(29, 28)) >> 28)

#define DDR_PHY_DTPR4_DTPR4_RESERVED_31_30(x)    (((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DTPR4_DTPR4_RESERVED_31_30_M     GENMASK(31, 30)
#define DDR_PHY_DTPR4_DTPR4_RESERVED_31_30_X(x)  (((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DTPR5 */
#define DDR_PHY_DTPR5(t)          (t + 0x124)

#define DDR_PHY_DTPR5_TWTR(x)                    ((x) & GENMASK(4, 0))
#define DDR_PHY_DTPR5_TWTR_M                     GENMASK(4, 0)
#define DDR_PHY_DTPR5_TWTR_X(x)                  ((x) & GENMASK(4, 0))

#define DDR_PHY_DTPR5_DTPR5_RESERVED_7_5(x)      (((x) << 5) & GENMASK(7, 5))
#define DDR_PHY_DTPR5_DTPR5_RESERVED_7_5_M       GENMASK(7, 5)
#define DDR_PHY_DTPR5_DTPR5_RESERVED_7_5_X(x)    (((x) & GENMASK(7, 5)) >> 5)

#define DDR_PHY_DTPR5_TRCD(x)                    (((x) << 8) & GENMASK(14, 8))
#define DDR_PHY_DTPR5_TRCD_M                     GENMASK(14, 8)
#define DDR_PHY_DTPR5_TRCD_X(x)                  (((x) & GENMASK(14, 8)) >> 8)

#define DDR_PHY_DTPR5_DTPR5_RESERVED_15(x)       (((x) << 15) & GENMASK(15, 15))
#define DDR_PHY_DTPR5_DTPR5_RESERVED_15_M        GENMASK(15, 15)
#define DDR_PHY_DTPR5_DTPR5_RESERVED_15_X(x)     (((x) & GENMASK(15, 15)) >> 15)

#define DDR_PHY_DTPR5_TRC(x)                     (((x) << 16) & GENMASK(23, 16))
#define DDR_PHY_DTPR5_TRC_M                      GENMASK(23, 16)
#define DDR_PHY_DTPR5_TRC_X(x)                   (((x) & GENMASK(23, 16)) >> 16)

#define DDR_PHY_DTPR5_DTPR5_RESERVED_31_24(x)    (((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_DTPR5_DTPR5_RESERVED_31_24_M     GENMASK(31, 24)
#define DDR_PHY_DTPR5_DTPR5_RESERVED_31_24_X(x)  (((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:DTPR6 */
#define DDR_PHY_DTPR6(t)          (t + 0x128)

#define DDR_PHY_DTPR6_PUBRL(x)                   ((x) & GENMASK(5, 0))
#define DDR_PHY_DTPR6_PUBRL_M                    GENMASK(5, 0)
#define DDR_PHY_DTPR6_PUBRL_X(x)                 ((x) & GENMASK(5, 0))

#define DDR_PHY_DTPR6_DTPR6_RESERVED_7_6(x)      (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DTPR6_DTPR6_RESERVED_7_6_M       GENMASK(7, 6)
#define DDR_PHY_DTPR6_DTPR6_RESERVED_7_6_X(x)    (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DTPR6_PUBWL(x)                   (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DTPR6_PUBWL_M                    GENMASK(13, 8)
#define DDR_PHY_DTPR6_PUBWL_X(x)                 (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DTPR6_RESERVED_29_14(x)          (((x) << 14) & GENMASK(29, 14))
#define DDR_PHY_DTPR6_RESERVED_29_14_M           GENMASK(29, 14)
#define DDR_PHY_DTPR6_RESERVED_29_14_X(x)        (((x) & GENMASK(29, 14)) >> 14)

#define DDR_PHY_DTPR6_PUBRLEN(x)                 (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DTPR6_PUBRLEN_M                  GENMASK(30, 30)
#define DDR_PHY_DTPR6_PUBRLEN_X(x)               (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DTPR6_PUBWLEN(x)                 (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DTPR6_PUBWLEN_M                  GENMASK(31, 31)
#define DDR_PHY_DTPR6_PUBWLEN_X(x)               (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:RDIMMGCR0 */
#define DDR_PHY_RDIMMGCR0(t)      (t + 0x140)

#define DDR_PHY_RDIMMGCR0_RDIMM(x)               ((x) & GENMASK(0, 0))
#define DDR_PHY_RDIMMGCR0_RDIMM_M                GENMASK(0, 0)
#define DDR_PHY_RDIMMGCR0_RDIMM_X(x)             ((x) & GENMASK(0, 0))

#define DDR_PHY_RDIMMGCR0_ERRNOREG(x)            (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_RDIMMGCR0_ERRNOREG_M             GENMASK(1, 1)
#define DDR_PHY_RDIMMGCR0_ERRNOREG_X(x)          (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_RDIMMGCR0_SOPERR(x)              (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_RDIMMGCR0_SOPERR_M               GENMASK(2, 2)
#define DDR_PHY_RDIMMGCR0_SOPERR_X(x)            (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_RDIMMGCR0_PERRDIS(x)             (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_RDIMMGCR0_PERRDIS_M              GENMASK(3, 3)
#define DDR_PHY_RDIMMGCR0_PERRDIS_X(x)           (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_RDIMMGCR0_RESERVED_13_4(x)       (((x) << 4) & GENMASK(13, 4))
#define DDR_PHY_RDIMMGCR0_RESERVED_13_4_M        GENMASK(13, 4)
#define DDR_PHY_RDIMMGCR0_RESERVED_13_4_X(x)     (((x) & GENMASK(13, 4)) >> 4)

#define DDR_PHY_RDIMMGCR0_PARINODT(x)            (((x) << 14) & GENMASK(14, 14))
#define DDR_PHY_RDIMMGCR0_PARINODT_M             GENMASK(14, 14)
#define DDR_PHY_RDIMMGCR0_PARINODT_X(x)          (((x) & GENMASK(14, 14)) >> 14)

#define DDR_PHY_RDIMMGCR0_RDIMMGCR0_RESERVED_15(x)\
	(((x) << 15) & GENMASK(15, 15))
#define DDR_PHY_RDIMMGCR0_RDIMMGCR0_RESERVED_15_M GENMASK(15, 15)
#define DDR_PHY_RDIMMGCR0_RDIMMGCR0_RESERVED_15_X(x)\
	(((x) & GENMASK(15, 15)) >> 15)

#define DDR_PHY_RDIMMGCR0_PARINPDR(x)            (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_RDIMMGCR0_PARINPDR_M             GENMASK(16, 16)
#define DDR_PHY_RDIMMGCR0_PARINPDR_X(x)          (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_RDIMMGCR0_PARINIOM(x)            (((x) << 17) & GENMASK(17, 17))
#define DDR_PHY_RDIMMGCR0_PARINIOM_M             GENMASK(17, 17)
#define DDR_PHY_RDIMMGCR0_PARINIOM_X(x)          (((x) & GENMASK(17, 17)) >> 17)

#define DDR_PHY_RDIMMGCR0_LRDIMM(x)              (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_RDIMMGCR0_LRDIMM_M               GENMASK(18, 18)
#define DDR_PHY_RDIMMGCR0_LRDIMM_X(x)            (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_RDIMMGCR0_ERROUTODT(x)           (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_RDIMMGCR0_ERROUTODT_M            GENMASK(19, 19)
#define DDR_PHY_RDIMMGCR0_ERROUTODT_X(x)         (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_RDIMMGCR0_RDIMMGCR0_RESERVED_20(x)\
	(((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_RDIMMGCR0_RDIMMGCR0_RESERVED_20_M GENMASK(20, 20)
#define DDR_PHY_RDIMMGCR0_RDIMMGCR0_RESERVED_20_X(x)\
	(((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_RDIMMGCR0_ERROUTPDR(x)           (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_RDIMMGCR0_ERROUTPDR_M            GENMASK(21, 21)
#define DDR_PHY_RDIMMGCR0_ERROUTPDR_X(x)         (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_RDIMMGCR0_ERROUTIOM(x)           (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_RDIMMGCR0_ERROUTIOM_M            GENMASK(22, 22)
#define DDR_PHY_RDIMMGCR0_ERROUTIOM_X(x)         (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_RDIMMGCR0_ERROUTOE(x)            (((x) << 23) & GENMASK(23, 23))
#define DDR_PHY_RDIMMGCR0_ERROUTOE_M             GENMASK(23, 23)
#define DDR_PHY_RDIMMGCR0_ERROUTOE_X(x)          (((x) & GENMASK(23, 23)) >> 23)

#define DDR_PHY_RDIMMGCR0_RDIMMODT(x)            (((x) << 24) & GENMASK(24, 24))
#define DDR_PHY_RDIMMGCR0_RDIMMODT_M             GENMASK(24, 24)
#define DDR_PHY_RDIMMGCR0_RDIMMODT_X(x)          (((x) & GENMASK(24, 24)) >> 24)

#define DDR_PHY_RDIMMGCR0_RESERVED_25(x)         (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_RDIMMGCR0_RESERVED_25_M          GENMASK(25, 25)
#define DDR_PHY_RDIMMGCR0_RESERVED_25_X(x)       (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_RDIMMGCR0_RDIMMPDR(x)            (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_RDIMMGCR0_RDIMMPDR_M             GENMASK(26, 26)
#define DDR_PHY_RDIMMGCR0_RDIMMPDR_X(x)          (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_RDIMMGCR0_RDIMMIOM(x)            (((x) << 27) & GENMASK(27, 27))
#define DDR_PHY_RDIMMGCR0_RDIMMIOM_M             GENMASK(27, 27)
#define DDR_PHY_RDIMMGCR0_RDIMMIOM_X(x)          (((x) & GENMASK(27, 27)) >> 27)

#define DDR_PHY_RDIMMGCR0_QCSENOE(x)             (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_RDIMMGCR0_QCSENOE_M              GENMASK(28, 28)
#define DDR_PHY_RDIMMGCR0_QCSENOE_X(x)           (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_RDIMMGCR0_MIRROROE(x)            (((x) << 29) & GENMASK(29, 29))
#define DDR_PHY_RDIMMGCR0_MIRROROE_M             GENMASK(29, 29)
#define DDR_PHY_RDIMMGCR0_MIRROROE_X(x)          (((x) & GENMASK(29, 29)) >> 29)

#define DDR_PHY_RDIMMGCR0_QCSEN(x)               (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_RDIMMGCR0_QCSEN_M                GENMASK(30, 30)
#define DDR_PHY_RDIMMGCR0_QCSEN_X(x)             (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_RDIMMGCR0_MIRROR(x)              (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_RDIMMGCR0_MIRROR_M               GENMASK(31, 31)
#define DDR_PHY_RDIMMGCR0_MIRROR_X(x)            (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:RDIMMGCR1 */
#define DDR_PHY_RDIMMGCR1(t)      (t + 0x144)

#define DDR_PHY_RDIMMGCR1_TBCSTAB(x)             ((x) & GENMASK(13, 0))
#define DDR_PHY_RDIMMGCR1_TBCSTAB_M              GENMASK(13, 0)
#define DDR_PHY_RDIMMGCR1_TBCSTAB_X(x)           ((x) & GENMASK(13, 0))

#define DDR_PHY_RDIMMGCR1_RDIMMGCR1_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_RDIMMGCR1_RDIMMGCR1_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_RDIMMGCR1_RDIMMGCR1_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_RDIMMGCR1_TBCMRD(x)              (((x) << 16) & GENMASK(18, 16))
#define DDR_PHY_RDIMMGCR1_TBCMRD_M               GENMASK(18, 16)
#define DDR_PHY_RDIMMGCR1_TBCMRD_X(x)            (((x) & GENMASK(18, 16)) >> 16)

#define DDR_PHY_RDIMMGCR1_RDIMMGCR1_RESERVED_19(x)\
	(((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_RDIMMGCR1_RDIMMGCR1_RESERVED_19_M GENMASK(19, 19)
#define DDR_PHY_RDIMMGCR1_RDIMMGCR1_RESERVED_19_X(x)\
	(((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_RDIMMGCR1_TBCMRD_L(x)            (((x) << 20) & GENMASK(22, 20))
#define DDR_PHY_RDIMMGCR1_TBCMRD_L_M             GENMASK(22, 20)
#define DDR_PHY_RDIMMGCR1_TBCMRD_L_X(x)          (((x) & GENMASK(22, 20)) >> 20)

#define DDR_PHY_RDIMMGCR1_RDIMMGCR1_RESERVED_23(x)\
	(((x) << 23) & GENMASK(23, 23))
#define DDR_PHY_RDIMMGCR1_RDIMMGCR1_RESERVED_23_M GENMASK(23, 23)
#define DDR_PHY_RDIMMGCR1_RDIMMGCR1_RESERVED_23_X(x)\
	(((x) & GENMASK(23, 23)) >> 23)

#define DDR_PHY_RDIMMGCR1_TBCMRD_L2(x)           (((x) << 24) & GENMASK(26, 24))
#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_M            GENMASK(26, 24)
#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_X(x)         (((x) & GENMASK(26, 24)) >> 24)

#define DDR_PHY_RDIMMGCR1_RDIMMGCR1_RESERVED_27(x)\
	(((x) << 27) & GENMASK(27, 27))
#define DDR_PHY_RDIMMGCR1_RDIMMGCR1_RESERVED_27_M GENMASK(27, 27)
#define DDR_PHY_RDIMMGCR1_RDIMMGCR1_RESERVED_27_X(x)\
	(((x) & GENMASK(27, 27)) >> 27)

#define DDR_PHY_RDIMMGCR1_A17BID(x)              (((x) << 28) & GENMASK(31, 28))
#define DDR_PHY_RDIMMGCR1_A17BID_M               GENMASK(31, 28)
#define DDR_PHY_RDIMMGCR1_A17BID_X(x)            (((x) & GENMASK(31, 28)) >> 28)

/*      DDR_PHY:DWC_DDRPHY_PUB:RDIMMGCR2 */
#define DDR_PHY_RDIMMGCR2(t)      (t + 0x148)

/*      DDR_PHY:DWC_DDRPHY_PUB:RDIMMCR0 */
#define DDR_PHY_RDIMMCR0(t)       (t + 0x150)

#define DDR_PHY_RDIMMCR0_RDIMMCR0_RC0(x)         ((x) & GENMASK(3, 0))
#define DDR_PHY_RDIMMCR0_RDIMMCR0_RC0_M          GENMASK(3, 0)
#define DDR_PHY_RDIMMCR0_RDIMMCR0_RC0_X(x)       ((x) & GENMASK(3, 0))

#define DDR_PHY_RDIMMCR0_RDIMMCR0_RC1(x)         (((x) << 4) & GENMASK(7, 4))
#define DDR_PHY_RDIMMCR0_RDIMMCR0_RC1_M          GENMASK(7, 4)
#define DDR_PHY_RDIMMCR0_RDIMMCR0_RC1_X(x)       (((x) & GENMASK(7, 4)) >> 4)

#define DDR_PHY_RDIMMCR0_RDIMMCR0_RC2(x)         (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_RDIMMCR0_RDIMMCR0_RC2_M          GENMASK(11, 8)
#define DDR_PHY_RDIMMCR0_RDIMMCR0_RC2_X(x)       (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_RDIMMCR0_RDIMMCR0_RC3(x)         (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_RDIMMCR0_RDIMMCR0_RC3_M          GENMASK(15, 12)
#define DDR_PHY_RDIMMCR0_RDIMMCR0_RC3_X(x)       (((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_RDIMMCR0_RDIMMCR0_RC4(x)         (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_RDIMMCR0_RDIMMCR0_RC4_M          GENMASK(19, 16)
#define DDR_PHY_RDIMMCR0_RDIMMCR0_RC4_X(x)       (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_RDIMMCR0_RDIMMCR0_RC5(x)         (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_RDIMMCR0_RDIMMCR0_RC5_M          GENMASK(23, 20)
#define DDR_PHY_RDIMMCR0_RDIMMCR0_RC5_X(x)       (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_RDIMMCR0_RDIMMCR0_RC6(x)         (((x) << 24) & GENMASK(27, 24))
#define DDR_PHY_RDIMMCR0_RDIMMCR0_RC6_M          GENMASK(27, 24)
#define DDR_PHY_RDIMMCR0_RDIMMCR0_RC6_X(x)       (((x) & GENMASK(27, 24)) >> 24)

#define DDR_PHY_RDIMMCR0_RDIMMCR0_RC7(x)         (((x) << 28) & GENMASK(31, 28))
#define DDR_PHY_RDIMMCR0_RDIMMCR0_RC7_M          GENMASK(31, 28)
#define DDR_PHY_RDIMMCR0_RDIMMCR0_RC7_X(x)       (((x) & GENMASK(31, 28)) >> 28)

/*      DDR_PHY:DWC_DDRPHY_PUB:RDIMMCR0_DDR4 */
#define DDR_PHY_RDIMMCR0_DDR4(t)  (t + 0x150)

#define DDR_PHY_RDIMMCR0_DDR4_RDIMMCR0_DDR4_RC0(x) ((x) & GENMASK(3, 0))
#define DDR_PHY_RDIMMCR0_DDR4_RDIMMCR0_DDR4_RC0_M GENMASK(3, 0)
#define DDR_PHY_RDIMMCR0_DDR4_RDIMMCR0_DDR4_RC0_X(x) ((x) & GENMASK(3, 0))

#define DDR_PHY_RDIMMCR0_DDR4_RDIMMCR0_DDR4_RC1(x) (((x) << 4) & GENMASK(7, 4))
#define DDR_PHY_RDIMMCR0_DDR4_RDIMMCR0_DDR4_RC1_M GENMASK(7, 4)
#define DDR_PHY_RDIMMCR0_DDR4_RDIMMCR0_DDR4_RC1_X(x)\
	(((x) & GENMASK(7, 4)) >> 4)

#define DDR_PHY_RDIMMCR0_DDR4_RDIMMCR0_DDR4_RC2(x) (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_RDIMMCR0_DDR4_RDIMMCR0_DDR4_RC2_M GENMASK(11, 8)
#define DDR_PHY_RDIMMCR0_DDR4_RDIMMCR0_DDR4_RC2_X(x)\
	(((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_RDIMMCR0_DDR4_RDIMMCR0_DDR4_RC3(x)\
	(((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_RDIMMCR0_DDR4_RDIMMCR0_DDR4_RC3_M GENMASK(15, 12)
#define DDR_PHY_RDIMMCR0_DDR4_RDIMMCR0_DDR4_RC3_X(x)\
	(((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_RDIMMCR0_DDR4_RDIMMCR0_DDR4_RC4(x)\
	(((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_RDIMMCR0_DDR4_RDIMMCR0_DDR4_RC4_M GENMASK(19, 16)
#define DDR_PHY_RDIMMCR0_DDR4_RDIMMCR0_DDR4_RC4_X(x)\
	(((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_RDIMMCR0_DDR4_RDIMMCR0_DDR4_RC5(x)\
	(((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_RDIMMCR0_DDR4_RDIMMCR0_DDR4_RC5_M GENMASK(23, 20)
#define DDR_PHY_RDIMMCR0_DDR4_RDIMMCR0_DDR4_RC5_X(x)\
	(((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_RDIMMCR0_DDR4_RDIMMCR0_DDR4_RC6(x)\
	(((x) << 24) & GENMASK(27, 24))
#define DDR_PHY_RDIMMCR0_DDR4_RDIMMCR0_DDR4_RC6_M GENMASK(27, 24)
#define DDR_PHY_RDIMMCR0_DDR4_RDIMMCR0_DDR4_RC6_X(x)\
	(((x) & GENMASK(27, 24)) >> 24)

#define DDR_PHY_RDIMMCR0_DDR4_RDIMMCR0_DDR4_RC7(x)\
	(((x) << 28) & GENMASK(31, 28))
#define DDR_PHY_RDIMMCR0_DDR4_RDIMMCR0_DDR4_RC7_M GENMASK(31, 28)
#define DDR_PHY_RDIMMCR0_DDR4_RDIMMCR0_DDR4_RC7_X(x)\
	(((x) & GENMASK(31, 28)) >> 28)

/*      DDR_PHY:DWC_DDRPHY_PUB:RDIMMCR1 */
#define DDR_PHY_RDIMMCR1(t)       (t + 0x154)

#define DDR_PHY_RDIMMCR1_RDIMMCR1_RC8(x)         ((x) & GENMASK(3, 0))
#define DDR_PHY_RDIMMCR1_RDIMMCR1_RC8_M          GENMASK(3, 0)
#define DDR_PHY_RDIMMCR1_RDIMMCR1_RC8_X(x)       ((x) & GENMASK(3, 0))

#define DDR_PHY_RDIMMCR1_RDIMMCR1_RC9(x)         (((x) << 4) & GENMASK(7, 4))
#define DDR_PHY_RDIMMCR1_RDIMMCR1_RC9_M          GENMASK(7, 4)
#define DDR_PHY_RDIMMCR1_RDIMMCR1_RC9_X(x)       (((x) & GENMASK(7, 4)) >> 4)

#define DDR_PHY_RDIMMCR1_RDIMMCR1_RC10(x)        (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_RDIMMCR1_RDIMMCR1_RC10_M         GENMASK(11, 8)
#define DDR_PHY_RDIMMCR1_RDIMMCR1_RC10_X(x)      (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_RDIMMCR1_RDIMMCR1_RC11(x)        (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_RDIMMCR1_RDIMMCR1_RC11_M         GENMASK(15, 12)
#define DDR_PHY_RDIMMCR1_RDIMMCR1_RC11_X(x)      (((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_RDIMMCR1_RDIMMCR1_RC12(x)        (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_RDIMMCR1_RDIMMCR1_RC12_M         GENMASK(19, 16)
#define DDR_PHY_RDIMMCR1_RDIMMCR1_RC12_X(x)      (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_RDIMMCR1_RDIMMCR1_RC13(x)        (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_RDIMMCR1_RDIMMCR1_RC13_M         GENMASK(23, 20)
#define DDR_PHY_RDIMMCR1_RDIMMCR1_RC13_X(x)      (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_RDIMMCR1_RDIMMCR1_RC14(x)        (((x) << 24) & GENMASK(27, 24))
#define DDR_PHY_RDIMMCR1_RDIMMCR1_RC14_M         GENMASK(27, 24)
#define DDR_PHY_RDIMMCR1_RDIMMCR1_RC14_X(x)      (((x) & GENMASK(27, 24)) >> 24)

#define DDR_PHY_RDIMMCR1_RDIMMCR1_RC15(x)        (((x) << 28) & GENMASK(31, 28))
#define DDR_PHY_RDIMMCR1_RDIMMCR1_RC15_M         GENMASK(31, 28)
#define DDR_PHY_RDIMMCR1_RDIMMCR1_RC15_X(x)      (((x) & GENMASK(31, 28)) >> 28)

/*      DDR_PHY:DWC_DDRPHY_PUB:RDIMMCR1_DDR4 */
#define DDR_PHY_RDIMMCR1_DDR4(t)  (t + 0x154)

#define DDR_PHY_RDIMMCR1_DDR4_RDIMMCR1_DDR4_RC8(x) ((x) & GENMASK(3, 0))
#define DDR_PHY_RDIMMCR1_DDR4_RDIMMCR1_DDR4_RC8_M GENMASK(3, 0)
#define DDR_PHY_RDIMMCR1_DDR4_RDIMMCR1_DDR4_RC8_X(x) ((x) & GENMASK(3, 0))

#define DDR_PHY_RDIMMCR1_DDR4_RDIMMCR1_DDR4_RC9(x) (((x) << 4) & GENMASK(7, 4))
#define DDR_PHY_RDIMMCR1_DDR4_RDIMMCR1_DDR4_RC9_M GENMASK(7, 4)
#define DDR_PHY_RDIMMCR1_DDR4_RDIMMCR1_DDR4_RC9_X(x)\
	(((x) & GENMASK(7, 4)) >> 4)

#define DDR_PHY_RDIMMCR1_DDR4_RDIMMCR1_DDR4_RC10(x)\
	(((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_RDIMMCR1_DDR4_RDIMMCR1_DDR4_RC10_M GENMASK(11, 8)
#define DDR_PHY_RDIMMCR1_DDR4_RDIMMCR1_DDR4_RC10_X(x)\
	(((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_RDIMMCR1_DDR4_RDIMMCR1_DDR4_RC11(x)\
	(((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_RDIMMCR1_DDR4_RDIMMCR1_DDR4_RC11_M GENMASK(15, 12)
#define DDR_PHY_RDIMMCR1_DDR4_RDIMMCR1_DDR4_RC11_X(x)\
	(((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_RDIMMCR1_DDR4_RDIMMCR1_DDR4_RC12(x)\
	(((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_RDIMMCR1_DDR4_RDIMMCR1_DDR4_RC12_M GENMASK(19, 16)
#define DDR_PHY_RDIMMCR1_DDR4_RDIMMCR1_DDR4_RC12_X(x)\
	(((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_RDIMMCR1_DDR4_RDIMMCR1_DDR4_RC13(x)\
	(((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_RDIMMCR1_DDR4_RDIMMCR1_DDR4_RC13_M GENMASK(23, 20)
#define DDR_PHY_RDIMMCR1_DDR4_RDIMMCR1_DDR4_RC13_X(x)\
	(((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_RDIMMCR1_DDR4_RDIMMCR1_DDR4_RC14(x)\
	(((x) << 24) & GENMASK(27, 24))
#define DDR_PHY_RDIMMCR1_DDR4_RDIMMCR1_DDR4_RC14_M GENMASK(27, 24)
#define DDR_PHY_RDIMMCR1_DDR4_RDIMMCR1_DDR4_RC14_X(x)\
	(((x) & GENMASK(27, 24)) >> 24)

#define DDR_PHY_RDIMMCR1_DDR4_RDIMMCR1_DDR4_RC15(x)\
	(((x) << 28) & GENMASK(31, 28))
#define DDR_PHY_RDIMMCR1_DDR4_RDIMMCR1_DDR4_RC15_M GENMASK(31, 28)
#define DDR_PHY_RDIMMCR1_DDR4_RDIMMCR1_DDR4_RC15_X(x)\
	(((x) & GENMASK(31, 28)) >> 28)

/*      DDR_PHY:DWC_DDRPHY_PUB:RDIMMCR2 */
#define DDR_PHY_RDIMMCR2(t)       (t + 0x158)

#define DDR_PHY_RDIMMCR2_RC1X(x)                 ((x) & GENMASK(7, 0))
#define DDR_PHY_RDIMMCR2_RC1X_M                  GENMASK(7, 0)
#define DDR_PHY_RDIMMCR2_RC1X_X(x)               ((x) & GENMASK(7, 0))

#define DDR_PHY_RDIMMCR2_RC2X(x)                 (((x) << 8) & GENMASK(15, 8))
#define DDR_PHY_RDIMMCR2_RC2X_M                  GENMASK(15, 8)
#define DDR_PHY_RDIMMCR2_RC2X_X(x)               (((x) & GENMASK(15, 8)) >> 8)

#define DDR_PHY_RDIMMCR2_RC3X(x)                 (((x) << 16) & GENMASK(23, 16))
#define DDR_PHY_RDIMMCR2_RC3X_M                  GENMASK(23, 16)
#define DDR_PHY_RDIMMCR2_RC3X_X(x)               (((x) & GENMASK(23, 16)) >> 16)

#define DDR_PHY_RDIMMCR2_RC4X(x)                 (((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_RDIMMCR2_RC4X_M                  GENMASK(31, 24)
#define DDR_PHY_RDIMMCR2_RC4X_X(x)               (((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:RDIMMCR3 */
#define DDR_PHY_RDIMMCR3(t)       (t + 0x15c)

#define DDR_PHY_RDIMMCR3_RC5X(x)                 ((x) & GENMASK(7, 0))
#define DDR_PHY_RDIMMCR3_RC5X_M                  GENMASK(7, 0)
#define DDR_PHY_RDIMMCR3_RC5X_X(x)               ((x) & GENMASK(7, 0))

#define DDR_PHY_RDIMMCR3_RC6X(x)                 (((x) << 8) & GENMASK(15, 8))
#define DDR_PHY_RDIMMCR3_RC6X_M                  GENMASK(15, 8)
#define DDR_PHY_RDIMMCR3_RC6X_X(x)               (((x) & GENMASK(15, 8)) >> 8)

#define DDR_PHY_RDIMMCR3_RC7X(x)                 (((x) << 16) & GENMASK(23, 16))
#define DDR_PHY_RDIMMCR3_RC7X_M                  GENMASK(23, 16)
#define DDR_PHY_RDIMMCR3_RC7X_X(x)               (((x) & GENMASK(23, 16)) >> 16)

#define DDR_PHY_RDIMMCR3_RC8X(x)                 (((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_RDIMMCR3_RC8X_M                  GENMASK(31, 24)
#define DDR_PHY_RDIMMCR3_RC8X_X(x)               (((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:RDIMMCR4 */
#define DDR_PHY_RDIMMCR4(t)       (t + 0x160)

#define DDR_PHY_RDIMMCR4_RC9X(x)                 ((x) & GENMASK(7, 0))
#define DDR_PHY_RDIMMCR4_RC9X_M                  GENMASK(7, 0)
#define DDR_PHY_RDIMMCR4_RC9X_X(x)               ((x) & GENMASK(7, 0))

#define DDR_PHY_RDIMMCR4_RCAX(x)                 (((x) << 8) & GENMASK(15, 8))
#define DDR_PHY_RDIMMCR4_RCAX_M                  GENMASK(15, 8)
#define DDR_PHY_RDIMMCR4_RCAX_X(x)               (((x) & GENMASK(15, 8)) >> 8)

#define DDR_PHY_RDIMMCR4_RCBX(x)                 (((x) << 16) & GENMASK(23, 16))
#define DDR_PHY_RDIMMCR4_RCBX_M                  GENMASK(23, 16)
#define DDR_PHY_RDIMMCR4_RCBX_X(x)               (((x) & GENMASK(23, 16)) >> 16)

#define DDR_PHY_RDIMMCR4_RCXX(x)                 (((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_RDIMMCR4_RCXX_M                  GENMASK(31, 24)
#define DDR_PHY_RDIMMCR4_RCXX_X(x)               (((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:SCHCR0 */
#define DDR_PHY_SCHCR0(t)         (t + 0x168)

#define DDR_PHY_SCHCR0_SCHTRIG(x)                ((x) & GENMASK(3, 0))
#define DDR_PHY_SCHCR0_SCHTRIG_M                 GENMASK(3, 0)
#define DDR_PHY_SCHCR0_SCHTRIG_X(x)              ((x) & GENMASK(3, 0))

#define DDR_PHY_SCHCR0_CMD(x)                    (((x) << 4) & GENMASK(7, 4))
#define DDR_PHY_SCHCR0_CMD_M                     GENMASK(7, 4)
#define DDR_PHY_SCHCR0_CMD_X(x)                  (((x) & GENMASK(7, 4)) >> 4)

#define DDR_PHY_SCHCR0_SP_CMD(x)                 (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_SCHCR0_SP_CMD_M                  GENMASK(11, 8)
#define DDR_PHY_SCHCR0_SP_CMD_X(x)               (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_SCHCR0_SCHCR0_RESERVED_13_12(x)  (((x) << 12) & GENMASK(13, 12))
#define DDR_PHY_SCHCR0_SCHCR0_RESERVED_13_12_M   GENMASK(13, 12)
#define DDR_PHY_SCHCR0_SCHCR0_RESERVED_13_12_X(x)\
	(((x) & GENMASK(13, 12)) >> 12)

#define DDR_PHY_SCHCR0_SCHDQV(x)                 (((x) << 14) & GENMASK(31, 14))
#define DDR_PHY_SCHCR0_SCHDQV_M                  GENMASK(31, 14)
#define DDR_PHY_SCHCR0_SCHDQV_X(x)               (((x) & GENMASK(31, 14)) >> 14)

/*      DDR_PHY:DWC_DDRPHY_PUB:SCHCR1 */
#define DDR_PHY_SCHCR1(t)         (t + 0x16c)

#define DDR_PHY_SCHCR1_SCHCR1_RESERVED_1_0(x)    ((x) & GENMASK(1, 0))
#define DDR_PHY_SCHCR1_SCHCR1_RESERVED_1_0_M     GENMASK(1, 0)
#define DDR_PHY_SCHCR1_SCHCR1_RESERVED_1_0_X(x)  ((x) & GENMASK(1, 0))

#define DDR_PHY_SCHCR1_ALLRANK(x)                (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_SCHCR1_ALLRANK_M                 GENMASK(2, 2)
#define DDR_PHY_SCHCR1_ALLRANK_X(x)              (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_SCHCR1_SCHCR1_RESERVED_3(x)      (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_SCHCR1_SCHCR1_RESERVED_3_M       GENMASK(3, 3)
#define DDR_PHY_SCHCR1_SCHCR1_RESERVED_3_X(x)    (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_SCHCR1_SCBK(x)                   (((x) << 4) & GENMASK(5, 4))
#define DDR_PHY_SCHCR1_SCBK_M                    GENMASK(5, 4)
#define DDR_PHY_SCHCR1_SCBK_X(x)                 (((x) & GENMASK(5, 4)) >> 4)

#define DDR_PHY_SCHCR1_SCBG(x)                   (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_SCHCR1_SCBG_M                    GENMASK(7, 6)
#define DDR_PHY_SCHCR1_SCBG_X(x)                 (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_SCHCR1_SCADDR(x)                 (((x) << 8) & GENMASK(27, 8))
#define DDR_PHY_SCHCR1_SCADDR_M                  GENMASK(27, 8)
#define DDR_PHY_SCHCR1_SCADDR_X(x)               (((x) & GENMASK(27, 8)) >> 8)

#define DDR_PHY_SCHCR1_SCRNK(x)                  (((x) << 28) & GENMASK(31, 28))
#define DDR_PHY_SCHCR1_SCRNK_M                   GENMASK(31, 28)
#define DDR_PHY_SCHCR1_SCRNK_X(x)                (((x) & GENMASK(31, 28)) >> 28)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR0 */
#define DDR_PHY_MR0(t)            (t + 0x180)

#define DDR_PHY_MR0_MR0_BL(x)                    ((x) & GENMASK(1, 0))
#define DDR_PHY_MR0_MR0_BL_M                     GENMASK(1, 0)
#define DDR_PHY_MR0_MR0_BL_X(x)                  ((x) & GENMASK(1, 0))

#define DDR_PHY_MR0_MR0_CL_2(x)                  (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_MR0_MR0_CL_2_M                   GENMASK(2, 2)
#define DDR_PHY_MR0_MR0_CL_2_X(x)                (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_MR0_MR0_BT(x)                    (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_MR0_MR0_BT_M                     GENMASK(3, 3)
#define DDR_PHY_MR0_MR0_BT_X(x)                  (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_MR0_MR0_CL_6_4(x)                (((x) << 4) & GENMASK(6, 4))
#define DDR_PHY_MR0_MR0_CL_6_4_M                 GENMASK(6, 4)
#define DDR_PHY_MR0_MR0_CL_6_4_X(x)              (((x) & GENMASK(6, 4)) >> 4)

#define DDR_PHY_MR0_MR0_TM(x)                    (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_MR0_MR0_TM_M                     GENMASK(7, 7)
#define DDR_PHY_MR0_MR0_TM_X(x)                  (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_MR0_MR0_DR(x)                    (((x) << 8) & GENMASK(8, 8))
#define DDR_PHY_MR0_MR0_DR_M                     GENMASK(8, 8)
#define DDR_PHY_MR0_MR0_DR_X(x)                  (((x) & GENMASK(8, 8)) >> 8)

#define DDR_PHY_MR0_WR(x)                        (((x) << 9) & GENMASK(11, 9))
#define DDR_PHY_MR0_WR_M                         GENMASK(11, 9)
#define DDR_PHY_MR0_WR_X(x)                      (((x) & GENMASK(11, 9)) >> 9)

#define DDR_PHY_MR0_PD(x)                        (((x) << 12) & GENMASK(12, 12))
#define DDR_PHY_MR0_PD_M                         GENMASK(12, 12)
#define DDR_PHY_MR0_PD_X(x)                      (((x) & GENMASK(12, 12)) >> 12)

#define DDR_PHY_MR0_MR0_RSVD_15_13(x)            (((x) << 13) & GENMASK(15, 13))
#define DDR_PHY_MR0_MR0_RSVD_15_13_M             GENMASK(15, 13)
#define DDR_PHY_MR0_MR0_RSVD_15_13_X(x)          (((x) & GENMASK(15, 13)) >> 13)

#define DDR_PHY_MR0_MR0_RESERVED_31_16(x)        (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR0_MR0_RESERVED_31_16_M         GENMASK(31, 16)
#define DDR_PHY_MR0_MR0_RESERVED_31_16_X(x)      (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR0_DDR4 */
#define DDR_PHY_MR0_DDR4(t)       (t + 0x180)

#define DDR_PHY_MR0_DDR4_MR0_DDR4_BL(x)          ((x) & GENMASK(1, 0))
#define DDR_PHY_MR0_DDR4_MR0_DDR4_BL_M           GENMASK(1, 0)
#define DDR_PHY_MR0_DDR4_MR0_DDR4_BL_X(x)        ((x) & GENMASK(1, 0))

#define DDR_PHY_MR0_DDR4_MR0_DDR4_CL_2(x)        (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_MR0_DDR4_MR0_DDR4_CL_2_M         GENMASK(2, 2)
#define DDR_PHY_MR0_DDR4_MR0_DDR4_CL_2_X(x)      (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_MR0_DDR4_MR0_DDR4_BT(x)          (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_MR0_DDR4_MR0_DDR4_BT_M           GENMASK(3, 3)
#define DDR_PHY_MR0_DDR4_MR0_DDR4_BT_X(x)        (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_MR0_DDR4_MR0_DDR4_CL_6_4(x)      (((x) << 4) & GENMASK(6, 4))
#define DDR_PHY_MR0_DDR4_MR0_DDR4_CL_6_4_M       GENMASK(6, 4)
#define DDR_PHY_MR0_DDR4_MR0_DDR4_CL_6_4_X(x)    (((x) & GENMASK(6, 4)) >> 4)

#define DDR_PHY_MR0_DDR4_MR0_DDR4_TM(x)          (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_MR0_DDR4_MR0_DDR4_TM_M           GENMASK(7, 7)
#define DDR_PHY_MR0_DDR4_MR0_DDR4_TM_X(x)        (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_MR0_DDR4_MR0_DDR4_DR(x)          (((x) << 8) & GENMASK(8, 8))
#define DDR_PHY_MR0_DDR4_MR0_DDR4_DR_M           GENMASK(8, 8)
#define DDR_PHY_MR0_DDR4_MR0_DDR4_DR_X(x)        (((x) & GENMASK(8, 8)) >> 8)

#define DDR_PHY_MR0_DDR4_WR_11_9(x)              (((x) << 9) & GENMASK(11, 9))
#define DDR_PHY_MR0_DDR4_WR_11_9_M               GENMASK(11, 9)
#define DDR_PHY_MR0_DDR4_WR_11_9_X(x)            (((x) & GENMASK(11, 9)) >> 9)

#define DDR_PHY_MR0_DDR4_CL_12(x)                (((x) << 12) & GENMASK(12, 12))
#define DDR_PHY_MR0_DDR4_CL_12_M                 GENMASK(12, 12)
#define DDR_PHY_MR0_DDR4_CL_12_X(x)              (((x) & GENMASK(12, 12)) >> 12)

#define DDR_PHY_MR0_DDR4_WR_13(x)                (((x) << 13) & GENMASK(13, 13))
#define DDR_PHY_MR0_DDR4_WR_13_M                 GENMASK(13, 13)
#define DDR_PHY_MR0_DDR4_WR_13_X(x)              (((x) & GENMASK(13, 13)) >> 13)

#define DDR_PHY_MR0_DDR4_RSVD_15_14(x)           (((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_MR0_DDR4_RSVD_15_14_M            GENMASK(15, 14)
#define DDR_PHY_MR0_DDR4_RSVD_15_14_X(x)         (((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_MR0_DDR4_MR0_DDR4_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR0_DDR4_MR0_DDR4_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_MR0_DDR4_MR0_DDR4_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR0_LPDDR2 */
#define DDR_PHY_MR0_LPDDR2(t)     (t + 0x180)

#define DDR_PHY_MR0_LPDDR2_MR0_LPDDR2_RSVD_15_0(x) ((x) & GENMASK(15, 0))
#define DDR_PHY_MR0_LPDDR2_MR0_LPDDR2_RSVD_15_0_M GENMASK(15, 0)
#define DDR_PHY_MR0_LPDDR2_MR0_LPDDR2_RSVD_15_0_X(x) ((x) & GENMASK(15, 0))

#define DDR_PHY_MR0_LPDDR2_MR0_LPDDR2_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR0_LPDDR2_MR0_LPDDR2_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_MR0_LPDDR2_MR0_LPDDR2_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR0_LPDDR3 */
#define DDR_PHY_MR0_LPDDR3(t)     (t + 0x180)

#define DDR_PHY_MR0_LPDDR3_MR0_LPDDR3_RSVD_15_0(x) ((x) & GENMASK(15, 0))
#define DDR_PHY_MR0_LPDDR3_MR0_LPDDR3_RSVD_15_0_M GENMASK(15, 0)
#define DDR_PHY_MR0_LPDDR3_MR0_LPDDR3_RSVD_15_0_X(x) ((x) & GENMASK(15, 0))

#define DDR_PHY_MR0_LPDDR3_MR0_LPDDR3_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR0_LPDDR3_MR0_LPDDR3_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_MR0_LPDDR3_MR0_LPDDR3_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR1 */
#define DDR_PHY_MR1(t)            (t + 0x184)

#define DDR_PHY_MR1_MR1_DE(x)                    ((x) & GENMASK(0, 0))
#define DDR_PHY_MR1_MR1_DE_M                     GENMASK(0, 0)
#define DDR_PHY_MR1_MR1_DE_X(x)                  ((x) & GENMASK(0, 0))

#define DDR_PHY_MR1_DIC_1(x)                     (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_MR1_DIC_1_M                      GENMASK(1, 1)
#define DDR_PHY_MR1_DIC_1_X(x)                   (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_MR1_RTT_2(x)                     (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_MR1_RTT_2_M                      GENMASK(2, 2)
#define DDR_PHY_MR1_RTT_2_X(x)                   (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_MR1_MR1_AL(x)                    (((x) << 3) & GENMASK(4, 3))
#define DDR_PHY_MR1_MR1_AL_M                     GENMASK(4, 3)
#define DDR_PHY_MR1_MR1_AL_X(x)                  (((x) & GENMASK(4, 3)) >> 3)

#define DDR_PHY_MR1_DIC_5(x)                     (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_MR1_DIC_5_M                      GENMASK(5, 5)
#define DDR_PHY_MR1_DIC_5_X(x)                   (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_MR1_RTT_6(x)                     (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_MR1_RTT_6_M                      GENMASK(6, 6)
#define DDR_PHY_MR1_RTT_6_X(x)                   (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_MR1_MR1_LEVEL(x)                 (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_MR1_MR1_LEVEL_M                  GENMASK(7, 7)
#define DDR_PHY_MR1_MR1_LEVEL_X(x)               (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_MR1_MR1_RSVD_8(x)                (((x) << 8) & GENMASK(8, 8))
#define DDR_PHY_MR1_MR1_RSVD_8_M                 GENMASK(8, 8)
#define DDR_PHY_MR1_MR1_RSVD_8_X(x)              (((x) & GENMASK(8, 8)) >> 8)

#define DDR_PHY_MR1_RTT_9(x)                     (((x) << 9) & GENMASK(9, 9))
#define DDR_PHY_MR1_RTT_9_M                      GENMASK(9, 9)
#define DDR_PHY_MR1_RTT_9_X(x)                   (((x) & GENMASK(9, 9)) >> 9)

#define DDR_PHY_MR1_RSVD_10(x)                   (((x) << 10) & GENMASK(10, 10))
#define DDR_PHY_MR1_RSVD_10_M                    GENMASK(10, 10)
#define DDR_PHY_MR1_RSVD_10_X(x)                 (((x) & GENMASK(10, 10)) >> 10)

#define DDR_PHY_MR1_MR1_TDQS(x)                  (((x) << 11) & GENMASK(11, 11))
#define DDR_PHY_MR1_MR1_TDQS_M                   GENMASK(11, 11)
#define DDR_PHY_MR1_MR1_TDQS_X(x)                (((x) & GENMASK(11, 11)) >> 11)

#define DDR_PHY_MR1_MR1_QOFF(x)                  (((x) << 12) & GENMASK(12, 12))
#define DDR_PHY_MR1_MR1_QOFF_M                   GENMASK(12, 12)
#define DDR_PHY_MR1_MR1_QOFF_X(x)                (((x) & GENMASK(12, 12)) >> 12)

#define DDR_PHY_MR1_MR1_RSVD_15_13(x)            (((x) << 13) & GENMASK(15, 13))
#define DDR_PHY_MR1_MR1_RSVD_15_13_M             GENMASK(15, 13)
#define DDR_PHY_MR1_MR1_RSVD_15_13_X(x)          (((x) & GENMASK(15, 13)) >> 13)

#define DDR_PHY_MR1_MR1_RESERVED_31_16(x)        (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR1_MR1_RESERVED_31_16_M         GENMASK(31, 16)
#define DDR_PHY_MR1_MR1_RESERVED_31_16_X(x)      (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR1_DDR4 */
#define DDR_PHY_MR1_DDR4(t)       (t + 0x184)

#define DDR_PHY_MR1_DDR4_MR1_DDR4_DE(x)          ((x) & GENMASK(0, 0))
#define DDR_PHY_MR1_DDR4_MR1_DDR4_DE_M           GENMASK(0, 0)
#define DDR_PHY_MR1_DDR4_MR1_DDR4_DE_X(x)        ((x) & GENMASK(0, 0))

#define DDR_PHY_MR1_DDR4_DIC(x)                  (((x) << 1) & GENMASK(2, 1))
#define DDR_PHY_MR1_DDR4_DIC_M                   GENMASK(2, 1)
#define DDR_PHY_MR1_DDR4_DIC_X(x)                (((x) & GENMASK(2, 1)) >> 1)

#define DDR_PHY_MR1_DDR4_MR1_DDR4_AL(x)          (((x) << 3) & GENMASK(4, 3))
#define DDR_PHY_MR1_DDR4_MR1_DDR4_AL_M           GENMASK(4, 3)
#define DDR_PHY_MR1_DDR4_MR1_DDR4_AL_X(x)        (((x) & GENMASK(4, 3)) >> 3)

#define DDR_PHY_MR1_DDR4_RSVD_6_5(x)             (((x) << 5) & GENMASK(6, 5))
#define DDR_PHY_MR1_DDR4_RSVD_6_5_M              GENMASK(6, 5)
#define DDR_PHY_MR1_DDR4_RSVD_6_5_X(x)           (((x) & GENMASK(6, 5)) >> 5)

#define DDR_PHY_MR1_DDR4_MR1_DDR4_LEVEL(x)       (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_MR1_DDR4_MR1_DDR4_LEVEL_M        GENMASK(7, 7)
#define DDR_PHY_MR1_DDR4_MR1_DDR4_LEVEL_X(x)     (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_MR1_DDR4_RTT(x)                  (((x) << 8) & GENMASK(10, 8))
#define DDR_PHY_MR1_DDR4_RTT_M                   GENMASK(10, 8)
#define DDR_PHY_MR1_DDR4_RTT_X(x)                (((x) & GENMASK(10, 8)) >> 8)

#define DDR_PHY_MR1_DDR4_MR1_DDR4_TDQS(x)        (((x) << 11) & GENMASK(11, 11))
#define DDR_PHY_MR1_DDR4_MR1_DDR4_TDQS_M         GENMASK(11, 11)
#define DDR_PHY_MR1_DDR4_MR1_DDR4_TDQS_X(x)      (((x) & GENMASK(11, 11)) >> 11)

#define DDR_PHY_MR1_DDR4_MR1_DDR4_QOFF(x)        (((x) << 12) & GENMASK(12, 12))
#define DDR_PHY_MR1_DDR4_MR1_DDR4_QOFF_M         GENMASK(12, 12)
#define DDR_PHY_MR1_DDR4_MR1_DDR4_QOFF_X(x)      (((x) & GENMASK(12, 12)) >> 12)

#define DDR_PHY_MR1_DDR4_MR1_DDR4_RSVD_15_13(x)  (((x) << 13) & GENMASK(15, 13))
#define DDR_PHY_MR1_DDR4_MR1_DDR4_RSVD_15_13_M   GENMASK(15, 13)
#define DDR_PHY_MR1_DDR4_MR1_DDR4_RSVD_15_13_X(x)\
	(((x) & GENMASK(15, 13)) >> 13)

#define DDR_PHY_MR1_DDR4_MR1_DDR4_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR1_DDR4_MR1_DDR4_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_MR1_DDR4_MR1_DDR4_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR1_LPDDR2 */
#define DDR_PHY_MR1_LPDDR2(t)     (t + 0x184)

#define DDR_PHY_MR1_LPDDR2_MR1_LPDDR2_BL(x)      ((x) & GENMASK(2, 0))
#define DDR_PHY_MR1_LPDDR2_MR1_LPDDR2_BL_M       GENMASK(2, 0)
#define DDR_PHY_MR1_LPDDR2_MR1_LPDDR2_BL_X(x)    ((x) & GENMASK(2, 0))

#define DDR_PHY_MR1_LPDDR2_MR1_LPDDR2_BT(x)      (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_MR1_LPDDR2_MR1_LPDDR2_BT_M       GENMASK(3, 3)
#define DDR_PHY_MR1_LPDDR2_MR1_LPDDR2_BT_X(x)    (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_MR1_LPDDR2_MR1_LPDDR2_WC(x)      (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_MR1_LPDDR2_MR1_LPDDR2_WC_M       GENMASK(4, 4)
#define DDR_PHY_MR1_LPDDR2_MR1_LPDDR2_WC_X(x)    (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_MR1_LPDDR2_MR1_LPDDR2_NWR(x)     (((x) << 5) & GENMASK(7, 5))
#define DDR_PHY_MR1_LPDDR2_MR1_LPDDR2_NWR_M      GENMASK(7, 5)
#define DDR_PHY_MR1_LPDDR2_MR1_LPDDR2_NWR_X(x)   (((x) & GENMASK(7, 5)) >> 5)

#define DDR_PHY_MR1_LPDDR2_MR1_LPDDR2_RSVD_15_8(x) (((x) << 8) & GENMASK(15, 8))
#define DDR_PHY_MR1_LPDDR2_MR1_LPDDR2_RSVD_15_8_M GENMASK(15, 8)
#define DDR_PHY_MR1_LPDDR2_MR1_LPDDR2_RSVD_15_8_X(x)\
	(((x) & GENMASK(15, 8)) >> 8)

#define DDR_PHY_MR1_LPDDR2_MR1_LPDDR2_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR1_LPDDR2_MR1_LPDDR2_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_MR1_LPDDR2_MR1_LPDDR2_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR1_LPDDR3 */
#define DDR_PHY_MR1_LPDDR3(t)     (t + 0x184)

#define DDR_PHY_MR1_LPDDR3_MR1_LPDDR3_BL(x)      ((x) & GENMASK(2, 0))
#define DDR_PHY_MR1_LPDDR3_MR1_LPDDR3_BL_M       GENMASK(2, 0)
#define DDR_PHY_MR1_LPDDR3_MR1_LPDDR3_BL_X(x)    ((x) & GENMASK(2, 0))

#define DDR_PHY_MR1_LPDDR3_MR1_LPDDR3_BT(x)      (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_MR1_LPDDR3_MR1_LPDDR3_BT_M       GENMASK(3, 3)
#define DDR_PHY_MR1_LPDDR3_MR1_LPDDR3_BT_X(x)    (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_MR1_LPDDR3_MR1_LPDDR3_WC(x)      (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_MR1_LPDDR3_MR1_LPDDR3_WC_M       GENMASK(4, 4)
#define DDR_PHY_MR1_LPDDR3_MR1_LPDDR3_WC_X(x)    (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_MR1_LPDDR3_MR1_LPDDR3_NWR(x)     (((x) << 5) & GENMASK(7, 5))
#define DDR_PHY_MR1_LPDDR3_MR1_LPDDR3_NWR_M      GENMASK(7, 5)
#define DDR_PHY_MR1_LPDDR3_MR1_LPDDR3_NWR_X(x)   (((x) & GENMASK(7, 5)) >> 5)

#define DDR_PHY_MR1_LPDDR3_MR1_LPDDR3_RSVD_15_8(x) (((x) << 8) & GENMASK(15, 8))
#define DDR_PHY_MR1_LPDDR3_MR1_LPDDR3_RSVD_15_8_M GENMASK(15, 8)
#define DDR_PHY_MR1_LPDDR3_MR1_LPDDR3_RSVD_15_8_X(x)\
	(((x) & GENMASK(15, 8)) >> 8)

#define DDR_PHY_MR1_LPDDR3_MR1_LPDDR3_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR1_LPDDR3_MR1_LPDDR3_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_MR1_LPDDR3_MR1_LPDDR3_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR2 */
#define DDR_PHY_MR2(t)            (t + 0x188)

#define DDR_PHY_MR2_PASR(x)                      ((x) & GENMASK(2, 0))
#define DDR_PHY_MR2_PASR_M                       GENMASK(2, 0)
#define DDR_PHY_MR2_PASR_X(x)                    ((x) & GENMASK(2, 0))

#define DDR_PHY_MR2_MR2_CWL(x)                   (((x) << 3) & GENMASK(5, 3))
#define DDR_PHY_MR2_MR2_CWL_M                    GENMASK(5, 3)
#define DDR_PHY_MR2_MR2_CWL_X(x)                 (((x) & GENMASK(5, 3)) >> 3)

#define DDR_PHY_MR2_ASR(x)                       (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_MR2_ASR_M                        GENMASK(6, 6)
#define DDR_PHY_MR2_ASR_X(x)                     (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_MR2_SRT(x)                       (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_MR2_SRT_M                        GENMASK(7, 7)
#define DDR_PHY_MR2_SRT_X(x)                     (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_MR2_MR2_RSVD_8(x)                (((x) << 8) & GENMASK(8, 8))
#define DDR_PHY_MR2_MR2_RSVD_8_M                 GENMASK(8, 8)
#define DDR_PHY_MR2_MR2_RSVD_8_X(x)              (((x) & GENMASK(8, 8)) >> 8)

#define DDR_PHY_MR2_MR2_RTT_WR(x)                (((x) << 9) & GENMASK(10, 9))
#define DDR_PHY_MR2_MR2_RTT_WR_M                 GENMASK(10, 9)
#define DDR_PHY_MR2_MR2_RTT_WR_X(x)              (((x) & GENMASK(10, 9)) >> 9)

#define DDR_PHY_MR2_RSVD_15_11(x)                (((x) << 11) & GENMASK(15, 11))
#define DDR_PHY_MR2_RSVD_15_11_M                 GENMASK(15, 11)
#define DDR_PHY_MR2_RSVD_15_11_X(x)              (((x) & GENMASK(15, 11)) >> 11)

#define DDR_PHY_MR2_MR2_RESERVED_31_16(x)        (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR2_MR2_RESERVED_31_16_M         GENMASK(31, 16)
#define DDR_PHY_MR2_MR2_RESERVED_31_16_X(x)      (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR2_DDR4 */
#define DDR_PHY_MR2_DDR4(t)       (t + 0x188)

#define DDR_PHY_MR2_DDR4_RSVD_2_0(x)             ((x) & GENMASK(2, 0))
#define DDR_PHY_MR2_DDR4_RSVD_2_0_M              GENMASK(2, 0)
#define DDR_PHY_MR2_DDR4_RSVD_2_0_X(x)           ((x) & GENMASK(2, 0))

#define DDR_PHY_MR2_DDR4_MR2_DDR4_CWL(x)         (((x) << 3) & GENMASK(5, 3))
#define DDR_PHY_MR2_DDR4_MR2_DDR4_CWL_M          GENMASK(5, 3)
#define DDR_PHY_MR2_DDR4_MR2_DDR4_CWL_X(x)       (((x) & GENMASK(5, 3)) >> 3)

#define DDR_PHY_MR2_DDR4_LPASR(x)                (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_MR2_DDR4_LPASR_M                 GENMASK(7, 6)
#define DDR_PHY_MR2_DDR4_LPASR_X(x)              (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_MR2_DDR4_MR2_DDR4_RSVD_8(x)      (((x) << 8) & GENMASK(8, 8))
#define DDR_PHY_MR2_DDR4_MR2_DDR4_RSVD_8_M       GENMASK(8, 8)
#define DDR_PHY_MR2_DDR4_MR2_DDR4_RSVD_8_X(x)    (((x) & GENMASK(8, 8)) >> 8)

#define DDR_PHY_MR2_DDR4_MR2_DDR4_RTT_WR(x)      (((x) << 9) & GENMASK(11, 9))
#define DDR_PHY_MR2_DDR4_MR2_DDR4_RTT_WR_M       GENMASK(11, 9)
#define DDR_PHY_MR2_DDR4_MR2_DDR4_RTT_WR_X(x)    (((x) & GENMASK(11, 9)) >> 9)

#define DDR_PHY_MR2_DDR4_WRCRC(x)                (((x) << 12) & GENMASK(12, 12))
#define DDR_PHY_MR2_DDR4_WRCRC_M                 GENMASK(12, 12)
#define DDR_PHY_MR2_DDR4_WRCRC_X(x)              (((x) & GENMASK(12, 12)) >> 12)

#define DDR_PHY_MR2_DDR4_MR2_DDR4_RSVD_15_13(x)  (((x) << 13) & GENMASK(15, 13))
#define DDR_PHY_MR2_DDR4_MR2_DDR4_RSVD_15_13_M   GENMASK(15, 13)
#define DDR_PHY_MR2_DDR4_MR2_DDR4_RSVD_15_13_X(x)\
	(((x) & GENMASK(15, 13)) >> 13)

#define DDR_PHY_MR2_DDR4_MR2_DDR4_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR2_DDR4_MR2_DDR4_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_MR2_DDR4_MR2_DDR4_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR2_LPDDR2 */
#define DDR_PHY_MR2_LPDDR2(t)     (t + 0x188)

#define DDR_PHY_MR2_LPDDR2_MR2_LPDDR2_RL_WL(x)   ((x) & GENMASK(3, 0))
#define DDR_PHY_MR2_LPDDR2_MR2_LPDDR2_RL_WL_M    GENMASK(3, 0)
#define DDR_PHY_MR2_LPDDR2_MR2_LPDDR2_RL_WL_X(x) ((x) & GENMASK(3, 0))

#define DDR_PHY_MR2_LPDDR2_MR2_LPDDR2_RSVD_15_4(x) (((x) << 4) & GENMASK(15, 4))
#define DDR_PHY_MR2_LPDDR2_MR2_LPDDR2_RSVD_15_4_M GENMASK(15, 4)
#define DDR_PHY_MR2_LPDDR2_MR2_LPDDR2_RSVD_15_4_X(x)\
	(((x) & GENMASK(15, 4)) >> 4)

#define DDR_PHY_MR2_LPDDR2_MR2_LPDDR2_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR2_LPDDR2_MR2_LPDDR2_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_MR2_LPDDR2_MR2_LPDDR2_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR2_LPDDR3 */
#define DDR_PHY_MR2_LPDDR3(t)     (t + 0x188)

#define DDR_PHY_MR2_LPDDR3_MR2_LPDDR3_RL_WL(x)   ((x) & GENMASK(3, 0))
#define DDR_PHY_MR2_LPDDR3_MR2_LPDDR3_RL_WL_M    GENMASK(3, 0)
#define DDR_PHY_MR2_LPDDR3_MR2_LPDDR3_RL_WL_X(x) ((x) & GENMASK(3, 0))

#define DDR_PHY_MR2_LPDDR3_NWRE(x)               (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_MR2_LPDDR3_NWRE_M                GENMASK(4, 4)
#define DDR_PHY_MR2_LPDDR3_NWRE_X(x)             (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_MR2_LPDDR3_MR2_LPDDR3_RSVD_5(x)  (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_MR2_LPDDR3_MR2_LPDDR3_RSVD_5_M   GENMASK(5, 5)
#define DDR_PHY_MR2_LPDDR3_MR2_LPDDR3_RSVD_5_X(x) (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_MR2_LPDDR3_WLSEL(x)              (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_MR2_LPDDR3_WLSEL_M               GENMASK(6, 6)
#define DDR_PHY_MR2_LPDDR3_WLSEL_X(x)            (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_MR2_LPDDR3_WRLVL(x)              (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_MR2_LPDDR3_WRLVL_M               GENMASK(7, 7)
#define DDR_PHY_MR2_LPDDR3_WRLVL_X(x)            (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_MR2_LPDDR3_MR2_LPDDR3_RSVD_15_8(x) (((x) << 8) & GENMASK(15, 8))
#define DDR_PHY_MR2_LPDDR3_MR2_LPDDR3_RSVD_15_8_M GENMASK(15, 8)
#define DDR_PHY_MR2_LPDDR3_MR2_LPDDR3_RSVD_15_8_X(x)\
	(((x) & GENMASK(15, 8)) >> 8)

#define DDR_PHY_MR2_LPDDR3_MR2_LPDDR3_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR2_LPDDR3_MR2_LPDDR3_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_MR2_LPDDR3_MR2_LPDDR3_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR3 */
#define DDR_PHY_MR3(t)            (t + 0x18c)

#define DDR_PHY_MR3_MR3_MPRLOC(x)                ((x) & GENMASK(1, 0))
#define DDR_PHY_MR3_MR3_MPRLOC_M                 GENMASK(1, 0)
#define DDR_PHY_MR3_MR3_MPRLOC_X(x)              ((x) & GENMASK(1, 0))

#define DDR_PHY_MR3_MPR(x)                       (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_MR3_MPR_M                        GENMASK(2, 2)
#define DDR_PHY_MR3_MPR_X(x)                     (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_MR3_RSVD_15_3(x)                 (((x) << 3) & GENMASK(15, 3))
#define DDR_PHY_MR3_RSVD_15_3_M                  GENMASK(15, 3)
#define DDR_PHY_MR3_RSVD_15_3_X(x)               (((x) & GENMASK(15, 3)) >> 3)

#define DDR_PHY_MR3_MR3_RESERVED_31_16(x)        (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR3_MR3_RESERVED_31_16_M         GENMASK(31, 16)
#define DDR_PHY_MR3_MR3_RESERVED_31_16_X(x)      (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR3_DDR4 */
#define DDR_PHY_MR3_DDR4(t)       (t + 0x18c)

#define DDR_PHY_MR3_DDR4_MPRPSEL(x)              ((x) & GENMASK(1, 0))
#define DDR_PHY_MR3_DDR4_MPRPSEL_M               GENMASK(1, 0)
#define DDR_PHY_MR3_DDR4_MPRPSEL_X(x)            ((x) & GENMASK(1, 0))

#define DDR_PHY_MR3_DDR4_MPRO(x)                 (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_MR3_DDR4_MPRO_M                  GENMASK(2, 2)
#define DDR_PHY_MR3_DDR4_MPRO_X(x)               (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_MR3_DDR4_GDM(x)                  (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_MR3_DDR4_GDM_M                   GENMASK(3, 3)
#define DDR_PHY_MR3_DDR4_GDM_X(x)                (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_MR3_DDR4_PDA(x)                  (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_MR3_DDR4_PDA_M                   GENMASK(4, 4)
#define DDR_PHY_MR3_DDR4_PDA_X(x)                (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_MR3_DDR4_TSR(x)                  (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_MR3_DDR4_TSR_M                   GENMASK(5, 5)
#define DDR_PHY_MR3_DDR4_TSR_X(x)                (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_MR3_DDR4_FGRM(x)                 (((x) << 6) & GENMASK(8, 6))
#define DDR_PHY_MR3_DDR4_FGRM_M                  GENMASK(8, 6)
#define DDR_PHY_MR3_DDR4_FGRM_X(x)               (((x) & GENMASK(8, 6)) >> 6)

#define DDR_PHY_MR3_DDR4_WCL(x)                  (((x) << 9) & GENMASK(10, 9))
#define DDR_PHY_MR3_DDR4_WCL_M                   GENMASK(10, 9)
#define DDR_PHY_MR3_DDR4_WCL_X(x)                (((x) & GENMASK(10, 9)) >> 9)

#define DDR_PHY_MR3_DDR4_MPRRF(x)                (((x) << 11) & GENMASK(12, 11))
#define DDR_PHY_MR3_DDR4_MPRRF_M                 GENMASK(12, 11)
#define DDR_PHY_MR3_DDR4_MPRRF_X(x)              (((x) & GENMASK(12, 11)) >> 11)

#define DDR_PHY_MR3_DDR4_MR3_DDR4_RSVD_15_13(x)  (((x) << 13) & GENMASK(15, 13))
#define DDR_PHY_MR3_DDR4_MR3_DDR4_RSVD_15_13_M   GENMASK(15, 13)
#define DDR_PHY_MR3_DDR4_MR3_DDR4_RSVD_15_13_X(x)\
	(((x) & GENMASK(15, 13)) >> 13)

#define DDR_PHY_MR3_DDR4_MR3_DDR4_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR3_DDR4_MR3_DDR4_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_MR3_DDR4_MR3_DDR4_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR3_LPDDR2 */
#define DDR_PHY_MR3_LPDDR2(t)     (t + 0x18c)

#define DDR_PHY_MR3_LPDDR2_MR3_LPDDR2_DS(x)      ((x) & GENMASK(3, 0))
#define DDR_PHY_MR3_LPDDR2_MR3_LPDDR2_DS_M       GENMASK(3, 0)
#define DDR_PHY_MR3_LPDDR2_MR3_LPDDR2_DS_X(x)    ((x) & GENMASK(3, 0))

#define DDR_PHY_MR3_LPDDR2_MR3_LPDDR2_RSVD_15_4(x) (((x) << 4) & GENMASK(15, 4))
#define DDR_PHY_MR3_LPDDR2_MR3_LPDDR2_RSVD_15_4_M GENMASK(15, 4)
#define DDR_PHY_MR3_LPDDR2_MR3_LPDDR2_RSVD_15_4_X(x)\
	(((x) & GENMASK(15, 4)) >> 4)

#define DDR_PHY_MR3_LPDDR2_MR3_LPDDR2_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR3_LPDDR2_MR3_LPDDR2_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_MR3_LPDDR2_MR3_LPDDR2_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR3_LPDDR3 */
#define DDR_PHY_MR3_LPDDR3(t)     (t + 0x18c)

#define DDR_PHY_MR3_LPDDR3_MR3_LPDDR3_DS(x)      ((x) & GENMASK(3, 0))
#define DDR_PHY_MR3_LPDDR3_MR3_LPDDR3_DS_M       GENMASK(3, 0)
#define DDR_PHY_MR3_LPDDR3_MR3_LPDDR3_DS_X(x)    ((x) & GENMASK(3, 0))

#define DDR_PHY_MR3_LPDDR3_MR3_LPDDR3_RSVD_15_4(x) (((x) << 4) & GENMASK(15, 4))
#define DDR_PHY_MR3_LPDDR3_MR3_LPDDR3_RSVD_15_4_M GENMASK(15, 4)
#define DDR_PHY_MR3_LPDDR3_MR3_LPDDR3_RSVD_15_4_X(x)\
	(((x) & GENMASK(15, 4)) >> 4)

#define DDR_PHY_MR3_LPDDR3_MR3_LPDDR3_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR3_LPDDR3_MR3_LPDDR3_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_MR3_LPDDR3_MR3_LPDDR3_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR4 */
#define DDR_PHY_MR4(t)            (t + 0x190)

#define DDR_PHY_MR4_MR4_RSVD_15_0(x)             ((x) & GENMASK(15, 0))
#define DDR_PHY_MR4_MR4_RSVD_15_0_M              GENMASK(15, 0)
#define DDR_PHY_MR4_MR4_RSVD_15_0_X(x)           ((x) & GENMASK(15, 0))

#define DDR_PHY_MR4_MR4_RESERVED_31_16(x)        (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR4_MR4_RESERVED_31_16_M         GENMASK(31, 16)
#define DDR_PHY_MR4_MR4_RESERVED_31_16_X(x)      (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR4_DDR4 */
#define DDR_PHY_MR4_DDR4(t)       (t + 0x190)

#define DDR_PHY_MR4_DDR4_RSVD_0(x)               ((x) & GENMASK(0, 0))
#define DDR_PHY_MR4_DDR4_RSVD_0_M                GENMASK(0, 0)
#define DDR_PHY_MR4_DDR4_RSVD_0_X(x)             ((x) & GENMASK(0, 0))

#define DDR_PHY_MR4_DDR4_MPDM(x)                 (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_MR4_DDR4_MPDM_M                  GENMASK(1, 1)
#define DDR_PHY_MR4_DDR4_MPDM_X(x)               (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_MR4_DDR4_TCRR(x)                 (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_MR4_DDR4_TCRR_M                  GENMASK(2, 2)
#define DDR_PHY_MR4_DDR4_TCRR_X(x)               (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_MR4_DDR4_TCRM(x)                 (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_MR4_DDR4_TCRM_M                  GENMASK(3, 3)
#define DDR_PHY_MR4_DDR4_TCRM_X(x)               (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_MR4_DDR4_IVM(x)                  (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_MR4_DDR4_IVM_M                   GENMASK(4, 4)
#define DDR_PHY_MR4_DDR4_IVM_X(x)                (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_MR4_DDR4_MR4_DDR4_RSVD_5(x)      (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_MR4_DDR4_MR4_DDR4_RSVD_5_M       GENMASK(5, 5)
#define DDR_PHY_MR4_DDR4_MR4_DDR4_RSVD_5_X(x)    (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_MR4_DDR4_CS2CMDL(x)              (((x) << 6) & GENMASK(8, 6))
#define DDR_PHY_MR4_DDR4_CS2CMDL_M               GENMASK(8, 6)
#define DDR_PHY_MR4_DDR4_CS2CMDL_X(x)            (((x) & GENMASK(8, 6)) >> 6)

#define DDR_PHY_MR4_DDR4_SRA(x)                  (((x) << 9) & GENMASK(9, 9))
#define DDR_PHY_MR4_DDR4_SRA_M                   GENMASK(9, 9)
#define DDR_PHY_MR4_DDR4_SRA_X(x)                (((x) & GENMASK(9, 9)) >> 9)

#define DDR_PHY_MR4_DDR4_RPTM(x)                 (((x) << 10) & GENMASK(10, 10))
#define DDR_PHY_MR4_DDR4_RPTM_M                  GENMASK(10, 10)
#define DDR_PHY_MR4_DDR4_RPTM_X(x)               (((x) & GENMASK(10, 10)) >> 10)

#define DDR_PHY_MR4_DDR4_RDP(x)                  (((x) << 11) & GENMASK(11, 11))
#define DDR_PHY_MR4_DDR4_RDP_M                   GENMASK(11, 11)
#define DDR_PHY_MR4_DDR4_RDP_X(x)                (((x) & GENMASK(11, 11)) >> 11)

#define DDR_PHY_MR4_DDR4_WRP(x)                  (((x) << 12) & GENMASK(12, 12))
#define DDR_PHY_MR4_DDR4_WRP_M                   GENMASK(12, 12)
#define DDR_PHY_MR4_DDR4_WRP_X(x)                (((x) & GENMASK(12, 12)) >> 12)

#define DDR_PHY_MR4_DDR4_MR4_DDR4_RSVD_15_13(x)  (((x) << 13) & GENMASK(15, 13))
#define DDR_PHY_MR4_DDR4_MR4_DDR4_RSVD_15_13_M   GENMASK(15, 13)
#define DDR_PHY_MR4_DDR4_MR4_DDR4_RSVD_15_13_X(x)\
	(((x) & GENMASK(15, 13)) >> 13)

#define DDR_PHY_MR4_DDR4_MR4_DDR4_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR4_DDR4_MR4_DDR4_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_MR4_DDR4_MR4_DDR4_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR4_LPDDR2 */
#define DDR_PHY_MR4_LPDDR2(t)     (t + 0x190)

#define DDR_PHY_MR4_LPDDR2_MR4_LPDDR2_RSVD_15_0(x) ((x) & GENMASK(15, 0))
#define DDR_PHY_MR4_LPDDR2_MR4_LPDDR2_RSVD_15_0_M GENMASK(15, 0)
#define DDR_PHY_MR4_LPDDR2_MR4_LPDDR2_RSVD_15_0_X(x) ((x) & GENMASK(15, 0))

#define DDR_PHY_MR4_LPDDR2_MR4_LPDDR2_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR4_LPDDR2_MR4_LPDDR2_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_MR4_LPDDR2_MR4_LPDDR2_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR4_LPDDR3 */
#define DDR_PHY_MR4_LPDDR3(t)     (t + 0x190)

#define DDR_PHY_MR4_LPDDR3_MR4_LPDDR3_RSVD_15_0(x) ((x) & GENMASK(15, 0))
#define DDR_PHY_MR4_LPDDR3_MR4_LPDDR3_RSVD_15_0_M GENMASK(15, 0)
#define DDR_PHY_MR4_LPDDR3_MR4_LPDDR3_RSVD_15_0_X(x) ((x) & GENMASK(15, 0))

#define DDR_PHY_MR4_LPDDR3_MR4_LPDDR3_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR4_LPDDR3_MR4_LPDDR3_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_MR4_LPDDR3_MR4_LPDDR3_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR5 */
#define DDR_PHY_MR5(t)            (t + 0x194)

#define DDR_PHY_MR5_MR5_RSVD_15_0(x)             ((x) & GENMASK(15, 0))
#define DDR_PHY_MR5_MR5_RSVD_15_0_M              GENMASK(15, 0)
#define DDR_PHY_MR5_MR5_RSVD_15_0_X(x)           ((x) & GENMASK(15, 0))

#define DDR_PHY_MR5_MR5_RESERVED_31_16(x)        (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR5_MR5_RESERVED_31_16_M         GENMASK(31, 16)
#define DDR_PHY_MR5_MR5_RESERVED_31_16_X(x)      (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR5_DDR4 */
#define DDR_PHY_MR5_DDR4(t)       (t + 0x194)

#define DDR_PHY_MR5_DDR4_CAPM(x)                 ((x) & GENMASK(2, 0))
#define DDR_PHY_MR5_DDR4_CAPM_M                  GENMASK(2, 0)
#define DDR_PHY_MR5_DDR4_CAPM_X(x)               ((x) & GENMASK(2, 0))

#define DDR_PHY_MR5_DDR4_CRCEC(x)                (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_MR5_DDR4_CRCEC_M                 GENMASK(3, 3)
#define DDR_PHY_MR5_DDR4_CRCEC_X(x)              (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_MR5_DDR4_CAPES(x)                (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_MR5_DDR4_CAPES_M                 GENMASK(4, 4)
#define DDR_PHY_MR5_DDR4_CAPES_X(x)              (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_MR5_DDR4_ODTIBPD(x)              (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_MR5_DDR4_ODTIBPD_M               GENMASK(5, 5)
#define DDR_PHY_MR5_DDR4_ODTIBPD_X(x)            (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_MR5_DDR4_RTTPARK(x)              (((x) << 6) & GENMASK(8, 6))
#define DDR_PHY_MR5_DDR4_RTTPARK_M               GENMASK(8, 6)
#define DDR_PHY_MR5_DDR4_RTTPARK_X(x)            (((x) & GENMASK(8, 6)) >> 6)

#define DDR_PHY_MR5_DDR4_CAPPE(x)                (((x) << 9) & GENMASK(9, 9))
#define DDR_PHY_MR5_DDR4_CAPPE_M                 GENMASK(9, 9)
#define DDR_PHY_MR5_DDR4_CAPPE_X(x)              (((x) & GENMASK(9, 9)) >> 9)

#define DDR_PHY_MR5_DDR4_DM(x)                   (((x) << 10) & GENMASK(10, 10))
#define DDR_PHY_MR5_DDR4_DM_M                    GENMASK(10, 10)
#define DDR_PHY_MR5_DDR4_DM_X(x)                 (((x) & GENMASK(10, 10)) >> 10)

#define DDR_PHY_MR5_DDR4_MR5_DDR4_WDBI(x)        (((x) << 11) & GENMASK(11, 11))
#define DDR_PHY_MR5_DDR4_MR5_DDR4_WDBI_M         GENMASK(11, 11)
#define DDR_PHY_MR5_DDR4_MR5_DDR4_WDBI_X(x)      (((x) & GENMASK(11, 11)) >> 11)

#define DDR_PHY_MR5_DDR4_MR5_DDR4_RDBI(x)        (((x) << 12) & GENMASK(12, 12))
#define DDR_PHY_MR5_DDR4_MR5_DDR4_RDBI_M         GENMASK(12, 12)
#define DDR_PHY_MR5_DDR4_MR5_DDR4_RDBI_X(x)      (((x) & GENMASK(12, 12)) >> 12)

#define DDR_PHY_MR5_DDR4_MR5_DDR4_RSVD_15_13(x)  (((x) << 13) & GENMASK(15, 13))
#define DDR_PHY_MR5_DDR4_MR5_DDR4_RSVD_15_13_M   GENMASK(15, 13)
#define DDR_PHY_MR5_DDR4_MR5_DDR4_RSVD_15_13_X(x)\
	(((x) & GENMASK(15, 13)) >> 13)

#define DDR_PHY_MR5_DDR4_MR5_DDR4_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR5_DDR4_MR5_DDR4_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_MR5_DDR4_MR5_DDR4_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR5_LPDDR2 */
#define DDR_PHY_MR5_LPDDR2(t)     (t + 0x194)

#define DDR_PHY_MR5_LPDDR2_MR5_LPDDR2_RSVD_15_0(x) ((x) & GENMASK(15, 0))
#define DDR_PHY_MR5_LPDDR2_MR5_LPDDR2_RSVD_15_0_M GENMASK(15, 0)
#define DDR_PHY_MR5_LPDDR2_MR5_LPDDR2_RSVD_15_0_X(x) ((x) & GENMASK(15, 0))

#define DDR_PHY_MR5_LPDDR2_MR5_LPDDR2_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR5_LPDDR2_MR5_LPDDR2_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_MR5_LPDDR2_MR5_LPDDR2_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR5_LPDDR3 */
#define DDR_PHY_MR5_LPDDR3(t)     (t + 0x194)

#define DDR_PHY_MR5_LPDDR3_MR5_LPDDR3_RSVD_15_0(x) ((x) & GENMASK(15, 0))
#define DDR_PHY_MR5_LPDDR3_MR5_LPDDR3_RSVD_15_0_M GENMASK(15, 0)
#define DDR_PHY_MR5_LPDDR3_MR5_LPDDR3_RSVD_15_0_X(x) ((x) & GENMASK(15, 0))

#define DDR_PHY_MR5_LPDDR3_MR5_LPDDR3_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR5_LPDDR3_MR5_LPDDR3_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_MR5_LPDDR3_MR5_LPDDR3_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR6 */
#define DDR_PHY_MR6(t)            (t + 0x198)

#define DDR_PHY_MR6_MR6_RSVD_15_0(x)             ((x) & GENMASK(15, 0))
#define DDR_PHY_MR6_MR6_RSVD_15_0_M              GENMASK(15, 0)
#define DDR_PHY_MR6_MR6_RSVD_15_0_X(x)           ((x) & GENMASK(15, 0))

#define DDR_PHY_MR6_MR6_RESERVED_31_16(x)        (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR6_MR6_RESERVED_31_16_M         GENMASK(31, 16)
#define DDR_PHY_MR6_MR6_RESERVED_31_16_X(x)      (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR6_DDR4 */
#define DDR_PHY_MR6_DDR4(t)       (t + 0x198)

#define DDR_PHY_MR6_DDR4_VDQTVAL(x)              ((x) & GENMASK(5, 0))
#define DDR_PHY_MR6_DDR4_VDQTVAL_M               GENMASK(5, 0)
#define DDR_PHY_MR6_DDR4_VDQTVAL_X(x)            ((x) & GENMASK(5, 0))

#define DDR_PHY_MR6_DDR4_VDQTRG(x)               (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_MR6_DDR4_VDQTRG_M                GENMASK(6, 6)
#define DDR_PHY_MR6_DDR4_VDQTRG_X(x)             (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_MR6_DDR4_VDDQTEN(x)              (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_MR6_DDR4_VDDQTEN_M               GENMASK(7, 7)
#define DDR_PHY_MR6_DDR4_VDDQTEN_X(x)            (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_MR6_DDR4_RSVD_9_8(x)             (((x) << 8) & GENMASK(9, 8))
#define DDR_PHY_MR6_DDR4_RSVD_9_8_M              GENMASK(9, 8)
#define DDR_PHY_MR6_DDR4_RSVD_9_8_X(x)           (((x) & GENMASK(9, 8)) >> 8)

#define DDR_PHY_MR6_DDR4_TCCD_L(x)               (((x) << 10) & GENMASK(12, 10))
#define DDR_PHY_MR6_DDR4_TCCD_L_M                GENMASK(12, 10)
#define DDR_PHY_MR6_DDR4_TCCD_L_X(x)             (((x) & GENMASK(12, 10)) >> 10)

#define DDR_PHY_MR6_DDR4_MR6_DDR4_RSVD_15_13(x)  (((x) << 13) & GENMASK(15, 13))
#define DDR_PHY_MR6_DDR4_MR6_DDR4_RSVD_15_13_M   GENMASK(15, 13)
#define DDR_PHY_MR6_DDR4_MR6_DDR4_RSVD_15_13_X(x)\
	(((x) & GENMASK(15, 13)) >> 13)

#define DDR_PHY_MR6_DDR4_MR6_DDR4_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR6_DDR4_MR6_DDR4_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_MR6_DDR4_MR6_DDR4_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR6_LPDDR2 */
#define DDR_PHY_MR6_LPDDR2(t)     (t + 0x198)

#define DDR_PHY_MR6_LPDDR2_MR6_LPDDR2_RSVD_15_0(x) ((x) & GENMASK(15, 0))
#define DDR_PHY_MR6_LPDDR2_MR6_LPDDR2_RSVD_15_0_M GENMASK(15, 0)
#define DDR_PHY_MR6_LPDDR2_MR6_LPDDR2_RSVD_15_0_X(x) ((x) & GENMASK(15, 0))

#define DDR_PHY_MR6_LPDDR2_MR6_LPDDR2_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR6_LPDDR2_MR6_LPDDR2_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_MR6_LPDDR2_MR6_LPDDR2_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR6_LPDDR3 */
#define DDR_PHY_MR6_LPDDR3(t)     (t + 0x198)

#define DDR_PHY_MR6_LPDDR3_MR6_LPDDR3_RSVD_15_0(x) ((x) & GENMASK(15, 0))
#define DDR_PHY_MR6_LPDDR3_MR6_LPDDR3_RSVD_15_0_M GENMASK(15, 0)
#define DDR_PHY_MR6_LPDDR3_MR6_LPDDR3_RSVD_15_0_X(x) ((x) & GENMASK(15, 0))

#define DDR_PHY_MR6_LPDDR3_MR6_LPDDR3_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR6_LPDDR3_MR6_LPDDR3_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_MR6_LPDDR3_MR6_LPDDR3_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR7 */
#define DDR_PHY_MR7(t)            (t + 0x19c)

#define DDR_PHY_MR7_MR7_RSVD_15_0(x)             ((x) & GENMASK(15, 0))
#define DDR_PHY_MR7_MR7_RSVD_15_0_M              GENMASK(15, 0)
#define DDR_PHY_MR7_MR7_RSVD_15_0_X(x)           ((x) & GENMASK(15, 0))

#define DDR_PHY_MR7_MR7_RESERVED_31_16(x)        (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR7_MR7_RESERVED_31_16_M         GENMASK(31, 16)
#define DDR_PHY_MR7_MR7_RESERVED_31_16_X(x)      (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR7_DDR4 */
#define DDR_PHY_MR7_DDR4(t)       (t + 0x19c)

#define DDR_PHY_MR7_DDR4_MR7_DDR4_RSVD_15_0(x)   ((x) & GENMASK(15, 0))
#define DDR_PHY_MR7_DDR4_MR7_DDR4_RSVD_15_0_M    GENMASK(15, 0)
#define DDR_PHY_MR7_DDR4_MR7_DDR4_RSVD_15_0_X(x) ((x) & GENMASK(15, 0))

#define DDR_PHY_MR7_DDR4_MR7_DDR4_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR7_DDR4_MR7_DDR4_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_MR7_DDR4_MR7_DDR4_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR7_LPDDR2 */
#define DDR_PHY_MR7_LPDDR2(t)     (t + 0x19c)

#define DDR_PHY_MR7_LPDDR2_MR7_LPDDR2_RSVD_15_0(x) ((x) & GENMASK(15, 0))
#define DDR_PHY_MR7_LPDDR2_MR7_LPDDR2_RSVD_15_0_M GENMASK(15, 0)
#define DDR_PHY_MR7_LPDDR2_MR7_LPDDR2_RSVD_15_0_X(x) ((x) & GENMASK(15, 0))

#define DDR_PHY_MR7_LPDDR2_MR7_LPDDR2_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR7_LPDDR2_MR7_LPDDR2_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_MR7_LPDDR2_MR7_LPDDR2_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR7_LPDDR3 */
#define DDR_PHY_MR7_LPDDR3(t)     (t + 0x19c)

#define DDR_PHY_MR7_LPDDR3_MR7_LPDDR3_RSVD_15_0(x) ((x) & GENMASK(15, 0))
#define DDR_PHY_MR7_LPDDR3_MR7_LPDDR3_RSVD_15_0_M GENMASK(15, 0)
#define DDR_PHY_MR7_LPDDR3_MR7_LPDDR3_RSVD_15_0_X(x) ((x) & GENMASK(15, 0))

#define DDR_PHY_MR7_LPDDR3_MR7_LPDDR3_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR7_LPDDR3_MR7_LPDDR3_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_MR7_LPDDR3_MR7_LPDDR3_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR11 */
#define DDR_PHY_MR11(t)           (t + 0x1ac)

#define DDR_PHY_MR11_MR11_RSVD_15_0(x)           ((x) & GENMASK(15, 0))
#define DDR_PHY_MR11_MR11_RSVD_15_0_M            GENMASK(15, 0)
#define DDR_PHY_MR11_MR11_RSVD_15_0_X(x)         ((x) & GENMASK(15, 0))

#define DDR_PHY_MR11_MR11_RESERVED_31_16(x)      (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR11_MR11_RESERVED_31_16_M       GENMASK(31, 16)
#define DDR_PHY_MR11_MR11_RESERVED_31_16_X(x)    (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR11_DDR4 */
#define DDR_PHY_MR11_DDR4(t)      (t + 0x1ac)

#define DDR_PHY_MR11_DDR4_MR11_DDR4_RSVD_15_0(x) ((x) & GENMASK(15, 0))
#define DDR_PHY_MR11_DDR4_MR11_DDR4_RSVD_15_0_M  GENMASK(15, 0)
#define DDR_PHY_MR11_DDR4_MR11_DDR4_RSVD_15_0_X(x) ((x) & GENMASK(15, 0))

#define DDR_PHY_MR11_DDR4_MR11_DDR4_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR11_DDR4_MR11_DDR4_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_MR11_DDR4_MR11_DDR4_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR11_LPDDR2 */
#define DDR_PHY_MR11_LPDDR2(t)    (t + 0x1ac)

#define DDR_PHY_MR11_LPDDR2_MR11_LPDDR2_RSVD_15_0(x) ((x) & GENMASK(15, 0))
#define DDR_PHY_MR11_LPDDR2_MR11_LPDDR2_RSVD_15_0_M GENMASK(15, 0)
#define DDR_PHY_MR11_LPDDR2_MR11_LPDDR2_RSVD_15_0_X(x) ((x) & GENMASK(15, 0))

#define DDR_PHY_MR11_LPDDR2_MR11_LPDDR2_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR11_LPDDR2_MR11_LPDDR2_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_MR11_LPDDR2_MR11_LPDDR2_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:MR11_LPDDR3 */
#define DDR_PHY_MR11_LPDDR3(t)    (t + 0x1ac)

#define DDR_PHY_MR11_LPDDR3_DQODT(x)             ((x) & GENMASK(1, 0))
#define DDR_PHY_MR11_LPDDR3_DQODT_M              GENMASK(1, 0)
#define DDR_PHY_MR11_LPDDR3_DQODT_X(x)           ((x) & GENMASK(1, 0))

#define DDR_PHY_MR11_LPDDR3_PDCTL(x)             (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_MR11_LPDDR3_PDCTL_M              GENMASK(2, 2)
#define DDR_PHY_MR11_LPDDR3_PDCTL_X(x)           (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_MR11_LPDDR3_MR11_LPDDR3_RSVD_15_0(x)\
	(((x) << 3) & GENMASK(15, 3))
#define DDR_PHY_MR11_LPDDR3_MR11_LPDDR3_RSVD_15_0_M GENMASK(15, 3)
#define DDR_PHY_MR11_LPDDR3_MR11_LPDDR3_RSVD_15_0_X(x)\
	(((x) & GENMASK(15, 3)) >> 3)

#define DDR_PHY_MR11_LPDDR3_MR11_LPDDR3_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_MR11_LPDDR3_MR11_LPDDR3_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_MR11_LPDDR3_MR11_LPDDR3_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DTCR0 */
#define DDR_PHY_DTCR0(t)          (t + 0x200)

#define DDR_PHY_DTCR0_DTRPTN(x)                  ((x) & GENMASK(3, 0))
#define DDR_PHY_DTCR0_DTRPTN_M                   GENMASK(3, 0)
#define DDR_PHY_DTCR0_DTRPTN_X(x)                ((x) & GENMASK(3, 0))

#define DDR_PHY_DTCR0_RESERVED_5_4(x)            (((x) << 4) & GENMASK(5, 4))
#define DDR_PHY_DTCR0_RESERVED_5_4_M             GENMASK(5, 4)
#define DDR_PHY_DTCR0_RESERVED_5_4_X(x)          (((x) & GENMASK(5, 4)) >> 4)

#define DDR_PHY_DTCR0_DTMPR(x)                   (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DTCR0_DTMPR_M                    GENMASK(6, 6)
#define DDR_PHY_DTCR0_DTMPR_X(x)                 (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DTCR0_DTCMPD(x)                  (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_DTCR0_DTCMPD_M                   GENMASK(7, 7)
#define DDR_PHY_DTCR0_DTCMPD_X(x)                (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_DTCR0_RESERVED_10_8(x)           (((x) << 8) & GENMASK(10, 8))
#define DDR_PHY_DTCR0_RESERVED_10_8_M            GENMASK(10, 8)
#define DDR_PHY_DTCR0_RESERVED_10_8_X(x)         (((x) & GENMASK(10, 8)) >> 8)

#define DDR_PHY_DTCR0_DTDBS4(x)                  (((x) << 11) & GENMASK(11, 11))
#define DDR_PHY_DTCR0_DTDBS4_M                   GENMASK(11, 11)
#define DDR_PHY_DTCR0_DTDBS4_X(x)                (((x) & GENMASK(11, 11)) >> 11)

#define DDR_PHY_DTCR0_DTWBDDM(x)                 (((x) << 12) & GENMASK(12, 12))
#define DDR_PHY_DTCR0_DTWBDDM_M                  GENMASK(12, 12)
#define DDR_PHY_DTCR0_DTWBDDM_X(x)               (((x) & GENMASK(12, 12)) >> 12)

#define DDR_PHY_DTCR0_DTBDC(x)                   (((x) << 13) & GENMASK(13, 13))
#define DDR_PHY_DTCR0_DTBDC_M                    GENMASK(13, 13)
#define DDR_PHY_DTCR0_DTBDC_X(x)                 (((x) & GENMASK(13, 13)) >> 13)

#define DDR_PHY_DTCR0_DTRDBITR(x)                (((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DTCR0_DTRDBITR_M                 GENMASK(15, 14)
#define DDR_PHY_DTCR0_DTRDBITR_X(x)              (((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DTCR0_DTDBS(x)                   (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DTCR0_DTDBS_M                    GENMASK(19, 16)
#define DDR_PHY_DTCR0_DTDBS_X(x)                 (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DTCR0_DTDEN(x)                   (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DTCR0_DTDEN_M                    GENMASK(20, 20)
#define DDR_PHY_DTCR0_DTDEN_X(x)                 (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DTCR0_DTDSTP(x)                  (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DTCR0_DTDSTP_M                   GENMASK(21, 21)
#define DDR_PHY_DTCR0_DTDSTP_X(x)                (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DTCR0_DTEXD(x)                   (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DTCR0_DTEXD_M                    GENMASK(22, 22)
#define DDR_PHY_DTCR0_DTEXD_X(x)                 (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DTCR0_DTCR0_RESERVED_23(x)       (((x) << 23) & GENMASK(23, 23))
#define DDR_PHY_DTCR0_DTCR0_RESERVED_23_M        GENMASK(23, 23)
#define DDR_PHY_DTCR0_DTCR0_RESERVED_23_X(x)     (((x) & GENMASK(23, 23)) >> 23)

#define DDR_PHY_DTCR0_DTDRS(x)                   (((x) << 24) & GENMASK(25, 24))
#define DDR_PHY_DTCR0_DTDRS_M                    GENMASK(25, 24)
#define DDR_PHY_DTCR0_DTDRS_X(x)                 (((x) & GENMASK(25, 24)) >> 24)

#define DDR_PHY_DTCR0_DTCR0_RESERVED_27_26(x)    (((x) << 26) & GENMASK(27, 26))
#define DDR_PHY_DTCR0_DTCR0_RESERVED_27_26_M     GENMASK(27, 26)
#define DDR_PHY_DTCR0_DTCR0_RESERVED_27_26_X(x)  (((x) & GENMASK(27, 26)) >> 26)

#define DDR_PHY_DTCR0_RFSHDT(x)                  (((x) << 28) & GENMASK(31, 28))
#define DDR_PHY_DTCR0_RFSHDT_M                   GENMASK(31, 28)
#define DDR_PHY_DTCR0_RFSHDT_X(x)                (((x) & GENMASK(31, 28)) >> 28)

/*      DDR_PHY:DWC_DDRPHY_PUB:DTCR1 */
#define DDR_PHY_DTCR1(t)          (t + 0x204)

#define DDR_PHY_DTCR1_BSTEN(x)                   ((x) & GENMASK(0, 0))
#define DDR_PHY_DTCR1_BSTEN_M                    GENMASK(0, 0)
#define DDR_PHY_DTCR1_BSTEN_X(x)                 ((x) & GENMASK(0, 0))

#define DDR_PHY_DTCR1_RDLVLEN(x)                 (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DTCR1_RDLVLEN_M                  GENMASK(1, 1)
#define DDR_PHY_DTCR1_RDLVLEN_X(x)               (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DTCR1_RDPRMBL_TRN(x)             (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DTCR1_RDPRMBL_TRN_M              GENMASK(2, 2)
#define DDR_PHY_DTCR1_RDPRMBL_TRN_X(x)           (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DTCR1_DTCR1_RESERVED_3(x)        (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DTCR1_DTCR1_RESERVED_3_M         GENMASK(3, 3)
#define DDR_PHY_DTCR1_DTCR1_RESERVED_3_X(x)      (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DTCR1_RDLVLGS(x)                 (((x) << 4) & GENMASK(6, 4))
#define DDR_PHY_DTCR1_RDLVLGS_M                  GENMASK(6, 4)
#define DDR_PHY_DTCR1_RDLVLGS_X(x)               (((x) & GENMASK(6, 4)) >> 4)

#define DDR_PHY_DTCR1_DTCR1_RESERVED_7(x)        (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_DTCR1_DTCR1_RESERVED_7_M         GENMASK(7, 7)
#define DDR_PHY_DTCR1_DTCR1_RESERVED_7_X(x)      (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_DTCR1_RDLVLGDIFF(x)              (((x) << 8) & GENMASK(10, 8))
#define DDR_PHY_DTCR1_RDLVLGDIFF_M               GENMASK(10, 8)
#define DDR_PHY_DTCR1_RDLVLGDIFF_X(x)            (((x) & GENMASK(10, 8)) >> 8)

#define DDR_PHY_DTCR1_WLVLDPRD(x)                (((x) << 11) & GENMASK(11, 11))
#define DDR_PHY_DTCR1_WLVLDPRD_M                 GENMASK(11, 11)
#define DDR_PHY_DTCR1_WLVLDPRD_X(x)              (((x) & GENMASK(11, 11)) >> 11)

#define DDR_PHY_DTCR1_DTRANK(x)                  (((x) << 12) & GENMASK(13, 12))
#define DDR_PHY_DTCR1_DTRANK_M                   GENMASK(13, 12)
#define DDR_PHY_DTCR1_DTRANK_X(x)                (((x) & GENMASK(13, 12)) >> 12)

#define DDR_PHY_DTCR1_DTCR1_RESERVED_15_14(x)    (((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DTCR1_DTCR1_RESERVED_15_14_M     GENMASK(15, 14)
#define DDR_PHY_DTCR1_DTCR1_RESERVED_15_14_X(x)  (((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DTCR1_RANKEN(x)                  (((x) << 16) & GENMASK(17, 16))
#define DDR_PHY_DTCR1_RANKEN_M                   GENMASK(17, 16)
#define DDR_PHY_DTCR1_RANKEN_X(x)                (((x) & GENMASK(17, 16)) >> 16)

#define DDR_PHY_DTCR1_RANKEN_RSVD(x)             (((x) << 18) & GENMASK(31, 18))
#define DDR_PHY_DTCR1_RANKEN_RSVD_M              GENMASK(31, 18)
#define DDR_PHY_DTCR1_RANKEN_RSVD_X(x)           (((x) & GENMASK(31, 18)) >> 18)

/*      DDR_PHY:DWC_DDRPHY_PUB:DTAR0 */
#define DDR_PHY_DTAR0(t)          (t + 0x208)

#define DDR_PHY_DTAR0_DTROW(x)                   ((x) & GENMASK(17, 0))
#define DDR_PHY_DTAR0_DTROW_M                    GENMASK(17, 0)
#define DDR_PHY_DTAR0_DTROW_X(x)                 ((x) & GENMASK(17, 0))

#define DDR_PHY_DTAR0_DTAR0_RESERVED_19_18(x)    (((x) << 18) & GENMASK(19, 18))
#define DDR_PHY_DTAR0_DTAR0_RESERVED_19_18_M     GENMASK(19, 18)
#define DDR_PHY_DTAR0_DTAR0_RESERVED_19_18_X(x)  (((x) & GENMASK(19, 18)) >> 18)

#define DDR_PHY_DTAR0_DTBGBK0(x)                 (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DTAR0_DTBGBK0_M                  GENMASK(23, 20)
#define DDR_PHY_DTAR0_DTBGBK0_X(x)               (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DTAR0_DTBGBK1(x)                 (((x) << 24) & GENMASK(27, 24))
#define DDR_PHY_DTAR0_DTBGBK1_M                  GENMASK(27, 24)
#define DDR_PHY_DTAR0_DTBGBK1_X(x)               (((x) & GENMASK(27, 24)) >> 24)

#define DDR_PHY_DTAR0_DTAR0_MPRLOC(x)            (((x) << 28) & GENMASK(29, 28))
#define DDR_PHY_DTAR0_DTAR0_MPRLOC_M             GENMASK(29, 28)
#define DDR_PHY_DTAR0_DTAR0_MPRLOC_X(x)          (((x) & GENMASK(29, 28)) >> 28)

#define DDR_PHY_DTAR0_DTAR0_RESERVED_31_30(x)    (((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DTAR0_DTAR0_RESERVED_31_30_M     GENMASK(31, 30)
#define DDR_PHY_DTAR0_DTAR0_RESERVED_31_30_X(x)  (((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DTAR1 */
#define DDR_PHY_DTAR1(t)          (t + 0x20c)

#define DDR_PHY_DTAR1_DTCOL0(x)                  ((x) & GENMASK(8, 0))
#define DDR_PHY_DTAR1_DTCOL0_M                   GENMASK(8, 0)
#define DDR_PHY_DTAR1_DTCOL0_X(x)                ((x) & GENMASK(8, 0))

#define DDR_PHY_DTAR1_DTAR1_RESERVED_15_9(x)     (((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DTAR1_DTAR1_RESERVED_15_9_M      GENMASK(15, 9)
#define DDR_PHY_DTAR1_DTAR1_RESERVED_15_9_X(x)   (((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DTAR1_DTCOL1(x)                  (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DTAR1_DTCOL1_M                   GENMASK(24, 16)
#define DDR_PHY_DTAR1_DTCOL1_X(x)                (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DTAR1_DTAR1_RESERVED_31_25(x)    (((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DTAR1_DTAR1_RESERVED_31_25_M     GENMASK(31, 25)
#define DDR_PHY_DTAR1_DTAR1_RESERVED_31_25_X(x)  (((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DTAR2 */
#define DDR_PHY_DTAR2(t)          (t + 0x210)

#define DDR_PHY_DTAR2_DTCOL2(x)                  ((x) & GENMASK(8, 0))
#define DDR_PHY_DTAR2_DTCOL2_M                   GENMASK(8, 0)
#define DDR_PHY_DTAR2_DTCOL2_X(x)                ((x) & GENMASK(8, 0))

#define DDR_PHY_DTAR2_DTAR2_RESERVED_15_9(x)     (((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DTAR2_DTAR2_RESERVED_15_9_M      GENMASK(15, 9)
#define DDR_PHY_DTAR2_DTAR2_RESERVED_15_9_X(x)   (((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DTAR2_DTCOL3(x)                  (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DTAR2_DTCOL3_M                   GENMASK(24, 16)
#define DDR_PHY_DTAR2_DTCOL3_X(x)                (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DTAR2_DTAR2_RESERVED_31_25(x)    (((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DTAR2_DTAR2_RESERVED_31_25_M     GENMASK(31, 25)
#define DDR_PHY_DTAR2_DTAR2_RESERVED_31_25_X(x)  (((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DTDR0 */
#define DDR_PHY_DTDR0(t)          (t + 0x218)

#define DDR_PHY_DTDR0_DTBYTE0(x)                 ((x) & GENMASK(7, 0))
#define DDR_PHY_DTDR0_DTBYTE0_M                  GENMASK(7, 0)
#define DDR_PHY_DTDR0_DTBYTE0_X(x)               ((x) & GENMASK(7, 0))

#define DDR_PHY_DTDR0_DTBYTE1(x)                 (((x) << 8) & GENMASK(15, 8))
#define DDR_PHY_DTDR0_DTBYTE1_M                  GENMASK(15, 8)
#define DDR_PHY_DTDR0_DTBYTE1_X(x)               (((x) & GENMASK(15, 8)) >> 8)

#define DDR_PHY_DTDR0_DTBYTE2(x)                 (((x) << 16) & GENMASK(23, 16))
#define DDR_PHY_DTDR0_DTBYTE2_M                  GENMASK(23, 16)
#define DDR_PHY_DTDR0_DTBYTE2_X(x)               (((x) & GENMASK(23, 16)) >> 16)

#define DDR_PHY_DTDR0_DTBYTE3(x)                 (((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_DTDR0_DTBYTE3_M                  GENMASK(31, 24)
#define DDR_PHY_DTDR0_DTBYTE3_X(x)               (((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:DTDR1 */
#define DDR_PHY_DTDR1(t)          (t + 0x21c)

#define DDR_PHY_DTDR1_DTBYTE4(x)                 ((x) & GENMASK(7, 0))
#define DDR_PHY_DTDR1_DTBYTE4_M                  GENMASK(7, 0)
#define DDR_PHY_DTDR1_DTBYTE4_X(x)               ((x) & GENMASK(7, 0))

#define DDR_PHY_DTDR1_DTBYTE5(x)                 (((x) << 8) & GENMASK(15, 8))
#define DDR_PHY_DTDR1_DTBYTE5_M                  GENMASK(15, 8)
#define DDR_PHY_DTDR1_DTBYTE5_X(x)               (((x) & GENMASK(15, 8)) >> 8)

#define DDR_PHY_DTDR1_DTBYTE6(x)                 (((x) << 16) & GENMASK(23, 16))
#define DDR_PHY_DTDR1_DTBYTE6_M                  GENMASK(23, 16)
#define DDR_PHY_DTDR1_DTBYTE6_X(x)               (((x) & GENMASK(23, 16)) >> 16)

#define DDR_PHY_DTDR1_DTBYTE7(x)                 (((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_DTDR1_DTBYTE7_M                  GENMASK(31, 24)
#define DDR_PHY_DTDR1_DTBYTE7_X(x)               (((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:UDDR0 */
#define DDR_PHY_UDDR0(t)          (t + 0x220)

#define DDR_PHY_UDDR0_UDBEAT0(x)                 ((x) & GENMASK(7, 0))
#define DDR_PHY_UDDR0_UDBEAT0_M                  GENMASK(7, 0)
#define DDR_PHY_UDDR0_UDBEAT0_X(x)               ((x) & GENMASK(7, 0))

#define DDR_PHY_UDDR0_UDBEAT1(x)                 (((x) << 8) & GENMASK(15, 8))
#define DDR_PHY_UDDR0_UDBEAT1_M                  GENMASK(15, 8)
#define DDR_PHY_UDDR0_UDBEAT1_X(x)               (((x) & GENMASK(15, 8)) >> 8)

#define DDR_PHY_UDDR0_UDBEAT2(x)                 (((x) << 16) & GENMASK(23, 16))
#define DDR_PHY_UDDR0_UDBEAT2_M                  GENMASK(23, 16)
#define DDR_PHY_UDDR0_UDBEAT2_X(x)               (((x) & GENMASK(23, 16)) >> 16)

#define DDR_PHY_UDDR0_UDBEAT3(x)                 (((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_UDDR0_UDBEAT3_M                  GENMASK(31, 24)
#define DDR_PHY_UDDR0_UDBEAT3_X(x)               (((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:UDDR1 */
#define DDR_PHY_UDDR1(t)          (t + 0x224)

#define DDR_PHY_UDDR1_UDBEAT4(x)                 ((x) & GENMASK(7, 0))
#define DDR_PHY_UDDR1_UDBEAT4_M                  GENMASK(7, 0)
#define DDR_PHY_UDDR1_UDBEAT4_X(x)               ((x) & GENMASK(7, 0))

#define DDR_PHY_UDDR1_UDBEAT5(x)                 (((x) << 8) & GENMASK(15, 8))
#define DDR_PHY_UDDR1_UDBEAT5_M                  GENMASK(15, 8)
#define DDR_PHY_UDDR1_UDBEAT5_X(x)               (((x) & GENMASK(15, 8)) >> 8)

#define DDR_PHY_UDDR1_UDBEAT6(x)                 (((x) << 16) & GENMASK(23, 16))
#define DDR_PHY_UDDR1_UDBEAT6_M                  GENMASK(23, 16)
#define DDR_PHY_UDDR1_UDBEAT6_X(x)               (((x) & GENMASK(23, 16)) >> 16)

#define DDR_PHY_UDDR1_UDBEAT7(x)                 (((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_UDDR1_UDBEAT7_M                  GENMASK(31, 24)
#define DDR_PHY_UDDR1_UDBEAT7_X(x)               (((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:DTEDR0 */
#define DDR_PHY_DTEDR0(t)         (t + 0x230)

#define DDR_PHY_DTEDR0_DTWLMN(x)                 ((x) & GENMASK(8, 0))
#define DDR_PHY_DTEDR0_DTWLMN_M                  GENMASK(8, 0)
#define DDR_PHY_DTEDR0_DTWLMN_X(x)               ((x) & GENMASK(8, 0))

#define DDR_PHY_DTEDR0_DTWLMX(x)                 (((x) << 9) & GENMASK(17, 9))
#define DDR_PHY_DTEDR0_DTWLMX_M                  GENMASK(17, 9)
#define DDR_PHY_DTEDR0_DTWLMX_X(x)               (((x) & GENMASK(17, 9)) >> 9)

#define DDR_PHY_DTEDR0_DTWBMN(x)                 (((x) << 18) & GENMASK(23, 18))
#define DDR_PHY_DTEDR0_DTWBMN_M                  GENMASK(23, 18)
#define DDR_PHY_DTEDR0_DTWBMN_X(x)               (((x) & GENMASK(23, 18)) >> 18)

#define DDR_PHY_DTEDR0_DTWBMX(x)                 (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DTEDR0_DTWBMX_M                  GENMASK(29, 24)
#define DDR_PHY_DTEDR0_DTWBMX_X(x)               (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DTEDR0_DTEDR0_RESERVED_31_30(x)  (((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DTEDR0_DTEDR0_RESERVED_31_30_M   GENMASK(31, 30)
#define DDR_PHY_DTEDR0_DTEDR0_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DTEDR1 */
#define DDR_PHY_DTEDR1(t)         (t + 0x234)

#define DDR_PHY_DTEDR1_DTEDR1_DTRLMN(x)          ((x) & GENMASK(8, 0))
#define DDR_PHY_DTEDR1_DTEDR1_DTRLMN_M           GENMASK(8, 0)
#define DDR_PHY_DTEDR1_DTEDR1_DTRLMN_X(x)        ((x) & GENMASK(8, 0))

#define DDR_PHY_DTEDR1_DTEDR1_DTRLMX(x)          (((x) << 9) & GENMASK(17, 9))
#define DDR_PHY_DTEDR1_DTEDR1_DTRLMX_M           GENMASK(17, 9)
#define DDR_PHY_DTEDR1_DTEDR1_DTRLMX_X(x)        (((x) & GENMASK(17, 9)) >> 9)

#define DDR_PHY_DTEDR1_DTEDR1_DTRBMN(x)          (((x) << 18) & GENMASK(23, 18))
#define DDR_PHY_DTEDR1_DTEDR1_DTRBMN_M           GENMASK(23, 18)
#define DDR_PHY_DTEDR1_DTEDR1_DTRBMN_X(x)        (((x) & GENMASK(23, 18)) >> 18)

#define DDR_PHY_DTEDR1_DTEDR1_DTRBMX(x)          (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DTEDR1_DTEDR1_DTRBMX_M           GENMASK(29, 24)
#define DDR_PHY_DTEDR1_DTEDR1_DTRBMX_X(x)        (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DTEDR1_DTEDR1_RESERVED_31_30(x)  (((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DTEDR1_DTEDR1_RESERVED_31_30_M   GENMASK(31, 30)
#define DDR_PHY_DTEDR1_DTEDR1_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DTEDR2 */
#define DDR_PHY_DTEDR2(t)         (t + 0x238)

#define DDR_PHY_DTEDR2_DTEDR2_DTRLMN(x)          ((x) & GENMASK(8, 0))
#define DDR_PHY_DTEDR2_DTEDR2_DTRLMN_M           GENMASK(8, 0)
#define DDR_PHY_DTEDR2_DTEDR2_DTRLMN_X(x)        ((x) & GENMASK(8, 0))

#define DDR_PHY_DTEDR2_DTEDR2_DTRLMX(x)          (((x) << 9) & GENMASK(17, 9))
#define DDR_PHY_DTEDR2_DTEDR2_DTRLMX_M           GENMASK(17, 9)
#define DDR_PHY_DTEDR2_DTEDR2_DTRLMX_X(x)        (((x) & GENMASK(17, 9)) >> 9)

#define DDR_PHY_DTEDR2_DTEDR2_DTRBMN(x)          (((x) << 18) & GENMASK(23, 18))
#define DDR_PHY_DTEDR2_DTEDR2_DTRBMN_M           GENMASK(23, 18)
#define DDR_PHY_DTEDR2_DTEDR2_DTRBMN_X(x)        (((x) & GENMASK(23, 18)) >> 18)

#define DDR_PHY_DTEDR2_DTEDR2_DTRBMX(x)          (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DTEDR2_DTEDR2_DTRBMX_M           GENMASK(29, 24)
#define DDR_PHY_DTEDR2_DTEDR2_DTRBMX_X(x)        (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DTEDR2_DTEDR2_RESERVED_31_30(x)  (((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DTEDR2_DTEDR2_RESERVED_31_30_M   GENMASK(31, 30)
#define DDR_PHY_DTEDR2_DTEDR2_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:VTDR */
#define DDR_PHY_VTDR(t)           (t + 0x23c)

#define DDR_PHY_VTDR_DVREFMN(x)                  ((x) & GENMASK(5, 0))
#define DDR_PHY_VTDR_DVREFMN_M                   GENMASK(5, 0)
#define DDR_PHY_VTDR_DVREFMN_X(x)                ((x) & GENMASK(5, 0))

#define DDR_PHY_VTDR_VTDR_RESERVED_7_6(x)        (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_VTDR_VTDR_RESERVED_7_6_M         GENMASK(7, 6)
#define DDR_PHY_VTDR_VTDR_RESERVED_7_6_X(x)      (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_VTDR_DVREFMX(x)                  (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_VTDR_DVREFMX_M                   GENMASK(13, 8)
#define DDR_PHY_VTDR_DVREFMX_X(x)                (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_VTDR_VTDR_RESERVED_15_14(x)      (((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_VTDR_VTDR_RESERVED_15_14_M       GENMASK(15, 14)
#define DDR_PHY_VTDR_VTDR_RESERVED_15_14_X(x)    (((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_VTDR_HVREFMN(x)                  (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_VTDR_HVREFMN_M                   GENMASK(21, 16)
#define DDR_PHY_VTDR_HVREFMN_X(x)                (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_VTDR_VTDR_RESERVED_23_22(x)      (((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_VTDR_VTDR_RESERVED_23_22_M       GENMASK(23, 22)
#define DDR_PHY_VTDR_VTDR_RESERVED_23_22_X(x)    (((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_VTDR_HVREFMX(x)                  (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_VTDR_HVREFMX_M                   GENMASK(29, 24)
#define DDR_PHY_VTDR_HVREFMX_X(x)                (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_VTDR_VTDR_RESERVED_31_30(x)      (((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_VTDR_VTDR_RESERVED_31_30_M       GENMASK(31, 30)
#define DDR_PHY_VTDR_VTDR_RESERVED_31_30_X(x)    (((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:CATR0 */
#define DDR_PHY_CATR0(t)          (t + 0x240)

#define DDR_PHY_CATR0_CA1BYTE0(x)                ((x) & GENMASK(3, 0))
#define DDR_PHY_CATR0_CA1BYTE0_M                 GENMASK(3, 0)
#define DDR_PHY_CATR0_CA1BYTE0_X(x)              ((x) & GENMASK(3, 0))

#define DDR_PHY_CATR0_CA1BYTE1(x)                (((x) << 4) & GENMASK(7, 4))
#define DDR_PHY_CATR0_CA1BYTE1_M                 GENMASK(7, 4)
#define DDR_PHY_CATR0_CA1BYTE1_X(x)              (((x) & GENMASK(7, 4)) >> 4)

#define DDR_PHY_CATR0_CAADR(x)                   (((x) << 8) & GENMASK(12, 8))
#define DDR_PHY_CATR0_CAADR_M                    GENMASK(12, 8)
#define DDR_PHY_CATR0_CAADR_X(x)                 (((x) & GENMASK(12, 8)) >> 8)

#define DDR_PHY_CATR0_CATR0_RESERVED_15_13(x)    (((x) << 13) & GENMASK(15, 13))
#define DDR_PHY_CATR0_CATR0_RESERVED_15_13_M     GENMASK(15, 13)
#define DDR_PHY_CATR0_CATR0_RESERVED_15_13_X(x)  (((x) & GENMASK(15, 13)) >> 13)

#define DDR_PHY_CATR0_CACD(x)                    (((x) << 16) & GENMASK(20, 16))
#define DDR_PHY_CATR0_CACD_M                     GENMASK(20, 16)
#define DDR_PHY_CATR0_CACD_X(x)                  (((x) & GENMASK(20, 16)) >> 16)

#define DDR_PHY_CATR0_RESERVED_31_21(x)          (((x) << 21) & GENMASK(31, 21))
#define DDR_PHY_CATR0_RESERVED_31_21_M           GENMASK(31, 21)
#define DDR_PHY_CATR0_RESERVED_31_21_X(x)        (((x) & GENMASK(31, 21)) >> 21)

/*      DDR_PHY:DWC_DDRPHY_PUB:CATR1 */
#define DDR_PHY_CATR1(t)          (t + 0x244)

#define DDR_PHY_CATR1_CAENT(x)                   ((x) & GENMASK(3, 0))
#define DDR_PHY_CATR1_CAENT_M                    GENMASK(3, 0)
#define DDR_PHY_CATR1_CAENT_X(x)                 ((x) & GENMASK(3, 0))

#define DDR_PHY_CATR1_CAEXT(x)                   (((x) << 4) & GENMASK(7, 4))
#define DDR_PHY_CATR1_CAEXT_M                    GENMASK(7, 4)
#define DDR_PHY_CATR1_CAEXT_X(x)                 (((x) & GENMASK(7, 4)) >> 4)

#define DDR_PHY_CATR1_CACKEL(x)                  (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_CATR1_CACKEL_M                   GENMASK(11, 8)
#define DDR_PHY_CATR1_CACKEL_X(x)                (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_CATR1_CACKEH(x)                  (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_CATR1_CACKEH_M                   GENMASK(15, 12)
#define DDR_PHY_CATR1_CACKEH_X(x)                (((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_CATR1_CAMRZ(x)                   (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_CATR1_CAMRZ_M                    GENMASK(19, 16)
#define DDR_PHY_CATR1_CAMRZ_X(x)                 (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_CATR1_CA0BYTE0(x)                (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_CATR1_CA0BYTE0_M                 GENMASK(23, 20)
#define DDR_PHY_CATR1_CA0BYTE0_X(x)              (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_CATR1_CA0BYTE1(x)                (((x) << 24) & GENMASK(27, 24))
#define DDR_PHY_CATR1_CA0BYTE1_M                 GENMASK(27, 24)
#define DDR_PHY_CATR1_CA0BYTE1_X(x)              (((x) & GENMASK(27, 24)) >> 24)

#define DDR_PHY_CATR1_CATR1_RESERVED_31_28(x)    (((x) << 28) & GENMASK(31, 28))
#define DDR_PHY_CATR1_CATR1_RESERVED_31_28_M     GENMASK(31, 28)
#define DDR_PHY_CATR1_CATR1_RESERVED_31_28_X(x)  (((x) & GENMASK(31, 28)) >> 28)

/*      DDR_PHY:DWC_DDRPHY_PUB:DQSDR0 */
#define DDR_PHY_DQSDR0(t)         (t + 0x250)

#define DDR_PHY_DQSDR0_DFTDTEN(x)                ((x) & GENMASK(0, 0))
#define DDR_PHY_DQSDR0_DFTDTEN_M                 GENMASK(0, 0)
#define DDR_PHY_DQSDR0_DFTDTEN_X(x)              ((x) & GENMASK(0, 0))

#define DDR_PHY_DQSDR0_DFTDTMODE(x)              (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DQSDR0_DFTDTMODE_M               GENMASK(1, 1)
#define DDR_PHY_DQSDR0_DFTDTMODE_X(x)            (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DQSDR0_DFTUPMODE(x)              (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DQSDR0_DFTUPMODE_M               GENMASK(3, 2)
#define DDR_PHY_DQSDR0_DFTUPMODE_X(x)            (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DQSDR0_DFTGPULSE(x)              (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DQSDR0_DFTGPULSE_M               GENMASK(4, 4)
#define DDR_PHY_DQSDR0_DFTGPULSE_X(x)            (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DQSDR0_DFTSRMODE(x)              (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DQSDR0_DFTSRMODE_M               GENMASK(5, 5)
#define DDR_PHY_DQSDR0_DFTSRMODE_X(x)            (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DQSDR0_DFTPDMODE(x)              (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DQSDR0_DFTPDMODE_M               GENMASK(6, 6)
#define DDR_PHY_DQSDR0_DFTPDMODE_X(x)            (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DQSDR0_DQSDR0_RESERVED_7(x)      (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_DQSDR0_DQSDR0_RESERVED_7_M       GENMASK(7, 7)
#define DDR_PHY_DQSDR0_DQSDR0_RESERVED_7_X(x)    (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_DQSDR0_DFTUPDRD(x)               (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DQSDR0_DFTUPDRD_M                GENMASK(11, 8)
#define DDR_PHY_DQSDR0_DFTUPDRD_X(x)             (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DQSDR0_PHYUPDRD(x)               (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_DQSDR0_PHYUPDRD_M                GENMASK(15, 12)
#define DDR_PHY_DQSDR0_PHYUPDRD_X(x)             (((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_DQSDR0_CTLUPDRD(x)               (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DQSDR0_CTLUPDRD_M                GENMASK(19, 16)
#define DDR_PHY_DQSDR0_CTLUPDRD_X(x)             (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DQSDR0_DFTRDSPC(x)               (((x) << 20) & GENMASK(21, 20))
#define DDR_PHY_DQSDR0_DFTRDSPC_M                GENMASK(21, 20)
#define DDR_PHY_DQSDR0_DFTRDSPC_X(x)             (((x) & GENMASK(21, 20)) >> 20)

#define DDR_PHY_DQSDR0_DFTIDLRD(x)               (((x) << 22) & GENMASK(25, 22))
#define DDR_PHY_DQSDR0_DFTIDLRD_M                GENMASK(25, 22)
#define DDR_PHY_DQSDR0_DFTIDLRD_X(x)             (((x) & GENMASK(25, 22)) >> 22)

#define DDR_PHY_DQSDR0_DFTDDLUP(x)               (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_DQSDR0_DFTDDLUP_M                GENMASK(26, 26)
#define DDR_PHY_DQSDR0_DFTDDLUP_X(x)             (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_DQSDR0_DFTZQUP(x)                (((x) << 27) & GENMASK(27, 27))
#define DDR_PHY_DQSDR0_DFTZQUP_M                 GENMASK(27, 27)
#define DDR_PHY_DQSDR0_DFTZQUP_X(x)              (((x) & GENMASK(27, 27)) >> 27)

#define DDR_PHY_DQSDR0_DFTDLY(x)                 (((x) << 28) & GENMASK(31, 28))
#define DDR_PHY_DQSDR0_DFTDLY_M                  GENMASK(31, 28)
#define DDR_PHY_DQSDR0_DFTDLY_X(x)               (((x) & GENMASK(31, 28)) >> 28)

/*      DDR_PHY:DWC_DDRPHY_PUB:DQSDR1 */
#define DDR_PHY_DQSDR1(t)         (t + 0x254)

#define DDR_PHY_DQSDR1_DFTRDIDLC(x)              ((x) & GENMASK(7, 0))
#define DDR_PHY_DQSDR1_DFTRDIDLC_M               GENMASK(7, 0)
#define DDR_PHY_DQSDR1_DFTRDIDLC_X(x)            ((x) & GENMASK(7, 0))

#define DDR_PHY_DQSDR1_DFTRDB2BC(x)              (((x) << 8) & GENMASK(15, 8))
#define DDR_PHY_DQSDR1_DFTRDB2BC_M               GENMASK(15, 8)
#define DDR_PHY_DQSDR1_DFTRDB2BC_X(x)            (((x) & GENMASK(15, 8)) >> 8)

#define DDR_PHY_DQSDR1_DFTRDIDLF(x)              (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DQSDR1_DFTRDIDLF_M               GENMASK(19, 16)
#define DDR_PHY_DQSDR1_DFTRDIDLF_X(x)            (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DQSDR1_DFTRDB2BF(x)              (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DQSDR1_DFTRDB2BF_M               GENMASK(23, 20)
#define DDR_PHY_DQSDR1_DFTRDB2BF_X(x)            (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DQSDR1_PUDFTUP(x)                (((x) << 24) & GENMASK(24, 24))
#define DDR_PHY_DQSDR1_PUDFTUP_M                 GENMASK(24, 24)
#define DDR_PHY_DQSDR1_PUDFTUP_X(x)              (((x) & GENMASK(24, 24)) >> 24)

#define DDR_PHY_DQSDR1_CUDFTUP(x)                (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_DQSDR1_CUDFTUP_M                 GENMASK(25, 25)
#define DDR_PHY_DQSDR1_CUDFTUP_X(x)              (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_DQSDR1_DFTB2BRD(x)               (((x) << 26) & GENMASK(29, 26))
#define DDR_PHY_DQSDR1_DFTB2BRD_M                GENMASK(29, 26)
#define DDR_PHY_DQSDR1_DFTB2BRD_X(x)             (((x) & GENMASK(29, 26)) >> 26)

#define DDR_PHY_DQSDR1_DQSDR1_RESERVED_31_30(x)  (((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DQSDR1_DQSDR1_RESERVED_31_30_M   GENMASK(31, 30)
#define DDR_PHY_DQSDR1_DQSDR1_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DQSDR2 */
#define DDR_PHY_DQSDR2(t)         (t + 0x258)

#define DDR_PHY_DQSDR2_DFTMNTPRD(x)              ((x) & GENMASK(15, 0))
#define DDR_PHY_DQSDR2_DFTMNTPRD_M               GENMASK(15, 0)
#define DDR_PHY_DQSDR2_DFTMNTPRD_X(x)            ((x) & GENMASK(15, 0))

#define DDR_PHY_DQSDR2_DFTTHRSH(x)               (((x) << 16) & GENMASK(23, 16))
#define DDR_PHY_DQSDR2_DFTTHRSH_M                GENMASK(23, 16)
#define DDR_PHY_DQSDR2_DFTTHRSH_X(x)             (((x) & GENMASK(23, 16)) >> 16)

#define DDR_PHY_DQSDR2_DQSDR2_RESERVED_31_24(x)  (((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_DQSDR2_DQSDR2_RESERVED_31_24_M   GENMASK(31, 24)
#define DDR_PHY_DQSDR2_DQSDR2_RESERVED_31_24_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:DCUAR */
#define DDR_PHY_DCUAR(t)          (t + 0x300)

#define DDR_PHY_DCUAR_CWADDR_W(x)                ((x) & GENMASK(3, 0))
#define DDR_PHY_DCUAR_CWADDR_W_M                 GENMASK(3, 0)
#define DDR_PHY_DCUAR_CWADDR_W_X(x)              ((x) & GENMASK(3, 0))

#define DDR_PHY_DCUAR_CSADDR_W(x)                (((x) << 4) & GENMASK(7, 4))
#define DDR_PHY_DCUAR_CSADDR_W_M                 GENMASK(7, 4)
#define DDR_PHY_DCUAR_CSADDR_W_X(x)              (((x) & GENMASK(7, 4)) >> 4)

#define DDR_PHY_DCUAR_CSEL(x)                    (((x) << 8) & GENMASK(9, 8))
#define DDR_PHY_DCUAR_CSEL_M                     GENMASK(9, 8)
#define DDR_PHY_DCUAR_CSEL_X(x)                  (((x) & GENMASK(9, 8)) >> 8)

#define DDR_PHY_DCUAR_INCA(x)                    (((x) << 10) & GENMASK(10, 10))
#define DDR_PHY_DCUAR_INCA_M                     GENMASK(10, 10)
#define DDR_PHY_DCUAR_INCA_X(x)                  (((x) & GENMASK(10, 10)) >> 10)

#define DDR_PHY_DCUAR_ATYPE(x)                   (((x) << 11) & GENMASK(11, 11))
#define DDR_PHY_DCUAR_ATYPE_M                    GENMASK(11, 11)
#define DDR_PHY_DCUAR_ATYPE_X(x)                 (((x) & GENMASK(11, 11)) >> 11)

#define DDR_PHY_DCUAR_CWADDR_R(x)                (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_DCUAR_CWADDR_R_M                 GENMASK(15, 12)
#define DDR_PHY_DCUAR_CWADDR_R_X(x)              (((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_DCUAR_CSADDR_R(x)                (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DCUAR_CSADDR_R_M                 GENMASK(19, 16)
#define DDR_PHY_DCUAR_CSADDR_R_X(x)              (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DCUAR_DCUAR_RESERVED_31_20(x)    (((x) << 20) & GENMASK(31, 20))
#define DDR_PHY_DCUAR_DCUAR_RESERVED_31_20_M     GENMASK(31, 20)
#define DDR_PHY_DCUAR_DCUAR_RESERVED_31_20_X(x)  (((x) & GENMASK(31, 20)) >> 20)

/*      DDR_PHY:DWC_DDRPHY_PUB:DCUDR */
#define DDR_PHY_DCUDR(t)          (t + 0x304)

/*      DDR_PHY:DWC_DDRPHY_PUB:DCURR */
#define DDR_PHY_DCURR(t)          (t + 0x308)

#define DDR_PHY_DCURR_DINST(x)                   ((x) & GENMASK(3, 0))
#define DDR_PHY_DCURR_DINST_M                    GENMASK(3, 0)
#define DDR_PHY_DCURR_DINST_X(x)                 ((x) & GENMASK(3, 0))

#define DDR_PHY_DCURR_SADDR(x)                   (((x) << 4) & GENMASK(7, 4))
#define DDR_PHY_DCURR_SADDR_M                    GENMASK(7, 4)
#define DDR_PHY_DCURR_SADDR_X(x)                 (((x) & GENMASK(7, 4)) >> 4)

#define DDR_PHY_DCURR_EADDR(x)                   (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DCURR_EADDR_M                    GENMASK(11, 8)
#define DDR_PHY_DCURR_EADDR_X(x)                 (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DCURR_DCURR_NFAIL(x)             (((x) << 12) & GENMASK(19, 12))
#define DDR_PHY_DCURR_DCURR_NFAIL_M              GENMASK(19, 12)
#define DDR_PHY_DCURR_DCURR_NFAIL_X(x)           (((x) & GENMASK(19, 12)) >> 12)

#define DDR_PHY_DCURR_SONF(x)                    (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DCURR_SONF_M                     GENMASK(20, 20)
#define DDR_PHY_DCURR_SONF_X(x)                  (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DCURR_SCOF(x)                    (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DCURR_SCOF_M                     GENMASK(21, 21)
#define DDR_PHY_DCURR_SCOF_X(x)                  (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DCURR_RCEN(x)                    (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DCURR_RCEN_M                     GENMASK(22, 22)
#define DDR_PHY_DCURR_RCEN_X(x)                  (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DCURR_XCEN(x)                    (((x) << 23) & GENMASK(23, 23))
#define DDR_PHY_DCURR_XCEN_M                     GENMASK(23, 23)
#define DDR_PHY_DCURR_XCEN_X(x)                  (((x) & GENMASK(23, 23)) >> 23)

#define DDR_PHY_DCURR_DCURR_RESERVED_31_24(x)    (((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_DCURR_DCURR_RESERVED_31_24_M     GENMASK(31, 24)
#define DDR_PHY_DCURR_DCURR_RESERVED_31_24_X(x)  (((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:DCULR */
#define DDR_PHY_DCULR(t)          (t + 0x30c)

#define DDR_PHY_DCULR_LSADDR(x)                  ((x) & GENMASK(3, 0))
#define DDR_PHY_DCULR_LSADDR_M                   GENMASK(3, 0)
#define DDR_PHY_DCULR_LSADDR_X(x)                ((x) & GENMASK(3, 0))

#define DDR_PHY_DCULR_LEADDR(x)                  (((x) << 4) & GENMASK(7, 4))
#define DDR_PHY_DCULR_LEADDR_M                   GENMASK(7, 4)
#define DDR_PHY_DCULR_LEADDR_X(x)                (((x) & GENMASK(7, 4)) >> 4)

#define DDR_PHY_DCULR_LCNT(x)                    (((x) << 8) & GENMASK(15, 8))
#define DDR_PHY_DCULR_LCNT_M                     GENMASK(15, 8)
#define DDR_PHY_DCULR_LCNT_X(x)                  (((x) & GENMASK(15, 8)) >> 8)

#define DDR_PHY_DCULR_LINF(x)                    (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DCULR_LINF_M                     GENMASK(16, 16)
#define DDR_PHY_DCULR_LINF_X(x)                  (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DCULR_IDA(x)                     (((x) << 17) & GENMASK(17, 17))
#define DDR_PHY_DCULR_IDA_M                      GENMASK(17, 17)
#define DDR_PHY_DCULR_IDA_X(x)                   (((x) & GENMASK(17, 17)) >> 17)

#define DDR_PHY_DCULR_RESERVED_27_18(x)          (((x) << 18) & GENMASK(27, 18))
#define DDR_PHY_DCULR_RESERVED_27_18_M           GENMASK(27, 18)
#define DDR_PHY_DCULR_RESERVED_27_18_X(x)        (((x) & GENMASK(27, 18)) >> 18)

#define DDR_PHY_DCULR_XLEADDR(x)                 (((x) << 28) & GENMASK(31, 28))
#define DDR_PHY_DCULR_XLEADDR_M                  GENMASK(31, 28)
#define DDR_PHY_DCULR_XLEADDR_X(x)               (((x) & GENMASK(31, 28)) >> 28)

/*      DDR_PHY:DWC_DDRPHY_PUB:DCUGCR */
#define DDR_PHY_DCUGCR(t)         (t + 0x310)

#define DDR_PHY_DCUGCR_RCSW(x)                   ((x) & GENMASK(15, 0))
#define DDR_PHY_DCUGCR_RCSW_M                    GENMASK(15, 0)
#define DDR_PHY_DCUGCR_RCSW_X(x)                 ((x) & GENMASK(15, 0))

#define DDR_PHY_DCUGCR_DCUGCR_RESERVED_31_16(x)  (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DCUGCR_DCUGCR_RESERVED_31_16_M   GENMASK(31, 16)
#define DDR_PHY_DCUGCR_DCUGCR_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DCUTPR */
#define DDR_PHY_DCUTPR(t)         (t + 0x314)

#define DDR_PHY_DCUTPR_TDCUT0(x)                 ((x) & GENMASK(7, 0))
#define DDR_PHY_DCUTPR_TDCUT0_M                  GENMASK(7, 0)
#define DDR_PHY_DCUTPR_TDCUT0_X(x)               ((x) & GENMASK(7, 0))

#define DDR_PHY_DCUTPR_TDCUT1(x)                 (((x) << 8) & GENMASK(15, 8))
#define DDR_PHY_DCUTPR_TDCUT1_M                  GENMASK(15, 8)
#define DDR_PHY_DCUTPR_TDCUT1_X(x)               (((x) & GENMASK(15, 8)) >> 8)

#define DDR_PHY_DCUTPR_TDCUT2(x)                 (((x) << 16) & GENMASK(23, 16))
#define DDR_PHY_DCUTPR_TDCUT2_M                  GENMASK(23, 16)
#define DDR_PHY_DCUTPR_TDCUT2_X(x)               (((x) & GENMASK(23, 16)) >> 16)

#define DDR_PHY_DCUTPR_DCUTPR_RESERVED_31_24(x)  (((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_DCUTPR_DCUTPR_RESERVED_31_24_M   GENMASK(31, 24)
#define DDR_PHY_DCUTPR_DCUTPR_RESERVED_31_24_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:DCUSR0 */
#define DDR_PHY_DCUSR0(t)         (t + 0x318)

#define DDR_PHY_DCUSR0_RDONE(x)                  ((x) & GENMASK(0, 0))
#define DDR_PHY_DCUSR0_RDONE_M                   GENMASK(0, 0)
#define DDR_PHY_DCUSR0_RDONE_X(x)                ((x) & GENMASK(0, 0))

#define DDR_PHY_DCUSR0_CFAIL(x)                  (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DCUSR0_CFAIL_M                   GENMASK(1, 1)
#define DDR_PHY_DCUSR0_CFAIL_X(x)                (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DCUSR0_CFULL(x)                  (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DCUSR0_CFULL_M                   GENMASK(2, 2)
#define DDR_PHY_DCUSR0_CFULL_X(x)                (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DCUSR0_RESERVED_31_3(x)          (((x) << 3) & GENMASK(31, 3))
#define DDR_PHY_DCUSR0_RESERVED_31_3_M           GENMASK(31, 3)
#define DDR_PHY_DCUSR0_RESERVED_31_3_X(x)        (((x) & GENMASK(31, 3)) >> 3)

/*      DDR_PHY:DWC_DDRPHY_PUB:DCUSR1 */
#define DDR_PHY_DCUSR1(t)         (t + 0x31c)

#define DDR_PHY_DCUSR1_RDCNT(x)                  ((x) & GENMASK(15, 0))
#define DDR_PHY_DCUSR1_RDCNT_M                   GENMASK(15, 0)
#define DDR_PHY_DCUSR1_RDCNT_X(x)                ((x) & GENMASK(15, 0))

#define DDR_PHY_DCUSR1_FLCNT(x)                  (((x) << 16) & GENMASK(23, 16))
#define DDR_PHY_DCUSR1_FLCNT_M                   GENMASK(23, 16)
#define DDR_PHY_DCUSR1_FLCNT_X(x)                (((x) & GENMASK(23, 16)) >> 16)

#define DDR_PHY_DCUSR1_LPCNT(x)                  (((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_DCUSR1_LPCNT_M                   GENMASK(31, 24)
#define DDR_PHY_DCUSR1_LPCNT_X(x)                (((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:BISTRR */
#define DDR_PHY_BISTRR(t)         (t + 0x400)

#define DDR_PHY_BISTRR_BINST(x)                  ((x) & GENMASK(2, 0))
#define DDR_PHY_BISTRR_BINST_M                   GENMASK(2, 0)
#define DDR_PHY_BISTRR_BINST_X(x)                ((x) & GENMASK(2, 0))

#define DDR_PHY_BISTRR_BMODE(x)                  (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_BISTRR_BMODE_M                   GENMASK(3, 3)
#define DDR_PHY_BISTRR_BMODE_X(x)                (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_BISTRR_BINF(x)                   (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_BISTRR_BINF_M                    GENMASK(4, 4)
#define DDR_PHY_BISTRR_BINF_X(x)                 (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_BISTRR_BISTRR_NFAIL(x)           (((x) << 5) & GENMASK(12, 5))
#define DDR_PHY_BISTRR_BISTRR_NFAIL_M            GENMASK(12, 5)
#define DDR_PHY_BISTRR_BISTRR_NFAIL_X(x)         (((x) & GENMASK(12, 5)) >> 5)

#define DDR_PHY_BISTRR_BSONF(x)                  (((x) << 13) & GENMASK(13, 13))
#define DDR_PHY_BISTRR_BSONF_M                   GENMASK(13, 13)
#define DDR_PHY_BISTRR_BSONF_X(x)                (((x) & GENMASK(13, 13)) >> 13)

#define DDR_PHY_BISTRR_BDXEN(x)                  (((x) << 14) & GENMASK(14, 14))
#define DDR_PHY_BISTRR_BDXEN_M                   GENMASK(14, 14)
#define DDR_PHY_BISTRR_BDXEN_X(x)                (((x) & GENMASK(14, 14)) >> 14)

#define DDR_PHY_BISTRR_BACEN(x)                  (((x) << 15) & GENMASK(15, 15))
#define DDR_PHY_BISTRR_BACEN_M                   GENMASK(15, 15)
#define DDR_PHY_BISTRR_BACEN_X(x)                (((x) & GENMASK(15, 15)) >> 15)

#define DDR_PHY_BISTRR_BDMEN(x)                  (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_BISTRR_BDMEN_M                   GENMASK(16, 16)
#define DDR_PHY_BISTRR_BDMEN_X(x)                (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_BISTRR_BDPAT(x)                  (((x) << 17) & GENMASK(21, 17))
#define DDR_PHY_BISTRR_BDPAT_M                   GENMASK(21, 17)
#define DDR_PHY_BISTRR_BDPAT_X(x)                (((x) & GENMASK(21, 17)) >> 17)

#define DDR_PHY_BISTRR_BDXSEL(x)                 (((x) << 22) & GENMASK(25, 22))
#define DDR_PHY_BISTRR_BDXSEL_M                  GENMASK(25, 22)
#define DDR_PHY_BISTRR_BDXSEL_X(x)               (((x) & GENMASK(25, 22)) >> 22)

#define DDR_PHY_BISTRR_BCKSEL(x)                 (((x) << 26) & GENMASK(27, 26))
#define DDR_PHY_BISTRR_BCKSEL_M                  GENMASK(27, 26)
#define DDR_PHY_BISTRR_BCKSEL_X(x)               (((x) & GENMASK(27, 26)) >> 26)

#define DDR_PHY_BISTRR_BCCSEL(x)                 (((x) << 28) & GENMASK(29, 28))
#define DDR_PHY_BISTRR_BCCSEL_M                  GENMASK(29, 28)
#define DDR_PHY_BISTRR_BCCSEL_X(x)               (((x) & GENMASK(29, 28)) >> 28)

#define DDR_PHY_BISTRR_BSOMA(x)                  (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_BISTRR_BSOMA_M                   GENMASK(30, 30)
#define DDR_PHY_BISTRR_BSOMA_X(x)                (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_BISTRR_BISTRR_RESERVED_31(x)     (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_BISTRR_BISTRR_RESERVED_31_M      GENMASK(31, 31)
#define DDR_PHY_BISTRR_BISTRR_RESERVED_31_X(x)   (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:BISTWCR */
#define DDR_PHY_BISTWCR(t)        (t + 0x404)

#define DDR_PHY_BISTWCR_BWCNT(x)                 ((x) & GENMASK(15, 0))
#define DDR_PHY_BISTWCR_BWCNT_M                  GENMASK(15, 0)
#define DDR_PHY_BISTWCR_BWCNT_X(x)               ((x) & GENMASK(15, 0))

#define DDR_PHY_BISTWCR_BISTWCR_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_BISTWCR_BISTWCR_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_BISTWCR_BISTWCR_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:BISTMSKR0 */
#define DDR_PHY_BISTMSKR0(t)      (t + 0x408)

#define DDR_PHY_BISTMSKR0_AMSK(x)                ((x) & GENMASK(17, 0))
#define DDR_PHY_BISTMSKR0_AMSK_M                 GENMASK(17, 0)
#define DDR_PHY_BISTMSKR0_AMSK_X(x)              ((x) & GENMASK(17, 0))

#define DDR_PHY_BISTMSKR0_BISTMSKR0_RESERVED_18(x)\
	(((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_BISTMSKR0_BISTMSKR0_RESERVED_18_M GENMASK(18, 18)
#define DDR_PHY_BISTMSKR0_BISTMSKR0_RESERVED_18_X(x)\
	(((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_BISTMSKR0_ACTMSK(x)              (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_BISTMSKR0_ACTMSK_M               GENMASK(19, 19)
#define DDR_PHY_BISTMSKR0_ACTMSK_X(x)            (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_BISTMSKR0_CSMSK(x)               (((x) << 20) & GENMASK(21, 20))
#define DDR_PHY_BISTMSKR0_CSMSK_M                GENMASK(21, 20)
#define DDR_PHY_BISTMSKR0_CSMSK_X(x)             (((x) & GENMASK(21, 20)) >> 20)

#define DDR_PHY_BISTMSKR0_CSMSK_RSVD(x)          (((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_BISTMSKR0_CSMSK_RSVD_M           GENMASK(31, 22)
#define DDR_PHY_BISTMSKR0_CSMSK_RSVD_X(x)        (((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:BISTMSKR1 */
#define DDR_PHY_BISTMSKR1(t)      (t + 0x40c)

#define DDR_PHY_BISTMSKR1_X4DMMSK(x)             ((x) & GENMASK(3, 0))
#define DDR_PHY_BISTMSKR1_X4DMMSK_M              GENMASK(3, 0)
#define DDR_PHY_BISTMSKR1_X4DMMSK_X(x)           ((x) & GENMASK(3, 0))

#define DDR_PHY_BISTMSKR1_BAMSK(x)               (((x) << 4) & GENMASK(7, 4))
#define DDR_PHY_BISTMSKR1_BAMSK_M                GENMASK(7, 4)
#define DDR_PHY_BISTMSKR1_BAMSK_X(x)             (((x) & GENMASK(7, 4)) >> 4)

#define DDR_PHY_BISTMSKR1_CKEMSK(x)              (((x) << 8) & GENMASK(9, 8))
#define DDR_PHY_BISTMSKR1_CKEMSK_M               GENMASK(9, 8)
#define DDR_PHY_BISTMSKR1_CKEMSK_X(x)            (((x) & GENMASK(9, 8)) >> 8)

#define DDR_PHY_BISTMSKR1_CKEMSK_RSVD(x)         (((x) << 10) & GENMASK(15, 10))
#define DDR_PHY_BISTMSKR1_CKEMSK_RSVD_M          GENMASK(15, 10)
#define DDR_PHY_BISTMSKR1_CKEMSK_RSVD_X(x)       (((x) & GENMASK(15, 10)) >> 10)

#define DDR_PHY_BISTMSKR1_ODTMSK(x)              (((x) << 16) & GENMASK(17, 16))
#define DDR_PHY_BISTMSKR1_ODTMSK_M               GENMASK(17, 16)
#define DDR_PHY_BISTMSKR1_ODTMSK_X(x)            (((x) & GENMASK(17, 16)) >> 16)

#define DDR_PHY_BISTMSKR1_ODTMSK_RSVD(x)         (((x) << 18) & GENMASK(23, 18))
#define DDR_PHY_BISTMSKR1_ODTMSK_RSVD_M          GENMASK(23, 18)
#define DDR_PHY_BISTMSKR1_ODTMSK_RSVD_X(x)       (((x) & GENMASK(23, 18)) >> 18)

#define DDR_PHY_BISTMSKR1_CIDMSK(x)              (((x) << 24) & GENMASK(24, 24))
#define DDR_PHY_BISTMSKR1_CIDMSK_M               GENMASK(24, 24)
#define DDR_PHY_BISTMSKR1_CIDMSK_X(x)            (((x) & GENMASK(24, 24)) >> 24)

#define DDR_PHY_BISTMSKR1_CIDMSK_RSVD(x)         (((x) << 25) & GENMASK(26, 25))
#define DDR_PHY_BISTMSKR1_CIDMSK_RSVD_M          GENMASK(26, 25)
#define DDR_PHY_BISTMSKR1_CIDMSK_RSVD_X(x)       (((x) & GENMASK(26, 25)) >> 25)

#define DDR_PHY_BISTMSKR1_PARINMSK(x)            (((x) << 27) & GENMASK(27, 27))
#define DDR_PHY_BISTMSKR1_PARINMSK_M             GENMASK(27, 27)
#define DDR_PHY_BISTMSKR1_PARINMSK_X(x)          (((x) & GENMASK(27, 27)) >> 27)

#define DDR_PHY_BISTMSKR1_DMMSK(x)               (((x) << 28) & GENMASK(31, 28))
#define DDR_PHY_BISTMSKR1_DMMSK_M                GENMASK(31, 28)
#define DDR_PHY_BISTMSKR1_DMMSK_X(x)             (((x) & GENMASK(31, 28)) >> 28)

/*      DDR_PHY:DWC_DDRPHY_PUB:BISTMSKR2 */
#define DDR_PHY_BISTMSKR2(t)      (t + 0x410)

/*      DDR_PHY:DWC_DDRPHY_PUB:BISTLSR */
#define DDR_PHY_BISTLSR(t)        (t + 0x414)

/*      DDR_PHY:DWC_DDRPHY_PUB:BISTAR0 */
#define DDR_PHY_BISTAR0(t)        (t + 0x418)

#define DDR_PHY_BISTAR0_BCOL(x)                  ((x) & GENMASK(11, 0))
#define DDR_PHY_BISTAR0_BCOL_M                   GENMASK(11, 0)
#define DDR_PHY_BISTAR0_BCOL_X(x)                ((x) & GENMASK(11, 0))

#define DDR_PHY_BISTAR0_BISTAR0_RESERVED_27_12(x)\
	(((x) << 12) & GENMASK(27, 12))
#define DDR_PHY_BISTAR0_BISTAR0_RESERVED_27_12_M GENMASK(27, 12)
#define DDR_PHY_BISTAR0_BISTAR0_RESERVED_27_12_X(x)\
	(((x) & GENMASK(27, 12)) >> 12)

#define DDR_PHY_BISTAR0_BBANK(x)                 (((x) << 28) & GENMASK(31, 28))
#define DDR_PHY_BISTAR0_BBANK_M                  GENMASK(31, 28)
#define DDR_PHY_BISTAR0_BBANK_X(x)               (((x) & GENMASK(31, 28)) >> 28)

/*      DDR_PHY:DWC_DDRPHY_PUB:BISTAR1 */
#define DDR_PHY_BISTAR1(t)        (t + 0x41c)

#define DDR_PHY_BISTAR1_BRANK(x)                 ((x) & GENMASK(3, 0))
#define DDR_PHY_BISTAR1_BRANK_M                  GENMASK(3, 0)
#define DDR_PHY_BISTAR1_BRANK_X(x)               ((x) & GENMASK(3, 0))

#define DDR_PHY_BISTAR1_BAINC(x)                 (((x) << 4) & GENMASK(15, 4))
#define DDR_PHY_BISTAR1_BAINC_M                  GENMASK(15, 4)
#define DDR_PHY_BISTAR1_BAINC_X(x)               (((x) & GENMASK(15, 4)) >> 4)

#define DDR_PHY_BISTAR1_BMRANK(x)                (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_BISTAR1_BMRANK_M                 GENMASK(19, 16)
#define DDR_PHY_BISTAR1_BMRANK_X(x)              (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_BISTAR1_BISTAR1_RESERVED_31_20(x)\
	(((x) << 20) & GENMASK(31, 20))
#define DDR_PHY_BISTAR1_BISTAR1_RESERVED_31_20_M GENMASK(31, 20)
#define DDR_PHY_BISTAR1_BISTAR1_RESERVED_31_20_X(x)\
	(((x) & GENMASK(31, 20)) >> 20)

/*      DDR_PHY:DWC_DDRPHY_PUB:BISTAR2 */
#define DDR_PHY_BISTAR2(t)        (t + 0x420)

#define DDR_PHY_BISTAR2_BMCOL(x)                 ((x) & GENMASK(11, 0))
#define DDR_PHY_BISTAR2_BMCOL_M                  GENMASK(11, 0)
#define DDR_PHY_BISTAR2_BMCOL_X(x)               ((x) & GENMASK(11, 0))

#define DDR_PHY_BISTAR2_BISTAR2_RESERVED_27_12(x)\
	(((x) << 12) & GENMASK(27, 12))
#define DDR_PHY_BISTAR2_BISTAR2_RESERVED_27_12_M GENMASK(27, 12)
#define DDR_PHY_BISTAR2_BISTAR2_RESERVED_27_12_X(x)\
	(((x) & GENMASK(27, 12)) >> 12)

#define DDR_PHY_BISTAR2_BMBANK(x)                (((x) << 28) & GENMASK(31, 28))
#define DDR_PHY_BISTAR2_BMBANK_M                 GENMASK(31, 28)
#define DDR_PHY_BISTAR2_BMBANK_X(x)              (((x) & GENMASK(31, 28)) >> 28)

/*      DDR_PHY:DWC_DDRPHY_PUB:BISTAR3 */
#define DDR_PHY_BISTAR3(t)        (t + 0x424)

#define DDR_PHY_BISTAR3_BROW(x)                  ((x) & GENMASK(17, 0))
#define DDR_PHY_BISTAR3_BROW_M                   GENMASK(17, 0)
#define DDR_PHY_BISTAR3_BROW_X(x)                ((x) & GENMASK(17, 0))

#define DDR_PHY_BISTAR3_BISTAR3_RESERVED_31_18(x)\
	(((x) << 18) & GENMASK(31, 18))
#define DDR_PHY_BISTAR3_BISTAR3_RESERVED_31_18_M GENMASK(31, 18)
#define DDR_PHY_BISTAR3_BISTAR3_RESERVED_31_18_X(x)\
	(((x) & GENMASK(31, 18)) >> 18)

/*      DDR_PHY:DWC_DDRPHY_PUB:BISTAR4 */
#define DDR_PHY_BISTAR4(t)        (t + 0x428)

#define DDR_PHY_BISTAR4_BMROW(x)                 ((x) & GENMASK(17, 0))
#define DDR_PHY_BISTAR4_BMROW_M                  GENMASK(17, 0)
#define DDR_PHY_BISTAR4_BMROW_X(x)               ((x) & GENMASK(17, 0))

#define DDR_PHY_BISTAR4_BISTAR4_RESERVED_31_18(x)\
	(((x) << 18) & GENMASK(31, 18))
#define DDR_PHY_BISTAR4_BISTAR4_RESERVED_31_18_M GENMASK(31, 18)
#define DDR_PHY_BISTAR4_BISTAR4_RESERVED_31_18_X(x)\
	(((x) & GENMASK(31, 18)) >> 18)

/*      DDR_PHY:DWC_DDRPHY_PUB:BISTUDPR */
#define DDR_PHY_BISTUDPR(t)       (t + 0x42c)

#define DDR_PHY_BISTUDPR_BUDP0(x)                ((x) & GENMASK(15, 0))
#define DDR_PHY_BISTUDPR_BUDP0_M                 GENMASK(15, 0)
#define DDR_PHY_BISTUDPR_BUDP0_X(x)              ((x) & GENMASK(15, 0))

#define DDR_PHY_BISTUDPR_BUDP1(x)                (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_BISTUDPR_BUDP1_M                 GENMASK(31, 16)
#define DDR_PHY_BISTUDPR_BUDP1_X(x)              (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:BISTGSR */
#define DDR_PHY_BISTGSR(t)        (t + 0x430)

#define DDR_PHY_BISTGSR_BDONE(x)                 ((x) & GENMASK(0, 0))
#define DDR_PHY_BISTGSR_BDONE_M                  GENMASK(0, 0)
#define DDR_PHY_BISTGSR_BDONE_X(x)               ((x) & GENMASK(0, 0))

#define DDR_PHY_BISTGSR_BACERR(x)                (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_BISTGSR_BACERR_M                 GENMASK(1, 1)
#define DDR_PHY_BISTGSR_BACERR_X(x)              (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_BISTGSR_BDXERR(x)                (((x) << 2) & GENMASK(10, 2))
#define DDR_PHY_BISTGSR_BDXERR_M                 GENMASK(10, 2)
#define DDR_PHY_BISTGSR_BDXERR_X(x)              (((x) & GENMASK(10, 2)) >> 2)

#define DDR_PHY_BISTGSR_X4DMBER(x)               (((x) << 11) & GENMASK(14, 11))
#define DDR_PHY_BISTGSR_X4DMBER_M                GENMASK(14, 11)
#define DDR_PHY_BISTGSR_X4DMBER_X(x)             (((x) & GENMASK(14, 11)) >> 11)

#define DDR_PHY_BISTGSR_RESERVED_19_15(x)        (((x) << 15) & GENMASK(19, 15))
#define DDR_PHY_BISTGSR_RESERVED_19_15_M         GENMASK(19, 15)
#define DDR_PHY_BISTGSR_RESERVED_19_15_X(x)      (((x) & GENMASK(19, 15)) >> 15)

#define DDR_PHY_BISTGSR_DMBER(x)                 (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_BISTGSR_DMBER_M                  GENMASK(23, 20)
#define DDR_PHY_BISTGSR_DMBER_X(x)               (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_BISTGSR_BISTGSR_RESERVED_27_24(x)\
	(((x) << 24) & GENMASK(27, 24))
#define DDR_PHY_BISTGSR_BISTGSR_RESERVED_27_24_M GENMASK(27, 24)
#define DDR_PHY_BISTGSR_BISTGSR_RESERVED_27_24_X(x)\
	(((x) & GENMASK(27, 24)) >> 24)

#define DDR_PHY_BISTGSR_RASBER(x)                (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_BISTGSR_RASBER_M                 GENMASK(28, 28)
#define DDR_PHY_BISTGSR_RASBER_X(x)              (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_BISTGSR_RESERVED_29(x)           (((x) << 29) & GENMASK(29, 29))
#define DDR_PHY_BISTGSR_RESERVED_29_M            GENMASK(29, 29)
#define DDR_PHY_BISTGSR_RESERVED_29_X(x)         (((x) & GENMASK(29, 29)) >> 29)

#define DDR_PHY_BISTGSR_PARBER(x)                (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_BISTGSR_PARBER_M                 GENMASK(30, 30)
#define DDR_PHY_BISTGSR_PARBER_X(x)              (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_BISTGSR_BISTGSR_RESERVED_31(x)   (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_BISTGSR_BISTGSR_RESERVED_31_M    GENMASK(31, 31)
#define DDR_PHY_BISTGSR_BISTGSR_RESERVED_31_X(x) (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:BISTWER0 */
#define DDR_PHY_BISTWER0(t)       (t + 0x434)

#define DDR_PHY_BISTWER0_ACWER(x)                ((x) & GENMASK(17, 0))
#define DDR_PHY_BISTWER0_ACWER_M                 GENMASK(17, 0)
#define DDR_PHY_BISTWER0_ACWER_X(x)              ((x) & GENMASK(17, 0))

#define DDR_PHY_BISTWER0_BISTWER0_RESERVED_31_18(x)\
	(((x) << 18) & GENMASK(31, 18))
#define DDR_PHY_BISTWER0_BISTWER0_RESERVED_31_18_M GENMASK(31, 18)
#define DDR_PHY_BISTWER0_BISTWER0_RESERVED_31_18_X(x)\
	(((x) & GENMASK(31, 18)) >> 18)

/*      DDR_PHY:DWC_DDRPHY_PUB:BISTWER1 */
#define DDR_PHY_BISTWER1(t)       (t + 0x438)

#define DDR_PHY_BISTWER1_DXWER(x)                ((x) & GENMASK(15, 0))
#define DDR_PHY_BISTWER1_DXWER_M                 GENMASK(15, 0)
#define DDR_PHY_BISTWER1_DXWER_X(x)              ((x) & GENMASK(15, 0))

#define DDR_PHY_BISTWER1_BISTWER1_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_BISTWER1_BISTWER1_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_BISTWER1_BISTWER1_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:BISTBER0 */
#define DDR_PHY_BISTBER0(t)       (t + 0x43c)

#define DDR_PHY_BISTBER0_BISTBER0_ABER(x)        ((x) & GENMASK(15, 0))
#define DDR_PHY_BISTBER0_BISTBER0_ABER_M         GENMASK(15, 0)
#define DDR_PHY_BISTBER0_BISTBER0_ABER_X(x)      ((x) & GENMASK(15, 0))

#define DDR_PHY_BISTBER0_BISTBER0_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_BISTBER0_BISTBER0_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_BISTBER0_BISTBER0_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:BISTBER1 */
#define DDR_PHY_BISTBER1(t)       (t + 0x440)

#define DDR_PHY_BISTBER1_BABER(x)                ((x) & GENMASK(3, 0))
#define DDR_PHY_BISTBER1_BABER_M                 GENMASK(3, 0)
#define DDR_PHY_BISTBER1_BABER_X(x)              ((x) & GENMASK(3, 0))

#define DDR_PHY_BISTBER1_BISTBER1_RESERVED_7_4(x) (((x) << 4) & GENMASK(7, 4))
#define DDR_PHY_BISTBER1_BISTBER1_RESERVED_7_4_M GENMASK(7, 4)
#define DDR_PHY_BISTBER1_BISTBER1_RESERVED_7_4_X(x) (((x) & GENMASK(7, 4)) >> 4)

#define DDR_PHY_BISTBER1_CSBER(x)                (((x) << 8) & GENMASK(19, 8))
#define DDR_PHY_BISTBER1_CSBER_M                 GENMASK(19, 8)
#define DDR_PHY_BISTBER1_CSBER_X(x)              (((x) & GENMASK(19, 8)) >> 8)

#define DDR_PHY_BISTBER1_BISTBER1_RESERVED_31_20(x)\
	(((x) << 20) & GENMASK(31, 20))
#define DDR_PHY_BISTBER1_BISTBER1_RESERVED_31_20_M GENMASK(31, 20)
#define DDR_PHY_BISTBER1_BISTBER1_RESERVED_31_20_X(x)\
	(((x) & GENMASK(31, 20)) >> 20)

/*      DDR_PHY:DWC_DDRPHY_PUB:BISTBER2 */
#define DDR_PHY_BISTBER2(t)       (t + 0x444)

#define DDR_PHY_BISTBER2_DQBER0(x)               ((x) & GENMASK(15, 0))
#define DDR_PHY_BISTBER2_DQBER0_M                GENMASK(15, 0)
#define DDR_PHY_BISTBER2_DQBER0_X(x)             ((x) & GENMASK(15, 0))

#define DDR_PHY_BISTBER2_BISTBER2_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_BISTBER2_BISTBER2_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_BISTBER2_BISTBER2_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:BISTBER3 */
#define DDR_PHY_BISTBER3(t)       (t + 0x448)

#define DDR_PHY_BISTBER3_DQBER1(x)               ((x) & GENMASK(15, 0))
#define DDR_PHY_BISTBER3_DQBER1_M                GENMASK(15, 0)
#define DDR_PHY_BISTBER3_DQBER1_X(x)             ((x) & GENMASK(15, 0))

#define DDR_PHY_BISTBER3_BISTBER3_RESERVED_31_16(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_BISTBER3_BISTBER3_RESERVED_31_16_M GENMASK(31, 16)
#define DDR_PHY_BISTBER3_BISTBER3_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:BISTBER4 */
#define DDR_PHY_BISTBER4(t)       (t + 0x44c)

#define DDR_PHY_BISTBER4_BISTBER4_ABER(x)        ((x) & GENMASK(1, 0))
#define DDR_PHY_BISTBER4_BISTBER4_ABER_M         GENMASK(1, 0)
#define DDR_PHY_BISTBER4_BISTBER4_ABER_X(x)      ((x) & GENMASK(1, 0))

#define DDR_PHY_BISTBER4_BISTBER4_RESERVED_7_2(x) (((x) << 2) & GENMASK(7, 2))
#define DDR_PHY_BISTBER4_BISTBER4_RESERVED_7_2_M GENMASK(7, 2)
#define DDR_PHY_BISTBER4_BISTBER4_RESERVED_7_2_X(x) (((x) & GENMASK(7, 2)) >> 2)

#define DDR_PHY_BISTBER4_CIDBER(x)               (((x) << 8) & GENMASK(10, 8))
#define DDR_PHY_BISTBER4_CIDBER_M                GENMASK(10, 8)
#define DDR_PHY_BISTBER4_CIDBER_X(x)             (((x) & GENMASK(10, 8)) >> 8)

#define DDR_PHY_BISTBER4_RESERVED_31_11(x)       (((x) << 11) & GENMASK(31, 11))
#define DDR_PHY_BISTBER4_RESERVED_31_11_M        GENMASK(31, 11)
#define DDR_PHY_BISTBER4_RESERVED_31_11_X(x)     (((x) & GENMASK(31, 11)) >> 11)

/*      DDR_PHY:DWC_DDRPHY_PUB:BISTWCSR */
#define DDR_PHY_BISTWCSR(t)       (t + 0x450)

#define DDR_PHY_BISTWCSR_ACWCNT(x)               ((x) & GENMASK(15, 0))
#define DDR_PHY_BISTWCSR_ACWCNT_M                GENMASK(15, 0)
#define DDR_PHY_BISTWCSR_ACWCNT_X(x)             ((x) & GENMASK(15, 0))

#define DDR_PHY_BISTWCSR_DXWCNT(x)               (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_BISTWCSR_DXWCNT_M                GENMASK(31, 16)
#define DDR_PHY_BISTWCSR_DXWCNT_X(x)             (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:BISTFWR0 */
#define DDR_PHY_BISTFWR0(t)       (t + 0x454)

#define DDR_PHY_BISTFWR0_AWEBS(x)                ((x) & GENMASK(17, 0))
#define DDR_PHY_BISTFWR0_AWEBS_M                 GENMASK(17, 0)
#define DDR_PHY_BISTFWR0_AWEBS_X(x)              ((x) & GENMASK(17, 0))

#define DDR_PHY_BISTFWR0_ACTWEBS(x)              (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_BISTFWR0_ACTWEBS_M               GENMASK(18, 18)
#define DDR_PHY_BISTFWR0_ACTWEBS_X(x)            (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_BISTFWR0_BISTFWR0_RESERVED_19(x) (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_BISTFWR0_BISTFWR0_RESERVED_19_M  GENMASK(19, 19)
#define DDR_PHY_BISTFWR0_BISTFWR0_RESERVED_19_X(x)\
	(((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_BISTFWR0_CSWEBS(x)               (((x) << 20) & GENMASK(31, 20))
#define DDR_PHY_BISTFWR0_CSWEBS_M                GENMASK(31, 20)
#define DDR_PHY_BISTFWR0_CSWEBS_X(x)             (((x) & GENMASK(31, 20)) >> 20)

/*      DDR_PHY:DWC_DDRPHY_PUB:BISTFWR1 */
#define DDR_PHY_BISTFWR1(t)       (t + 0x458)

#define DDR_PHY_BISTFWR1_CKEWEBS(x)              ((x) & GENMASK(7, 0))
#define DDR_PHY_BISTFWR1_CKEWEBS_M               GENMASK(7, 0)
#define DDR_PHY_BISTFWR1_CKEWEBS_X(x)            ((x) & GENMASK(7, 0))

#define DDR_PHY_BISTFWR1_ODTWEBS(x)              (((x) << 8) & GENMASK(15, 8))
#define DDR_PHY_BISTFWR1_ODTWEBS_M               GENMASK(15, 8)
#define DDR_PHY_BISTFWR1_ODTWEBS_X(x)            (((x) & GENMASK(15, 8)) >> 8)

#define DDR_PHY_BISTFWR1_BAWEBS(x)               (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_BISTFWR1_BAWEBS_M                GENMASK(19, 16)
#define DDR_PHY_BISTFWR1_BAWEBS_X(x)             (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_BISTFWR1_CIDWEBS(x)              (((x) << 20) & GENMASK(22, 20))
#define DDR_PHY_BISTFWR1_CIDWEBS_M               GENMASK(22, 20)
#define DDR_PHY_BISTFWR1_CIDWEBS_X(x)            (((x) & GENMASK(22, 20)) >> 20)

#define DDR_PHY_BISTFWR1_BISTFWR1_RESERVED_23(x) (((x) << 23) & GENMASK(23, 23))
#define DDR_PHY_BISTFWR1_BISTFWR1_RESERVED_23_M  GENMASK(23, 23)
#define DDR_PHY_BISTFWR1_BISTFWR1_RESERVED_23_X(x)\
	(((x) & GENMASK(23, 23)) >> 23)

#define DDR_PHY_BISTFWR1_X4DMWEBS(x)             (((x) << 24) & GENMASK(27, 24))
#define DDR_PHY_BISTFWR1_X4DMWEBS_M              GENMASK(27, 24)
#define DDR_PHY_BISTFWR1_X4DMWEBS_X(x)           (((x) & GENMASK(27, 24)) >> 24)

#define DDR_PHY_BISTFWR1_DMWEBS(x)               (((x) << 28) & GENMASK(31, 28))
#define DDR_PHY_BISTFWR1_DMWEBS_M                GENMASK(31, 28)
#define DDR_PHY_BISTFWR1_DMWEBS_X(x)             (((x) & GENMASK(31, 28)) >> 28)

/*      DDR_PHY:DWC_DDRPHY_PUB:BISTFWR2 */
#define DDR_PHY_BISTFWR2(t)       (t + 0x45c)

/*      DDR_PHY:DWC_DDRPHY_PUB:BISTBER5 */
#define DDR_PHY_BISTBER5(t)       (t + 0x460)

#define DDR_PHY_BISTBER5_CKEBER(x)               ((x) & GENMASK(7, 0))
#define DDR_PHY_BISTBER5_CKEBER_M                GENMASK(7, 0)
#define DDR_PHY_BISTBER5_CKEBER_X(x)             ((x) & GENMASK(7, 0))

#define DDR_PHY_BISTBER5_BISTBER5_RESERVED_15_8(x) (((x) << 8) & GENMASK(15, 8))
#define DDR_PHY_BISTBER5_BISTBER5_RESERVED_15_8_M GENMASK(15, 8)
#define DDR_PHY_BISTBER5_BISTBER5_RESERVED_15_8_X(x)\
	(((x) & GENMASK(15, 8)) >> 8)

#define DDR_PHY_BISTBER5_ODTBER(x)               (((x) << 16) & GENMASK(23, 16))
#define DDR_PHY_BISTBER5_ODTBER_M                GENMASK(23, 16)
#define DDR_PHY_BISTBER5_ODTBER_X(x)             (((x) & GENMASK(23, 16)) >> 16)

#define DDR_PHY_BISTBER5_BISTBER5_RESERVED_31_24(x)\
	(((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_BISTBER5_BISTBER5_RESERVED_31_24_M GENMASK(31, 24)
#define DDR_PHY_BISTBER5_BISTBER5_RESERVED_31_24_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:RANKIDR */
#define DDR_PHY_RANKIDR(t)        (t + 0x4dc)

#define DDR_PHY_RANKIDR_RANKWID(x)               ((x) & GENMASK(3, 0))
#define DDR_PHY_RANKIDR_RANKWID_M                GENMASK(3, 0)
#define DDR_PHY_RANKIDR_RANKWID_X(x)             ((x) & GENMASK(3, 0))

#define DDR_PHY_RANKIDR_RESERVED_15_4(x)         (((x) << 4) & GENMASK(15, 4))
#define DDR_PHY_RANKIDR_RESERVED_15_4_M          GENMASK(15, 4)
#define DDR_PHY_RANKIDR_RESERVED_15_4_X(x)       (((x) & GENMASK(15, 4)) >> 4)

#define DDR_PHY_RANKIDR_RANKRID(x)               (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_RANKIDR_RANKRID_M                GENMASK(19, 16)
#define DDR_PHY_RANKIDR_RANKRID_X(x)             (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_RANKIDR_RANKIDR_RESERVED_31_20(x)\
	(((x) << 20) & GENMASK(31, 20))
#define DDR_PHY_RANKIDR_RANKIDR_RESERVED_31_20_M GENMASK(31, 20)
#define DDR_PHY_RANKIDR_RANKIDR_RESERVED_31_20_X(x)\
	(((x) & GENMASK(31, 20)) >> 20)

/*      DDR_PHY:DWC_DDRPHY_PUB:RIOCR0 */
#define DDR_PHY_RIOCR0(t)         (t + 0x4e0)

#define DDR_PHY_RIOCR0_CSODT(x)                  ((x) & GENMASK(1, 0))
#define DDR_PHY_RIOCR0_CSODT_M                   GENMASK(1, 0)
#define DDR_PHY_RIOCR0_CSODT_X(x)                ((x) & GENMASK(1, 0))

#define DDR_PHY_RIOCR0_CSODT_RSVD(x)             (((x) << 2) & GENMASK(11, 2))
#define DDR_PHY_RIOCR0_CSODT_RSVD_M              GENMASK(11, 2)
#define DDR_PHY_RIOCR0_CSODT_RSVD_X(x)           (((x) & GENMASK(11, 2)) >> 2)

#define DDR_PHY_RIOCR0_RIOCR0_RESERVED_15_12(x)  (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_RIOCR0_RIOCR0_RESERVED_15_12_M   GENMASK(15, 12)
#define DDR_PHY_RIOCR0_RIOCR0_RESERVED_15_12_X(x)\
	(((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_RIOCR0_CSPDR(x)                  (((x) << 16) & GENMASK(17, 16))
#define DDR_PHY_RIOCR0_CSPDR_M                   GENMASK(17, 16)
#define DDR_PHY_RIOCR0_CSPDR_X(x)                (((x) & GENMASK(17, 16)) >> 16)

#define DDR_PHY_RIOCR0_CSPDR_RSVD(x)             (((x) << 18) & GENMASK(27, 18))
#define DDR_PHY_RIOCR0_CSPDR_RSVD_M              GENMASK(27, 18)
#define DDR_PHY_RIOCR0_CSPDR_RSVD_X(x)           (((x) & GENMASK(27, 18)) >> 18)

#define DDR_PHY_RIOCR0_RIOCR0_RESERVED_31_28(x)  (((x) << 28) & GENMASK(31, 28))
#define DDR_PHY_RIOCR0_RIOCR0_RESERVED_31_28_M   GENMASK(31, 28)
#define DDR_PHY_RIOCR0_RIOCR0_RESERVED_31_28_X(x)\
	(((x) & GENMASK(31, 28)) >> 28)

/*      DDR_PHY:DWC_DDRPHY_PUB:RIOCR1 */
#define DDR_PHY_RIOCR1(t)         (t + 0x4e4)

#define DDR_PHY_RIOCR1_CKEODT(x)                 ((x) & GENMASK(1, 0))
#define DDR_PHY_RIOCR1_CKEODT_M                  GENMASK(1, 0)
#define DDR_PHY_RIOCR1_CKEODT_X(x)               ((x) & GENMASK(1, 0))

#define DDR_PHY_RIOCR1_CKEODT_RSVD(x)            (((x) << 2) & GENMASK(7, 2))
#define DDR_PHY_RIOCR1_CKEODT_RSVD_M             GENMASK(7, 2)
#define DDR_PHY_RIOCR1_CKEODT_RSVD_X(x)          (((x) & GENMASK(7, 2)) >> 2)

#define DDR_PHY_RIOCR1_CKEPDR(x)                 (((x) << 8) & GENMASK(9, 8))
#define DDR_PHY_RIOCR1_CKEPDR_M                  GENMASK(9, 8)
#define DDR_PHY_RIOCR1_CKEPDR_X(x)               (((x) & GENMASK(9, 8)) >> 8)

#define DDR_PHY_RIOCR1_CKEPDR_RSVD(x)            (((x) << 10) & GENMASK(15, 10))
#define DDR_PHY_RIOCR1_CKEPDR_RSVD_M             GENMASK(15, 10)
#define DDR_PHY_RIOCR1_CKEPDR_RSVD_X(x)          (((x) & GENMASK(15, 10)) >> 10)

#define DDR_PHY_RIOCR1_ODTODT(x)                 (((x) << 16) & GENMASK(17, 16))
#define DDR_PHY_RIOCR1_ODTODT_M                  GENMASK(17, 16)
#define DDR_PHY_RIOCR1_ODTODT_X(x)               (((x) & GENMASK(17, 16)) >> 16)

#define DDR_PHY_RIOCR1_ODTODT_RSVD(x)            (((x) << 18) & GENMASK(23, 18))
#define DDR_PHY_RIOCR1_ODTODT_RSVD_M             GENMASK(23, 18)
#define DDR_PHY_RIOCR1_ODTODT_RSVD_X(x)          (((x) & GENMASK(23, 18)) >> 18)

#define DDR_PHY_RIOCR1_ODTPDR(x)                 (((x) << 24) & GENMASK(25, 24))
#define DDR_PHY_RIOCR1_ODTPDR_M                  GENMASK(25, 24)
#define DDR_PHY_RIOCR1_ODTPDR_X(x)               (((x) & GENMASK(25, 24)) >> 24)

#define DDR_PHY_RIOCR1_ODTPDR_RSVD(x)            (((x) << 26) & GENMASK(31, 26))
#define DDR_PHY_RIOCR1_ODTPDR_RSVD_M             GENMASK(31, 26)
#define DDR_PHY_RIOCR1_ODTPDR_RSVD_X(x)          (((x) & GENMASK(31, 26)) >> 26)

/*      DDR_PHY:DWC_DDRPHY_PUB:RIOCR2 */
#define DDR_PHY_RIOCR2(t)         (t + 0x4e8)

#define DDR_PHY_RIOCR2_CSOEMODE(x)               ((x) & GENMASK(3, 0))
#define DDR_PHY_RIOCR2_CSOEMODE_M                GENMASK(3, 0)
#define DDR_PHY_RIOCR2_CSOEMODE_X(x)             ((x) & GENMASK(3, 0))

#define DDR_PHY_RIOCR2_CSOEMODE_RSVD(x)          (((x) << 4) & GENMASK(23, 4))
#define DDR_PHY_RIOCR2_CSOEMODE_RSVD_M           GENMASK(23, 4)
#define DDR_PHY_RIOCR2_CSOEMODE_RSVD_X(x)        (((x) & GENMASK(23, 4)) >> 4)

#define DDR_PHY_RIOCR2_COEMODE(x)                (((x) << 24) & GENMASK(25, 24))
#define DDR_PHY_RIOCR2_COEMODE_M                 GENMASK(25, 24)
#define DDR_PHY_RIOCR2_COEMODE_X(x)              (((x) & GENMASK(25, 24)) >> 24)

#define DDR_PHY_RIOCR2_COEMODE_RSVD(x)           (((x) << 26) & GENMASK(29, 26))
#define DDR_PHY_RIOCR2_COEMODE_RSVD_M            GENMASK(29, 26)
#define DDR_PHY_RIOCR2_COEMODE_RSVD_X(x)         (((x) & GENMASK(29, 26)) >> 26)

#define DDR_PHY_RIOCR2_RIOCR2_RESERVED_31_30(x)  (((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_RIOCR2_RIOCR2_RESERVED_31_30_M   GENMASK(31, 30)
#define DDR_PHY_RIOCR2_RIOCR2_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:RIOCR3 */
#define DDR_PHY_RIOCR3(t)         (t + 0x4ec)

/*      DDR_PHY:DWC_DDRPHY_PUB:RIOCR4 */
#define DDR_PHY_RIOCR4(t)         (t + 0x4f0)

#define DDR_PHY_RIOCR4_CKEOEMODE(x)              ((x) & GENMASK(3, 0))
#define DDR_PHY_RIOCR4_CKEOEMODE_M               GENMASK(3, 0)
#define DDR_PHY_RIOCR4_CKEOEMODE_X(x)            ((x) & GENMASK(3, 0))

#define DDR_PHY_RIOCR4_CKEOEMODE_RSVD(x)         (((x) << 4) & GENMASK(15, 4))
#define DDR_PHY_RIOCR4_CKEOEMODE_RSVD_M          GENMASK(15, 4)
#define DDR_PHY_RIOCR4_CKEOEMODE_RSVD_X(x)       (((x) & GENMASK(15, 4)) >> 4)

#define DDR_PHY_RIOCR4_RIOCR4_RESERVED_31_16(x)  (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_RIOCR4_RIOCR4_RESERVED_31_16_M   GENMASK(31, 16)
#define DDR_PHY_RIOCR4_RIOCR4_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:RIOCR5 */
#define DDR_PHY_RIOCR5(t)         (t + 0x4f4)

#define DDR_PHY_RIOCR5_ODTOEMODE(x)              ((x) & GENMASK(3, 0))
#define DDR_PHY_RIOCR5_ODTOEMODE_M               GENMASK(3, 0)
#define DDR_PHY_RIOCR5_ODTOEMODE_X(x)            ((x) & GENMASK(3, 0))

#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD(x)         (((x) << 4) & GENMASK(15, 4))
#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_M          GENMASK(15, 4)
#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_X(x)       (((x) & GENMASK(15, 4)) >> 4)

#define DDR_PHY_RIOCR5_RIOCR5_RESERVED_31_16(x)  (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_RIOCR5_RIOCR5_RESERVED_31_16_M   GENMASK(31, 16)
#define DDR_PHY_RIOCR5_RIOCR5_RESERVED_31_16_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:ACIOCR0 */
#define DDR_PHY_ACIOCR0(t)        (t + 0x500)

#define DDR_PHY_ACIOCR0_ACIOM(x)                 ((x) & GENMASK(0, 0))
#define DDR_PHY_ACIOCR0_ACIOM_M                  GENMASK(0, 0)
#define DDR_PHY_ACIOCR0_ACIOM_X(x)               ((x) & GENMASK(0, 0))

#define DDR_PHY_ACIOCR0_RESERVED_1(x)            (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_ACIOCR0_RESERVED_1_M             GENMASK(1, 1)
#define DDR_PHY_ACIOCR0_RESERVED_1_X(x)          (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_ACIOCR0_ACODT(x)                 (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_ACIOCR0_ACODT_M                  GENMASK(2, 2)
#define DDR_PHY_ACIOCR0_ACODT_X(x)               (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_ACIOCR0_ACIOCR0_RESERVED_3(x)    (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_ACIOCR0_ACIOCR0_RESERVED_3_M     GENMASK(3, 3)
#define DDR_PHY_ACIOCR0_ACIOCR0_RESERVED_3_X(x)  (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_ACIOCR0_ACPDR(x)                 (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_ACIOCR0_ACPDR_M                  GENMASK(4, 4)
#define DDR_PHY_ACIOCR0_ACPDR_X(x)               (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_ACIOCR0_CKODT(x)                 (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_ACIOCR0_CKODT_M                  GENMASK(5, 5)
#define DDR_PHY_ACIOCR0_CKODT_X(x)               (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_ACIOCR0_CKODT_RSVD(x)            (((x) << 6) & GENMASK(8, 6))
#define DDR_PHY_ACIOCR0_CKODT_RSVD_M             GENMASK(8, 6)
#define DDR_PHY_ACIOCR0_CKODT_RSVD_X(x)          (((x) & GENMASK(8, 6)) >> 6)

#define DDR_PHY_ACIOCR0_RESERVED_9(x)            (((x) << 9) & GENMASK(9, 9))
#define DDR_PHY_ACIOCR0_RESERVED_9_M             GENMASK(9, 9)
#define DDR_PHY_ACIOCR0_RESERVED_9_X(x)          (((x) & GENMASK(9, 9)) >> 9)

#define DDR_PHY_ACIOCR0_CKPDR(x)                 (((x) << 10) & GENMASK(10, 10))
#define DDR_PHY_ACIOCR0_CKPDR_M                  GENMASK(10, 10)
#define DDR_PHY_ACIOCR0_CKPDR_X(x)               (((x) & GENMASK(10, 10)) >> 10)

#define DDR_PHY_ACIOCR0_CKPDR_RSVD(x)            (((x) << 11) & GENMASK(13, 11))
#define DDR_PHY_ACIOCR0_CKPDR_RSVD_M             GENMASK(13, 11)
#define DDR_PHY_ACIOCR0_CKPDR_RSVD_X(x)          (((x) & GENMASK(13, 11)) >> 11)

#define DDR_PHY_ACIOCR0_RESERVED_25_14(x)        (((x) << 14) & GENMASK(25, 14))
#define DDR_PHY_ACIOCR0_RESERVED_25_14_M         GENMASK(25, 14)
#define DDR_PHY_ACIOCR0_RESERVED_25_14_X(x)      (((x) & GENMASK(25, 14)) >> 14)

#define DDR_PHY_ACIOCR0_RSTODT(x)                (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_ACIOCR0_RSTODT_M                 GENMASK(26, 26)
#define DDR_PHY_ACIOCR0_RSTODT_X(x)              (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_ACIOCR0_ACIOCR0_RESERVED_27(x)   (((x) << 27) & GENMASK(27, 27))
#define DDR_PHY_ACIOCR0_ACIOCR0_RESERVED_27_M    GENMASK(27, 27)
#define DDR_PHY_ACIOCR0_ACIOCR0_RESERVED_27_X(x) (((x) & GENMASK(27, 27)) >> 27)

#define DDR_PHY_ACIOCR0_RSTPDR(x)                (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_ACIOCR0_RSTPDR_M                 GENMASK(28, 28)
#define DDR_PHY_ACIOCR0_RSTPDR_X(x)              (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_ACIOCR0_RSTIOM(x)                (((x) << 29) & GENMASK(29, 29))
#define DDR_PHY_ACIOCR0_RSTIOM_M                 GENMASK(29, 29)
#define DDR_PHY_ACIOCR0_RSTIOM_X(x)              (((x) & GENMASK(29, 29)) >> 29)

#define DDR_PHY_ACIOCR0_ACSR(x)                  (((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_ACIOCR0_ACSR_M                   GENMASK(31, 30)
#define DDR_PHY_ACIOCR0_ACSR_X(x)                (((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:ACIOCR1 */
#define DDR_PHY_ACIOCR1(t)        (t + 0x504)

/*      DDR_PHY:DWC_DDRPHY_PUB:ACIOCR2 */
#define DDR_PHY_ACIOCR2(t)        (t + 0x508)

/*      DDR_PHY:DWC_DDRPHY_PUB:ACIOCR3 */
#define DDR_PHY_ACIOCR3(t)        (t + 0x50c)

#define DDR_PHY_ACIOCR3_CKOEMODE(x)              ((x) & GENMASK(1, 0))
#define DDR_PHY_ACIOCR3_CKOEMODE_M               GENMASK(1, 0)
#define DDR_PHY_ACIOCR3_CKOEMODE_X(x)            ((x) & GENMASK(1, 0))

#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD(x)         (((x) << 2) & GENMASK(7, 2))
#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_M          GENMASK(7, 2)
#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_X(x)       (((x) & GENMASK(7, 2)) >> 2)

#define DDR_PHY_ACIOCR3_ACIOCR3_RESERVED_15_8(x) (((x) << 8) & GENMASK(15, 8))
#define DDR_PHY_ACIOCR3_ACIOCR3_RESERVED_15_8_M  GENMASK(15, 8)
#define DDR_PHY_ACIOCR3_ACIOCR3_RESERVED_15_8_X(x) (((x) & GENMASK(15, 8)) >> 8)

#define DDR_PHY_ACIOCR3_ACTOEMODE(x)             (((x) << 16) & GENMASK(17, 16))
#define DDR_PHY_ACIOCR3_ACTOEMODE_M              GENMASK(17, 16)
#define DDR_PHY_ACIOCR3_ACTOEMODE_X(x)           (((x) & GENMASK(17, 16)) >> 16)

#define DDR_PHY_ACIOCR3_A16OEMODE(x)             (((x) << 18) & GENMASK(19, 18))
#define DDR_PHY_ACIOCR3_A16OEMODE_M              GENMASK(19, 18)
#define DDR_PHY_ACIOCR3_A16OEMODE_X(x)           (((x) & GENMASK(19, 18)) >> 18)

#define DDR_PHY_ACIOCR3_A17OEMODE(x)             (((x) << 20) & GENMASK(21, 20))
#define DDR_PHY_ACIOCR3_A17OEMODE_M              GENMASK(21, 20)
#define DDR_PHY_ACIOCR3_A17OEMODE_X(x)           (((x) & GENMASK(21, 20)) >> 20)

#define DDR_PHY_ACIOCR3_BAOEMODE(x)              (((x) << 22) & GENMASK(25, 22))
#define DDR_PHY_ACIOCR3_BAOEMODE_M               GENMASK(25, 22)
#define DDR_PHY_ACIOCR3_BAOEMODE_X(x)            (((x) & GENMASK(25, 22)) >> 22)

#define DDR_PHY_ACIOCR3_BGOEMODE(x)              (((x) << 26) & GENMASK(29, 26))
#define DDR_PHY_ACIOCR3_BGOEMODE_M               GENMASK(29, 26)
#define DDR_PHY_ACIOCR3_BGOEMODE_X(x)            (((x) & GENMASK(29, 26)) >> 26)

#define DDR_PHY_ACIOCR3_PAROEMODE(x)             (((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_ACIOCR3_PAROEMODE_M              GENMASK(31, 30)
#define DDR_PHY_ACIOCR3_PAROEMODE_X(x)           (((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:ACIOCR4 */
#define DDR_PHY_ACIOCR4(t)        (t + 0x510)

/*      DDR_PHY:DWC_DDRPHY_PUB:IOVCR0 */
#define DDR_PHY_IOVCR0(t)         (t + 0x520)

#define DDR_PHY_IOVCR0_ACVREFISEL(x)             ((x) & GENMASK(5, 0))
#define DDR_PHY_IOVCR0_ACVREFISEL_M              GENMASK(5, 0)
#define DDR_PHY_IOVCR0_ACVREFISEL_X(x)           ((x) & GENMASK(5, 0))

#define DDR_PHY_IOVCR0_IOVCR0_RESERVED_7_6(x)    (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_IOVCR0_IOVCR0_RESERVED_7_6_M     GENMASK(7, 6)
#define DDR_PHY_IOVCR0_IOVCR0_RESERVED_7_6_X(x)  (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_IOVCR0_ACVREFSSEL(x)             (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_IOVCR0_ACVREFSSEL_M              GENMASK(13, 8)
#define DDR_PHY_IOVCR0_ACVREFSSEL_X(x)           (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_IOVCR0_IOVCR0_RESERVED_15_14(x)  (((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_IOVCR0_IOVCR0_RESERVED_15_14_M   GENMASK(15, 14)
#define DDR_PHY_IOVCR0_IOVCR0_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_IOVCR0_ACVREFESEL(x)             (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_IOVCR0_ACVREFESEL_M              GENMASK(21, 16)
#define DDR_PHY_IOVCR0_ACVREFESEL_X(x)           (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_IOVCR0_IOVCR0_RESERVED_23_22(x)  (((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_IOVCR0_IOVCR0_RESERVED_23_22_M   GENMASK(23, 22)
#define DDR_PHY_IOVCR0_IOVCR0_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_IOVCR0_ACVREFIEN(x)              (((x) << 24) & GENMASK(24, 24))
#define DDR_PHY_IOVCR0_ACVREFIEN_M               GENMASK(24, 24)
#define DDR_PHY_IOVCR0_ACVREFIEN_X(x)            (((x) & GENMASK(24, 24)) >> 24)

#define DDR_PHY_IOVCR0_ACVREFSEN(x)              (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_IOVCR0_ACVREFSEN_M               GENMASK(25, 25)
#define DDR_PHY_IOVCR0_ACVREFSEN_X(x)            (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_IOVCR0_ACVREFEEN(x)              (((x) << 26) & GENMASK(27, 26))
#define DDR_PHY_IOVCR0_ACVREFEEN_M               GENMASK(27, 26)
#define DDR_PHY_IOVCR0_ACVREFEEN_X(x)            (((x) & GENMASK(27, 26)) >> 26)

#define DDR_PHY_IOVCR0_ACVREFPEN(x)              (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_IOVCR0_ACVREFPEN_M               GENMASK(28, 28)
#define DDR_PHY_IOVCR0_ACVREFPEN_X(x)            (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_IOVCR0_ACVREFIOM(x)              (((x) << 29) & GENMASK(31, 29))
#define DDR_PHY_IOVCR0_ACVREFIOM_M               GENMASK(31, 29)
#define DDR_PHY_IOVCR0_ACVREFIOM_X(x)            (((x) & GENMASK(31, 29)) >> 29)

/*      DDR_PHY:DWC_DDRPHY_PUB:IOVCR1 */
#define DDR_PHY_IOVCR1(t)         (t + 0x524)

#define DDR_PHY_IOVCR1_ZQVREFISEL(x)             ((x) & GENMASK(5, 0))
#define DDR_PHY_IOVCR1_ZQVREFISEL_M              GENMASK(5, 0)
#define DDR_PHY_IOVCR1_ZQVREFISEL_X(x)           ((x) & GENMASK(5, 0))

#define DDR_PHY_IOVCR1_IOVCR1_RESERVED_7_6(x)    (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_IOVCR1_IOVCR1_RESERVED_7_6_M     GENMASK(7, 6)
#define DDR_PHY_IOVCR1_IOVCR1_RESERVED_7_6_X(x)  (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_IOVCR1_ZQVREFIEN(x)              (((x) << 8) & GENMASK(8, 8))
#define DDR_PHY_IOVCR1_ZQVREFIEN_M               GENMASK(8, 8)
#define DDR_PHY_IOVCR1_ZQVREFIEN_X(x)            (((x) & GENMASK(8, 8)) >> 8)

#define DDR_PHY_IOVCR1_ZQVREFPEN(x)              (((x) << 9) & GENMASK(9, 9))
#define DDR_PHY_IOVCR1_ZQVREFPEN_M               GENMASK(9, 9)
#define DDR_PHY_IOVCR1_ZQVREFPEN_X(x)            (((x) & GENMASK(9, 9)) >> 9)

#define DDR_PHY_IOVCR1_IOVCR1_RESERVED_31_10(x)  (((x) << 10) & GENMASK(31, 10))
#define DDR_PHY_IOVCR1_IOVCR1_RESERVED_31_10_M   GENMASK(31, 10)
#define DDR_PHY_IOVCR1_IOVCR1_RESERVED_31_10_X(x)\
	(((x) & GENMASK(31, 10)) >> 10)

/*      DDR_PHY:DWC_DDRPHY_PUB:VTCR0 */
#define DDR_PHY_VTCR0(t)          (t + 0x528)

#define DDR_PHY_VTCR0_DVINIT(x)                  ((x) & GENMASK(5, 0))
#define DDR_PHY_VTCR0_DVINIT_M                   GENMASK(5, 0)
#define DDR_PHY_VTCR0_DVINIT_X(x)                ((x) & GENMASK(5, 0))

#define DDR_PHY_VTCR0_DVMIN(x)                   (((x) << 6) & GENMASK(11, 6))
#define DDR_PHY_VTCR0_DVMIN_M                    GENMASK(11, 6)
#define DDR_PHY_VTCR0_DVMIN_X(x)                 (((x) & GENMASK(11, 6)) >> 6)

#define DDR_PHY_VTCR0_DVMAX(x)                   (((x) << 12) & GENMASK(17, 12))
#define DDR_PHY_VTCR0_DVMAX_M                    GENMASK(17, 12)
#define DDR_PHY_VTCR0_DVMAX_X(x)                 (((x) & GENMASK(17, 12)) >> 12)

#define DDR_PHY_VTCR0_DVSS(x)                    (((x) << 18) & GENMASK(21, 18))
#define DDR_PHY_VTCR0_DVSS_M                     GENMASK(21, 18)
#define DDR_PHY_VTCR0_DVSS_X(x)                  (((x) & GENMASK(21, 18)) >> 18)

#define DDR_PHY_VTCR0_RESERVED_26_22(x)          (((x) << 22) & GENMASK(26, 22))
#define DDR_PHY_VTCR0_RESERVED_26_22_M           GENMASK(26, 22)
#define DDR_PHY_VTCR0_RESERVED_26_22_X(x)        (((x) & GENMASK(26, 22)) >> 22)

#define DDR_PHY_VTCR0_PDAEN(x)                   (((x) << 27) & GENMASK(27, 27))
#define DDR_PHY_VTCR0_PDAEN_M                    GENMASK(27, 27)
#define DDR_PHY_VTCR0_PDAEN_X(x)                 (((x) & GENMASK(27, 27)) >> 27)

#define DDR_PHY_VTCR0_DVEN(x)                    (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_VTCR0_DVEN_M                     GENMASK(28, 28)
#define DDR_PHY_VTCR0_DVEN_X(x)                  (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_VTCR0_TVREF(x)                   (((x) << 29) & GENMASK(31, 29))
#define DDR_PHY_VTCR0_TVREF_M                    GENMASK(31, 29)
#define DDR_PHY_VTCR0_TVREF_X(x)                 (((x) & GENMASK(31, 29)) >> 29)

/*      DDR_PHY:DWC_DDRPHY_PUB:VTCR1 */
#define DDR_PHY_VTCR1(t)          (t + 0x52c)

#define DDR_PHY_VTCR1_HVIO(x)                    ((x) & GENMASK(0, 0))
#define DDR_PHY_VTCR1_HVIO_M                     GENMASK(0, 0)
#define DDR_PHY_VTCR1_HVIO_X(x)                  ((x) & GENMASK(0, 0))

#define DDR_PHY_VTCR1_HVEN(x)                    (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_VTCR1_HVEN_M                     GENMASK(1, 1)
#define DDR_PHY_VTCR1_HVEN_X(x)                  (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_VTCR1_ENUM(x)                    (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_VTCR1_ENUM_M                     GENMASK(2, 2)
#define DDR_PHY_VTCR1_ENUM_X(x)                  (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_VTCR1_EOFF(x)                    (((x) << 3) & GENMASK(4, 3))
#define DDR_PHY_VTCR1_EOFF_M                     GENMASK(4, 3)
#define DDR_PHY_VTCR1_EOFF_X(x)                  (((x) & GENMASK(4, 3)) >> 3)

#define DDR_PHY_VTCR1_TVREFIO(x)                 (((x) << 5) & GENMASK(7, 5))
#define DDR_PHY_VTCR1_TVREFIO_M                  GENMASK(7, 5)
#define DDR_PHY_VTCR1_TVREFIO_X(x)               (((x) & GENMASK(7, 5)) >> 5)

#define DDR_PHY_VTCR1_SHREN(x)                   (((x) << 8) & GENMASK(8, 8))
#define DDR_PHY_VTCR1_SHREN_M                    GENMASK(8, 8)
#define DDR_PHY_VTCR1_SHREN_X(x)                 (((x) & GENMASK(8, 8)) >> 8)

#define DDR_PHY_VTCR1_SHRNK(x)                   (((x) << 9) & GENMASK(10, 9))
#define DDR_PHY_VTCR1_SHRNK_M                    GENMASK(10, 9)
#define DDR_PHY_VTCR1_SHRNK_X(x)                 (((x) & GENMASK(10, 9)) >> 9)

#define DDR_PHY_VTCR1_RESERVED_11(x)             (((x) << 11) & GENMASK(11, 11))
#define DDR_PHY_VTCR1_RESERVED_11_M              GENMASK(11, 11)
#define DDR_PHY_VTCR1_RESERVED_11_X(x)           (((x) & GENMASK(11, 11)) >> 11)

#define DDR_PHY_VTCR1_VWCR(x)                    (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_VTCR1_VWCR_M                     GENMASK(15, 12)
#define DDR_PHY_VTCR1_VWCR_X(x)                  (((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_VTCR1_HVMIN(x)                   (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_VTCR1_HVMIN_M                    GENMASK(21, 16)
#define DDR_PHY_VTCR1_HVMIN_X(x)                 (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_VTCR1_HVMAX(x)                   (((x) << 22) & GENMASK(27, 22))
#define DDR_PHY_VTCR1_HVMAX_M                    GENMASK(27, 22)
#define DDR_PHY_VTCR1_HVMAX_X(x)                 (((x) & GENMASK(27, 22)) >> 22)

#define DDR_PHY_VTCR1_HVSS(x)                    (((x) << 28) & GENMASK(31, 28))
#define DDR_PHY_VTCR1_HVSS_M                     GENMASK(31, 28)
#define DDR_PHY_VTCR1_HVSS_X(x)                  (((x) & GENMASK(31, 28)) >> 28)

/*      DDR_PHY:DWC_DDRPHY_PUB:ACBDLR0 */
#define DDR_PHY_ACBDLR0(t)        (t + 0x540)

#define DDR_PHY_ACBDLR0_CK0BD(x)                 ((x) & GENMASK(5, 0))
#define DDR_PHY_ACBDLR0_CK0BD_M                  GENMASK(5, 0)
#define DDR_PHY_ACBDLR0_CK0BD_X(x)               ((x) & GENMASK(5, 0))

#define DDR_PHY_ACBDLR0_ACBDLR0_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_ACBDLR0_ACBDLR0_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_ACBDLR0_ACBDLR0_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_ACBDLR0_CK1BD(x)                 (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_ACBDLR0_CK1BD_M                  GENMASK(13, 8)
#define DDR_PHY_ACBDLR0_CK1BD_X(x)               (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_ACBDLR0_ACBDLR0_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_ACBDLR0_ACBDLR0_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_ACBDLR0_ACBDLR0_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_ACBDLR0_CK2BD(x)                 (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_ACBDLR0_CK2BD_M                  GENMASK(21, 16)
#define DDR_PHY_ACBDLR0_CK2BD_X(x)               (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_ACBDLR0_ACBDLR0_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_ACBDLR0_ACBDLR0_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_ACBDLR0_ACBDLR0_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_ACBDLR0_CK3BD(x)                 (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_ACBDLR0_CK3BD_M                  GENMASK(29, 24)
#define DDR_PHY_ACBDLR0_CK3BD_X(x)               (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_ACBDLR0_ACBDLR0_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_ACBDLR0_ACBDLR0_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_ACBDLR0_ACBDLR0_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:ACBDLR1 */
#define DDR_PHY_ACBDLR1(t)        (t + 0x544)

#define DDR_PHY_ACBDLR1_ACTBD(x)                 ((x) & GENMASK(5, 0))
#define DDR_PHY_ACBDLR1_ACTBD_M                  GENMASK(5, 0)
#define DDR_PHY_ACBDLR1_ACTBD_X(x)               ((x) & GENMASK(5, 0))

#define DDR_PHY_ACBDLR1_ACBDLR1_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_ACBDLR1_ACBDLR1_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_ACBDLR1_ACBDLR1_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_ACBDLR1_A17BD(x)                 (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_ACBDLR1_A17BD_M                  GENMASK(13, 8)
#define DDR_PHY_ACBDLR1_A17BD_X(x)               (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_ACBDLR1_ACBDLR1_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_ACBDLR1_ACBDLR1_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_ACBDLR1_ACBDLR1_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_ACBDLR1_A16BD(x)                 (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_ACBDLR1_A16BD_M                  GENMASK(21, 16)
#define DDR_PHY_ACBDLR1_A16BD_X(x)               (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_ACBDLR1_ACBDLR1_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_ACBDLR1_ACBDLR1_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_ACBDLR1_ACBDLR1_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_ACBDLR1_PARBD(x)                 (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_ACBDLR1_PARBD_M                  GENMASK(29, 24)
#define DDR_PHY_ACBDLR1_PARBD_X(x)               (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_ACBDLR1_ACBDLR1_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_ACBDLR1_ACBDLR1_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_ACBDLR1_ACBDLR1_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:ACBDLR2 */
#define DDR_PHY_ACBDLR2(t)        (t + 0x548)

#define DDR_PHY_ACBDLR2_BA0BD(x)                 ((x) & GENMASK(5, 0))
#define DDR_PHY_ACBDLR2_BA0BD_M                  GENMASK(5, 0)
#define DDR_PHY_ACBDLR2_BA0BD_X(x)               ((x) & GENMASK(5, 0))

#define DDR_PHY_ACBDLR2_ACBDLR2_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_ACBDLR2_ACBDLR2_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_ACBDLR2_ACBDLR2_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_ACBDLR2_BA1BD(x)                 (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_ACBDLR2_BA1BD_M                  GENMASK(13, 8)
#define DDR_PHY_ACBDLR2_BA1BD_X(x)               (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_ACBDLR2_ACBDLR2_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_ACBDLR2_ACBDLR2_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_ACBDLR2_ACBDLR2_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_ACBDLR2_BG0BD(x)                 (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_ACBDLR2_BG0BD_M                  GENMASK(21, 16)
#define DDR_PHY_ACBDLR2_BG0BD_X(x)               (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_ACBDLR2_ACBDLR2_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_ACBDLR2_ACBDLR2_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_ACBDLR2_ACBDLR2_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_ACBDLR2_BG1BD(x)                 (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_ACBDLR2_BG1BD_M                  GENMASK(29, 24)
#define DDR_PHY_ACBDLR2_BG1BD_X(x)               (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_ACBDLR2_ACBDLR2_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_ACBDLR2_ACBDLR2_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_ACBDLR2_ACBDLR2_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:ACBDLR3 */
#define DDR_PHY_ACBDLR3(t)        (t + 0x54c)

#define DDR_PHY_ACBDLR3_CS0BD(x)                 ((x) & GENMASK(5, 0))
#define DDR_PHY_ACBDLR3_CS0BD_M                  GENMASK(5, 0)
#define DDR_PHY_ACBDLR3_CS0BD_X(x)               ((x) & GENMASK(5, 0))

#define DDR_PHY_ACBDLR3_ACBDLR3_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_ACBDLR3_ACBDLR3_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_ACBDLR3_ACBDLR3_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_ACBDLR3_CS1BD(x)                 (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_ACBDLR3_CS1BD_M                  GENMASK(13, 8)
#define DDR_PHY_ACBDLR3_CS1BD_X(x)               (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_ACBDLR3_ACBDLR3_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_ACBDLR3_ACBDLR3_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_ACBDLR3_ACBDLR3_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_ACBDLR3_CS2BD(x)                 (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_ACBDLR3_CS2BD_M                  GENMASK(21, 16)
#define DDR_PHY_ACBDLR3_CS2BD_X(x)               (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_ACBDLR3_ACBDLR3_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_ACBDLR3_ACBDLR3_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_ACBDLR3_ACBDLR3_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_ACBDLR3_CS3BD(x)                 (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_ACBDLR3_CS3BD_M                  GENMASK(29, 24)
#define DDR_PHY_ACBDLR3_CS3BD_X(x)               (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_ACBDLR3_ACBDLR3_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_ACBDLR3_ACBDLR3_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_ACBDLR3_ACBDLR3_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:ACBDLR4 */
#define DDR_PHY_ACBDLR4(t)        (t + 0x550)

#define DDR_PHY_ACBDLR4_ODT0BD(x)                ((x) & GENMASK(5, 0))
#define DDR_PHY_ACBDLR4_ODT0BD_M                 GENMASK(5, 0)
#define DDR_PHY_ACBDLR4_ODT0BD_X(x)              ((x) & GENMASK(5, 0))

#define DDR_PHY_ACBDLR4_ACBDLR4_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_ACBDLR4_ACBDLR4_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_ACBDLR4_ACBDLR4_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_ACBDLR4_ODT1BD(x)                (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_ACBDLR4_ODT1BD_M                 GENMASK(13, 8)
#define DDR_PHY_ACBDLR4_ODT1BD_X(x)              (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_ACBDLR4_ACBDLR4_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_ACBDLR4_ACBDLR4_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_ACBDLR4_ACBDLR4_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_ACBDLR4_ODT2BD(x)                (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_ACBDLR4_ODT2BD_M                 GENMASK(21, 16)
#define DDR_PHY_ACBDLR4_ODT2BD_X(x)              (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_ACBDLR4_ACBDLR4_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_ACBDLR4_ACBDLR4_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_ACBDLR4_ACBDLR4_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_ACBDLR4_ODT3BD(x)                (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_ACBDLR4_ODT3BD_M                 GENMASK(29, 24)
#define DDR_PHY_ACBDLR4_ODT3BD_X(x)              (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_ACBDLR4_ACBDLR4_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_ACBDLR4_ACBDLR4_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_ACBDLR4_ACBDLR4_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:ACBDLR5 */
#define DDR_PHY_ACBDLR5(t)        (t + 0x554)

#define DDR_PHY_ACBDLR5_CKE0BD(x)                ((x) & GENMASK(5, 0))
#define DDR_PHY_ACBDLR5_CKE0BD_M                 GENMASK(5, 0)
#define DDR_PHY_ACBDLR5_CKE0BD_X(x)              ((x) & GENMASK(5, 0))

#define DDR_PHY_ACBDLR5_ACBDLR5_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_ACBDLR5_ACBDLR5_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_ACBDLR5_ACBDLR5_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_ACBDLR5_CKE1BD(x)                (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_ACBDLR5_CKE1BD_M                 GENMASK(13, 8)
#define DDR_PHY_ACBDLR5_CKE1BD_X(x)              (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_ACBDLR5_ACBDLR5_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_ACBDLR5_ACBDLR5_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_ACBDLR5_ACBDLR5_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_ACBDLR5_CKE2BD(x)                (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_ACBDLR5_CKE2BD_M                 GENMASK(21, 16)
#define DDR_PHY_ACBDLR5_CKE2BD_X(x)              (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_ACBDLR5_ACBDLR5_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_ACBDLR5_ACBDLR5_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_ACBDLR5_ACBDLR5_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_ACBDLR5_CKE3BD(x)                (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_ACBDLR5_CKE3BD_M                 GENMASK(29, 24)
#define DDR_PHY_ACBDLR5_CKE3BD_X(x)              (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_ACBDLR5_ACBDLR5_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_ACBDLR5_ACBDLR5_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_ACBDLR5_ACBDLR5_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:ACBDLR6 */
#define DDR_PHY_ACBDLR6(t)        (t + 0x558)

#define DDR_PHY_ACBDLR6_A00BD(x)                 ((x) & GENMASK(5, 0))
#define DDR_PHY_ACBDLR6_A00BD_M                  GENMASK(5, 0)
#define DDR_PHY_ACBDLR6_A00BD_X(x)               ((x) & GENMASK(5, 0))

#define DDR_PHY_ACBDLR6_ACBDLR6_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_ACBDLR6_ACBDLR6_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_ACBDLR6_ACBDLR6_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_ACBDLR6_A01BD(x)                 (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_ACBDLR6_A01BD_M                  GENMASK(13, 8)
#define DDR_PHY_ACBDLR6_A01BD_X(x)               (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_ACBDLR6_ACBDLR6_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_ACBDLR6_ACBDLR6_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_ACBDLR6_ACBDLR6_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_ACBDLR6_A02BD(x)                 (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_ACBDLR6_A02BD_M                  GENMASK(21, 16)
#define DDR_PHY_ACBDLR6_A02BD_X(x)               (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_ACBDLR6_ACBDLR6_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_ACBDLR6_ACBDLR6_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_ACBDLR6_ACBDLR6_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_ACBDLR6_A03BD(x)                 (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_ACBDLR6_A03BD_M                  GENMASK(29, 24)
#define DDR_PHY_ACBDLR6_A03BD_X(x)               (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_ACBDLR6_ACBDLR6_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_ACBDLR6_ACBDLR6_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_ACBDLR6_ACBDLR6_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:ACBDLR7 */
#define DDR_PHY_ACBDLR7(t)        (t + 0x55c)

#define DDR_PHY_ACBDLR7_A04BD(x)                 ((x) & GENMASK(5, 0))
#define DDR_PHY_ACBDLR7_A04BD_M                  GENMASK(5, 0)
#define DDR_PHY_ACBDLR7_A04BD_X(x)               ((x) & GENMASK(5, 0))

#define DDR_PHY_ACBDLR7_ACBDLR7_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_ACBDLR7_ACBDLR7_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_ACBDLR7_ACBDLR7_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_ACBDLR7_A05BD(x)                 (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_ACBDLR7_A05BD_M                  GENMASK(13, 8)
#define DDR_PHY_ACBDLR7_A05BD_X(x)               (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_ACBDLR7_ACBDLR7_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_ACBDLR7_ACBDLR7_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_ACBDLR7_ACBDLR7_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_ACBDLR7_A06BD(x)                 (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_ACBDLR7_A06BD_M                  GENMASK(21, 16)
#define DDR_PHY_ACBDLR7_A06BD_X(x)               (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_ACBDLR7_ACBDLR7_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_ACBDLR7_ACBDLR7_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_ACBDLR7_ACBDLR7_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_ACBDLR7_A07BD(x)                 (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_ACBDLR7_A07BD_M                  GENMASK(29, 24)
#define DDR_PHY_ACBDLR7_A07BD_X(x)               (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_ACBDLR7_ACBDLR7_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_ACBDLR7_ACBDLR7_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_ACBDLR7_ACBDLR7_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:ACBDLR8 */
#define DDR_PHY_ACBDLR8(t)        (t + 0x560)

#define DDR_PHY_ACBDLR8_A08BD(x)                 ((x) & GENMASK(5, 0))
#define DDR_PHY_ACBDLR8_A08BD_M                  GENMASK(5, 0)
#define DDR_PHY_ACBDLR8_A08BD_X(x)               ((x) & GENMASK(5, 0))

#define DDR_PHY_ACBDLR8_ACBDLR8_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_ACBDLR8_ACBDLR8_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_ACBDLR8_ACBDLR8_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_ACBDLR8_A09BD(x)                 (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_ACBDLR8_A09BD_M                  GENMASK(13, 8)
#define DDR_PHY_ACBDLR8_A09BD_X(x)               (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_ACBDLR8_ACBDLR8_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_ACBDLR8_ACBDLR8_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_ACBDLR8_ACBDLR8_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_ACBDLR8_A10BD(x)                 (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_ACBDLR8_A10BD_M                  GENMASK(21, 16)
#define DDR_PHY_ACBDLR8_A10BD_X(x)               (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_ACBDLR8_ACBDLR8_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_ACBDLR8_ACBDLR8_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_ACBDLR8_ACBDLR8_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_ACBDLR8_A11BD(x)                 (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_ACBDLR8_A11BD_M                  GENMASK(29, 24)
#define DDR_PHY_ACBDLR8_A11BD_X(x)               (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_ACBDLR8_ACBDLR8_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_ACBDLR8_ACBDLR8_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_ACBDLR8_ACBDLR8_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:ACBDLR9 */
#define DDR_PHY_ACBDLR9(t)        (t + 0x564)

#define DDR_PHY_ACBDLR9_A12BD(x)                 ((x) & GENMASK(5, 0))
#define DDR_PHY_ACBDLR9_A12BD_M                  GENMASK(5, 0)
#define DDR_PHY_ACBDLR9_A12BD_X(x)               ((x) & GENMASK(5, 0))

#define DDR_PHY_ACBDLR9_ACBDLR9_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_ACBDLR9_ACBDLR9_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_ACBDLR9_ACBDLR9_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_ACBDLR9_A13BD(x)                 (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_ACBDLR9_A13BD_M                  GENMASK(13, 8)
#define DDR_PHY_ACBDLR9_A13BD_X(x)               (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_ACBDLR9_ACBDLR9_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_ACBDLR9_ACBDLR9_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_ACBDLR9_ACBDLR9_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_ACBDLR9_A14BD(x)                 (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_ACBDLR9_A14BD_M                  GENMASK(21, 16)
#define DDR_PHY_ACBDLR9_A14BD_X(x)               (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_ACBDLR9_ACBDLR9_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_ACBDLR9_ACBDLR9_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_ACBDLR9_ACBDLR9_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_ACBDLR9_A15BD(x)                 (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_ACBDLR9_A15BD_M                  GENMASK(29, 24)
#define DDR_PHY_ACBDLR9_A15BD_X(x)               (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_ACBDLR9_ACBDLR9_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_ACBDLR9_ACBDLR9_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_ACBDLR9_ACBDLR9_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:ACBDLR10 */
#define DDR_PHY_ACBDLR10(t)       (t + 0x568)

#define DDR_PHY_ACBDLR10_ACBDLR10_RESERVED_7_0(x) ((x) & GENMASK(7, 0))
#define DDR_PHY_ACBDLR10_ACBDLR10_RESERVED_7_0_M GENMASK(7, 0)
#define DDR_PHY_ACBDLR10_ACBDLR10_RESERVED_7_0_X(x) ((x) & GENMASK(7, 0))

#define DDR_PHY_ACBDLR10_CID0BD(x)               (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_ACBDLR10_CID0BD_M                GENMASK(13, 8)
#define DDR_PHY_ACBDLR10_CID0BD_X(x)             (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_ACBDLR10_ACBDLR10_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_ACBDLR10_ACBDLR10_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_ACBDLR10_ACBDLR10_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_ACBDLR10_CID1BD(x)               (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_ACBDLR10_CID1BD_M                GENMASK(21, 16)
#define DDR_PHY_ACBDLR10_CID1BD_X(x)             (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_ACBDLR10_ACBDLR10_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_ACBDLR10_ACBDLR10_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_ACBDLR10_ACBDLR10_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_ACBDLR10_CID2BD(x)               (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_ACBDLR10_CID2BD_M                GENMASK(29, 24)
#define DDR_PHY_ACBDLR10_CID2BD_X(x)             (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_ACBDLR10_ACBDLR10_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_ACBDLR10_ACBDLR10_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_ACBDLR10_ACBDLR10_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:ACBDLR11 */
#define DDR_PHY_ACBDLR11(t)       (t + 0x56c)

#define DDR_PHY_ACBDLR11_CS4BD(x)                ((x) & GENMASK(5, 0))
#define DDR_PHY_ACBDLR11_CS4BD_M                 GENMASK(5, 0)
#define DDR_PHY_ACBDLR11_CS4BD_X(x)              ((x) & GENMASK(5, 0))

#define DDR_PHY_ACBDLR11_ACBDLR11_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_ACBDLR11_ACBDLR11_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_ACBDLR11_ACBDLR11_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_ACBDLR11_CS5BD(x)                (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_ACBDLR11_CS5BD_M                 GENMASK(13, 8)
#define DDR_PHY_ACBDLR11_CS5BD_X(x)              (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_ACBDLR11_ACBDLR11_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_ACBDLR11_ACBDLR11_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_ACBDLR11_ACBDLR11_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_ACBDLR11_CS6BD(x)                (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_ACBDLR11_CS6BD_M                 GENMASK(21, 16)
#define DDR_PHY_ACBDLR11_CS6BD_X(x)              (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_ACBDLR11_ACBDLR11_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_ACBDLR11_ACBDLR11_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_ACBDLR11_ACBDLR11_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_ACBDLR11_CS7BD(x)                (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_ACBDLR11_CS7BD_M                 GENMASK(29, 24)
#define DDR_PHY_ACBDLR11_CS7BD_X(x)              (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_ACBDLR11_ACBDLR11_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_ACBDLR11_ACBDLR11_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_ACBDLR11_ACBDLR11_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:ACBDLR12 */
#define DDR_PHY_ACBDLR12(t)       (t + 0x570)

#define DDR_PHY_ACBDLR12_CS8BD(x)                ((x) & GENMASK(5, 0))
#define DDR_PHY_ACBDLR12_CS8BD_M                 GENMASK(5, 0)
#define DDR_PHY_ACBDLR12_CS8BD_X(x)              ((x) & GENMASK(5, 0))

#define DDR_PHY_ACBDLR12_ACBDLR12_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_ACBDLR12_ACBDLR12_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_ACBDLR12_ACBDLR12_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_ACBDLR12_CS9BD(x)                (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_ACBDLR12_CS9BD_M                 GENMASK(13, 8)
#define DDR_PHY_ACBDLR12_CS9BD_X(x)              (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_ACBDLR12_ACBDLR12_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_ACBDLR12_ACBDLR12_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_ACBDLR12_ACBDLR12_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_ACBDLR12_CS10BD(x)               (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_ACBDLR12_CS10BD_M                GENMASK(21, 16)
#define DDR_PHY_ACBDLR12_CS10BD_X(x)             (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_ACBDLR12_ACBDLR12_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_ACBDLR12_ACBDLR12_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_ACBDLR12_ACBDLR12_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_ACBDLR12_CS11BD(x)               (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_ACBDLR12_CS11BD_M                GENMASK(29, 24)
#define DDR_PHY_ACBDLR12_CS11BD_X(x)             (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_ACBDLR12_ACBDLR12_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_ACBDLR12_ACBDLR12_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_ACBDLR12_ACBDLR12_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:ACBDLR13 */
#define DDR_PHY_ACBDLR13(t)       (t + 0x574)

#define DDR_PHY_ACBDLR13_ODT4BD(x)               ((x) & GENMASK(5, 0))
#define DDR_PHY_ACBDLR13_ODT4BD_M                GENMASK(5, 0)
#define DDR_PHY_ACBDLR13_ODT4BD_X(x)             ((x) & GENMASK(5, 0))

#define DDR_PHY_ACBDLR13_ACBDLR13_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_ACBDLR13_ACBDLR13_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_ACBDLR13_ACBDLR13_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_ACBDLR13_ODT5BD(x)               (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_ACBDLR13_ODT5BD_M                GENMASK(13, 8)
#define DDR_PHY_ACBDLR13_ODT5BD_X(x)             (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_ACBDLR13_ACBDLR13_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_ACBDLR13_ACBDLR13_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_ACBDLR13_ACBDLR13_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_ACBDLR13_ODT6BD(x)               (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_ACBDLR13_ODT6BD_M                GENMASK(21, 16)
#define DDR_PHY_ACBDLR13_ODT6BD_X(x)             (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_ACBDLR13_ACBDLR13_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_ACBDLR13_ACBDLR13_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_ACBDLR13_ACBDLR13_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_ACBDLR13_ODT7BD(x)               (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_ACBDLR13_ODT7BD_M                GENMASK(29, 24)
#define DDR_PHY_ACBDLR13_ODT7BD_X(x)             (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_ACBDLR13_ACBDLR13_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_ACBDLR13_ACBDLR13_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_ACBDLR13_ACBDLR13_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:ACBDLR14 */
#define DDR_PHY_ACBDLR14(t)       (t + 0x578)

#define DDR_PHY_ACBDLR14_CKE4BD(x)               ((x) & GENMASK(5, 0))
#define DDR_PHY_ACBDLR14_CKE4BD_M                GENMASK(5, 0)
#define DDR_PHY_ACBDLR14_CKE4BD_X(x)             ((x) & GENMASK(5, 0))

#define DDR_PHY_ACBDLR14_ACBDLR14_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_ACBDLR14_ACBDLR14_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_ACBDLR14_ACBDLR14_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_ACBDLR14_CKE5BD(x)               (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_ACBDLR14_CKE5BD_M                GENMASK(13, 8)
#define DDR_PHY_ACBDLR14_CKE5BD_X(x)             (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_ACBDLR14_ACBDLR14_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_ACBDLR14_ACBDLR14_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_ACBDLR14_ACBDLR14_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_ACBDLR14_CKE6BD(x)               (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_ACBDLR14_CKE6BD_M                GENMASK(21, 16)
#define DDR_PHY_ACBDLR14_CKE6BD_X(x)             (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_ACBDLR14_ACBDLR14_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_ACBDLR14_ACBDLR14_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_ACBDLR14_ACBDLR14_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_ACBDLR14_CKE7BD(x)               (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_ACBDLR14_CKE7BD_M                GENMASK(29, 24)
#define DDR_PHY_ACBDLR14_CKE7BD_X(x)             (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_ACBDLR14_ACBDLR14_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_ACBDLR14_ACBDLR14_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_ACBDLR14_ACBDLR14_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:ACLCDLR */
#define DDR_PHY_ACLCDLR(t)        (t + 0x580)

#define DDR_PHY_ACLCDLR_ACD(x)                   ((x) & GENMASK(8, 0))
#define DDR_PHY_ACLCDLR_ACD_M                    GENMASK(8, 0)
#define DDR_PHY_ACLCDLR_ACD_X(x)                 ((x) & GENMASK(8, 0))

#define DDR_PHY_ACLCDLR_ACLCDLR_RESERVED_31_9(x) (((x) << 9) & GENMASK(31, 9))
#define DDR_PHY_ACLCDLR_ACLCDLR_RESERVED_31_9_M  GENMASK(31, 9)
#define DDR_PHY_ACLCDLR_ACLCDLR_RESERVED_31_9_X(x) (((x) & GENMASK(31, 9)) >> 9)

/*      DDR_PHY:DWC_DDRPHY_PUB:ACMDLR0 */
#define DDR_PHY_ACMDLR0(t)        (t + 0x5a0)

#define DDR_PHY_ACMDLR0_ACMDLR0_IPRD(x)          ((x) & GENMASK(8, 0))
#define DDR_PHY_ACMDLR0_ACMDLR0_IPRD_M           GENMASK(8, 0)
#define DDR_PHY_ACMDLR0_ACMDLR0_IPRD_X(x)        ((x) & GENMASK(8, 0))

#define DDR_PHY_ACMDLR0_ACMDLR0_RESERVED_15_9(x) (((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_ACMDLR0_ACMDLR0_RESERVED_15_9_M  GENMASK(15, 9)
#define DDR_PHY_ACMDLR0_ACMDLR0_RESERVED_15_9_X(x) (((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_ACMDLR0_ACMDLR0_TPRD(x)          (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_ACMDLR0_ACMDLR0_TPRD_M           GENMASK(24, 16)
#define DDR_PHY_ACMDLR0_ACMDLR0_TPRD_X(x)        (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_ACMDLR0_ACMDLR0_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_ACMDLR0_ACMDLR0_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_ACMDLR0_ACMDLR0_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:ACMDLR1 */
#define DDR_PHY_ACMDLR1(t)        (t + 0x5a4)

#define DDR_PHY_ACMDLR1_ACMDLR1_MDLD(x)          ((x) & GENMASK(8, 0))
#define DDR_PHY_ACMDLR1_ACMDLR1_MDLD_M           GENMASK(8, 0)
#define DDR_PHY_ACMDLR1_ACMDLR1_MDLD_X(x)        ((x) & GENMASK(8, 0))

#define DDR_PHY_ACMDLR1_ACMDLR1_RESERVED_31_9(x) (((x) << 9) & GENMASK(31, 9))
#define DDR_PHY_ACMDLR1_ACMDLR1_RESERVED_31_9_M  GENMASK(31, 9)
#define DDR_PHY_ACMDLR1_ACMDLR1_RESERVED_31_9_X(x) (((x) & GENMASK(31, 9)) >> 9)

/*      DDR_PHY:DWC_DDRPHY_PUB:ZQCR */
#define DDR_PHY_ZQCR(t)           (t + 0x680)

#define DDR_PHY_ZQCR_RESERVED_0(x)               ((x) & GENMASK(0, 0))
#define DDR_PHY_ZQCR_RESERVED_0_M                GENMASK(0, 0)
#define DDR_PHY_ZQCR_RESERVED_0_X(x)             ((x) & GENMASK(0, 0))

#define DDR_PHY_ZQCR_TERM_OFF(x)                 (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_ZQCR_TERM_OFF_M                  GENMASK(1, 1)
#define DDR_PHY_ZQCR_TERM_OFF_X(x)               (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_ZQCR_ZQPD(x)                     (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_ZQCR_ZQPD_M                      GENMASK(2, 2)
#define DDR_PHY_ZQCR_ZQPD_X(x)                   (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_ZQCR_ZQCR_RESERVED_7_3(x)        (((x) << 3) & GENMASK(7, 3))
#define DDR_PHY_ZQCR_ZQCR_RESERVED_7_3_M         GENMASK(7, 3)
#define DDR_PHY_ZQCR_ZQCR_RESERVED_7_3_X(x)      (((x) & GENMASK(7, 3)) >> 3)

#define DDR_PHY_ZQCR_PGWAIT(x)                   (((x) << 8) & GENMASK(10, 8))
#define DDR_PHY_ZQCR_PGWAIT_M                    GENMASK(10, 8)
#define DDR_PHY_ZQCR_PGWAIT_X(x)                 (((x) & GENMASK(10, 8)) >> 8)

#define DDR_PHY_ZQCR_ZCALT(x)                    (((x) << 11) & GENMASK(13, 11))
#define DDR_PHY_ZQCR_ZCALT_M                     GENMASK(13, 11)
#define DDR_PHY_ZQCR_ZCALT_X(x)                  (((x) & GENMASK(13, 11)) >> 11)

#define DDR_PHY_ZQCR_AVGMAX(x)                   (((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_ZQCR_AVGMAX_M                    GENMASK(15, 14)
#define DDR_PHY_ZQCR_AVGMAX_X(x)                 (((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_ZQCR_AVGEN(x)                    (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_ZQCR_AVGEN_M                     GENMASK(16, 16)
#define DDR_PHY_ZQCR_AVGEN_X(x)                  (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_ZQCR_IODLMT(x)                   (((x) << 17) & GENMASK(24, 17))
#define DDR_PHY_ZQCR_IODLMT_M                    GENMASK(24, 17)
#define DDR_PHY_ZQCR_IODLMT_X(x)                 (((x) & GENMASK(24, 17)) >> 17)

#define DDR_PHY_ZQCR_RESERVED_26_25(x)           (((x) << 25) & GENMASK(26, 25))
#define DDR_PHY_ZQCR_RESERVED_26_25_M            GENMASK(26, 25)
#define DDR_PHY_ZQCR_RESERVED_26_25_X(x)         (((x) & GENMASK(26, 25)) >> 25)

#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE(x)     (((x) << 27) & GENMASK(27, 27))
#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_M      GENMASK(27, 27)
#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_X(x)   (((x) & GENMASK(27, 27)) >> 27)

#define DDR_PHY_ZQCR_ZQCR_RESERVED_31_28(x)      (((x) << 28) & GENMASK(31, 28))
#define DDR_PHY_ZQCR_ZQCR_RESERVED_31_28_M       GENMASK(31, 28)
#define DDR_PHY_ZQCR_ZQCR_RESERVED_31_28_X(x)    (((x) & GENMASK(31, 28)) >> 28)

/*      DDR_PHY:DWC_DDRPHY_PUB:ZQ0PR */
#define DDR_PHY_ZQ0PR(t)          (t + 0x684)

#define DDR_PHY_ZQ0PR_ZQ0PR_RESERVED_7_0(x)      ((x) & GENMASK(7, 0))
#define DDR_PHY_ZQ0PR_ZQ0PR_RESERVED_7_0_M       GENMASK(7, 0)
#define DDR_PHY_ZQ0PR_ZQ0PR_RESERVED_7_0_X(x)    ((x) & GENMASK(7, 0))

#define DDR_PHY_ZQ0PR_ZQ0PR_ZPROG_ASYM_DRV_PU(x) (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_ZQ0PR_ZQ0PR_ZPROG_ASYM_DRV_PU_M  GENMASK(11, 8)
#define DDR_PHY_ZQ0PR_ZQ0PR_ZPROG_ASYM_DRV_PU_X(x) (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_ZQ0PR_ZQ0PR_ZPROG_ASYM_DRV_PD(x) (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_ZQ0PR_ZQ0PR_ZPROG_ASYM_DRV_PD_M  GENMASK(15, 12)
#define DDR_PHY_ZQ0PR_ZQ0PR_ZPROG_ASYM_DRV_PD_X(x)\
	(((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_ZQ0PR_ZQ0PR_ZPROG_PU_ODT_ONLY(x) (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_ZQ0PR_ZQ0PR_ZPROG_PU_ODT_ONLY_M  GENMASK(19, 16)
#define DDR_PHY_ZQ0PR_ZQ0PR_ZPROG_PU_ODT_ONLY_X(x)\
	(((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_ZQ0PR_ZQ0PR_PU_DRV_ADJUST(x)     (((x) << 20) & GENMASK(21, 20))
#define DDR_PHY_ZQ0PR_ZQ0PR_PU_DRV_ADJUST_M      GENMASK(21, 20)
#define DDR_PHY_ZQ0PR_ZQ0PR_PU_DRV_ADJUST_X(x)   (((x) & GENMASK(21, 20)) >> 20)

#define DDR_PHY_ZQ0PR_ZQ0PR_PD_DRV_ADJUST(x)     (((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_ZQ0PR_ZQ0PR_PD_DRV_ADJUST_M      GENMASK(23, 22)
#define DDR_PHY_ZQ0PR_ZQ0PR_PD_DRV_ADJUST_X(x)   (((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_ZQ0PR_ZQ0PR_RESERVED_27_24(x)    (((x) << 24) & GENMASK(27, 24))
#define DDR_PHY_ZQ0PR_ZQ0PR_RESERVED_27_24_M     GENMASK(27, 24)
#define DDR_PHY_ZQ0PR_ZQ0PR_RESERVED_27_24_X(x)  (((x) & GENMASK(27, 24)) >> 24)

#define DDR_PHY_ZQ0PR_ZQ0PR_PU_ODT_ONLY(x)       (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_ZQ0PR_ZQ0PR_PU_ODT_ONLY_M        GENMASK(28, 28)
#define DDR_PHY_ZQ0PR_ZQ0PR_PU_ODT_ONLY_X(x)     (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_ZQ0PR_ZQ0PR_ZSEGBYP(x)           (((x) << 29) & GENMASK(29, 29))
#define DDR_PHY_ZQ0PR_ZQ0PR_ZSEGBYP_M            GENMASK(29, 29)
#define DDR_PHY_ZQ0PR_ZQ0PR_ZSEGBYP_X(x)         (((x) & GENMASK(29, 29)) >> 29)

#define DDR_PHY_ZQ0PR_ZQ0PR_ODT_ZDEN(x)          (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_ZQ0PR_ZQ0PR_ODT_ZDEN_M           GENMASK(30, 30)
#define DDR_PHY_ZQ0PR_ZQ0PR_ODT_ZDEN_X(x)        (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_ZQ0PR_ZQ0PR_DRV_ZDEN(x)          (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_ZQ0PR_ZQ0PR_DRV_ZDEN_M           GENMASK(31, 31)
#define DDR_PHY_ZQ0PR_ZQ0PR_DRV_ZDEN_X(x)        (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:ZQ0DR */
#define DDR_PHY_ZQ0DR(t)          (t + 0x688)

/*      DDR_PHY:DWC_DDRPHY_PUB:ZQ0SR */
#define DDR_PHY_ZQ0SR(t)          (t + 0x68c)

#define DDR_PHY_ZQ0SR_ZQ0SR_ZPD(x)               ((x) & GENMASK(1, 0))
#define DDR_PHY_ZQ0SR_ZQ0SR_ZPD_M                GENMASK(1, 0)
#define DDR_PHY_ZQ0SR_ZQ0SR_ZPD_X(x)             ((x) & GENMASK(1, 0))

#define DDR_PHY_ZQ0SR_ZQ0SR_ZPU(x)               (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_ZQ0SR_ZQ0SR_ZPU_M                GENMASK(3, 2)
#define DDR_PHY_ZQ0SR_ZQ0SR_ZPU_X(x)             (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_ZQ0SR_ZQ0SR_OPD(x)               (((x) << 4) & GENMASK(5, 4))
#define DDR_PHY_ZQ0SR_ZQ0SR_OPD_M                GENMASK(5, 4)
#define DDR_PHY_ZQ0SR_ZQ0SR_OPD_X(x)             (((x) & GENMASK(5, 4)) >> 4)

#define DDR_PHY_ZQ0SR_ZQ0SR_OPU(x)               (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_ZQ0SR_ZQ0SR_OPU_M                GENMASK(7, 6)
#define DDR_PHY_ZQ0SR_ZQ0SR_OPU_X(x)             (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_ZQ0SR_ZQ0SR_ZERR(x)              (((x) << 8) & GENMASK(8, 8))
#define DDR_PHY_ZQ0SR_ZQ0SR_ZERR_M               GENMASK(8, 8)
#define DDR_PHY_ZQ0SR_ZQ0SR_ZERR_X(x)            (((x) & GENMASK(8, 8)) >> 8)

#define DDR_PHY_ZQ0SR_ZQ0SR_ZDONE(x)             (((x) << 9) & GENMASK(9, 9))
#define DDR_PHY_ZQ0SR_ZQ0SR_ZDONE_M              GENMASK(9, 9)
#define DDR_PHY_ZQ0SR_ZQ0SR_ZDONE_X(x)           (((x) & GENMASK(9, 9)) >> 9)

#define DDR_PHY_ZQ0SR_ZQ0SR_PU_DRV_SAT(x)        (((x) << 10) & GENMASK(10, 10))
#define DDR_PHY_ZQ0SR_ZQ0SR_PU_DRV_SAT_M         GENMASK(10, 10)
#define DDR_PHY_ZQ0SR_ZQ0SR_PU_DRV_SAT_X(x)      (((x) & GENMASK(10, 10)) >> 10)

#define DDR_PHY_ZQ0SR_ZQ0SR_PD_DRV_SAT(x)        (((x) << 11) & GENMASK(11, 11))
#define DDR_PHY_ZQ0SR_ZQ0SR_PD_DRV_SAT_M         GENMASK(11, 11)
#define DDR_PHY_ZQ0SR_ZQ0SR_PD_DRV_SAT_X(x)      (((x) & GENMASK(11, 11)) >> 11)

#define DDR_PHY_ZQ0SR_ZQ0SR_RESERVED_31_12(x)    (((x) << 12) & GENMASK(31, 12))
#define DDR_PHY_ZQ0SR_ZQ0SR_RESERVED_31_12_M     GENMASK(31, 12)
#define DDR_PHY_ZQ0SR_ZQ0SR_RESERVED_31_12_X(x)  (((x) & GENMASK(31, 12)) >> 12)

/*      DDR_PHY:DWC_DDRPHY_PUB:ZQ1PR */
#define DDR_PHY_ZQ1PR(t)          (t + 0x694)

#define DDR_PHY_ZQ1PR_ZQ1PR_RESERVED_7_0(x)      ((x) & GENMASK(7, 0))
#define DDR_PHY_ZQ1PR_ZQ1PR_RESERVED_7_0_M       GENMASK(7, 0)
#define DDR_PHY_ZQ1PR_ZQ1PR_RESERVED_7_0_X(x)    ((x) & GENMASK(7, 0))

#define DDR_PHY_ZQ1PR_ZQ1PR_ZPROG_ASYM_DRV_PU(x) (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_ZQ1PR_ZQ1PR_ZPROG_ASYM_DRV_PU_M  GENMASK(11, 8)
#define DDR_PHY_ZQ1PR_ZQ1PR_ZPROG_ASYM_DRV_PU_X(x) (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_ZQ1PR_ZQ1PR_ZPROG_ASYM_DRV_PD(x) (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_ZQ1PR_ZQ1PR_ZPROG_ASYM_DRV_PD_M  GENMASK(15, 12)
#define DDR_PHY_ZQ1PR_ZQ1PR_ZPROG_ASYM_DRV_PD_X(x)\
	(((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_ZQ1PR_ZQ1PR_ZPROG_PU_ODT_ONLY(x) (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_ZQ1PR_ZQ1PR_ZPROG_PU_ODT_ONLY_M  GENMASK(19, 16)
#define DDR_PHY_ZQ1PR_ZQ1PR_ZPROG_PU_ODT_ONLY_X(x)\
	(((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_ZQ1PR_ZQ1PR_PU_DRV_ADJUST(x)     (((x) << 20) & GENMASK(21, 20))
#define DDR_PHY_ZQ1PR_ZQ1PR_PU_DRV_ADJUST_M      GENMASK(21, 20)
#define DDR_PHY_ZQ1PR_ZQ1PR_PU_DRV_ADJUST_X(x)   (((x) & GENMASK(21, 20)) >> 20)

#define DDR_PHY_ZQ1PR_ZQ1PR_PD_DRV_ADJUST(x)     (((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_ZQ1PR_ZQ1PR_PD_DRV_ADJUST_M      GENMASK(23, 22)
#define DDR_PHY_ZQ1PR_ZQ1PR_PD_DRV_ADJUST_X(x)   (((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_ZQ1PR_ZQ1PR_RESERVED_27_24(x)    (((x) << 24) & GENMASK(27, 24))
#define DDR_PHY_ZQ1PR_ZQ1PR_RESERVED_27_24_M     GENMASK(27, 24)
#define DDR_PHY_ZQ1PR_ZQ1PR_RESERVED_27_24_X(x)  (((x) & GENMASK(27, 24)) >> 24)

#define DDR_PHY_ZQ1PR_ZQ1PR_PU_ODT_ONLY(x)       (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_ZQ1PR_ZQ1PR_PU_ODT_ONLY_M        GENMASK(28, 28)
#define DDR_PHY_ZQ1PR_ZQ1PR_PU_ODT_ONLY_X(x)     (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_ZQ1PR_ZQ1PR_ZSEGBYP(x)           (((x) << 29) & GENMASK(29, 29))
#define DDR_PHY_ZQ1PR_ZQ1PR_ZSEGBYP_M            GENMASK(29, 29)
#define DDR_PHY_ZQ1PR_ZQ1PR_ZSEGBYP_X(x)         (((x) & GENMASK(29, 29)) >> 29)

#define DDR_PHY_ZQ1PR_ZQ1PR_ODT_ZDEN(x)          (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_ZQ1PR_ZQ1PR_ODT_ZDEN_M           GENMASK(30, 30)
#define DDR_PHY_ZQ1PR_ZQ1PR_ODT_ZDEN_X(x)        (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_ZQ1PR_ZQ1PR_DRV_ZDEN(x)          (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_ZQ1PR_ZQ1PR_DRV_ZDEN_M           GENMASK(31, 31)
#define DDR_PHY_ZQ1PR_ZQ1PR_DRV_ZDEN_X(x)        (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:ZQ1DR */
#define DDR_PHY_ZQ1DR(t)          (t + 0x698)

/*      DDR_PHY:DWC_DDRPHY_PUB:ZQ1SR */
#define DDR_PHY_ZQ1SR(t)          (t + 0x69c)

#define DDR_PHY_ZQ1SR_ZQ1SR_ZPD(x)               ((x) & GENMASK(1, 0))
#define DDR_PHY_ZQ1SR_ZQ1SR_ZPD_M                GENMASK(1, 0)
#define DDR_PHY_ZQ1SR_ZQ1SR_ZPD_X(x)             ((x) & GENMASK(1, 0))

#define DDR_PHY_ZQ1SR_ZQ1SR_ZPU(x)               (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_ZQ1SR_ZQ1SR_ZPU_M                GENMASK(3, 2)
#define DDR_PHY_ZQ1SR_ZQ1SR_ZPU_X(x)             (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_ZQ1SR_ZQ1SR_OPD(x)               (((x) << 4) & GENMASK(5, 4))
#define DDR_PHY_ZQ1SR_ZQ1SR_OPD_M                GENMASK(5, 4)
#define DDR_PHY_ZQ1SR_ZQ1SR_OPD_X(x)             (((x) & GENMASK(5, 4)) >> 4)

#define DDR_PHY_ZQ1SR_ZQ1SR_OPU(x)               (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_ZQ1SR_ZQ1SR_OPU_M                GENMASK(7, 6)
#define DDR_PHY_ZQ1SR_ZQ1SR_OPU_X(x)             (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_ZQ1SR_ZQ1SR_ZERR(x)              (((x) << 8) & GENMASK(8, 8))
#define DDR_PHY_ZQ1SR_ZQ1SR_ZERR_M               GENMASK(8, 8)
#define DDR_PHY_ZQ1SR_ZQ1SR_ZERR_X(x)            (((x) & GENMASK(8, 8)) >> 8)

#define DDR_PHY_ZQ1SR_ZQ1SR_ZDONE(x)             (((x) << 9) & GENMASK(9, 9))
#define DDR_PHY_ZQ1SR_ZQ1SR_ZDONE_M              GENMASK(9, 9)
#define DDR_PHY_ZQ1SR_ZQ1SR_ZDONE_X(x)           (((x) & GENMASK(9, 9)) >> 9)

#define DDR_PHY_ZQ1SR_ZQ1SR_PU_DRV_SAT(x)        (((x) << 10) & GENMASK(10, 10))
#define DDR_PHY_ZQ1SR_ZQ1SR_PU_DRV_SAT_M         GENMASK(10, 10)
#define DDR_PHY_ZQ1SR_ZQ1SR_PU_DRV_SAT_X(x)      (((x) & GENMASK(10, 10)) >> 10)

#define DDR_PHY_ZQ1SR_ZQ1SR_PD_DRV_SAT(x)        (((x) << 11) & GENMASK(11, 11))
#define DDR_PHY_ZQ1SR_ZQ1SR_PD_DRV_SAT_M         GENMASK(11, 11)
#define DDR_PHY_ZQ1SR_ZQ1SR_PD_DRV_SAT_X(x)      (((x) & GENMASK(11, 11)) >> 11)

#define DDR_PHY_ZQ1SR_ZQ1SR_RESERVED_31_12(x)    (((x) << 12) & GENMASK(31, 12))
#define DDR_PHY_ZQ1SR_ZQ1SR_RESERVED_31_12_M     GENMASK(31, 12)
#define DDR_PHY_ZQ1SR_ZQ1SR_RESERVED_31_12_X(x)  (((x) & GENMASK(31, 12)) >> 12)

/*      DDR_PHY:DWC_DDRPHY_PUB:ZQ2PR */
#define DDR_PHY_ZQ2PR(t)          (t + 0x6a4)

#define DDR_PHY_ZQ2PR_ZQ2PR_RESERVED_7_0(x)      ((x) & GENMASK(7, 0))
#define DDR_PHY_ZQ2PR_ZQ2PR_RESERVED_7_0_M       GENMASK(7, 0)
#define DDR_PHY_ZQ2PR_ZQ2PR_RESERVED_7_0_X(x)    ((x) & GENMASK(7, 0))

#define DDR_PHY_ZQ2PR_ZQ2PR_ZPROG_ASYM_DRV_PU(x) (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_ZQ2PR_ZQ2PR_ZPROG_ASYM_DRV_PU_M  GENMASK(11, 8)
#define DDR_PHY_ZQ2PR_ZQ2PR_ZPROG_ASYM_DRV_PU_X(x) (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_ZQ2PR_ZQ2PR_ZPROG_ASYM_DRV_PD(x) (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_ZQ2PR_ZQ2PR_ZPROG_ASYM_DRV_PD_M  GENMASK(15, 12)
#define DDR_PHY_ZQ2PR_ZQ2PR_ZPROG_ASYM_DRV_PD_X(x)\
	(((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_ZQ2PR_ZQ2PR_ZPROG_PU_ODT_ONLY(x) (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_ZQ2PR_ZQ2PR_ZPROG_PU_ODT_ONLY_M  GENMASK(19, 16)
#define DDR_PHY_ZQ2PR_ZQ2PR_ZPROG_PU_ODT_ONLY_X(x)\
	(((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_ZQ2PR_ZQ2PR_PU_DRV_ADJUST(x)     (((x) << 20) & GENMASK(21, 20))
#define DDR_PHY_ZQ2PR_ZQ2PR_PU_DRV_ADJUST_M      GENMASK(21, 20)
#define DDR_PHY_ZQ2PR_ZQ2PR_PU_DRV_ADJUST_X(x)   (((x) & GENMASK(21, 20)) >> 20)

#define DDR_PHY_ZQ2PR_ZQ2PR_PD_DRV_ADJUST(x)     (((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_ZQ2PR_ZQ2PR_PD_DRV_ADJUST_M      GENMASK(23, 22)
#define DDR_PHY_ZQ2PR_ZQ2PR_PD_DRV_ADJUST_X(x)   (((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_ZQ2PR_ZQ2PR_RESERVED_27_24(x)    (((x) << 24) & GENMASK(27, 24))
#define DDR_PHY_ZQ2PR_ZQ2PR_RESERVED_27_24_M     GENMASK(27, 24)
#define DDR_PHY_ZQ2PR_ZQ2PR_RESERVED_27_24_X(x)  (((x) & GENMASK(27, 24)) >> 24)

#define DDR_PHY_ZQ2PR_ZQ2PR_PU_ODT_ONLY(x)       (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_ZQ2PR_ZQ2PR_PU_ODT_ONLY_M        GENMASK(28, 28)
#define DDR_PHY_ZQ2PR_ZQ2PR_PU_ODT_ONLY_X(x)     (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_ZQ2PR_ZQ2PR_ZSEGBYP(x)           (((x) << 29) & GENMASK(29, 29))
#define DDR_PHY_ZQ2PR_ZQ2PR_ZSEGBYP_M            GENMASK(29, 29)
#define DDR_PHY_ZQ2PR_ZQ2PR_ZSEGBYP_X(x)         (((x) & GENMASK(29, 29)) >> 29)

#define DDR_PHY_ZQ2PR_ZQ2PR_ODT_ZDEN(x)          (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_ZQ2PR_ZQ2PR_ODT_ZDEN_M           GENMASK(30, 30)
#define DDR_PHY_ZQ2PR_ZQ2PR_ODT_ZDEN_X(x)        (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_ZQ2PR_ZQ2PR_DRV_ZDEN(x)          (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_ZQ2PR_ZQ2PR_DRV_ZDEN_M           GENMASK(31, 31)
#define DDR_PHY_ZQ2PR_ZQ2PR_DRV_ZDEN_X(x)        (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:ZQ2DR */
#define DDR_PHY_ZQ2DR(t)          (t + 0x6a8)

/*      DDR_PHY:DWC_DDRPHY_PUB:ZQ2SR */
#define DDR_PHY_ZQ2SR(t)          (t + 0x6ac)

#define DDR_PHY_ZQ2SR_ZQ2SR_ZPD(x)               ((x) & GENMASK(1, 0))
#define DDR_PHY_ZQ2SR_ZQ2SR_ZPD_M                GENMASK(1, 0)
#define DDR_PHY_ZQ2SR_ZQ2SR_ZPD_X(x)             ((x) & GENMASK(1, 0))

#define DDR_PHY_ZQ2SR_ZQ2SR_ZPU(x)               (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_ZQ2SR_ZQ2SR_ZPU_M                GENMASK(3, 2)
#define DDR_PHY_ZQ2SR_ZQ2SR_ZPU_X(x)             (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_ZQ2SR_ZQ2SR_OPD(x)               (((x) << 4) & GENMASK(5, 4))
#define DDR_PHY_ZQ2SR_ZQ2SR_OPD_M                GENMASK(5, 4)
#define DDR_PHY_ZQ2SR_ZQ2SR_OPD_X(x)             (((x) & GENMASK(5, 4)) >> 4)

#define DDR_PHY_ZQ2SR_ZQ2SR_OPU(x)               (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_ZQ2SR_ZQ2SR_OPU_M                GENMASK(7, 6)
#define DDR_PHY_ZQ2SR_ZQ2SR_OPU_X(x)             (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_ZQ2SR_ZQ2SR_ZERR(x)              (((x) << 8) & GENMASK(8, 8))
#define DDR_PHY_ZQ2SR_ZQ2SR_ZERR_M               GENMASK(8, 8)
#define DDR_PHY_ZQ2SR_ZQ2SR_ZERR_X(x)            (((x) & GENMASK(8, 8)) >> 8)

#define DDR_PHY_ZQ2SR_ZQ2SR_ZDONE(x)             (((x) << 9) & GENMASK(9, 9))
#define DDR_PHY_ZQ2SR_ZQ2SR_ZDONE_M              GENMASK(9, 9)
#define DDR_PHY_ZQ2SR_ZQ2SR_ZDONE_X(x)           (((x) & GENMASK(9, 9)) >> 9)

#define DDR_PHY_ZQ2SR_ZQ2SR_PU_DRV_SAT(x)        (((x) << 10) & GENMASK(10, 10))
#define DDR_PHY_ZQ2SR_ZQ2SR_PU_DRV_SAT_M         GENMASK(10, 10)
#define DDR_PHY_ZQ2SR_ZQ2SR_PU_DRV_SAT_X(x)      (((x) & GENMASK(10, 10)) >> 10)

#define DDR_PHY_ZQ2SR_ZQ2SR_PD_DRV_SAT(x)        (((x) << 11) & GENMASK(11, 11))
#define DDR_PHY_ZQ2SR_ZQ2SR_PD_DRV_SAT_M         GENMASK(11, 11)
#define DDR_PHY_ZQ2SR_ZQ2SR_PD_DRV_SAT_X(x)      (((x) & GENMASK(11, 11)) >> 11)

#define DDR_PHY_ZQ2SR_ZQ2SR_RESERVED_31_12(x)    (((x) << 12) & GENMASK(31, 12))
#define DDR_PHY_ZQ2SR_ZQ2SR_RESERVED_31_12_M     GENMASK(31, 12)
#define DDR_PHY_ZQ2SR_ZQ2SR_RESERVED_31_12_X(x)  (((x) & GENMASK(31, 12)) >> 12)

/*      DDR_PHY:DWC_DDRPHY_PUB:ZQ3PR */
#define DDR_PHY_ZQ3PR(t)          (t + 0x6b4)

#define DDR_PHY_ZQ3PR_ZQ3PR_RESERVED_7_0(x)      ((x) & GENMASK(7, 0))
#define DDR_PHY_ZQ3PR_ZQ3PR_RESERVED_7_0_M       GENMASK(7, 0)
#define DDR_PHY_ZQ3PR_ZQ3PR_RESERVED_7_0_X(x)    ((x) & GENMASK(7, 0))

#define DDR_PHY_ZQ3PR_ZQ3PR_ZPROG_ASYM_DRV_PU(x) (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_ZQ3PR_ZQ3PR_ZPROG_ASYM_DRV_PU_M  GENMASK(11, 8)
#define DDR_PHY_ZQ3PR_ZQ3PR_ZPROG_ASYM_DRV_PU_X(x) (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_ZQ3PR_ZQ3PR_ZPROG_ASYM_DRV_PD(x) (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_ZQ3PR_ZQ3PR_ZPROG_ASYM_DRV_PD_M  GENMASK(15, 12)
#define DDR_PHY_ZQ3PR_ZQ3PR_ZPROG_ASYM_DRV_PD_X(x)\
	(((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_ZQ3PR_ZQ3PR_ZPROG_PU_ODT_ONLY(x) (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_ZQ3PR_ZQ3PR_ZPROG_PU_ODT_ONLY_M  GENMASK(19, 16)
#define DDR_PHY_ZQ3PR_ZQ3PR_ZPROG_PU_ODT_ONLY_X(x)\
	(((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_ZQ3PR_ZQ3PR_PU_DRV_ADJUST(x)     (((x) << 20) & GENMASK(21, 20))
#define DDR_PHY_ZQ3PR_ZQ3PR_PU_DRV_ADJUST_M      GENMASK(21, 20)
#define DDR_PHY_ZQ3PR_ZQ3PR_PU_DRV_ADJUST_X(x)   (((x) & GENMASK(21, 20)) >> 20)

#define DDR_PHY_ZQ3PR_ZQ3PR_PD_DRV_ADJUST(x)     (((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_ZQ3PR_ZQ3PR_PD_DRV_ADJUST_M      GENMASK(23, 22)
#define DDR_PHY_ZQ3PR_ZQ3PR_PD_DRV_ADJUST_X(x)   (((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_ZQ3PR_ZQ3PR_RESERVED_27_24(x)    (((x) << 24) & GENMASK(27, 24))
#define DDR_PHY_ZQ3PR_ZQ3PR_RESERVED_27_24_M     GENMASK(27, 24)
#define DDR_PHY_ZQ3PR_ZQ3PR_RESERVED_27_24_X(x)  (((x) & GENMASK(27, 24)) >> 24)

#define DDR_PHY_ZQ3PR_ZQ3PR_PU_ODT_ONLY(x)       (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_ZQ3PR_ZQ3PR_PU_ODT_ONLY_M        GENMASK(28, 28)
#define DDR_PHY_ZQ3PR_ZQ3PR_PU_ODT_ONLY_X(x)     (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_ZQ3PR_ZQ3PR_ZSEGBYP(x)           (((x) << 29) & GENMASK(29, 29))
#define DDR_PHY_ZQ3PR_ZQ3PR_ZSEGBYP_M            GENMASK(29, 29)
#define DDR_PHY_ZQ3PR_ZQ3PR_ZSEGBYP_X(x)         (((x) & GENMASK(29, 29)) >> 29)

#define DDR_PHY_ZQ3PR_ZQ3PR_ODT_ZDEN(x)          (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_ZQ3PR_ZQ3PR_ODT_ZDEN_M           GENMASK(30, 30)
#define DDR_PHY_ZQ3PR_ZQ3PR_ODT_ZDEN_X(x)        (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_ZQ3PR_ZQ3PR_DRV_ZDEN(x)          (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_ZQ3PR_ZQ3PR_DRV_ZDEN_M           GENMASK(31, 31)
#define DDR_PHY_ZQ3PR_ZQ3PR_DRV_ZDEN_X(x)        (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:ZQ3DR */
#define DDR_PHY_ZQ3DR(t)          (t + 0x6b8)

/*      DDR_PHY:DWC_DDRPHY_PUB:ZQ3SR */
#define DDR_PHY_ZQ3SR(t)          (t + 0x6bc)

#define DDR_PHY_ZQ3SR_ZQ3SR_ZPD(x)               ((x) & GENMASK(1, 0))
#define DDR_PHY_ZQ3SR_ZQ3SR_ZPD_M                GENMASK(1, 0)
#define DDR_PHY_ZQ3SR_ZQ3SR_ZPD_X(x)             ((x) & GENMASK(1, 0))

#define DDR_PHY_ZQ3SR_ZQ3SR_ZPU(x)               (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_ZQ3SR_ZQ3SR_ZPU_M                GENMASK(3, 2)
#define DDR_PHY_ZQ3SR_ZQ3SR_ZPU_X(x)             (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_ZQ3SR_ZQ3SR_OPD(x)               (((x) << 4) & GENMASK(5, 4))
#define DDR_PHY_ZQ3SR_ZQ3SR_OPD_M                GENMASK(5, 4)
#define DDR_PHY_ZQ3SR_ZQ3SR_OPD_X(x)             (((x) & GENMASK(5, 4)) >> 4)

#define DDR_PHY_ZQ3SR_ZQ3SR_OPU(x)               (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_ZQ3SR_ZQ3SR_OPU_M                GENMASK(7, 6)
#define DDR_PHY_ZQ3SR_ZQ3SR_OPU_X(x)             (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_ZQ3SR_ZQ3SR_ZERR(x)              (((x) << 8) & GENMASK(8, 8))
#define DDR_PHY_ZQ3SR_ZQ3SR_ZERR_M               GENMASK(8, 8)
#define DDR_PHY_ZQ3SR_ZQ3SR_ZERR_X(x)            (((x) & GENMASK(8, 8)) >> 8)

#define DDR_PHY_ZQ3SR_ZQ3SR_ZDONE(x)             (((x) << 9) & GENMASK(9, 9))
#define DDR_PHY_ZQ3SR_ZQ3SR_ZDONE_M              GENMASK(9, 9)
#define DDR_PHY_ZQ3SR_ZQ3SR_ZDONE_X(x)           (((x) & GENMASK(9, 9)) >> 9)

#define DDR_PHY_ZQ3SR_ZQ3SR_PU_DRV_SAT(x)        (((x) << 10) & GENMASK(10, 10))
#define DDR_PHY_ZQ3SR_ZQ3SR_PU_DRV_SAT_M         GENMASK(10, 10)
#define DDR_PHY_ZQ3SR_ZQ3SR_PU_DRV_SAT_X(x)      (((x) & GENMASK(10, 10)) >> 10)

#define DDR_PHY_ZQ3SR_ZQ3SR_PD_DRV_SAT(x)        (((x) << 11) & GENMASK(11, 11))
#define DDR_PHY_ZQ3SR_ZQ3SR_PD_DRV_SAT_M         GENMASK(11, 11)
#define DDR_PHY_ZQ3SR_ZQ3SR_PD_DRV_SAT_X(x)      (((x) & GENMASK(11, 11)) >> 11)

#define DDR_PHY_ZQ3SR_ZQ3SR_RESERVED_31_12(x)    (((x) << 12) & GENMASK(31, 12))
#define DDR_PHY_ZQ3SR_ZQ3SR_RESERVED_31_12_M     GENMASK(31, 12)
#define DDR_PHY_ZQ3SR_ZQ3SR_RESERVED_31_12_X(x)  (((x) & GENMASK(31, 12)) >> 12)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0GCR0 */
#define DDR_PHY_DX0GCR0(t)        (t + 0x700)

#define DDR_PHY_DX0GCR0_DX0GCR0_DXEN(x)          ((x) & GENMASK(0, 0))
#define DDR_PHY_DX0GCR0_DX0GCR0_DXEN_M           GENMASK(0, 0)
#define DDR_PHY_DX0GCR0_DX0GCR0_DXEN_X(x)        ((x) & GENMASK(0, 0))

#define DDR_PHY_DX0GCR0_DX0GCR0_DXIOM(x)         (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX0GCR0_DX0GCR0_DXIOM_M          GENMASK(1, 1)
#define DDR_PHY_DX0GCR0_DX0GCR0_DXIOM_X(x)       (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX0GCR0_DX0GCR0_DQSGOE(x)        (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX0GCR0_DX0GCR0_DQSGOE_M         GENMASK(2, 2)
#define DDR_PHY_DX0GCR0_DX0GCR0_DQSGOE_X(x)      (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX0GCR0_DX0GCR0_DQSGODT(x)       (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX0GCR0_DX0GCR0_DQSGODT_M        GENMASK(3, 3)
#define DDR_PHY_DX0GCR0_DX0GCR0_DQSGODT_X(x)     (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX0GCR0_DX0GCR0_RESERVED_4(x)    (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX0GCR0_DX0GCR0_RESERVED_4_M     GENMASK(4, 4)
#define DDR_PHY_DX0GCR0_DX0GCR0_RESERVED_4_X(x)  (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX0GCR0_DX0GCR0_DQSGPDR(x)       (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX0GCR0_DX0GCR0_DQSGPDR_M        GENMASK(5, 5)
#define DDR_PHY_DX0GCR0_DX0GCR0_DQSGPDR_X(x)     (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX0GCR0_DX0GCR0_RESERVED_6(x)    (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX0GCR0_DX0GCR0_RESERVED_6_M     GENMASK(6, 6)
#define DDR_PHY_DX0GCR0_DX0GCR0_RESERVED_6_X(x)  (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX0GCR0_DX0GCR0_PDRAL(x)         (((x) << 7) & GENMASK(8, 7))
#define DDR_PHY_DX0GCR0_DX0GCR0_PDRAL_M          GENMASK(8, 7)
#define DDR_PHY_DX0GCR0_DX0GCR0_PDRAL_X(x)       (((x) & GENMASK(8, 7)) >> 7)

#define DDR_PHY_DX0GCR0_DX0GCR0_RTTOH(x)         (((x) << 9) & GENMASK(10, 9))
#define DDR_PHY_DX0GCR0_DX0GCR0_RTTOH_M          GENMASK(10, 9)
#define DDR_PHY_DX0GCR0_DX0GCR0_RTTOH_X(x)       (((x) & GENMASK(10, 9)) >> 9)

#define DDR_PHY_DX0GCR0_DX0GCR0_RTTOAL(x)        (((x) << 11) & GENMASK(11, 11))
#define DDR_PHY_DX0GCR0_DX0GCR0_RTTOAL_M         GENMASK(11, 11)
#define DDR_PHY_DX0GCR0_DX0GCR0_RTTOAL_X(x)      (((x) & GENMASK(11, 11)) >> 11)

#define DDR_PHY_DX0GCR0_DX0GCR0_DQSSEPDR(x)      (((x) << 12) & GENMASK(12, 12))
#define DDR_PHY_DX0GCR0_DX0GCR0_DQSSEPDR_M       GENMASK(12, 12)
#define DDR_PHY_DX0GCR0_DX0GCR0_DQSSEPDR_X(x)    (((x) & GENMASK(12, 12)) >> 12)

#define DDR_PHY_DX0GCR0_DX0GCR0_DQSNSEPDR(x)     (((x) << 13) & GENMASK(13, 13))
#define DDR_PHY_DX0GCR0_DX0GCR0_DQSNSEPDR_M      GENMASK(13, 13)
#define DDR_PHY_DX0GCR0_DX0GCR0_DQSNSEPDR_X(x)   (((x) & GENMASK(13, 13)) >> 13)

#define DDR_PHY_DX0GCR0_DX0GCR0_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX0GCR0_DX0GCR0_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX0GCR0_DX0GCR0_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX0GCR0_DX0GCR0_PLLRST(x)        (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX0GCR0_DX0GCR0_PLLRST_M         GENMASK(16, 16)
#define DDR_PHY_DX0GCR0_DX0GCR0_PLLRST_X(x)      (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX0GCR0_DX0GCR0_PLLPD(x)         (((x) << 17) & GENMASK(17, 17))
#define DDR_PHY_DX0GCR0_DX0GCR0_PLLPD_M          GENMASK(17, 17)
#define DDR_PHY_DX0GCR0_DX0GCR0_PLLPD_X(x)       (((x) & GENMASK(17, 17)) >> 17)

#define DDR_PHY_DX0GCR0_DX0GCR0_GSHIFT(x)        (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_DX0GCR0_DX0GCR0_GSHIFT_M         GENMASK(18, 18)
#define DDR_PHY_DX0GCR0_DX0GCR0_GSHIFT_X(x)      (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_DX0GCR0_DX0GCR0_PLLBYP(x)        (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_DX0GCR0_DX0GCR0_PLLBYP_M         GENMASK(19, 19)
#define DDR_PHY_DX0GCR0_DX0GCR0_PLLBYP_X(x)      (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_DX0GCR0_DX0GCR0_RDDLY(x)         (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX0GCR0_DX0GCR0_RDDLY_M          GENMASK(23, 20)
#define DDR_PHY_DX0GCR0_DX0GCR0_RDDLY_X(x)       (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX0GCR0_DX0GCR0_RESERVED_29_24(x)\
	(((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX0GCR0_DX0GCR0_RESERVED_29_24_M GENMASK(29, 24)
#define DDR_PHY_DX0GCR0_DX0GCR0_RESERVED_29_24_X(x)\
	(((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX0GCR0_DX0GCR0_MDLEN(x)         (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX0GCR0_DX0GCR0_MDLEN_M          GENMASK(30, 30)
#define DDR_PHY_DX0GCR0_DX0GCR0_MDLEN_X(x)       (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX0GCR0_DX0GCR0_CALBYP(x)        (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX0GCR0_DX0GCR0_CALBYP_M         GENMASK(31, 31)
#define DDR_PHY_DX0GCR0_DX0GCR0_CALBYP_X(x)      (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0GCR1 */
#define DDR_PHY_DX0GCR1(t)        (t + 0x704)

#define DDR_PHY_DX0GCR1_DX0GCR1_RESERVED_15_0(x) ((x) & GENMASK(15, 0))
#define DDR_PHY_DX0GCR1_DX0GCR1_RESERVED_15_0_M  GENMASK(15, 0)
#define DDR_PHY_DX0GCR1_DX0GCR1_RESERVED_15_0_X(x) ((x) & GENMASK(15, 0))

#define DDR_PHY_DX0GCR1_DX0GCR1_DXPDRMODE(x)     (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX0GCR1_DX0GCR1_DXPDRMODE_M      GENMASK(31, 16)
#define DDR_PHY_DX0GCR1_DX0GCR1_DXPDRMODE_X(x)   (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0GCR2 */
#define DDR_PHY_DX0GCR2(t)        (t + 0x708)

#define DDR_PHY_DX0GCR2_DX0GCR2_DXTEMODE(x)      ((x) & GENMASK(15, 0))
#define DDR_PHY_DX0GCR2_DX0GCR2_DXTEMODE_M       GENMASK(15, 0)
#define DDR_PHY_DX0GCR2_DX0GCR2_DXTEMODE_X(x)    ((x) & GENMASK(15, 0))

#define DDR_PHY_DX0GCR2_DX0GCR2_DXOEMODE(x)      (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX0GCR2_DX0GCR2_DXOEMODE_M       GENMASK(31, 16)
#define DDR_PHY_DX0GCR2_DX0GCR2_DXOEMODE_X(x)    (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0GCR3 */
#define DDR_PHY_DX0GCR3(t)        (t + 0x70c)

#define DDR_PHY_DX0GCR3_DX0GCR3_RESERVED_1_0(x)  ((x) & GENMASK(1, 0))
#define DDR_PHY_DX0GCR3_DX0GCR3_RESERVED_1_0_M   GENMASK(1, 0)
#define DDR_PHY_DX0GCR3_DX0GCR3_RESERVED_1_0_X(x) ((x) & GENMASK(1, 0))

#define DDR_PHY_DX0GCR3_DX0GCR3_DSPDRMODE(x)     (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DX0GCR3_DX0GCR3_DSPDRMODE_M      GENMASK(3, 2)
#define DDR_PHY_DX0GCR3_DX0GCR3_DSPDRMODE_X(x)   (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DX0GCR3_DX0GCR3_DSTEMODE(x)      (((x) << 4) & GENMASK(5, 4))
#define DDR_PHY_DX0GCR3_DX0GCR3_DSTEMODE_M       GENMASK(5, 4)
#define DDR_PHY_DX0GCR3_DX0GCR3_DSTEMODE_X(x)    (((x) & GENMASK(5, 4)) >> 4)

#define DDR_PHY_DX0GCR3_DX0GCR3_DSOEMODE(x)      (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX0GCR3_DX0GCR3_DSOEMODE_M       GENMASK(7, 6)
#define DDR_PHY_DX0GCR3_DX0GCR3_DSOEMODE_X(x)    (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX0GCR3_DX0GCR3_RESERVED_9_8(x)  (((x) << 8) & GENMASK(9, 8))
#define DDR_PHY_DX0GCR3_DX0GCR3_RESERVED_9_8_M   GENMASK(9, 8)
#define DDR_PHY_DX0GCR3_DX0GCR3_RESERVED_9_8_X(x) (((x) & GENMASK(9, 8)) >> 8)

#define DDR_PHY_DX0GCR3_DX0GCR3_DMPDRMODE(x)     (((x) << 10) & GENMASK(11, 10))
#define DDR_PHY_DX0GCR3_DX0GCR3_DMPDRMODE_M      GENMASK(11, 10)
#define DDR_PHY_DX0GCR3_DX0GCR3_DMPDRMODE_X(x)   (((x) & GENMASK(11, 10)) >> 10)

#define DDR_PHY_DX0GCR3_DX0GCR3_DMTEMODE(x)      (((x) << 12) & GENMASK(13, 12))
#define DDR_PHY_DX0GCR3_DX0GCR3_DMTEMODE_M       GENMASK(13, 12)
#define DDR_PHY_DX0GCR3_DX0GCR3_DMTEMODE_X(x)    (((x) & GENMASK(13, 12)) >> 12)

#define DDR_PHY_DX0GCR3_DX0GCR3_DMOEMODE(x)      (((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX0GCR3_DX0GCR3_DMOEMODE_M       GENMASK(15, 14)
#define DDR_PHY_DX0GCR3_DX0GCR3_DMOEMODE_X(x)    (((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX0GCR3_DX0GCR3_RESERVED_17_16(x)\
	(((x) << 16) & GENMASK(17, 16))
#define DDR_PHY_DX0GCR3_DX0GCR3_RESERVED_17_16_M GENMASK(17, 16)
#define DDR_PHY_DX0GCR3_DX0GCR3_RESERVED_17_16_X(x)\
	(((x) & GENMASK(17, 16)) >> 16)

#define DDR_PHY_DX0GCR3_DX0GCR3_OEBVT(x)         (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_DX0GCR3_DX0GCR3_OEBVT_M          GENMASK(18, 18)
#define DDR_PHY_DX0GCR3_DX0GCR3_OEBVT_X(x)       (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_DX0GCR3_DX0GCR3_PDRBVT(x)        (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_DX0GCR3_DX0GCR3_PDRBVT_M         GENMASK(19, 19)
#define DDR_PHY_DX0GCR3_DX0GCR3_PDRBVT_X(x)      (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_DX0GCR3_DX0GCR3_TEBVT(x)         (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX0GCR3_DX0GCR3_TEBVT_M          GENMASK(20, 20)
#define DDR_PHY_DX0GCR3_DX0GCR3_TEBVT_X(x)       (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX0GCR3_DX0GCR3_WDSBVT(x)        (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX0GCR3_DX0GCR3_WDSBVT_M         GENMASK(21, 21)
#define DDR_PHY_DX0GCR3_DX0GCR3_WDSBVT_X(x)      (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX0GCR3_DX0GCR3_RDSBVT(x)        (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX0GCR3_DX0GCR3_RDSBVT_M         GENMASK(22, 22)
#define DDR_PHY_DX0GCR3_DX0GCR3_RDSBVT_X(x)      (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX0GCR3_DX0GCR3_RGSLVT(x)        (((x) << 23) & GENMASK(23, 23))
#define DDR_PHY_DX0GCR3_DX0GCR3_RGSLVT_M         GENMASK(23, 23)
#define DDR_PHY_DX0GCR3_DX0GCR3_RGSLVT_X(x)      (((x) & GENMASK(23, 23)) >> 23)

#define DDR_PHY_DX0GCR3_DX0GCR3_WLLVT(x)         (((x) << 24) & GENMASK(24, 24))
#define DDR_PHY_DX0GCR3_DX0GCR3_WLLVT_M          GENMASK(24, 24)
#define DDR_PHY_DX0GCR3_DX0GCR3_WLLVT_X(x)       (((x) & GENMASK(24, 24)) >> 24)

#define DDR_PHY_DX0GCR3_DX0GCR3_WDLVT(x)         (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_DX0GCR3_DX0GCR3_WDLVT_M          GENMASK(25, 25)
#define DDR_PHY_DX0GCR3_DX0GCR3_WDLVT_X(x)       (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_DX0GCR3_DX0GCR3_RDLVT(x)         (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_DX0GCR3_DX0GCR3_RDLVT_M          GENMASK(26, 26)
#define DDR_PHY_DX0GCR3_DX0GCR3_RDLVT_X(x)       (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_DX0GCR3_DX0GCR3_RGLVT(x)         (((x) << 27) & GENMASK(27, 27))
#define DDR_PHY_DX0GCR3_DX0GCR3_RGLVT_M          GENMASK(27, 27)
#define DDR_PHY_DX0GCR3_DX0GCR3_RGLVT_X(x)       (((x) & GENMASK(27, 27)) >> 27)

#define DDR_PHY_DX0GCR3_DX0GCR3_WDBVT(x)         (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_DX0GCR3_DX0GCR3_WDBVT_M          GENMASK(28, 28)
#define DDR_PHY_DX0GCR3_DX0GCR3_WDBVT_X(x)       (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_DX0GCR3_DX0GCR3_RDBVT(x)         (((x) << 29) & GENMASK(29, 29))
#define DDR_PHY_DX0GCR3_DX0GCR3_RDBVT_M          GENMASK(29, 29)
#define DDR_PHY_DX0GCR3_DX0GCR3_RDBVT_X(x)       (((x) & GENMASK(29, 29)) >> 29)

#define DDR_PHY_DX0GCR3_DX0GCR3_WDMBVT(x)        (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX0GCR3_DX0GCR3_WDMBVT_M         GENMASK(30, 30)
#define DDR_PHY_DX0GCR3_DX0GCR3_WDMBVT_X(x)      (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX0GCR3_DX0GCR3_RDMBVT(x)        (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX0GCR3_DX0GCR3_RDMBVT_M         GENMASK(31, 31)
#define DDR_PHY_DX0GCR3_DX0GCR3_RDMBVT_X(x)      (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0GCR4 */
#define DDR_PHY_DX0GCR4(t)        (t + 0x710)

#define DDR_PHY_DX0GCR4_DX0GCR4_DXREFIMON(x)     ((x) & GENMASK(1, 0))
#define DDR_PHY_DX0GCR4_DX0GCR4_DXREFIMON_M      GENMASK(1, 0)
#define DDR_PHY_DX0GCR4_DX0GCR4_DXREFIMON_X(x)   ((x) & GENMASK(1, 0))

#define DDR_PHY_DX0GCR4_DX0GCR4_DXREFIEN(x)      (((x) << 2) & GENMASK(5, 2))
#define DDR_PHY_DX0GCR4_DX0GCR4_DXREFIEN_M       GENMASK(5, 2)
#define DDR_PHY_DX0GCR4_DX0GCR4_DXREFIEN_X(x)    (((x) & GENMASK(5, 2)) >> 2)

#define DDR_PHY_DX0GCR4_DX0GCR4_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX0GCR4_DX0GCR4_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX0GCR4_DX0GCR4_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX0GCR4_DX0GCR4_DXREFSSEL(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX0GCR4_DX0GCR4_DXREFSSEL_M      GENMASK(13, 8)
#define DDR_PHY_DX0GCR4_DX0GCR4_DXREFSSEL_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX0GCR4_DX0GCR4_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX0GCR4_DX0GCR4_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX0GCR4_DX0GCR4_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX0GCR4_DX0GCR4_DXREFESEL(x)     (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX0GCR4_DX0GCR4_DXREFESEL_M      GENMASK(21, 16)
#define DDR_PHY_DX0GCR4_DX0GCR4_DXREFESEL_X(x)   (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX0GCR4_DX0GCR4_RESERVED_24_22(x)\
	(((x) << 22) & GENMASK(24, 22))
#define DDR_PHY_DX0GCR4_DX0GCR4_RESERVED_24_22_M GENMASK(24, 22)
#define DDR_PHY_DX0GCR4_DX0GCR4_RESERVED_24_22_X(x)\
	(((x) & GENMASK(24, 22)) >> 22)

#define DDR_PHY_DX0GCR4_DX0GCR4_DXREFSEN(x)      (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_DX0GCR4_DX0GCR4_DXREFSEN_M       GENMASK(25, 25)
#define DDR_PHY_DX0GCR4_DX0GCR4_DXREFSEN_X(x)    (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_DX0GCR4_DX0GCR4_DXREFEEN(x)      (((x) << 26) & GENMASK(27, 26))
#define DDR_PHY_DX0GCR4_DX0GCR4_DXREFEEN_M       GENMASK(27, 26)
#define DDR_PHY_DX0GCR4_DX0GCR4_DXREFEEN_X(x)    (((x) & GENMASK(27, 26)) >> 26)

#define DDR_PHY_DX0GCR4_DX0GCR4_DXREFPEN(x)      (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_DX0GCR4_DX0GCR4_DXREFPEN_M       GENMASK(28, 28)
#define DDR_PHY_DX0GCR4_DX0GCR4_DXREFPEN_X(x)    (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_DX0GCR4_DX0GCR4_DXREFIOM(x)      (((x) << 29) & GENMASK(31, 29))
#define DDR_PHY_DX0GCR4_DX0GCR4_DXREFIOM_M       GENMASK(31, 29)
#define DDR_PHY_DX0GCR4_DX0GCR4_DXREFIOM_X(x)    (((x) & GENMASK(31, 29)) >> 29)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0GCR5 */
#define DDR_PHY_DX0GCR5(t)        (t + 0x714)

#define DDR_PHY_DX0GCR5_DX0GCR5_DXREFISELR0(x)   ((x) & GENMASK(5, 0))
#define DDR_PHY_DX0GCR5_DX0GCR5_DXREFISELR0_M    GENMASK(5, 0)
#define DDR_PHY_DX0GCR5_DX0GCR5_DXREFISELR0_X(x) ((x) & GENMASK(5, 0))

#define DDR_PHY_DX0GCR5_DX0GCR5_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX0GCR5_DX0GCR5_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX0GCR5_DX0GCR5_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX0GCR5_DX0GCR5_DXREFISELR1(x)   (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX0GCR5_DX0GCR5_DXREFISELR1_M    GENMASK(13, 8)
#define DDR_PHY_DX0GCR5_DX0GCR5_DXREFISELR1_X(x) (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX0GCR5_DX0GCR5_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX0GCR5_DX0GCR5_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX0GCR5_DX0GCR5_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX0GCR5_DX0GCR5_DXREFISELR2(x)   (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX0GCR5_DX0GCR5_DXREFISELR2_M    GENMASK(21, 16)
#define DDR_PHY_DX0GCR5_DX0GCR5_DXREFISELR2_X(x) (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX0GCR5_DX0GCR5_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX0GCR5_DX0GCR5_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX0GCR5_DX0GCR5_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX0GCR5_DX0GCR5_DXREFISELR3(x)   (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX0GCR5_DX0GCR5_DXREFISELR3_M    GENMASK(29, 24)
#define DDR_PHY_DX0GCR5_DX0GCR5_DXREFISELR3_X(x) (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX0GCR5_DX0GCR5_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX0GCR5_DX0GCR5_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX0GCR5_DX0GCR5_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0GCR6 */
#define DDR_PHY_DX0GCR6(t)        (t + 0x718)

#define DDR_PHY_DX0GCR6_DX0GCR6_DXDQVREFR0(x)    ((x) & GENMASK(5, 0))
#define DDR_PHY_DX0GCR6_DX0GCR6_DXDQVREFR0_M     GENMASK(5, 0)
#define DDR_PHY_DX0GCR6_DX0GCR6_DXDQVREFR0_X(x)  ((x) & GENMASK(5, 0))

#define DDR_PHY_DX0GCR6_DX0GCR6_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX0GCR6_DX0GCR6_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX0GCR6_DX0GCR6_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX0GCR6_DX0GCR6_DXDQVREFR1(x)    (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX0GCR6_DX0GCR6_DXDQVREFR1_M     GENMASK(13, 8)
#define DDR_PHY_DX0GCR6_DX0GCR6_DXDQVREFR1_X(x)  (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX0GCR6_DX0GCR6_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX0GCR6_DX0GCR6_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX0GCR6_DX0GCR6_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX0GCR6_DX0GCR6_DXDQVREFR2(x)    (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX0GCR6_DX0GCR6_DXDQVREFR2_M     GENMASK(21, 16)
#define DDR_PHY_DX0GCR6_DX0GCR6_DXDQVREFR2_X(x)  (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX0GCR6_DX0GCR6_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX0GCR6_DX0GCR6_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX0GCR6_DX0GCR6_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX0GCR6_DX0GCR6_DXDQVREFR3(x)    (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX0GCR6_DX0GCR6_DXDQVREFR3_M     GENMASK(29, 24)
#define DDR_PHY_DX0GCR6_DX0GCR6_DXDQVREFR3_X(x)  (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX0GCR6_DX0GCR6_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX0GCR6_DX0GCR6_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX0GCR6_DX0GCR6_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0GCR7 */
#define DDR_PHY_DX0GCR7(t)        (t + 0x71c)

#define DDR_PHY_DX0GCR7_DX0GCR7_RESERVED_1_0(x)  ((x) & GENMASK(1, 0))
#define DDR_PHY_DX0GCR7_DX0GCR7_RESERVED_1_0_M   GENMASK(1, 0)
#define DDR_PHY_DX0GCR7_DX0GCR7_RESERVED_1_0_X(x) ((x) & GENMASK(1, 0))

#define DDR_PHY_DX0GCR7_DX0GCR7_X4DSPDRMODE(x)   (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DX0GCR7_DX0GCR7_X4DSPDRMODE_M    GENMASK(3, 2)
#define DDR_PHY_DX0GCR7_DX0GCR7_X4DSPDRMODE_X(x) (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DX0GCR7_DX0GCR7_X4DSTEMODE(x)    (((x) << 4) & GENMASK(5, 4))
#define DDR_PHY_DX0GCR7_DX0GCR7_X4DSTEMODE_M     GENMASK(5, 4)
#define DDR_PHY_DX0GCR7_DX0GCR7_X4DSTEMODE_X(x)  (((x) & GENMASK(5, 4)) >> 4)

#define DDR_PHY_DX0GCR7_DX0GCR7_X4DSOEMODE(x)    (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX0GCR7_DX0GCR7_X4DSOEMODE_M     GENMASK(7, 6)
#define DDR_PHY_DX0GCR7_DX0GCR7_X4DSOEMODE_X(x)  (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX0GCR7_DX0GCR7_RESERVED_9_8(x)  (((x) << 8) & GENMASK(9, 8))
#define DDR_PHY_DX0GCR7_DX0GCR7_RESERVED_9_8_M   GENMASK(9, 8)
#define DDR_PHY_DX0GCR7_DX0GCR7_RESERVED_9_8_X(x) (((x) & GENMASK(9, 8)) >> 8)

#define DDR_PHY_DX0GCR7_DX0GCR7_X4DXPDRMODE(x)   (((x) << 10) & GENMASK(11, 10))
#define DDR_PHY_DX0GCR7_DX0GCR7_X4DXPDRMODE_M    GENMASK(11, 10)
#define DDR_PHY_DX0GCR7_DX0GCR7_X4DXPDRMODE_X(x) (((x) & GENMASK(11, 10)) >> 10)

#define DDR_PHY_DX0GCR7_DX0GCR7_X4DXTEMODE(x)    (((x) << 12) & GENMASK(13, 12))
#define DDR_PHY_DX0GCR7_DX0GCR7_X4DXTEMODE_M     GENMASK(13, 12)
#define DDR_PHY_DX0GCR7_DX0GCR7_X4DXTEMODE_X(x)  (((x) & GENMASK(13, 12)) >> 12)

#define DDR_PHY_DX0GCR7_DX0GCR7_X4DXOEMODE(x)    (((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX0GCR7_DX0GCR7_X4DXOEMODE_M     GENMASK(15, 14)
#define DDR_PHY_DX0GCR7_DX0GCR7_X4DXOEMODE_X(x)  (((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX0GCR7_DX0GCR7_X4DQSGOE(x)      (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX0GCR7_DX0GCR7_X4DQSGOE_M       GENMASK(16, 16)
#define DDR_PHY_DX0GCR7_DX0GCR7_X4DQSGOE_X(x)    (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX0GCR7_DX0GCR7_X4DQSGODT(x)     (((x) << 17) & GENMASK(17, 17))
#define DDR_PHY_DX0GCR7_DX0GCR7_X4DQSGODT_M      GENMASK(17, 17)
#define DDR_PHY_DX0GCR7_DX0GCR7_X4DQSGODT_X(x)   (((x) & GENMASK(17, 17)) >> 17)

#define DDR_PHY_DX0GCR7_DX0GCR7_RESERVED_18(x)   (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_DX0GCR7_DX0GCR7_RESERVED_18_M    GENMASK(18, 18)
#define DDR_PHY_DX0GCR7_DX0GCR7_RESERVED_18_X(x) (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_DX0GCR7_DX0GCR7_X4DQSGPDR(x)     (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_DX0GCR7_DX0GCR7_X4DQSGPDR_M      GENMASK(19, 19)
#define DDR_PHY_DX0GCR7_DX0GCR7_X4DQSGPDR_X(x)   (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_DX0GCR7_DX0GCR7_RESERVED_20(x)   (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX0GCR7_DX0GCR7_RESERVED_20_M    GENMASK(20, 20)
#define DDR_PHY_DX0GCR7_DX0GCR7_RESERVED_20_X(x) (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX0GCR7_DX0GCR7_X4DQSSEPDR(x)    (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX0GCR7_DX0GCR7_X4DQSSEPDR_M     GENMASK(21, 21)
#define DDR_PHY_DX0GCR7_DX0GCR7_X4DQSSEPDR_X(x)  (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX0GCR7_DX0GCR7_X4DQSNSEPDR(x)   (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX0GCR7_DX0GCR7_X4DQSNSEPDR_M    GENMASK(22, 22)
#define DDR_PHY_DX0GCR7_DX0GCR7_X4DQSNSEPDR_X(x) (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX0GCR7_DX0GCR7_X4RTTOH(x)       (((x) << 23) & GENMASK(24, 23))
#define DDR_PHY_DX0GCR7_DX0GCR7_X4RTTOH_M        GENMASK(24, 23)
#define DDR_PHY_DX0GCR7_DX0GCR7_X4RTTOH_X(x)     (((x) & GENMASK(24, 23)) >> 23)

#define DDR_PHY_DX0GCR7_DX0GCR7_X4RTTOAL(x)      (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_DX0GCR7_DX0GCR7_X4RTTOAL_M       GENMASK(25, 25)
#define DDR_PHY_DX0GCR7_DX0GCR7_X4RTTOAL_X(x)    (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_DX0GCR7_DX0GCR7_X4RDDLY(x)       (((x) << 26) & GENMASK(29, 26))
#define DDR_PHY_DX0GCR7_DX0GCR7_X4RDDLY_M        GENMASK(29, 26)
#define DDR_PHY_DX0GCR7_DX0GCR7_X4RDDLY_X(x)     (((x) & GENMASK(29, 26)) >> 26)

#define DDR_PHY_DX0GCR7_DX0GCR7_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX0GCR7_DX0GCR7_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX0GCR7_DX0GCR7_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0GCR8 */
#define DDR_PHY_DX0GCR8(t)        (t + 0x720)

#define DDR_PHY_DX0GCR8_DX0GCR8_X4DXREFISELR0(x) ((x) & GENMASK(5, 0))
#define DDR_PHY_DX0GCR8_DX0GCR8_X4DXREFISELR0_M  GENMASK(5, 0)
#define DDR_PHY_DX0GCR8_DX0GCR8_X4DXREFISELR0_X(x) ((x) & GENMASK(5, 0))

#define DDR_PHY_DX0GCR8_DX0GCR8_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX0GCR8_DX0GCR8_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX0GCR8_DX0GCR8_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX0GCR8_DX0GCR8_X4DXREFISELR1(x) (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX0GCR8_DX0GCR8_X4DXREFISELR1_M  GENMASK(13, 8)
#define DDR_PHY_DX0GCR8_DX0GCR8_X4DXREFISELR1_X(x) (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX0GCR8_DX0GCR8_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX0GCR8_DX0GCR8_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX0GCR8_DX0GCR8_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX0GCR8_DX0GCR8_X4DXREFISELR2(x) (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX0GCR8_DX0GCR8_X4DXREFISELR2_M  GENMASK(21, 16)
#define DDR_PHY_DX0GCR8_DX0GCR8_X4DXREFISELR2_X(x)\
	(((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX0GCR8_DX0GCR8_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX0GCR8_DX0GCR8_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX0GCR8_DX0GCR8_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX0GCR8_DX0GCR8_X4DXREFISELR3(x) (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX0GCR8_DX0GCR8_X4DXREFISELR3_M  GENMASK(29, 24)
#define DDR_PHY_DX0GCR8_DX0GCR8_X4DXREFISELR3_X(x)\
	(((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX0GCR8_DX0GCR8_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX0GCR8_DX0GCR8_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX0GCR8_DX0GCR8_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0GCR9 */
#define DDR_PHY_DX0GCR9(t)        (t + 0x724)

#define DDR_PHY_DX0GCR9_DX0GCR9_X4DXDQVREFR0(x)  ((x) & GENMASK(5, 0))
#define DDR_PHY_DX0GCR9_DX0GCR9_X4DXDQVREFR0_M   GENMASK(5, 0)
#define DDR_PHY_DX0GCR9_DX0GCR9_X4DXDQVREFR0_X(x) ((x) & GENMASK(5, 0))

#define DDR_PHY_DX0GCR9_DX0GCR9_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX0GCR9_DX0GCR9_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX0GCR9_DX0GCR9_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX0GCR9_DX0GCR9_X4DXDQVREFR1(x)  (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX0GCR9_DX0GCR9_X4DXDQVREFR1_M   GENMASK(13, 8)
#define DDR_PHY_DX0GCR9_DX0GCR9_X4DXDQVREFR1_X(x) (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX0GCR9_DX0GCR9_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX0GCR9_DX0GCR9_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX0GCR9_DX0GCR9_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX0GCR9_DX0GCR9_X4DXDQVREFR2(x)  (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX0GCR9_DX0GCR9_X4DXDQVREFR2_M   GENMASK(21, 16)
#define DDR_PHY_DX0GCR9_DX0GCR9_X4DXDQVREFR2_X(x)\
	(((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX0GCR9_DX0GCR9_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX0GCR9_DX0GCR9_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX0GCR9_DX0GCR9_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX0GCR9_DX0GCR9_X4DXDQVREFR3(x)  (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX0GCR9_DX0GCR9_X4DXDQVREFR3_M   GENMASK(29, 24)
#define DDR_PHY_DX0GCR9_DX0GCR9_X4DXDQVREFR3_X(x)\
	(((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX0GCR9_DX0GCR9_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX0GCR9_DX0GCR9_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX0GCR9_DX0GCR9_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0BDLR0 */
#define DDR_PHY_DX0BDLR0(t)       (t + 0x740)

#define DDR_PHY_DX0BDLR0_DX0BDLR0_DQ0WBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX0BDLR0_DX0BDLR0_DQ0WBD_M       GENMASK(5, 0)
#define DDR_PHY_DX0BDLR0_DX0BDLR0_DQ0WBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX0BDLR0_DX0BDLR0_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX0BDLR0_DX0BDLR0_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX0BDLR0_DX0BDLR0_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX0BDLR0_DX0BDLR0_DQ1WBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX0BDLR0_DX0BDLR0_DQ1WBD_M       GENMASK(13, 8)
#define DDR_PHY_DX0BDLR0_DX0BDLR0_DQ1WBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX0BDLR0_DX0BDLR0_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX0BDLR0_DX0BDLR0_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX0BDLR0_DX0BDLR0_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX0BDLR0_DX0BDLR0_DQ2WBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX0BDLR0_DX0BDLR0_DQ2WBD_M       GENMASK(21, 16)
#define DDR_PHY_DX0BDLR0_DX0BDLR0_DQ2WBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX0BDLR0_DX0BDLR0_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX0BDLR0_DX0BDLR0_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX0BDLR0_DX0BDLR0_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX0BDLR0_DX0BDLR0_DQ3WBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX0BDLR0_DX0BDLR0_DQ3WBD_M       GENMASK(29, 24)
#define DDR_PHY_DX0BDLR0_DX0BDLR0_DQ3WBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX0BDLR0_DX0BDLR0_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX0BDLR0_DX0BDLR0_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX0BDLR0_DX0BDLR0_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0BDLR1 */
#define DDR_PHY_DX0BDLR1(t)       (t + 0x744)

#define DDR_PHY_DX0BDLR1_DX0BDLR1_DQ4WBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX0BDLR1_DX0BDLR1_DQ4WBD_M       GENMASK(5, 0)
#define DDR_PHY_DX0BDLR1_DX0BDLR1_DQ4WBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX0BDLR1_DX0BDLR1_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX0BDLR1_DX0BDLR1_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX0BDLR1_DX0BDLR1_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX0BDLR1_DX0BDLR1_DQ5WBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX0BDLR1_DX0BDLR1_DQ5WBD_M       GENMASK(13, 8)
#define DDR_PHY_DX0BDLR1_DX0BDLR1_DQ5WBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX0BDLR1_DX0BDLR1_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX0BDLR1_DX0BDLR1_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX0BDLR1_DX0BDLR1_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX0BDLR1_DX0BDLR1_DQ6WBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX0BDLR1_DX0BDLR1_DQ6WBD_M       GENMASK(21, 16)
#define DDR_PHY_DX0BDLR1_DX0BDLR1_DQ6WBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX0BDLR1_DX0BDLR1_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX0BDLR1_DX0BDLR1_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX0BDLR1_DX0BDLR1_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX0BDLR1_DX0BDLR1_DQ7WBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX0BDLR1_DX0BDLR1_DQ7WBD_M       GENMASK(29, 24)
#define DDR_PHY_DX0BDLR1_DX0BDLR1_DQ7WBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX0BDLR1_DX0BDLR1_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX0BDLR1_DX0BDLR1_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX0BDLR1_DX0BDLR1_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0BDLR2 */
#define DDR_PHY_DX0BDLR2(t)       (t + 0x748)

#define DDR_PHY_DX0BDLR2_DX0BDLR2_DMWBD(x)       ((x) & GENMASK(5, 0))
#define DDR_PHY_DX0BDLR2_DX0BDLR2_DMWBD_M        GENMASK(5, 0)
#define DDR_PHY_DX0BDLR2_DX0BDLR2_DMWBD_X(x)     ((x) & GENMASK(5, 0))

#define DDR_PHY_DX0BDLR2_DX0BDLR2_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX0BDLR2_DX0BDLR2_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX0BDLR2_DX0BDLR2_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX0BDLR2_DX0BDLR2_DSWBD(x)       (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX0BDLR2_DX0BDLR2_DSWBD_M        GENMASK(13, 8)
#define DDR_PHY_DX0BDLR2_DX0BDLR2_DSWBD_X(x)     (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX0BDLR2_DX0BDLR2_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX0BDLR2_DX0BDLR2_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX0BDLR2_DX0BDLR2_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX0BDLR2_DX0BDLR2_DSOEBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX0BDLR2_DX0BDLR2_DSOEBD_M       GENMASK(21, 16)
#define DDR_PHY_DX0BDLR2_DX0BDLR2_DSOEBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX0BDLR2_DX0BDLR2_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX0BDLR2_DX0BDLR2_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX0BDLR2_DX0BDLR2_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0BDLR3 */
#define DDR_PHY_DX0BDLR3(t)       (t + 0x750)

#define DDR_PHY_DX0BDLR3_DX0BDLR3_DQ0RBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX0BDLR3_DX0BDLR3_DQ0RBD_M       GENMASK(5, 0)
#define DDR_PHY_DX0BDLR3_DX0BDLR3_DQ0RBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX0BDLR3_DX0BDLR3_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX0BDLR3_DX0BDLR3_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX0BDLR3_DX0BDLR3_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX0BDLR3_DX0BDLR3_DQ1RBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX0BDLR3_DX0BDLR3_DQ1RBD_M       GENMASK(13, 8)
#define DDR_PHY_DX0BDLR3_DX0BDLR3_DQ1RBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX0BDLR3_DX0BDLR3_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX0BDLR3_DX0BDLR3_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX0BDLR3_DX0BDLR3_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX0BDLR3_DX0BDLR3_DQ2RBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX0BDLR3_DX0BDLR3_DQ2RBD_M       GENMASK(21, 16)
#define DDR_PHY_DX0BDLR3_DX0BDLR3_DQ2RBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX0BDLR3_DX0BDLR3_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX0BDLR3_DX0BDLR3_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX0BDLR3_DX0BDLR3_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX0BDLR3_DX0BDLR3_DQ3RBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX0BDLR3_DX0BDLR3_DQ3RBD_M       GENMASK(29, 24)
#define DDR_PHY_DX0BDLR3_DX0BDLR3_DQ3RBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX0BDLR3_DX0BDLR3_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX0BDLR3_DX0BDLR3_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX0BDLR3_DX0BDLR3_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0BDLR4 */
#define DDR_PHY_DX0BDLR4(t)       (t + 0x754)

#define DDR_PHY_DX0BDLR4_DX0BDLR4_DQ4RBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX0BDLR4_DX0BDLR4_DQ4RBD_M       GENMASK(5, 0)
#define DDR_PHY_DX0BDLR4_DX0BDLR4_DQ4RBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX0BDLR4_DX0BDLR4_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX0BDLR4_DX0BDLR4_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX0BDLR4_DX0BDLR4_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX0BDLR4_DX0BDLR4_DQ5RBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX0BDLR4_DX0BDLR4_DQ5RBD_M       GENMASK(13, 8)
#define DDR_PHY_DX0BDLR4_DX0BDLR4_DQ5RBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX0BDLR4_DX0BDLR4_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX0BDLR4_DX0BDLR4_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX0BDLR4_DX0BDLR4_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX0BDLR4_DX0BDLR4_DQ6RBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX0BDLR4_DX0BDLR4_DQ6RBD_M       GENMASK(21, 16)
#define DDR_PHY_DX0BDLR4_DX0BDLR4_DQ6RBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX0BDLR4_DX0BDLR4_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX0BDLR4_DX0BDLR4_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX0BDLR4_DX0BDLR4_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX0BDLR4_DX0BDLR4_DQ7RBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX0BDLR4_DX0BDLR4_DQ7RBD_M       GENMASK(29, 24)
#define DDR_PHY_DX0BDLR4_DX0BDLR4_DQ7RBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX0BDLR4_DX0BDLR4_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX0BDLR4_DX0BDLR4_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX0BDLR4_DX0BDLR4_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0BDLR5 */
#define DDR_PHY_DX0BDLR5(t)       (t + 0x758)

#define DDR_PHY_DX0BDLR5_DX0BDLR5_DMRBD(x)       ((x) & GENMASK(5, 0))
#define DDR_PHY_DX0BDLR5_DX0BDLR5_DMRBD_M        GENMASK(5, 0)
#define DDR_PHY_DX0BDLR5_DX0BDLR5_DMRBD_X(x)     ((x) & GENMASK(5, 0))

#define DDR_PHY_DX0BDLR5_DX0BDLR5_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX0BDLR5_DX0BDLR5_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX0BDLR5_DX0BDLR5_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX0BDLR5_DX0BDLR5_DSRBD(x)       (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX0BDLR5_DX0BDLR5_DSRBD_M        GENMASK(13, 8)
#define DDR_PHY_DX0BDLR5_DX0BDLR5_DSRBD_X(x)     (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX0BDLR5_DX0BDLR5_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX0BDLR5_DX0BDLR5_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX0BDLR5_DX0BDLR5_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX0BDLR5_DX0BDLR5_DSNRBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX0BDLR5_DX0BDLR5_DSNRBD_M       GENMASK(21, 16)
#define DDR_PHY_DX0BDLR5_DX0BDLR5_DSNRBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX0BDLR5_DX0BDLR5_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX0BDLR5_DX0BDLR5_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX0BDLR5_DX0BDLR5_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0BDLR6 */
#define DDR_PHY_DX0BDLR6(t)       (t + 0x760)

#define DDR_PHY_DX0BDLR6_DX0BDLR6_RESERVED_7_0(x) ((x) & GENMASK(7, 0))
#define DDR_PHY_DX0BDLR6_DX0BDLR6_RESERVED_7_0_M GENMASK(7, 0)
#define DDR_PHY_DX0BDLR6_DX0BDLR6_RESERVED_7_0_X(x) ((x) & GENMASK(7, 0))

#define DDR_PHY_DX0BDLR6_DX0BDLR6_PDRBD(x)       (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX0BDLR6_DX0BDLR6_PDRBD_M        GENMASK(13, 8)
#define DDR_PHY_DX0BDLR6_DX0BDLR6_PDRBD_X(x)     (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX0BDLR6_DX0BDLR6_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX0BDLR6_DX0BDLR6_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX0BDLR6_DX0BDLR6_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX0BDLR6_DX0BDLR6_TERBD(x)       (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX0BDLR6_DX0BDLR6_TERBD_M        GENMASK(21, 16)
#define DDR_PHY_DX0BDLR6_DX0BDLR6_TERBD_X(x)     (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX0BDLR6_DX0BDLR6_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX0BDLR6_DX0BDLR6_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX0BDLR6_DX0BDLR6_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0BDLR7 */
#define DDR_PHY_DX0BDLR7(t)       (t + 0x764)

#define DDR_PHY_DX0BDLR7_DX0BDLR7_X4DMWBD(x)     ((x) & GENMASK(5, 0))
#define DDR_PHY_DX0BDLR7_DX0BDLR7_X4DMWBD_M      GENMASK(5, 0)
#define DDR_PHY_DX0BDLR7_DX0BDLR7_X4DMWBD_X(x)   ((x) & GENMASK(5, 0))

#define DDR_PHY_DX0BDLR7_DX0BDLR7_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX0BDLR7_DX0BDLR7_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX0BDLR7_DX0BDLR7_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX0BDLR7_DX0BDLR7_X4DSWBD(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX0BDLR7_DX0BDLR7_X4DSWBD_M      GENMASK(13, 8)
#define DDR_PHY_DX0BDLR7_DX0BDLR7_X4DSWBD_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX0BDLR7_DX0BDLR7_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX0BDLR7_DX0BDLR7_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX0BDLR7_DX0BDLR7_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX0BDLR7_DX0BDLR7_X4DSOEBD(x)    (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX0BDLR7_DX0BDLR7_X4DSOEBD_M     GENMASK(21, 16)
#define DDR_PHY_DX0BDLR7_DX0BDLR7_X4DSOEBD_X(x)  (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX0BDLR7_DX0BDLR7_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX0BDLR7_DX0BDLR7_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX0BDLR7_DX0BDLR7_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0BDLR8 */
#define DDR_PHY_DX0BDLR8(t)       (t + 0x768)

#define DDR_PHY_DX0BDLR8_DX0BDLR8_X4DMRBD(x)     ((x) & GENMASK(5, 0))
#define DDR_PHY_DX0BDLR8_DX0BDLR8_X4DMRBD_M      GENMASK(5, 0)
#define DDR_PHY_DX0BDLR8_DX0BDLR8_X4DMRBD_X(x)   ((x) & GENMASK(5, 0))

#define DDR_PHY_DX0BDLR8_DX0BDLR8_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX0BDLR8_DX0BDLR8_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX0BDLR8_DX0BDLR8_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX0BDLR8_DX0BDLR8_X4DSRBD(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX0BDLR8_DX0BDLR8_X4DSRBD_M      GENMASK(13, 8)
#define DDR_PHY_DX0BDLR8_DX0BDLR8_X4DSRBD_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX0BDLR8_DX0BDLR8_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX0BDLR8_DX0BDLR8_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX0BDLR8_DX0BDLR8_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX0BDLR8_DX0BDLR8_X4DSNRBD(x)    (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX0BDLR8_DX0BDLR8_X4DSNRBD_M     GENMASK(21, 16)
#define DDR_PHY_DX0BDLR8_DX0BDLR8_X4DSNRBD_X(x)  (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX0BDLR8_DX0BDLR8_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX0BDLR8_DX0BDLR8_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX0BDLR8_DX0BDLR8_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0BDLR9 */
#define DDR_PHY_DX0BDLR9(t)       (t + 0x76c)

#define DDR_PHY_DX0BDLR9_DX0BDLR9_RESERVED_7_0(x) ((x) & GENMASK(7, 0))
#define DDR_PHY_DX0BDLR9_DX0BDLR9_RESERVED_7_0_M GENMASK(7, 0)
#define DDR_PHY_DX0BDLR9_DX0BDLR9_RESERVED_7_0_X(x) ((x) & GENMASK(7, 0))

#define DDR_PHY_DX0BDLR9_DX0BDLR9_X4PDRBD(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX0BDLR9_DX0BDLR9_X4PDRBD_M      GENMASK(13, 8)
#define DDR_PHY_DX0BDLR9_DX0BDLR9_X4PDRBD_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX0BDLR9_DX0BDLR9_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX0BDLR9_DX0BDLR9_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX0BDLR9_DX0BDLR9_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX0BDLR9_DX0BDLR9_X4TERBD(x)     (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX0BDLR9_DX0BDLR9_X4TERBD_M      GENMASK(21, 16)
#define DDR_PHY_DX0BDLR9_DX0BDLR9_X4TERBD_X(x)   (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX0BDLR9_DX0BDLR9_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX0BDLR9_DX0BDLR9_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX0BDLR9_DX0BDLR9_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0LCDLR0 */
#define DDR_PHY_DX0LCDLR0(t)      (t + 0x780)

#define DDR_PHY_DX0LCDLR0_DX0LCDLR0_WLD(x)       ((x) & GENMASK(8, 0))
#define DDR_PHY_DX0LCDLR0_DX0LCDLR0_WLD_M        GENMASK(8, 0)
#define DDR_PHY_DX0LCDLR0_DX0LCDLR0_WLD_X(x)     ((x) & GENMASK(8, 0))

#define DDR_PHY_DX0LCDLR0_DX0LCDLR0_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX0LCDLR0_DX0LCDLR0_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX0LCDLR0_DX0LCDLR0_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX0LCDLR0_DX0LCDLR0_X4WLD(x)     (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX0LCDLR0_DX0LCDLR0_X4WLD_M      GENMASK(24, 16)
#define DDR_PHY_DX0LCDLR0_DX0LCDLR0_X4WLD_X(x)   (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX0LCDLR0_DX0LCDLR0_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX0LCDLR0_DX0LCDLR0_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX0LCDLR0_DX0LCDLR0_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0LCDLR1 */
#define DDR_PHY_DX0LCDLR1(t)      (t + 0x784)

#define DDR_PHY_DX0LCDLR1_DX0LCDLR1_WDQD(x)      ((x) & GENMASK(8, 0))
#define DDR_PHY_DX0LCDLR1_DX0LCDLR1_WDQD_M       GENMASK(8, 0)
#define DDR_PHY_DX0LCDLR1_DX0LCDLR1_WDQD_X(x)    ((x) & GENMASK(8, 0))

#define DDR_PHY_DX0LCDLR1_DX0LCDLR1_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX0LCDLR1_DX0LCDLR1_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX0LCDLR1_DX0LCDLR1_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX0LCDLR1_DX0LCDLR1_X4WDQD(x)    (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX0LCDLR1_DX0LCDLR1_X4WDQD_M     GENMASK(24, 16)
#define DDR_PHY_DX0LCDLR1_DX0LCDLR1_X4WDQD_X(x)  (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX0LCDLR1_DX0LCDLR1_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX0LCDLR1_DX0LCDLR1_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX0LCDLR1_DX0LCDLR1_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0LCDLR2 */
#define DDR_PHY_DX0LCDLR2(t)      (t + 0x788)

#define DDR_PHY_DX0LCDLR2_DX0LCDLR2_DQSGD(x)     ((x) & GENMASK(8, 0))
#define DDR_PHY_DX0LCDLR2_DX0LCDLR2_DQSGD_M      GENMASK(8, 0)
#define DDR_PHY_DX0LCDLR2_DX0LCDLR2_DQSGD_X(x)   ((x) & GENMASK(8, 0))

#define DDR_PHY_DX0LCDLR2_DX0LCDLR2_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX0LCDLR2_DX0LCDLR2_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX0LCDLR2_DX0LCDLR2_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX0LCDLR2_DX0LCDLR2_X4DQSGD(x)   (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX0LCDLR2_DX0LCDLR2_X4DQSGD_M    GENMASK(24, 16)
#define DDR_PHY_DX0LCDLR2_DX0LCDLR2_X4DQSGD_X(x) (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX0LCDLR2_DX0LCDLR2_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX0LCDLR2_DX0LCDLR2_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX0LCDLR2_DX0LCDLR2_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0LCDLR3 */
#define DDR_PHY_DX0LCDLR3(t)      (t + 0x78c)

#define DDR_PHY_DX0LCDLR3_DX0LCDLR3_RDQSD(x)     ((x) & GENMASK(8, 0))
#define DDR_PHY_DX0LCDLR3_DX0LCDLR3_RDQSD_M      GENMASK(8, 0)
#define DDR_PHY_DX0LCDLR3_DX0LCDLR3_RDQSD_X(x)   ((x) & GENMASK(8, 0))

#define DDR_PHY_DX0LCDLR3_DX0LCDLR3_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX0LCDLR3_DX0LCDLR3_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX0LCDLR3_DX0LCDLR3_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX0LCDLR3_DX0LCDLR3_X4RDQSD(x)   (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX0LCDLR3_DX0LCDLR3_X4RDQSD_M    GENMASK(24, 16)
#define DDR_PHY_DX0LCDLR3_DX0LCDLR3_X4RDQSD_X(x) (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX0LCDLR3_DX0LCDLR3_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX0LCDLR3_DX0LCDLR3_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX0LCDLR3_DX0LCDLR3_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0LCDLR4 */
#define DDR_PHY_DX0LCDLR4(t)      (t + 0x790)

#define DDR_PHY_DX0LCDLR4_DX0LCDLR4_RDQSND(x)    ((x) & GENMASK(8, 0))
#define DDR_PHY_DX0LCDLR4_DX0LCDLR4_RDQSND_M     GENMASK(8, 0)
#define DDR_PHY_DX0LCDLR4_DX0LCDLR4_RDQSND_X(x)  ((x) & GENMASK(8, 0))

#define DDR_PHY_DX0LCDLR4_DX0LCDLR4_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX0LCDLR4_DX0LCDLR4_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX0LCDLR4_DX0LCDLR4_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX0LCDLR4_DX0LCDLR4_X4RDQSND(x)  (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX0LCDLR4_DX0LCDLR4_X4RDQSND_M   GENMASK(24, 16)
#define DDR_PHY_DX0LCDLR4_DX0LCDLR4_X4RDQSND_X(x)\
	(((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX0LCDLR4_DX0LCDLR4_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX0LCDLR4_DX0LCDLR4_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX0LCDLR4_DX0LCDLR4_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0LCDLR5 */
#define DDR_PHY_DX0LCDLR5(t)      (t + 0x794)

#define DDR_PHY_DX0LCDLR5_DX0LCDLR5_DQSGSD(x)    ((x) & GENMASK(8, 0))
#define DDR_PHY_DX0LCDLR5_DX0LCDLR5_DQSGSD_M     GENMASK(8, 0)
#define DDR_PHY_DX0LCDLR5_DX0LCDLR5_DQSGSD_X(x)  ((x) & GENMASK(8, 0))

#define DDR_PHY_DX0LCDLR5_DX0LCDLR5_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX0LCDLR5_DX0LCDLR5_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX0LCDLR5_DX0LCDLR5_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX0LCDLR5_DX0LCDLR5_X4DQSGSD(x)  (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX0LCDLR5_DX0LCDLR5_X4DQSGSD_M   GENMASK(24, 16)
#define DDR_PHY_DX0LCDLR5_DX0LCDLR5_X4DQSGSD_X(x)\
	(((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX0LCDLR5_DX0LCDLR5_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX0LCDLR5_DX0LCDLR5_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX0LCDLR5_DX0LCDLR5_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0MDLR0 */
#define DDR_PHY_DX0MDLR0(t)       (t + 0x7a0)

#define DDR_PHY_DX0MDLR0_DX0MDLR0_IPRD(x)        ((x) & GENMASK(8, 0))
#define DDR_PHY_DX0MDLR0_DX0MDLR0_IPRD_M         GENMASK(8, 0)
#define DDR_PHY_DX0MDLR0_DX0MDLR0_IPRD_X(x)      ((x) & GENMASK(8, 0))

#define DDR_PHY_DX0MDLR0_DX0MDLR0_RESERVED_15_9(x) (((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX0MDLR0_DX0MDLR0_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX0MDLR0_DX0MDLR0_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX0MDLR0_DX0MDLR0_TPRD(x)        (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX0MDLR0_DX0MDLR0_TPRD_M         GENMASK(24, 16)
#define DDR_PHY_DX0MDLR0_DX0MDLR0_TPRD_X(x)      (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX0MDLR0_DX0MDLR0_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX0MDLR0_DX0MDLR0_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX0MDLR0_DX0MDLR0_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0MDLR1 */
#define DDR_PHY_DX0MDLR1(t)       (t + 0x7a4)

#define DDR_PHY_DX0MDLR1_DX0MDLR1_MDLD(x)        ((x) & GENMASK(8, 0))
#define DDR_PHY_DX0MDLR1_DX0MDLR1_MDLD_M         GENMASK(8, 0)
#define DDR_PHY_DX0MDLR1_DX0MDLR1_MDLD_X(x)      ((x) & GENMASK(8, 0))

#define DDR_PHY_DX0MDLR1_DX0MDLR1_RESERVED_31_9(x) (((x) << 9) & GENMASK(31, 9))
#define DDR_PHY_DX0MDLR1_DX0MDLR1_RESERVED_31_9_M GENMASK(31, 9)
#define DDR_PHY_DX0MDLR1_DX0MDLR1_RESERVED_31_9_X(x)\
	(((x) & GENMASK(31, 9)) >> 9)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0GTR0 */
#define DDR_PHY_DX0GTR0(t)        (t + 0x7c0)

#define DDR_PHY_DX0GTR0_DX0GTR0_DGSL(x)          ((x) & GENMASK(4, 0))
#define DDR_PHY_DX0GTR0_DX0GTR0_DGSL_M           GENMASK(4, 0)
#define DDR_PHY_DX0GTR0_DX0GTR0_DGSL_X(x)        ((x) & GENMASK(4, 0))

#define DDR_PHY_DX0GTR0_DX0GTR0_RESERVED_7_5(x)  (((x) << 5) & GENMASK(7, 5))
#define DDR_PHY_DX0GTR0_DX0GTR0_RESERVED_7_5_M   GENMASK(7, 5)
#define DDR_PHY_DX0GTR0_DX0GTR0_RESERVED_7_5_X(x) (((x) & GENMASK(7, 5)) >> 5)

#define DDR_PHY_DX0GTR0_DX0GTR0_X4DGSL(x)        (((x) << 8) & GENMASK(12, 8))
#define DDR_PHY_DX0GTR0_DX0GTR0_X4DGSL_M         GENMASK(12, 8)
#define DDR_PHY_DX0GTR0_DX0GTR0_X4DGSL_X(x)      (((x) & GENMASK(12, 8)) >> 8)

#define DDR_PHY_DX0GTR0_DX0GTR0_RESERVED_15_13(x)\
	(((x) << 13) & GENMASK(15, 13))
#define DDR_PHY_DX0GTR0_DX0GTR0_RESERVED_15_13_M GENMASK(15, 13)
#define DDR_PHY_DX0GTR0_DX0GTR0_RESERVED_15_13_X(x)\
	(((x) & GENMASK(15, 13)) >> 13)

#define DDR_PHY_DX0GTR0_DX0GTR0_WLSL(x)          (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DX0GTR0_DX0GTR0_WLSL_M           GENMASK(19, 16)
#define DDR_PHY_DX0GTR0_DX0GTR0_WLSL_X(x)        (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DX0GTR0_DX0GTR0_X4WLSL(x)        (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX0GTR0_DX0GTR0_X4WLSL_M         GENMASK(23, 20)
#define DDR_PHY_DX0GTR0_DX0GTR0_X4WLSL_X(x)      (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX0GTR0_DX0GTR0_RESERVED_31_24(x)\
	(((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_DX0GTR0_DX0GTR0_RESERVED_31_24_M GENMASK(31, 24)
#define DDR_PHY_DX0GTR0_DX0GTR0_RESERVED_31_24_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0RSR0 */
#define DDR_PHY_DX0RSR0(t)        (t + 0x7d0)

#define DDR_PHY_DX0RSR0_DX0RSR0_QSGERR(x)        ((x) & GENMASK(15, 0))
#define DDR_PHY_DX0RSR0_DX0RSR0_QSGERR_M         GENMASK(15, 0)
#define DDR_PHY_DX0RSR0_DX0RSR0_QSGERR_X(x)      ((x) & GENMASK(15, 0))

#define DDR_PHY_DX0RSR0_DX0RSR0_X4QSGERR(x)      (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX0RSR0_DX0RSR0_X4QSGERR_M       GENMASK(31, 16)
#define DDR_PHY_DX0RSR0_DX0RSR0_X4QSGERR_X(x)    (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0RSR1 */
#define DDR_PHY_DX0RSR1(t)        (t + 0x7d4)

#define DDR_PHY_DX0RSR1_DX0RSR1_RDLVLERR(x)      ((x) & GENMASK(15, 0))
#define DDR_PHY_DX0RSR1_DX0RSR1_RDLVLERR_M       GENMASK(15, 0)
#define DDR_PHY_DX0RSR1_DX0RSR1_RDLVLERR_X(x)    ((x) & GENMASK(15, 0))

#define DDR_PHY_DX0RSR1_DX0RSR1_X4RDLVLERR(x)    (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX0RSR1_DX0RSR1_X4RDLVLERR_M     GENMASK(31, 16)
#define DDR_PHY_DX0RSR1_DX0RSR1_X4RDLVLERR_X(x)  (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0RSR2 */
#define DDR_PHY_DX0RSR2(t)        (t + 0x7d8)

#define DDR_PHY_DX0RSR2_DX0RSR2_WLAWN(x)         ((x) & GENMASK(15, 0))
#define DDR_PHY_DX0RSR2_DX0RSR2_WLAWN_M          GENMASK(15, 0)
#define DDR_PHY_DX0RSR2_DX0RSR2_WLAWN_X(x)       ((x) & GENMASK(15, 0))

#define DDR_PHY_DX0RSR2_DX0RSR2_X4WLAWN(x)       (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX0RSR2_DX0RSR2_X4WLAWN_M        GENMASK(31, 16)
#define DDR_PHY_DX0RSR2_DX0RSR2_X4WLAWN_X(x)     (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0RSR3 */
#define DDR_PHY_DX0RSR3(t)        (t + 0x7dc)

#define DDR_PHY_DX0RSR3_DX0RSR3_WLAERR(x)        ((x) & GENMASK(15, 0))
#define DDR_PHY_DX0RSR3_DX0RSR3_WLAERR_M         GENMASK(15, 0)
#define DDR_PHY_DX0RSR3_DX0RSR3_WLAERR_X(x)      ((x) & GENMASK(15, 0))

#define DDR_PHY_DX0RSR3_DX0RSR3_X4WLAERR(x)      (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX0RSR3_DX0RSR3_X4WLAERR_M       GENMASK(31, 16)
#define DDR_PHY_DX0RSR3_DX0RSR3_X4WLAERR_X(x)    (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0GSR0 */
#define DDR_PHY_DX0GSR0(t)        (t + 0x7e0)

#define DDR_PHY_DX0GSR0_DX0GSR0_WDQCAL(x)        ((x) & GENMASK(0, 0))
#define DDR_PHY_DX0GSR0_DX0GSR0_WDQCAL_M         GENMASK(0, 0)
#define DDR_PHY_DX0GSR0_DX0GSR0_WDQCAL_X(x)      ((x) & GENMASK(0, 0))

#define DDR_PHY_DX0GSR0_DX0GSR0_RDQSCAL(x)       (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX0GSR0_DX0GSR0_RDQSCAL_M        GENMASK(1, 1)
#define DDR_PHY_DX0GSR0_DX0GSR0_RDQSCAL_X(x)     (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX0GSR0_DX0GSR0_RDQSNCAL(x)      (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX0GSR0_DX0GSR0_RDQSNCAL_M       GENMASK(2, 2)
#define DDR_PHY_DX0GSR0_DX0GSR0_RDQSNCAL_X(x)    (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX0GSR0_DX0GSR0_GDQSCAL(x)       (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX0GSR0_DX0GSR0_GDQSCAL_M        GENMASK(3, 3)
#define DDR_PHY_DX0GSR0_DX0GSR0_GDQSCAL_X(x)     (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX0GSR0_DX0GSR0_WLCAL(x)         (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX0GSR0_DX0GSR0_WLCAL_M          GENMASK(4, 4)
#define DDR_PHY_DX0GSR0_DX0GSR0_WLCAL_X(x)       (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX0GSR0_DX0GSR0_WLDONE(x)        (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX0GSR0_DX0GSR0_WLDONE_M         GENMASK(5, 5)
#define DDR_PHY_DX0GSR0_DX0GSR0_WLDONE_X(x)      (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX0GSR0_DX0GSR0_WLERR(x)         (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX0GSR0_DX0GSR0_WLERR_M          GENMASK(6, 6)
#define DDR_PHY_DX0GSR0_DX0GSR0_WLERR_X(x)       (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX0GSR0_DX0GSR0_WLPRD(x)         (((x) << 7) & GENMASK(15, 7))
#define DDR_PHY_DX0GSR0_DX0GSR0_WLPRD_M          GENMASK(15, 7)
#define DDR_PHY_DX0GSR0_DX0GSR0_WLPRD_X(x)       (((x) & GENMASK(15, 7)) >> 7)

#define DDR_PHY_DX0GSR0_DX0GSR0_DPLOCK(x)        (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX0GSR0_DX0GSR0_DPLOCK_M         GENMASK(16, 16)
#define DDR_PHY_DX0GSR0_DX0GSR0_DPLOCK_X(x)      (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX0GSR0_DX0GSR0_GDQSPRD(x)       (((x) << 17) & GENMASK(25, 17))
#define DDR_PHY_DX0GSR0_DX0GSR0_GDQSPRD_M        GENMASK(25, 17)
#define DDR_PHY_DX0GSR0_DX0GSR0_GDQSPRD_X(x)     (((x) & GENMASK(25, 17)) >> 17)

#define DDR_PHY_DX0GSR0_DX0GSR0_WLWN(x)          (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_DX0GSR0_DX0GSR0_WLWN_M           GENMASK(26, 26)
#define DDR_PHY_DX0GSR0_DX0GSR0_WLWN_X(x)        (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_DX0GSR0_DX0GSR0_RESERVED_29_27(x)\
	(((x) << 27) & GENMASK(29, 27))
#define DDR_PHY_DX0GSR0_DX0GSR0_RESERVED_29_27_M GENMASK(29, 27)
#define DDR_PHY_DX0GSR0_DX0GSR0_RESERVED_29_27_X(x)\
	(((x) & GENMASK(29, 27)) >> 27)

#define DDR_PHY_DX0GSR0_DX0GSR0_WLDQ(x)          (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX0GSR0_DX0GSR0_WLDQ_M           GENMASK(30, 30)
#define DDR_PHY_DX0GSR0_DX0GSR0_WLDQ_X(x)        (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX0GSR0_DX0GSR0_RESERVED_31(x)   (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX0GSR0_DX0GSR0_RESERVED_31_M    GENMASK(31, 31)
#define DDR_PHY_DX0GSR0_DX0GSR0_RESERVED_31_X(x) (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0GSR1 */
#define DDR_PHY_DX0GSR1(t)        (t + 0x7e4)

#define DDR_PHY_DX0GSR1_DX0GSR1_DLTDONE(x)       ((x) & GENMASK(0, 0))
#define DDR_PHY_DX0GSR1_DX0GSR1_DLTDONE_M        GENMASK(0, 0)
#define DDR_PHY_DX0GSR1_DX0GSR1_DLTDONE_X(x)     ((x) & GENMASK(0, 0))

#define DDR_PHY_DX0GSR1_DX0GSR1_DLTCODE(x)       (((x) << 1) & GENMASK(24, 1))
#define DDR_PHY_DX0GSR1_DX0GSR1_DLTCODE_M        GENMASK(24, 1)
#define DDR_PHY_DX0GSR1_DX0GSR1_DLTCODE_X(x)     (((x) & GENMASK(24, 1)) >> 1)

#define DDR_PHY_DX0GSR1_DX0GSR1_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX0GSR1_DX0GSR1_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX0GSR1_DX0GSR1_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0GSR2 */
#define DDR_PHY_DX0GSR2(t)        (t + 0x7e8)

#define DDR_PHY_DX0GSR2_DX0GSR2_RDERR(x)         ((x) & GENMASK(0, 0))
#define DDR_PHY_DX0GSR2_DX0GSR2_RDERR_M          GENMASK(0, 0)
#define DDR_PHY_DX0GSR2_DX0GSR2_RDERR_X(x)       ((x) & GENMASK(0, 0))

#define DDR_PHY_DX0GSR2_DX0GSR2_RDWN(x)          (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX0GSR2_DX0GSR2_RDWN_M           GENMASK(1, 1)
#define DDR_PHY_DX0GSR2_DX0GSR2_RDWN_X(x)        (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX0GSR2_DX0GSR2_WDERR(x)         (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX0GSR2_DX0GSR2_WDERR_M          GENMASK(2, 2)
#define DDR_PHY_DX0GSR2_DX0GSR2_WDERR_X(x)       (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX0GSR2_DX0GSR2_WDWN(x)          (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX0GSR2_DX0GSR2_WDWN_M           GENMASK(3, 3)
#define DDR_PHY_DX0GSR2_DX0GSR2_WDWN_X(x)        (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX0GSR2_DX0GSR2_REERR(x)         (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX0GSR2_DX0GSR2_REERR_M          GENMASK(4, 4)
#define DDR_PHY_DX0GSR2_DX0GSR2_REERR_X(x)       (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX0GSR2_DX0GSR2_REWN(x)          (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX0GSR2_DX0GSR2_REWN_M           GENMASK(5, 5)
#define DDR_PHY_DX0GSR2_DX0GSR2_REWN_X(x)        (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX0GSR2_DX0GSR2_WEERR(x)         (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX0GSR2_DX0GSR2_WEERR_M          GENMASK(6, 6)
#define DDR_PHY_DX0GSR2_DX0GSR2_WEERR_X(x)       (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX0GSR2_DX0GSR2_WEWN(x)          (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_DX0GSR2_DX0GSR2_WEWN_M           GENMASK(7, 7)
#define DDR_PHY_DX0GSR2_DX0GSR2_WEWN_X(x)        (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_DX0GSR2_DX0GSR2_ESTAT(x)         (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX0GSR2_DX0GSR2_ESTAT_M          GENMASK(11, 8)
#define DDR_PHY_DX0GSR2_DX0GSR2_ESTAT_X(x)       (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX0GSR2_DX0GSR2_DBDQ(x)          (((x) << 12) & GENMASK(19, 12))
#define DDR_PHY_DX0GSR2_DX0GSR2_DBDQ_M           GENMASK(19, 12)
#define DDR_PHY_DX0GSR2_DX0GSR2_DBDQ_X(x)        (((x) & GENMASK(19, 12)) >> 12)

#define DDR_PHY_DX0GSR2_DX0GSR2_SRDERR(x)        (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX0GSR2_DX0GSR2_SRDERR_M         GENMASK(20, 20)
#define DDR_PHY_DX0GSR2_DX0GSR2_SRDERR_X(x)      (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX0GSR2_DX0GSR2_RESERVED_21(x)   (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX0GSR2_DX0GSR2_RESERVED_21_M    GENMASK(21, 21)
#define DDR_PHY_DX0GSR2_DX0GSR2_RESERVED_21_X(x) (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX0GSR2_DX0GSR2_GSDQSCAL(x)      (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX0GSR2_DX0GSR2_GSDQSCAL_M       GENMASK(22, 22)
#define DDR_PHY_DX0GSR2_DX0GSR2_GSDQSCAL_X(x)    (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX0GSR2_DX0GSR2_GSDQSPRD(x)      (((x) << 23) & GENMASK(31, 23))
#define DDR_PHY_DX0GSR2_DX0GSR2_GSDQSPRD_M       GENMASK(31, 23)
#define DDR_PHY_DX0GSR2_DX0GSR2_GSDQSPRD_X(x)    (((x) & GENMASK(31, 23)) >> 23)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0GSR3 */
#define DDR_PHY_DX0GSR3(t)        (t + 0x7ec)

#define DDR_PHY_DX0GSR3_DX0GSR3_SRDPC(x)         ((x) & GENMASK(1, 0))
#define DDR_PHY_DX0GSR3_DX0GSR3_SRDPC_M          GENMASK(1, 0)
#define DDR_PHY_DX0GSR3_DX0GSR3_SRDPC_X(x)       ((x) & GENMASK(1, 0))

#define DDR_PHY_DX0GSR3_DX0GSR3_RESERVED_7_2(x)  (((x) << 2) & GENMASK(7, 2))
#define DDR_PHY_DX0GSR3_DX0GSR3_RESERVED_7_2_M   GENMASK(7, 2)
#define DDR_PHY_DX0GSR3_DX0GSR3_RESERVED_7_2_X(x) (((x) & GENMASK(7, 2)) >> 2)

#define DDR_PHY_DX0GSR3_DX0GSR3_HVERR(x)         (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX0GSR3_DX0GSR3_HVERR_M          GENMASK(11, 8)
#define DDR_PHY_DX0GSR3_DX0GSR3_HVERR_X(x)       (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX0GSR3_DX0GSR3_HVWRN(x)         (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_DX0GSR3_DX0GSR3_HVWRN_M          GENMASK(15, 12)
#define DDR_PHY_DX0GSR3_DX0GSR3_HVWRN_X(x)       (((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_DX0GSR3_DX0GSR3_DVERR(x)         (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DX0GSR3_DX0GSR3_DVERR_M          GENMASK(19, 16)
#define DDR_PHY_DX0GSR3_DX0GSR3_DVERR_X(x)       (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DX0GSR3_DX0GSR3_DVWRN(x)         (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX0GSR3_DX0GSR3_DVWRN_M          GENMASK(23, 20)
#define DDR_PHY_DX0GSR3_DX0GSR3_DVWRN_X(x)       (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX0GSR3_DX0GSR3_ESTAT(x)         (((x) << 24) & GENMASK(26, 24))
#define DDR_PHY_DX0GSR3_DX0GSR3_ESTAT_M          GENMASK(26, 24)
#define DDR_PHY_DX0GSR3_DX0GSR3_ESTAT_X(x)       (((x) & GENMASK(26, 24)) >> 24)

#define DDR_PHY_DX0GSR3_DX0GSR3_RESERVED_31_27(x)\
	(((x) << 27) & GENMASK(31, 27))
#define DDR_PHY_DX0GSR3_DX0GSR3_RESERVED_31_27_M GENMASK(31, 27)
#define DDR_PHY_DX0GSR3_DX0GSR3_RESERVED_31_27_X(x)\
	(((x) & GENMASK(31, 27)) >> 27)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0GSR4 */
#define DDR_PHY_DX0GSR4(t)        (t + 0x7f0)

#define DDR_PHY_DX0GSR4_DX0GSR4_X4WDQCAL(x)      ((x) & GENMASK(0, 0))
#define DDR_PHY_DX0GSR4_DX0GSR4_X4WDQCAL_M       GENMASK(0, 0)
#define DDR_PHY_DX0GSR4_DX0GSR4_X4WDQCAL_X(x)    ((x) & GENMASK(0, 0))

#define DDR_PHY_DX0GSR4_DX0GSR4_X4RDQSCAL(x)     (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX0GSR4_DX0GSR4_X4RDQSCAL_M      GENMASK(1, 1)
#define DDR_PHY_DX0GSR4_DX0GSR4_X4RDQSCAL_X(x)   (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX0GSR4_DX0GSR4_X4RDQSNCAL(x)    (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX0GSR4_DX0GSR4_X4RDQSNCAL_M     GENMASK(2, 2)
#define DDR_PHY_DX0GSR4_DX0GSR4_X4RDQSNCAL_X(x)  (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX0GSR4_DX0GSR4_X4GDQSCAL(x)     (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX0GSR4_DX0GSR4_X4GDQSCAL_M      GENMASK(3, 3)
#define DDR_PHY_DX0GSR4_DX0GSR4_X4GDQSCAL_X(x)   (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX0GSR4_DX0GSR4_X4WLCAL(x)       (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX0GSR4_DX0GSR4_X4WLCAL_M        GENMASK(4, 4)
#define DDR_PHY_DX0GSR4_DX0GSR4_X4WLCAL_X(x)     (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX0GSR4_DX0GSR4_X4WLDONE(x)      (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX0GSR4_DX0GSR4_X4WLDONE_M       GENMASK(5, 5)
#define DDR_PHY_DX0GSR4_DX0GSR4_X4WLDONE_X(x)    (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX0GSR4_DX0GSR4_X4WLERR(x)       (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX0GSR4_DX0GSR4_X4WLERR_M        GENMASK(6, 6)
#define DDR_PHY_DX0GSR4_DX0GSR4_X4WLERR_X(x)     (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX0GSR4_DX0GSR4_X4WLPRD(x)       (((x) << 7) & GENMASK(15, 7))
#define DDR_PHY_DX0GSR4_DX0GSR4_X4WLPRD_M        GENMASK(15, 7)
#define DDR_PHY_DX0GSR4_DX0GSR4_X4WLPRD_X(x)     (((x) & GENMASK(15, 7)) >> 7)

#define DDR_PHY_DX0GSR4_DX0GSR4_X4DPLOCK(x)      (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX0GSR4_DX0GSR4_X4DPLOCK_M       GENMASK(16, 16)
#define DDR_PHY_DX0GSR4_DX0GSR4_X4DPLOCK_X(x)    (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX0GSR4_DX0GSR4_X4GDQSPRD(x)     (((x) << 17) & GENMASK(25, 17))
#define DDR_PHY_DX0GSR4_DX0GSR4_X4GDQSPRD_M      GENMASK(25, 17)
#define DDR_PHY_DX0GSR4_DX0GSR4_X4GDQSPRD_X(x)   (((x) & GENMASK(25, 17)) >> 17)

#define DDR_PHY_DX0GSR4_DX0GSR4_X4WLWN(x)        (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_DX0GSR4_DX0GSR4_X4WLWN_M         GENMASK(26, 26)
#define DDR_PHY_DX0GSR4_DX0GSR4_X4WLWN_X(x)      (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_DX0GSR4_DX0GSR4_RESERVED_29_27(x)\
	(((x) << 27) & GENMASK(29, 27))
#define DDR_PHY_DX0GSR4_DX0GSR4_RESERVED_29_27_M GENMASK(29, 27)
#define DDR_PHY_DX0GSR4_DX0GSR4_RESERVED_29_27_X(x)\
	(((x) & GENMASK(29, 27)) >> 27)

#define DDR_PHY_DX0GSR4_DX0GSR4_X4WLDQ(x)        (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX0GSR4_DX0GSR4_X4WLDQ_M         GENMASK(30, 30)
#define DDR_PHY_DX0GSR4_DX0GSR4_X4WLDQ_X(x)      (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX0GSR4_DX0GSR4_RESERVED_31(x)   (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX0GSR4_DX0GSR4_RESERVED_31_M    GENMASK(31, 31)
#define DDR_PHY_DX0GSR4_DX0GSR4_RESERVED_31_X(x) (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0GSR5 */
#define DDR_PHY_DX0GSR5(t)        (t + 0x7f4)

#define DDR_PHY_DX0GSR5_DX0GSR5_X4RDERR(x)       ((x) & GENMASK(0, 0))
#define DDR_PHY_DX0GSR5_DX0GSR5_X4RDERR_M        GENMASK(0, 0)
#define DDR_PHY_DX0GSR5_DX0GSR5_X4RDERR_X(x)     ((x) & GENMASK(0, 0))

#define DDR_PHY_DX0GSR5_DX0GSR5_X4RDWN(x)        (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX0GSR5_DX0GSR5_X4RDWN_M         GENMASK(1, 1)
#define DDR_PHY_DX0GSR5_DX0GSR5_X4RDWN_X(x)      (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX0GSR5_DX0GSR5_X4WDERR(x)       (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX0GSR5_DX0GSR5_X4WDERR_M        GENMASK(2, 2)
#define DDR_PHY_DX0GSR5_DX0GSR5_X4WDERR_X(x)     (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX0GSR5_DX0GSR5_X4WDWN(x)        (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX0GSR5_DX0GSR5_X4WDWN_M         GENMASK(3, 3)
#define DDR_PHY_DX0GSR5_DX0GSR5_X4WDWN_X(x)      (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX0GSR5_DX0GSR5_X4REERR(x)       (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX0GSR5_DX0GSR5_X4REERR_M        GENMASK(4, 4)
#define DDR_PHY_DX0GSR5_DX0GSR5_X4REERR_X(x)     (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX0GSR5_DX0GSR5_X4REWN(x)        (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX0GSR5_DX0GSR5_X4REWN_M         GENMASK(5, 5)
#define DDR_PHY_DX0GSR5_DX0GSR5_X4REWN_X(x)      (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX0GSR5_DX0GSR5_X4WEERR(x)       (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX0GSR5_DX0GSR5_X4WEERR_M        GENMASK(6, 6)
#define DDR_PHY_DX0GSR5_DX0GSR5_X4WEERR_X(x)     (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX0GSR5_DX0GSR5_X4WEWN(x)        (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_DX0GSR5_DX0GSR5_X4WEWN_M         GENMASK(7, 7)
#define DDR_PHY_DX0GSR5_DX0GSR5_X4WEWN_X(x)      (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_DX0GSR5_DX0GSR5_X4ESTAT(x)       (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX0GSR5_DX0GSR5_X4ESTAT_M        GENMASK(11, 8)
#define DDR_PHY_DX0GSR5_DX0GSR5_X4ESTAT_X(x)     (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX0GSR5_DX0GSR5_RESERVED_19_12(x)\
	(((x) << 12) & GENMASK(19, 12))
#define DDR_PHY_DX0GSR5_DX0GSR5_RESERVED_19_12_M GENMASK(19, 12)
#define DDR_PHY_DX0GSR5_DX0GSR5_RESERVED_19_12_X(x)\
	(((x) & GENMASK(19, 12)) >> 12)

#define DDR_PHY_DX0GSR5_DX0GSR5_X4SRDERR(x)      (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX0GSR5_DX0GSR5_X4SRDERR_M       GENMASK(20, 20)
#define DDR_PHY_DX0GSR5_DX0GSR5_X4SRDERR_X(x)    (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX0GSR5_DX0GSR5_RESERVED_21(x)   (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX0GSR5_DX0GSR5_RESERVED_21_M    GENMASK(21, 21)
#define DDR_PHY_DX0GSR5_DX0GSR5_RESERVED_21_X(x) (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX0GSR5_DX0GSR5_X4GSDQSCAL(x)    (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX0GSR5_DX0GSR5_X4GSDQSCAL_M     GENMASK(22, 22)
#define DDR_PHY_DX0GSR5_DX0GSR5_X4GSDQSCAL_X(x)  (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX0GSR5_DX0GSR5_X4GSDQSPRD(x)    (((x) << 23) & GENMASK(31, 23))
#define DDR_PHY_DX0GSR5_DX0GSR5_X4GSDQSPRD_M     GENMASK(31, 23)
#define DDR_PHY_DX0GSR5_DX0GSR5_X4GSDQSPRD_X(x)  (((x) & GENMASK(31, 23)) >> 23)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX0GSR6 */
#define DDR_PHY_DX0GSR6(t)        (t + 0x7f8)

#define DDR_PHY_DX0GSR6_DX0GSR6_RESERVED_1_0(x)  ((x) & GENMASK(1, 0))
#define DDR_PHY_DX0GSR6_DX0GSR6_RESERVED_1_0_M   GENMASK(1, 0)
#define DDR_PHY_DX0GSR6_DX0GSR6_RESERVED_1_0_X(x) ((x) & GENMASK(1, 0))

#define DDR_PHY_DX0GSR6_DX0GSR6_X4SRDPC(x)       (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DX0GSR6_DX0GSR6_X4SRDPC_M        GENMASK(3, 2)
#define DDR_PHY_DX0GSR6_DX0GSR6_X4SRDPC_X(x)     (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DX0GSR6_DX0GSR6_RESERVED_7_4(x)  (((x) << 4) & GENMASK(7, 4))
#define DDR_PHY_DX0GSR6_DX0GSR6_RESERVED_7_4_M   GENMASK(7, 4)
#define DDR_PHY_DX0GSR6_DX0GSR6_RESERVED_7_4_X(x) (((x) & GENMASK(7, 4)) >> 4)

#define DDR_PHY_DX0GSR6_DX0GSR6_X4HVERR(x)       (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX0GSR6_DX0GSR6_X4HVERR_M        GENMASK(11, 8)
#define DDR_PHY_DX0GSR6_DX0GSR6_X4HVERR_X(x)     (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX0GSR6_DX0GSR6_X4HVWRN(x)       (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_DX0GSR6_DX0GSR6_X4HVWRN_M        GENMASK(15, 12)
#define DDR_PHY_DX0GSR6_DX0GSR6_X4HVWRN_X(x)     (((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_DX0GSR6_DX0GSR6_X4DVERR(x)       (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DX0GSR6_DX0GSR6_X4DVERR_M        GENMASK(19, 16)
#define DDR_PHY_DX0GSR6_DX0GSR6_X4DVERR_X(x)     (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DX0GSR6_DX0GSR6_X4DVWRN(x)       (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX0GSR6_DX0GSR6_X4DVWRN_M        GENMASK(23, 20)
#define DDR_PHY_DX0GSR6_DX0GSR6_X4DVWRN_X(x)     (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX0GSR6_DX0GSR6_RESERVED_31_24(x)\
	(((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_DX0GSR6_DX0GSR6_RESERVED_31_24_M GENMASK(31, 24)
#define DDR_PHY_DX0GSR6_DX0GSR6_RESERVED_31_24_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1GCR0 */
#define DDR_PHY_DX1GCR0(t)        (t + 0x800)

#define DDR_PHY_DX1GCR0_DX1GCR0_DXEN(x)          ((x) & GENMASK(0, 0))
#define DDR_PHY_DX1GCR0_DX1GCR0_DXEN_M           GENMASK(0, 0)
#define DDR_PHY_DX1GCR0_DX1GCR0_DXEN_X(x)        ((x) & GENMASK(0, 0))

#define DDR_PHY_DX1GCR0_DX1GCR0_DXIOM(x)         (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX1GCR0_DX1GCR0_DXIOM_M          GENMASK(1, 1)
#define DDR_PHY_DX1GCR0_DX1GCR0_DXIOM_X(x)       (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX1GCR0_DX1GCR0_DQSGOE(x)        (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX1GCR0_DX1GCR0_DQSGOE_M         GENMASK(2, 2)
#define DDR_PHY_DX1GCR0_DX1GCR0_DQSGOE_X(x)      (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX1GCR0_DX1GCR0_DQSGODT(x)       (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX1GCR0_DX1GCR0_DQSGODT_M        GENMASK(3, 3)
#define DDR_PHY_DX1GCR0_DX1GCR0_DQSGODT_X(x)     (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX1GCR0_DX1GCR0_RESERVED_4(x)    (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX1GCR0_DX1GCR0_RESERVED_4_M     GENMASK(4, 4)
#define DDR_PHY_DX1GCR0_DX1GCR0_RESERVED_4_X(x)  (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX1GCR0_DX1GCR0_DQSGPDR(x)       (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX1GCR0_DX1GCR0_DQSGPDR_M        GENMASK(5, 5)
#define DDR_PHY_DX1GCR0_DX1GCR0_DQSGPDR_X(x)     (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX1GCR0_DX1GCR0_RESERVED_6(x)    (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX1GCR0_DX1GCR0_RESERVED_6_M     GENMASK(6, 6)
#define DDR_PHY_DX1GCR0_DX1GCR0_RESERVED_6_X(x)  (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX1GCR0_DX1GCR0_PDRAL(x)         (((x) << 7) & GENMASK(8, 7))
#define DDR_PHY_DX1GCR0_DX1GCR0_PDRAL_M          GENMASK(8, 7)
#define DDR_PHY_DX1GCR0_DX1GCR0_PDRAL_X(x)       (((x) & GENMASK(8, 7)) >> 7)

#define DDR_PHY_DX1GCR0_DX1GCR0_RTTOH(x)         (((x) << 9) & GENMASK(10, 9))
#define DDR_PHY_DX1GCR0_DX1GCR0_RTTOH_M          GENMASK(10, 9)
#define DDR_PHY_DX1GCR0_DX1GCR0_RTTOH_X(x)       (((x) & GENMASK(10, 9)) >> 9)

#define DDR_PHY_DX1GCR0_DX1GCR0_RTTOAL(x)        (((x) << 11) & GENMASK(11, 11))
#define DDR_PHY_DX1GCR0_DX1GCR0_RTTOAL_M         GENMASK(11, 11)
#define DDR_PHY_DX1GCR0_DX1GCR0_RTTOAL_X(x)      (((x) & GENMASK(11, 11)) >> 11)

#define DDR_PHY_DX1GCR0_DX1GCR0_DQSSEPDR(x)      (((x) << 12) & GENMASK(12, 12))
#define DDR_PHY_DX1GCR0_DX1GCR0_DQSSEPDR_M       GENMASK(12, 12)
#define DDR_PHY_DX1GCR0_DX1GCR0_DQSSEPDR_X(x)    (((x) & GENMASK(12, 12)) >> 12)

#define DDR_PHY_DX1GCR0_DX1GCR0_DQSNSEPDR(x)     (((x) << 13) & GENMASK(13, 13))
#define DDR_PHY_DX1GCR0_DX1GCR0_DQSNSEPDR_M      GENMASK(13, 13)
#define DDR_PHY_DX1GCR0_DX1GCR0_DQSNSEPDR_X(x)   (((x) & GENMASK(13, 13)) >> 13)

#define DDR_PHY_DX1GCR0_DX1GCR0_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX1GCR0_DX1GCR0_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX1GCR0_DX1GCR0_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX1GCR0_DX1GCR0_PLLRST(x)        (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX1GCR0_DX1GCR0_PLLRST_M         GENMASK(16, 16)
#define DDR_PHY_DX1GCR0_DX1GCR0_PLLRST_X(x)      (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX1GCR0_DX1GCR0_PLLPD(x)         (((x) << 17) & GENMASK(17, 17))
#define DDR_PHY_DX1GCR0_DX1GCR0_PLLPD_M          GENMASK(17, 17)
#define DDR_PHY_DX1GCR0_DX1GCR0_PLLPD_X(x)       (((x) & GENMASK(17, 17)) >> 17)

#define DDR_PHY_DX1GCR0_DX1GCR0_GSHIFT(x)        (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_DX1GCR0_DX1GCR0_GSHIFT_M         GENMASK(18, 18)
#define DDR_PHY_DX1GCR0_DX1GCR0_GSHIFT_X(x)      (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_DX1GCR0_DX1GCR0_PLLBYP(x)        (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_DX1GCR0_DX1GCR0_PLLBYP_M         GENMASK(19, 19)
#define DDR_PHY_DX1GCR0_DX1GCR0_PLLBYP_X(x)      (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_DX1GCR0_DX1GCR0_RDDLY(x)         (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX1GCR0_DX1GCR0_RDDLY_M          GENMASK(23, 20)
#define DDR_PHY_DX1GCR0_DX1GCR0_RDDLY_X(x)       (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX1GCR0_DX1GCR0_RESERVED_29_24(x)\
	(((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX1GCR0_DX1GCR0_RESERVED_29_24_M GENMASK(29, 24)
#define DDR_PHY_DX1GCR0_DX1GCR0_RESERVED_29_24_X(x)\
	(((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX1GCR0_DX1GCR0_MDLEN(x)         (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX1GCR0_DX1GCR0_MDLEN_M          GENMASK(30, 30)
#define DDR_PHY_DX1GCR0_DX1GCR0_MDLEN_X(x)       (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX1GCR0_DX1GCR0_CALBYP(x)        (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX1GCR0_DX1GCR0_CALBYP_M         GENMASK(31, 31)
#define DDR_PHY_DX1GCR0_DX1GCR0_CALBYP_X(x)      (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1GCR1 */
#define DDR_PHY_DX1GCR1(t)        (t + 0x804)

#define DDR_PHY_DX1GCR1_DX1GCR1_RESERVED_15_0(x) ((x) & GENMASK(15, 0))
#define DDR_PHY_DX1GCR1_DX1GCR1_RESERVED_15_0_M  GENMASK(15, 0)
#define DDR_PHY_DX1GCR1_DX1GCR1_RESERVED_15_0_X(x) ((x) & GENMASK(15, 0))

#define DDR_PHY_DX1GCR1_DX1GCR1_DXPDRMODE(x)     (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX1GCR1_DX1GCR1_DXPDRMODE_M      GENMASK(31, 16)
#define DDR_PHY_DX1GCR1_DX1GCR1_DXPDRMODE_X(x)   (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1GCR2 */
#define DDR_PHY_DX1GCR2(t)        (t + 0x808)

#define DDR_PHY_DX1GCR2_DX1GCR2_DXTEMODE(x)      ((x) & GENMASK(15, 0))
#define DDR_PHY_DX1GCR2_DX1GCR2_DXTEMODE_M       GENMASK(15, 0)
#define DDR_PHY_DX1GCR2_DX1GCR2_DXTEMODE_X(x)    ((x) & GENMASK(15, 0))

#define DDR_PHY_DX1GCR2_DX1GCR2_DXOEMODE(x)      (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX1GCR2_DX1GCR2_DXOEMODE_M       GENMASK(31, 16)
#define DDR_PHY_DX1GCR2_DX1GCR2_DXOEMODE_X(x)    (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1GCR3 */
#define DDR_PHY_DX1GCR3(t)        (t + 0x80c)

#define DDR_PHY_DX1GCR3_DX1GCR3_RESERVED_1_0(x)  ((x) & GENMASK(1, 0))
#define DDR_PHY_DX1GCR3_DX1GCR3_RESERVED_1_0_M   GENMASK(1, 0)
#define DDR_PHY_DX1GCR3_DX1GCR3_RESERVED_1_0_X(x) ((x) & GENMASK(1, 0))

#define DDR_PHY_DX1GCR3_DX1GCR3_DSPDRMODE(x)     (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DX1GCR3_DX1GCR3_DSPDRMODE_M      GENMASK(3, 2)
#define DDR_PHY_DX1GCR3_DX1GCR3_DSPDRMODE_X(x)   (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DX1GCR3_DX1GCR3_DSTEMODE(x)      (((x) << 4) & GENMASK(5, 4))
#define DDR_PHY_DX1GCR3_DX1GCR3_DSTEMODE_M       GENMASK(5, 4)
#define DDR_PHY_DX1GCR3_DX1GCR3_DSTEMODE_X(x)    (((x) & GENMASK(5, 4)) >> 4)

#define DDR_PHY_DX1GCR3_DX1GCR3_DSOEMODE(x)      (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX1GCR3_DX1GCR3_DSOEMODE_M       GENMASK(7, 6)
#define DDR_PHY_DX1GCR3_DX1GCR3_DSOEMODE_X(x)    (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX1GCR3_DX1GCR3_RESERVED_9_8(x)  (((x) << 8) & GENMASK(9, 8))
#define DDR_PHY_DX1GCR3_DX1GCR3_RESERVED_9_8_M   GENMASK(9, 8)
#define DDR_PHY_DX1GCR3_DX1GCR3_RESERVED_9_8_X(x) (((x) & GENMASK(9, 8)) >> 8)

#define DDR_PHY_DX1GCR3_DX1GCR3_DMPDRMODE(x)     (((x) << 10) & GENMASK(11, 10))
#define DDR_PHY_DX1GCR3_DX1GCR3_DMPDRMODE_M      GENMASK(11, 10)
#define DDR_PHY_DX1GCR3_DX1GCR3_DMPDRMODE_X(x)   (((x) & GENMASK(11, 10)) >> 10)

#define DDR_PHY_DX1GCR3_DX1GCR3_DMTEMODE(x)      (((x) << 12) & GENMASK(13, 12))
#define DDR_PHY_DX1GCR3_DX1GCR3_DMTEMODE_M       GENMASK(13, 12)
#define DDR_PHY_DX1GCR3_DX1GCR3_DMTEMODE_X(x)    (((x) & GENMASK(13, 12)) >> 12)

#define DDR_PHY_DX1GCR3_DX1GCR3_DMOEMODE(x)      (((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX1GCR3_DX1GCR3_DMOEMODE_M       GENMASK(15, 14)
#define DDR_PHY_DX1GCR3_DX1GCR3_DMOEMODE_X(x)    (((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX1GCR3_DX1GCR3_RESERVED_17_16(x)\
	(((x) << 16) & GENMASK(17, 16))
#define DDR_PHY_DX1GCR3_DX1GCR3_RESERVED_17_16_M GENMASK(17, 16)
#define DDR_PHY_DX1GCR3_DX1GCR3_RESERVED_17_16_X(x)\
	(((x) & GENMASK(17, 16)) >> 16)

#define DDR_PHY_DX1GCR3_DX1GCR3_OEBVT(x)         (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_DX1GCR3_DX1GCR3_OEBVT_M          GENMASK(18, 18)
#define DDR_PHY_DX1GCR3_DX1GCR3_OEBVT_X(x)       (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_DX1GCR3_DX1GCR3_PDRBVT(x)        (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_DX1GCR3_DX1GCR3_PDRBVT_M         GENMASK(19, 19)
#define DDR_PHY_DX1GCR3_DX1GCR3_PDRBVT_X(x)      (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_DX1GCR3_DX1GCR3_TEBVT(x)         (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX1GCR3_DX1GCR3_TEBVT_M          GENMASK(20, 20)
#define DDR_PHY_DX1GCR3_DX1GCR3_TEBVT_X(x)       (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX1GCR3_DX1GCR3_WDSBVT(x)        (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX1GCR3_DX1GCR3_WDSBVT_M         GENMASK(21, 21)
#define DDR_PHY_DX1GCR3_DX1GCR3_WDSBVT_X(x)      (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX1GCR3_DX1GCR3_RDSBVT(x)        (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX1GCR3_DX1GCR3_RDSBVT_M         GENMASK(22, 22)
#define DDR_PHY_DX1GCR3_DX1GCR3_RDSBVT_X(x)      (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX1GCR3_DX1GCR3_RGSLVT(x)        (((x) << 23) & GENMASK(23, 23))
#define DDR_PHY_DX1GCR3_DX1GCR3_RGSLVT_M         GENMASK(23, 23)
#define DDR_PHY_DX1GCR3_DX1GCR3_RGSLVT_X(x)      (((x) & GENMASK(23, 23)) >> 23)

#define DDR_PHY_DX1GCR3_DX1GCR3_WLLVT(x)         (((x) << 24) & GENMASK(24, 24))
#define DDR_PHY_DX1GCR3_DX1GCR3_WLLVT_M          GENMASK(24, 24)
#define DDR_PHY_DX1GCR3_DX1GCR3_WLLVT_X(x)       (((x) & GENMASK(24, 24)) >> 24)

#define DDR_PHY_DX1GCR3_DX1GCR3_WDLVT(x)         (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_DX1GCR3_DX1GCR3_WDLVT_M          GENMASK(25, 25)
#define DDR_PHY_DX1GCR3_DX1GCR3_WDLVT_X(x)       (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_DX1GCR3_DX1GCR3_RDLVT(x)         (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_DX1GCR3_DX1GCR3_RDLVT_M          GENMASK(26, 26)
#define DDR_PHY_DX1GCR3_DX1GCR3_RDLVT_X(x)       (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_DX1GCR3_DX1GCR3_RGLVT(x)         (((x) << 27) & GENMASK(27, 27))
#define DDR_PHY_DX1GCR3_DX1GCR3_RGLVT_M          GENMASK(27, 27)
#define DDR_PHY_DX1GCR3_DX1GCR3_RGLVT_X(x)       (((x) & GENMASK(27, 27)) >> 27)

#define DDR_PHY_DX1GCR3_DX1GCR3_WDBVT(x)         (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_DX1GCR3_DX1GCR3_WDBVT_M          GENMASK(28, 28)
#define DDR_PHY_DX1GCR3_DX1GCR3_WDBVT_X(x)       (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_DX1GCR3_DX1GCR3_RDBVT(x)         (((x) << 29) & GENMASK(29, 29))
#define DDR_PHY_DX1GCR3_DX1GCR3_RDBVT_M          GENMASK(29, 29)
#define DDR_PHY_DX1GCR3_DX1GCR3_RDBVT_X(x)       (((x) & GENMASK(29, 29)) >> 29)

#define DDR_PHY_DX1GCR3_DX1GCR3_WDMBVT(x)        (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX1GCR3_DX1GCR3_WDMBVT_M         GENMASK(30, 30)
#define DDR_PHY_DX1GCR3_DX1GCR3_WDMBVT_X(x)      (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX1GCR3_DX1GCR3_RDMBVT(x)        (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX1GCR3_DX1GCR3_RDMBVT_M         GENMASK(31, 31)
#define DDR_PHY_DX1GCR3_DX1GCR3_RDMBVT_X(x)      (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1GCR4 */
#define DDR_PHY_DX1GCR4(t)        (t + 0x810)

#define DDR_PHY_DX1GCR4_DX1GCR4_DXREFIMON(x)     ((x) & GENMASK(1, 0))
#define DDR_PHY_DX1GCR4_DX1GCR4_DXREFIMON_M      GENMASK(1, 0)
#define DDR_PHY_DX1GCR4_DX1GCR4_DXREFIMON_X(x)   ((x) & GENMASK(1, 0))

#define DDR_PHY_DX1GCR4_DX1GCR4_DXREFIEN(x)      (((x) << 2) & GENMASK(5, 2))
#define DDR_PHY_DX1GCR4_DX1GCR4_DXREFIEN_M       GENMASK(5, 2)
#define DDR_PHY_DX1GCR4_DX1GCR4_DXREFIEN_X(x)    (((x) & GENMASK(5, 2)) >> 2)

#define DDR_PHY_DX1GCR4_DX1GCR4_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX1GCR4_DX1GCR4_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX1GCR4_DX1GCR4_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX1GCR4_DX1GCR4_DXREFSSEL(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX1GCR4_DX1GCR4_DXREFSSEL_M      GENMASK(13, 8)
#define DDR_PHY_DX1GCR4_DX1GCR4_DXREFSSEL_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX1GCR4_DX1GCR4_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX1GCR4_DX1GCR4_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX1GCR4_DX1GCR4_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX1GCR4_DX1GCR4_DXREFESEL(x)     (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX1GCR4_DX1GCR4_DXREFESEL_M      GENMASK(21, 16)
#define DDR_PHY_DX1GCR4_DX1GCR4_DXREFESEL_X(x)   (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX1GCR4_DX1GCR4_RESERVED_24_22(x)\
	(((x) << 22) & GENMASK(24, 22))
#define DDR_PHY_DX1GCR4_DX1GCR4_RESERVED_24_22_M GENMASK(24, 22)
#define DDR_PHY_DX1GCR4_DX1GCR4_RESERVED_24_22_X(x)\
	(((x) & GENMASK(24, 22)) >> 22)

#define DDR_PHY_DX1GCR4_DX1GCR4_DXREFSEN(x)      (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_DX1GCR4_DX1GCR4_DXREFSEN_M       GENMASK(25, 25)
#define DDR_PHY_DX1GCR4_DX1GCR4_DXREFSEN_X(x)    (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_DX1GCR4_DX1GCR4_DXREFEEN(x)      (((x) << 26) & GENMASK(27, 26))
#define DDR_PHY_DX1GCR4_DX1GCR4_DXREFEEN_M       GENMASK(27, 26)
#define DDR_PHY_DX1GCR4_DX1GCR4_DXREFEEN_X(x)    (((x) & GENMASK(27, 26)) >> 26)

#define DDR_PHY_DX1GCR4_DX1GCR4_DXREFPEN(x)      (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_DX1GCR4_DX1GCR4_DXREFPEN_M       GENMASK(28, 28)
#define DDR_PHY_DX1GCR4_DX1GCR4_DXREFPEN_X(x)    (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_DX1GCR4_DX1GCR4_DXREFIOM(x)      (((x) << 29) & GENMASK(31, 29))
#define DDR_PHY_DX1GCR4_DX1GCR4_DXREFIOM_M       GENMASK(31, 29)
#define DDR_PHY_DX1GCR4_DX1GCR4_DXREFIOM_X(x)    (((x) & GENMASK(31, 29)) >> 29)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1GCR5 */
#define DDR_PHY_DX1GCR5(t)        (t + 0x814)

#define DDR_PHY_DX1GCR5_DX1GCR5_DXREFISELR0(x)   ((x) & GENMASK(5, 0))
#define DDR_PHY_DX1GCR5_DX1GCR5_DXREFISELR0_M    GENMASK(5, 0)
#define DDR_PHY_DX1GCR5_DX1GCR5_DXREFISELR0_X(x) ((x) & GENMASK(5, 0))

#define DDR_PHY_DX1GCR5_DX1GCR5_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX1GCR5_DX1GCR5_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX1GCR5_DX1GCR5_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX1GCR5_DX1GCR5_DXREFISELR1(x)   (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX1GCR5_DX1GCR5_DXREFISELR1_M    GENMASK(13, 8)
#define DDR_PHY_DX1GCR5_DX1GCR5_DXREFISELR1_X(x) (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX1GCR5_DX1GCR5_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX1GCR5_DX1GCR5_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX1GCR5_DX1GCR5_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX1GCR5_DX1GCR5_DXREFISELR2(x)   (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX1GCR5_DX1GCR5_DXREFISELR2_M    GENMASK(21, 16)
#define DDR_PHY_DX1GCR5_DX1GCR5_DXREFISELR2_X(x) (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX1GCR5_DX1GCR5_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX1GCR5_DX1GCR5_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX1GCR5_DX1GCR5_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX1GCR5_DX1GCR5_DXREFISELR3(x)   (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX1GCR5_DX1GCR5_DXREFISELR3_M    GENMASK(29, 24)
#define DDR_PHY_DX1GCR5_DX1GCR5_DXREFISELR3_X(x) (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX1GCR5_DX1GCR5_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX1GCR5_DX1GCR5_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX1GCR5_DX1GCR5_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1GCR6 */
#define DDR_PHY_DX1GCR6(t)        (t + 0x818)

#define DDR_PHY_DX1GCR6_DX1GCR6_DXDQVREFR0(x)    ((x) & GENMASK(5, 0))
#define DDR_PHY_DX1GCR6_DX1GCR6_DXDQVREFR0_M     GENMASK(5, 0)
#define DDR_PHY_DX1GCR6_DX1GCR6_DXDQVREFR0_X(x)  ((x) & GENMASK(5, 0))

#define DDR_PHY_DX1GCR6_DX1GCR6_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX1GCR6_DX1GCR6_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX1GCR6_DX1GCR6_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX1GCR6_DX1GCR6_DXDQVREFR1(x)    (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX1GCR6_DX1GCR6_DXDQVREFR1_M     GENMASK(13, 8)
#define DDR_PHY_DX1GCR6_DX1GCR6_DXDQVREFR1_X(x)  (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX1GCR6_DX1GCR6_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX1GCR6_DX1GCR6_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX1GCR6_DX1GCR6_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX1GCR6_DX1GCR6_DXDQVREFR2(x)    (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX1GCR6_DX1GCR6_DXDQVREFR2_M     GENMASK(21, 16)
#define DDR_PHY_DX1GCR6_DX1GCR6_DXDQVREFR2_X(x)  (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX1GCR6_DX1GCR6_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX1GCR6_DX1GCR6_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX1GCR6_DX1GCR6_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX1GCR6_DX1GCR6_DXDQVREFR3(x)    (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX1GCR6_DX1GCR6_DXDQVREFR3_M     GENMASK(29, 24)
#define DDR_PHY_DX1GCR6_DX1GCR6_DXDQVREFR3_X(x)  (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX1GCR6_DX1GCR6_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX1GCR6_DX1GCR6_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX1GCR6_DX1GCR6_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1GCR7 */
#define DDR_PHY_DX1GCR7(t)        (t + 0x81c)

#define DDR_PHY_DX1GCR7_DX1GCR7_RESERVED_1_0(x)  ((x) & GENMASK(1, 0))
#define DDR_PHY_DX1GCR7_DX1GCR7_RESERVED_1_0_M   GENMASK(1, 0)
#define DDR_PHY_DX1GCR7_DX1GCR7_RESERVED_1_0_X(x) ((x) & GENMASK(1, 0))

#define DDR_PHY_DX1GCR7_DX1GCR7_X4DSPDRMODE(x)   (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DX1GCR7_DX1GCR7_X4DSPDRMODE_M    GENMASK(3, 2)
#define DDR_PHY_DX1GCR7_DX1GCR7_X4DSPDRMODE_X(x) (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DX1GCR7_DX1GCR7_X4DSTEMODE(x)    (((x) << 4) & GENMASK(5, 4))
#define DDR_PHY_DX1GCR7_DX1GCR7_X4DSTEMODE_M     GENMASK(5, 4)
#define DDR_PHY_DX1GCR7_DX1GCR7_X4DSTEMODE_X(x)  (((x) & GENMASK(5, 4)) >> 4)

#define DDR_PHY_DX1GCR7_DX1GCR7_X4DSOEMODE(x)    (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX1GCR7_DX1GCR7_X4DSOEMODE_M     GENMASK(7, 6)
#define DDR_PHY_DX1GCR7_DX1GCR7_X4DSOEMODE_X(x)  (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX1GCR7_DX1GCR7_RESERVED_9_8(x)  (((x) << 8) & GENMASK(9, 8))
#define DDR_PHY_DX1GCR7_DX1GCR7_RESERVED_9_8_M   GENMASK(9, 8)
#define DDR_PHY_DX1GCR7_DX1GCR7_RESERVED_9_8_X(x) (((x) & GENMASK(9, 8)) >> 8)

#define DDR_PHY_DX1GCR7_DX1GCR7_X4DXPDRMODE(x)   (((x) << 10) & GENMASK(11, 10))
#define DDR_PHY_DX1GCR7_DX1GCR7_X4DXPDRMODE_M    GENMASK(11, 10)
#define DDR_PHY_DX1GCR7_DX1GCR7_X4DXPDRMODE_X(x) (((x) & GENMASK(11, 10)) >> 10)

#define DDR_PHY_DX1GCR7_DX1GCR7_X4DXTEMODE(x)    (((x) << 12) & GENMASK(13, 12))
#define DDR_PHY_DX1GCR7_DX1GCR7_X4DXTEMODE_M     GENMASK(13, 12)
#define DDR_PHY_DX1GCR7_DX1GCR7_X4DXTEMODE_X(x)  (((x) & GENMASK(13, 12)) >> 12)

#define DDR_PHY_DX1GCR7_DX1GCR7_X4DXOEMODE(x)    (((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX1GCR7_DX1GCR7_X4DXOEMODE_M     GENMASK(15, 14)
#define DDR_PHY_DX1GCR7_DX1GCR7_X4DXOEMODE_X(x)  (((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX1GCR7_DX1GCR7_X4DQSGOE(x)      (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX1GCR7_DX1GCR7_X4DQSGOE_M       GENMASK(16, 16)
#define DDR_PHY_DX1GCR7_DX1GCR7_X4DQSGOE_X(x)    (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX1GCR7_DX1GCR7_X4DQSGODT(x)     (((x) << 17) & GENMASK(17, 17))
#define DDR_PHY_DX1GCR7_DX1GCR7_X4DQSGODT_M      GENMASK(17, 17)
#define DDR_PHY_DX1GCR7_DX1GCR7_X4DQSGODT_X(x)   (((x) & GENMASK(17, 17)) >> 17)

#define DDR_PHY_DX1GCR7_DX1GCR7_RESERVED_18(x)   (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_DX1GCR7_DX1GCR7_RESERVED_18_M    GENMASK(18, 18)
#define DDR_PHY_DX1GCR7_DX1GCR7_RESERVED_18_X(x) (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_DX1GCR7_DX1GCR7_X4DQSGPDR(x)     (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_DX1GCR7_DX1GCR7_X4DQSGPDR_M      GENMASK(19, 19)
#define DDR_PHY_DX1GCR7_DX1GCR7_X4DQSGPDR_X(x)   (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_DX1GCR7_DX1GCR7_RESERVED_20(x)   (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX1GCR7_DX1GCR7_RESERVED_20_M    GENMASK(20, 20)
#define DDR_PHY_DX1GCR7_DX1GCR7_RESERVED_20_X(x) (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX1GCR7_DX1GCR7_X4DQSSEPDR(x)    (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX1GCR7_DX1GCR7_X4DQSSEPDR_M     GENMASK(21, 21)
#define DDR_PHY_DX1GCR7_DX1GCR7_X4DQSSEPDR_X(x)  (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX1GCR7_DX1GCR7_X4DQSNSEPDR(x)   (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX1GCR7_DX1GCR7_X4DQSNSEPDR_M    GENMASK(22, 22)
#define DDR_PHY_DX1GCR7_DX1GCR7_X4DQSNSEPDR_X(x) (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX1GCR7_DX1GCR7_X4RTTOH(x)       (((x) << 23) & GENMASK(24, 23))
#define DDR_PHY_DX1GCR7_DX1GCR7_X4RTTOH_M        GENMASK(24, 23)
#define DDR_PHY_DX1GCR7_DX1GCR7_X4RTTOH_X(x)     (((x) & GENMASK(24, 23)) >> 23)

#define DDR_PHY_DX1GCR7_DX1GCR7_X4RTTOAL(x)      (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_DX1GCR7_DX1GCR7_X4RTTOAL_M       GENMASK(25, 25)
#define DDR_PHY_DX1GCR7_DX1GCR7_X4RTTOAL_X(x)    (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_DX1GCR7_DX1GCR7_X4RDDLY(x)       (((x) << 26) & GENMASK(29, 26))
#define DDR_PHY_DX1GCR7_DX1GCR7_X4RDDLY_M        GENMASK(29, 26)
#define DDR_PHY_DX1GCR7_DX1GCR7_X4RDDLY_X(x)     (((x) & GENMASK(29, 26)) >> 26)

#define DDR_PHY_DX1GCR7_DX1GCR7_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX1GCR7_DX1GCR7_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX1GCR7_DX1GCR7_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1GCR8 */
#define DDR_PHY_DX1GCR8(t)        (t + 0x820)

#define DDR_PHY_DX1GCR8_DX1GCR8_X4DXREFISELR0(x) ((x) & GENMASK(5, 0))
#define DDR_PHY_DX1GCR8_DX1GCR8_X4DXREFISELR0_M  GENMASK(5, 0)
#define DDR_PHY_DX1GCR8_DX1GCR8_X4DXREFISELR0_X(x) ((x) & GENMASK(5, 0))

#define DDR_PHY_DX1GCR8_DX1GCR8_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX1GCR8_DX1GCR8_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX1GCR8_DX1GCR8_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX1GCR8_DX1GCR8_X4DXREFISELR1(x) (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX1GCR8_DX1GCR8_X4DXREFISELR1_M  GENMASK(13, 8)
#define DDR_PHY_DX1GCR8_DX1GCR8_X4DXREFISELR1_X(x) (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX1GCR8_DX1GCR8_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX1GCR8_DX1GCR8_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX1GCR8_DX1GCR8_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX1GCR8_DX1GCR8_X4DXREFISELR2(x) (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX1GCR8_DX1GCR8_X4DXREFISELR2_M  GENMASK(21, 16)
#define DDR_PHY_DX1GCR8_DX1GCR8_X4DXREFISELR2_X(x)\
	(((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX1GCR8_DX1GCR8_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX1GCR8_DX1GCR8_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX1GCR8_DX1GCR8_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX1GCR8_DX1GCR8_X4DXREFISELR3(x) (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX1GCR8_DX1GCR8_X4DXREFISELR3_M  GENMASK(29, 24)
#define DDR_PHY_DX1GCR8_DX1GCR8_X4DXREFISELR3_X(x)\
	(((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX1GCR8_DX1GCR8_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX1GCR8_DX1GCR8_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX1GCR8_DX1GCR8_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1GCR9 */
#define DDR_PHY_DX1GCR9(t)        (t + 0x824)

#define DDR_PHY_DX1GCR9_DX1GCR9_X4DXDQVREFR0(x)  ((x) & GENMASK(5, 0))
#define DDR_PHY_DX1GCR9_DX1GCR9_X4DXDQVREFR0_M   GENMASK(5, 0)
#define DDR_PHY_DX1GCR9_DX1GCR9_X4DXDQVREFR0_X(x) ((x) & GENMASK(5, 0))

#define DDR_PHY_DX1GCR9_DX1GCR9_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX1GCR9_DX1GCR9_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX1GCR9_DX1GCR9_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX1GCR9_DX1GCR9_X4DXDQVREFR1(x)  (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX1GCR9_DX1GCR9_X4DXDQVREFR1_M   GENMASK(13, 8)
#define DDR_PHY_DX1GCR9_DX1GCR9_X4DXDQVREFR1_X(x) (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX1GCR9_DX1GCR9_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX1GCR9_DX1GCR9_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX1GCR9_DX1GCR9_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX1GCR9_DX1GCR9_X4DXDQVREFR2(x)  (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX1GCR9_DX1GCR9_X4DXDQVREFR2_M   GENMASK(21, 16)
#define DDR_PHY_DX1GCR9_DX1GCR9_X4DXDQVREFR2_X(x)\
	(((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX1GCR9_DX1GCR9_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX1GCR9_DX1GCR9_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX1GCR9_DX1GCR9_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX1GCR9_DX1GCR9_X4DXDQVREFR3(x)  (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX1GCR9_DX1GCR9_X4DXDQVREFR3_M   GENMASK(29, 24)
#define DDR_PHY_DX1GCR9_DX1GCR9_X4DXDQVREFR3_X(x)\
	(((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX1GCR9_DX1GCR9_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX1GCR9_DX1GCR9_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX1GCR9_DX1GCR9_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1BDLR0 */
#define DDR_PHY_DX1BDLR0(t)       (t + 0x840)

#define DDR_PHY_DX1BDLR0_DX1BDLR0_DQ0WBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX1BDLR0_DX1BDLR0_DQ0WBD_M       GENMASK(5, 0)
#define DDR_PHY_DX1BDLR0_DX1BDLR0_DQ0WBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX1BDLR0_DX1BDLR0_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX1BDLR0_DX1BDLR0_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX1BDLR0_DX1BDLR0_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX1BDLR0_DX1BDLR0_DQ1WBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX1BDLR0_DX1BDLR0_DQ1WBD_M       GENMASK(13, 8)
#define DDR_PHY_DX1BDLR0_DX1BDLR0_DQ1WBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX1BDLR0_DX1BDLR0_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX1BDLR0_DX1BDLR0_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX1BDLR0_DX1BDLR0_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX1BDLR0_DX1BDLR0_DQ2WBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX1BDLR0_DX1BDLR0_DQ2WBD_M       GENMASK(21, 16)
#define DDR_PHY_DX1BDLR0_DX1BDLR0_DQ2WBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX1BDLR0_DX1BDLR0_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX1BDLR0_DX1BDLR0_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX1BDLR0_DX1BDLR0_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX1BDLR0_DX1BDLR0_DQ3WBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX1BDLR0_DX1BDLR0_DQ3WBD_M       GENMASK(29, 24)
#define DDR_PHY_DX1BDLR0_DX1BDLR0_DQ3WBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX1BDLR0_DX1BDLR0_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX1BDLR0_DX1BDLR0_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX1BDLR0_DX1BDLR0_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1BDLR1 */
#define DDR_PHY_DX1BDLR1(t)       (t + 0x844)

#define DDR_PHY_DX1BDLR1_DX1BDLR1_DQ4WBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX1BDLR1_DX1BDLR1_DQ4WBD_M       GENMASK(5, 0)
#define DDR_PHY_DX1BDLR1_DX1BDLR1_DQ4WBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX1BDLR1_DX1BDLR1_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX1BDLR1_DX1BDLR1_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX1BDLR1_DX1BDLR1_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX1BDLR1_DX1BDLR1_DQ5WBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX1BDLR1_DX1BDLR1_DQ5WBD_M       GENMASK(13, 8)
#define DDR_PHY_DX1BDLR1_DX1BDLR1_DQ5WBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX1BDLR1_DX1BDLR1_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX1BDLR1_DX1BDLR1_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX1BDLR1_DX1BDLR1_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX1BDLR1_DX1BDLR1_DQ6WBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX1BDLR1_DX1BDLR1_DQ6WBD_M       GENMASK(21, 16)
#define DDR_PHY_DX1BDLR1_DX1BDLR1_DQ6WBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX1BDLR1_DX1BDLR1_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX1BDLR1_DX1BDLR1_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX1BDLR1_DX1BDLR1_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX1BDLR1_DX1BDLR1_DQ7WBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX1BDLR1_DX1BDLR1_DQ7WBD_M       GENMASK(29, 24)
#define DDR_PHY_DX1BDLR1_DX1BDLR1_DQ7WBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX1BDLR1_DX1BDLR1_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX1BDLR1_DX1BDLR1_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX1BDLR1_DX1BDLR1_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1BDLR2 */
#define DDR_PHY_DX1BDLR2(t)       (t + 0x848)

#define DDR_PHY_DX1BDLR2_DX1BDLR2_DMWBD(x)       ((x) & GENMASK(5, 0))
#define DDR_PHY_DX1BDLR2_DX1BDLR2_DMWBD_M        GENMASK(5, 0)
#define DDR_PHY_DX1BDLR2_DX1BDLR2_DMWBD_X(x)     ((x) & GENMASK(5, 0))

#define DDR_PHY_DX1BDLR2_DX1BDLR2_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX1BDLR2_DX1BDLR2_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX1BDLR2_DX1BDLR2_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX1BDLR2_DX1BDLR2_DSWBD(x)       (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX1BDLR2_DX1BDLR2_DSWBD_M        GENMASK(13, 8)
#define DDR_PHY_DX1BDLR2_DX1BDLR2_DSWBD_X(x)     (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX1BDLR2_DX1BDLR2_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX1BDLR2_DX1BDLR2_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX1BDLR2_DX1BDLR2_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX1BDLR2_DX1BDLR2_DSOEBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX1BDLR2_DX1BDLR2_DSOEBD_M       GENMASK(21, 16)
#define DDR_PHY_DX1BDLR2_DX1BDLR2_DSOEBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX1BDLR2_DX1BDLR2_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX1BDLR2_DX1BDLR2_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX1BDLR2_DX1BDLR2_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1BDLR3 */
#define DDR_PHY_DX1BDLR3(t)       (t + 0x850)

#define DDR_PHY_DX1BDLR3_DX1BDLR3_DQ0RBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX1BDLR3_DX1BDLR3_DQ0RBD_M       GENMASK(5, 0)
#define DDR_PHY_DX1BDLR3_DX1BDLR3_DQ0RBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX1BDLR3_DX1BDLR3_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX1BDLR3_DX1BDLR3_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX1BDLR3_DX1BDLR3_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX1BDLR3_DX1BDLR3_DQ1RBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX1BDLR3_DX1BDLR3_DQ1RBD_M       GENMASK(13, 8)
#define DDR_PHY_DX1BDLR3_DX1BDLR3_DQ1RBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX1BDLR3_DX1BDLR3_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX1BDLR3_DX1BDLR3_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX1BDLR3_DX1BDLR3_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX1BDLR3_DX1BDLR3_DQ2RBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX1BDLR3_DX1BDLR3_DQ2RBD_M       GENMASK(21, 16)
#define DDR_PHY_DX1BDLR3_DX1BDLR3_DQ2RBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX1BDLR3_DX1BDLR3_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX1BDLR3_DX1BDLR3_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX1BDLR3_DX1BDLR3_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX1BDLR3_DX1BDLR3_DQ3RBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX1BDLR3_DX1BDLR3_DQ3RBD_M       GENMASK(29, 24)
#define DDR_PHY_DX1BDLR3_DX1BDLR3_DQ3RBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX1BDLR3_DX1BDLR3_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX1BDLR3_DX1BDLR3_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX1BDLR3_DX1BDLR3_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1BDLR4 */
#define DDR_PHY_DX1BDLR4(t)       (t + 0x854)

#define DDR_PHY_DX1BDLR4_DX1BDLR4_DQ4RBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX1BDLR4_DX1BDLR4_DQ4RBD_M       GENMASK(5, 0)
#define DDR_PHY_DX1BDLR4_DX1BDLR4_DQ4RBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX1BDLR4_DX1BDLR4_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX1BDLR4_DX1BDLR4_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX1BDLR4_DX1BDLR4_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX1BDLR4_DX1BDLR4_DQ5RBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX1BDLR4_DX1BDLR4_DQ5RBD_M       GENMASK(13, 8)
#define DDR_PHY_DX1BDLR4_DX1BDLR4_DQ5RBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX1BDLR4_DX1BDLR4_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX1BDLR4_DX1BDLR4_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX1BDLR4_DX1BDLR4_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX1BDLR4_DX1BDLR4_DQ6RBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX1BDLR4_DX1BDLR4_DQ6RBD_M       GENMASK(21, 16)
#define DDR_PHY_DX1BDLR4_DX1BDLR4_DQ6RBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX1BDLR4_DX1BDLR4_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX1BDLR4_DX1BDLR4_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX1BDLR4_DX1BDLR4_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX1BDLR4_DX1BDLR4_DQ7RBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX1BDLR4_DX1BDLR4_DQ7RBD_M       GENMASK(29, 24)
#define DDR_PHY_DX1BDLR4_DX1BDLR4_DQ7RBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX1BDLR4_DX1BDLR4_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX1BDLR4_DX1BDLR4_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX1BDLR4_DX1BDLR4_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1BDLR5 */
#define DDR_PHY_DX1BDLR5(t)       (t + 0x858)

#define DDR_PHY_DX1BDLR5_DX1BDLR5_DMRBD(x)       ((x) & GENMASK(5, 0))
#define DDR_PHY_DX1BDLR5_DX1BDLR5_DMRBD_M        GENMASK(5, 0)
#define DDR_PHY_DX1BDLR5_DX1BDLR5_DMRBD_X(x)     ((x) & GENMASK(5, 0))

#define DDR_PHY_DX1BDLR5_DX1BDLR5_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX1BDLR5_DX1BDLR5_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX1BDLR5_DX1BDLR5_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX1BDLR5_DX1BDLR5_DSRBD(x)       (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX1BDLR5_DX1BDLR5_DSRBD_M        GENMASK(13, 8)
#define DDR_PHY_DX1BDLR5_DX1BDLR5_DSRBD_X(x)     (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX1BDLR5_DX1BDLR5_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX1BDLR5_DX1BDLR5_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX1BDLR5_DX1BDLR5_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX1BDLR5_DX1BDLR5_DSNRBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX1BDLR5_DX1BDLR5_DSNRBD_M       GENMASK(21, 16)
#define DDR_PHY_DX1BDLR5_DX1BDLR5_DSNRBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX1BDLR5_DX1BDLR5_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX1BDLR5_DX1BDLR5_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX1BDLR5_DX1BDLR5_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1BDLR6 */
#define DDR_PHY_DX1BDLR6(t)       (t + 0x860)

#define DDR_PHY_DX1BDLR6_DX1BDLR6_RESERVED_7_0(x) ((x) & GENMASK(7, 0))
#define DDR_PHY_DX1BDLR6_DX1BDLR6_RESERVED_7_0_M GENMASK(7, 0)
#define DDR_PHY_DX1BDLR6_DX1BDLR6_RESERVED_7_0_X(x) ((x) & GENMASK(7, 0))

#define DDR_PHY_DX1BDLR6_DX1BDLR6_PDRBD(x)       (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX1BDLR6_DX1BDLR6_PDRBD_M        GENMASK(13, 8)
#define DDR_PHY_DX1BDLR6_DX1BDLR6_PDRBD_X(x)     (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX1BDLR6_DX1BDLR6_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX1BDLR6_DX1BDLR6_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX1BDLR6_DX1BDLR6_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX1BDLR6_DX1BDLR6_TERBD(x)       (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX1BDLR6_DX1BDLR6_TERBD_M        GENMASK(21, 16)
#define DDR_PHY_DX1BDLR6_DX1BDLR6_TERBD_X(x)     (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX1BDLR6_DX1BDLR6_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX1BDLR6_DX1BDLR6_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX1BDLR6_DX1BDLR6_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1BDLR7 */
#define DDR_PHY_DX1BDLR7(t)       (t + 0x864)

#define DDR_PHY_DX1BDLR7_DX1BDLR7_X4DMWBD(x)     ((x) & GENMASK(5, 0))
#define DDR_PHY_DX1BDLR7_DX1BDLR7_X4DMWBD_M      GENMASK(5, 0)
#define DDR_PHY_DX1BDLR7_DX1BDLR7_X4DMWBD_X(x)   ((x) & GENMASK(5, 0))

#define DDR_PHY_DX1BDLR7_DX1BDLR7_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX1BDLR7_DX1BDLR7_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX1BDLR7_DX1BDLR7_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX1BDLR7_DX1BDLR7_X4DSWBD(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX1BDLR7_DX1BDLR7_X4DSWBD_M      GENMASK(13, 8)
#define DDR_PHY_DX1BDLR7_DX1BDLR7_X4DSWBD_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX1BDLR7_DX1BDLR7_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX1BDLR7_DX1BDLR7_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX1BDLR7_DX1BDLR7_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX1BDLR7_DX1BDLR7_X4DSOEBD(x)    (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX1BDLR7_DX1BDLR7_X4DSOEBD_M     GENMASK(21, 16)
#define DDR_PHY_DX1BDLR7_DX1BDLR7_X4DSOEBD_X(x)  (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX1BDLR7_DX1BDLR7_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX1BDLR7_DX1BDLR7_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX1BDLR7_DX1BDLR7_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1BDLR8 */
#define DDR_PHY_DX1BDLR8(t)       (t + 0x868)

#define DDR_PHY_DX1BDLR8_DX1BDLR8_X4DMRBD(x)     ((x) & GENMASK(5, 0))
#define DDR_PHY_DX1BDLR8_DX1BDLR8_X4DMRBD_M      GENMASK(5, 0)
#define DDR_PHY_DX1BDLR8_DX1BDLR8_X4DMRBD_X(x)   ((x) & GENMASK(5, 0))

#define DDR_PHY_DX1BDLR8_DX1BDLR8_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX1BDLR8_DX1BDLR8_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX1BDLR8_DX1BDLR8_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX1BDLR8_DX1BDLR8_X4DSRBD(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX1BDLR8_DX1BDLR8_X4DSRBD_M      GENMASK(13, 8)
#define DDR_PHY_DX1BDLR8_DX1BDLR8_X4DSRBD_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX1BDLR8_DX1BDLR8_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX1BDLR8_DX1BDLR8_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX1BDLR8_DX1BDLR8_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX1BDLR8_DX1BDLR8_X4DSNRBD(x)    (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX1BDLR8_DX1BDLR8_X4DSNRBD_M     GENMASK(21, 16)
#define DDR_PHY_DX1BDLR8_DX1BDLR8_X4DSNRBD_X(x)  (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX1BDLR8_DX1BDLR8_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX1BDLR8_DX1BDLR8_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX1BDLR8_DX1BDLR8_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1BDLR9 */
#define DDR_PHY_DX1BDLR9(t)       (t + 0x86c)

#define DDR_PHY_DX1BDLR9_DX1BDLR9_RESERVED_7_0(x) ((x) & GENMASK(7, 0))
#define DDR_PHY_DX1BDLR9_DX1BDLR9_RESERVED_7_0_M GENMASK(7, 0)
#define DDR_PHY_DX1BDLR9_DX1BDLR9_RESERVED_7_0_X(x) ((x) & GENMASK(7, 0))

#define DDR_PHY_DX1BDLR9_DX1BDLR9_X4PDRBD(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX1BDLR9_DX1BDLR9_X4PDRBD_M      GENMASK(13, 8)
#define DDR_PHY_DX1BDLR9_DX1BDLR9_X4PDRBD_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX1BDLR9_DX1BDLR9_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX1BDLR9_DX1BDLR9_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX1BDLR9_DX1BDLR9_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX1BDLR9_DX1BDLR9_X4TERBD(x)     (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX1BDLR9_DX1BDLR9_X4TERBD_M      GENMASK(21, 16)
#define DDR_PHY_DX1BDLR9_DX1BDLR9_X4TERBD_X(x)   (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX1BDLR9_DX1BDLR9_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX1BDLR9_DX1BDLR9_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX1BDLR9_DX1BDLR9_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1LCDLR0 */
#define DDR_PHY_DX1LCDLR0(t)      (t + 0x880)

#define DDR_PHY_DX1LCDLR0_DX1LCDLR0_WLD(x)       ((x) & GENMASK(8, 0))
#define DDR_PHY_DX1LCDLR0_DX1LCDLR0_WLD_M        GENMASK(8, 0)
#define DDR_PHY_DX1LCDLR0_DX1LCDLR0_WLD_X(x)     ((x) & GENMASK(8, 0))

#define DDR_PHY_DX1LCDLR0_DX1LCDLR0_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX1LCDLR0_DX1LCDLR0_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX1LCDLR0_DX1LCDLR0_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX1LCDLR0_DX1LCDLR0_X4WLD(x)     (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX1LCDLR0_DX1LCDLR0_X4WLD_M      GENMASK(24, 16)
#define DDR_PHY_DX1LCDLR0_DX1LCDLR0_X4WLD_X(x)   (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX1LCDLR0_DX1LCDLR0_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX1LCDLR0_DX1LCDLR0_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX1LCDLR0_DX1LCDLR0_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1LCDLR1 */
#define DDR_PHY_DX1LCDLR1(t)      (t + 0x884)

#define DDR_PHY_DX1LCDLR1_DX1LCDLR1_WDQD(x)      ((x) & GENMASK(8, 0))
#define DDR_PHY_DX1LCDLR1_DX1LCDLR1_WDQD_M       GENMASK(8, 0)
#define DDR_PHY_DX1LCDLR1_DX1LCDLR1_WDQD_X(x)    ((x) & GENMASK(8, 0))

#define DDR_PHY_DX1LCDLR1_DX1LCDLR1_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX1LCDLR1_DX1LCDLR1_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX1LCDLR1_DX1LCDLR1_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX1LCDLR1_DX1LCDLR1_X4WDQD(x)    (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX1LCDLR1_DX1LCDLR1_X4WDQD_M     GENMASK(24, 16)
#define DDR_PHY_DX1LCDLR1_DX1LCDLR1_X4WDQD_X(x)  (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX1LCDLR1_DX1LCDLR1_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX1LCDLR1_DX1LCDLR1_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX1LCDLR1_DX1LCDLR1_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1LCDLR2 */
#define DDR_PHY_DX1LCDLR2(t)      (t + 0x888)

#define DDR_PHY_DX1LCDLR2_DX1LCDLR2_DQSGD(x)     ((x) & GENMASK(8, 0))
#define DDR_PHY_DX1LCDLR2_DX1LCDLR2_DQSGD_M      GENMASK(8, 0)
#define DDR_PHY_DX1LCDLR2_DX1LCDLR2_DQSGD_X(x)   ((x) & GENMASK(8, 0))

#define DDR_PHY_DX1LCDLR2_DX1LCDLR2_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX1LCDLR2_DX1LCDLR2_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX1LCDLR2_DX1LCDLR2_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX1LCDLR2_DX1LCDLR2_X4DQSGD(x)   (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX1LCDLR2_DX1LCDLR2_X4DQSGD_M    GENMASK(24, 16)
#define DDR_PHY_DX1LCDLR2_DX1LCDLR2_X4DQSGD_X(x) (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX1LCDLR2_DX1LCDLR2_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX1LCDLR2_DX1LCDLR2_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX1LCDLR2_DX1LCDLR2_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1LCDLR3 */
#define DDR_PHY_DX1LCDLR3(t)      (t + 0x88c)

#define DDR_PHY_DX1LCDLR3_DX1LCDLR3_RDQSD(x)     ((x) & GENMASK(8, 0))
#define DDR_PHY_DX1LCDLR3_DX1LCDLR3_RDQSD_M      GENMASK(8, 0)
#define DDR_PHY_DX1LCDLR3_DX1LCDLR3_RDQSD_X(x)   ((x) & GENMASK(8, 0))

#define DDR_PHY_DX1LCDLR3_DX1LCDLR3_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX1LCDLR3_DX1LCDLR3_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX1LCDLR3_DX1LCDLR3_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX1LCDLR3_DX1LCDLR3_X4RDQSD(x)   (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX1LCDLR3_DX1LCDLR3_X4RDQSD_M    GENMASK(24, 16)
#define DDR_PHY_DX1LCDLR3_DX1LCDLR3_X4RDQSD_X(x) (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX1LCDLR3_DX1LCDLR3_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX1LCDLR3_DX1LCDLR3_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX1LCDLR3_DX1LCDLR3_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1LCDLR4 */
#define DDR_PHY_DX1LCDLR4(t)      (t + 0x890)

#define DDR_PHY_DX1LCDLR4_DX1LCDLR4_RDQSND(x)    ((x) & GENMASK(8, 0))
#define DDR_PHY_DX1LCDLR4_DX1LCDLR4_RDQSND_M     GENMASK(8, 0)
#define DDR_PHY_DX1LCDLR4_DX1LCDLR4_RDQSND_X(x)  ((x) & GENMASK(8, 0))

#define DDR_PHY_DX1LCDLR4_DX1LCDLR4_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX1LCDLR4_DX1LCDLR4_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX1LCDLR4_DX1LCDLR4_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX1LCDLR4_DX1LCDLR4_X4RDQSND(x)  (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX1LCDLR4_DX1LCDLR4_X4RDQSND_M   GENMASK(24, 16)
#define DDR_PHY_DX1LCDLR4_DX1LCDLR4_X4RDQSND_X(x)\
	(((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX1LCDLR4_DX1LCDLR4_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX1LCDLR4_DX1LCDLR4_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX1LCDLR4_DX1LCDLR4_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1LCDLR5 */
#define DDR_PHY_DX1LCDLR5(t)      (t + 0x894)

#define DDR_PHY_DX1LCDLR5_DX1LCDLR5_DQSGSD(x)    ((x) & GENMASK(8, 0))
#define DDR_PHY_DX1LCDLR5_DX1LCDLR5_DQSGSD_M     GENMASK(8, 0)
#define DDR_PHY_DX1LCDLR5_DX1LCDLR5_DQSGSD_X(x)  ((x) & GENMASK(8, 0))

#define DDR_PHY_DX1LCDLR5_DX1LCDLR5_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX1LCDLR5_DX1LCDLR5_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX1LCDLR5_DX1LCDLR5_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX1LCDLR5_DX1LCDLR5_X4DQSGSD(x)  (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX1LCDLR5_DX1LCDLR5_X4DQSGSD_M   GENMASK(24, 16)
#define DDR_PHY_DX1LCDLR5_DX1LCDLR5_X4DQSGSD_X(x)\
	(((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX1LCDLR5_DX1LCDLR5_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX1LCDLR5_DX1LCDLR5_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX1LCDLR5_DX1LCDLR5_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1MDLR0 */
#define DDR_PHY_DX1MDLR0(t)       (t + 0x8a0)

#define DDR_PHY_DX1MDLR0_DX1MDLR0_IPRD(x)        ((x) & GENMASK(8, 0))
#define DDR_PHY_DX1MDLR0_DX1MDLR0_IPRD_M         GENMASK(8, 0)
#define DDR_PHY_DX1MDLR0_DX1MDLR0_IPRD_X(x)      ((x) & GENMASK(8, 0))

#define DDR_PHY_DX1MDLR0_DX1MDLR0_RESERVED_15_9(x) (((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX1MDLR0_DX1MDLR0_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX1MDLR0_DX1MDLR0_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX1MDLR0_DX1MDLR0_TPRD(x)        (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX1MDLR0_DX1MDLR0_TPRD_M         GENMASK(24, 16)
#define DDR_PHY_DX1MDLR0_DX1MDLR0_TPRD_X(x)      (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX1MDLR0_DX1MDLR0_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX1MDLR0_DX1MDLR0_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX1MDLR0_DX1MDLR0_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1MDLR1 */
#define DDR_PHY_DX1MDLR1(t)       (t + 0x8a4)

#define DDR_PHY_DX1MDLR1_DX1MDLR1_MDLD(x)        ((x) & GENMASK(8, 0))
#define DDR_PHY_DX1MDLR1_DX1MDLR1_MDLD_M         GENMASK(8, 0)
#define DDR_PHY_DX1MDLR1_DX1MDLR1_MDLD_X(x)      ((x) & GENMASK(8, 0))

#define DDR_PHY_DX1MDLR1_DX1MDLR1_RESERVED_31_9(x) (((x) << 9) & GENMASK(31, 9))
#define DDR_PHY_DX1MDLR1_DX1MDLR1_RESERVED_31_9_M GENMASK(31, 9)
#define DDR_PHY_DX1MDLR1_DX1MDLR1_RESERVED_31_9_X(x)\
	(((x) & GENMASK(31, 9)) >> 9)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1GTR0 */
#define DDR_PHY_DX1GTR0(t)        (t + 0x8c0)

#define DDR_PHY_DX1GTR0_DX1GTR0_DGSL(x)          ((x) & GENMASK(4, 0))
#define DDR_PHY_DX1GTR0_DX1GTR0_DGSL_M           GENMASK(4, 0)
#define DDR_PHY_DX1GTR0_DX1GTR0_DGSL_X(x)        ((x) & GENMASK(4, 0))

#define DDR_PHY_DX1GTR0_DX1GTR0_RESERVED_7_5(x)  (((x) << 5) & GENMASK(7, 5))
#define DDR_PHY_DX1GTR0_DX1GTR0_RESERVED_7_5_M   GENMASK(7, 5)
#define DDR_PHY_DX1GTR0_DX1GTR0_RESERVED_7_5_X(x) (((x) & GENMASK(7, 5)) >> 5)

#define DDR_PHY_DX1GTR0_DX1GTR0_X4DGSL(x)        (((x) << 8) & GENMASK(12, 8))
#define DDR_PHY_DX1GTR0_DX1GTR0_X4DGSL_M         GENMASK(12, 8)
#define DDR_PHY_DX1GTR0_DX1GTR0_X4DGSL_X(x)      (((x) & GENMASK(12, 8)) >> 8)

#define DDR_PHY_DX1GTR0_DX1GTR0_RESERVED_15_13(x)\
	(((x) << 13) & GENMASK(15, 13))
#define DDR_PHY_DX1GTR0_DX1GTR0_RESERVED_15_13_M GENMASK(15, 13)
#define DDR_PHY_DX1GTR0_DX1GTR0_RESERVED_15_13_X(x)\
	(((x) & GENMASK(15, 13)) >> 13)

#define DDR_PHY_DX1GTR0_DX1GTR0_WLSL(x)          (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DX1GTR0_DX1GTR0_WLSL_M           GENMASK(19, 16)
#define DDR_PHY_DX1GTR0_DX1GTR0_WLSL_X(x)        (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DX1GTR0_DX1GTR0_X4WLSL(x)        (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX1GTR0_DX1GTR0_X4WLSL_M         GENMASK(23, 20)
#define DDR_PHY_DX1GTR0_DX1GTR0_X4WLSL_X(x)      (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX1GTR0_DX1GTR0_RESERVED_31_24(x)\
	(((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_DX1GTR0_DX1GTR0_RESERVED_31_24_M GENMASK(31, 24)
#define DDR_PHY_DX1GTR0_DX1GTR0_RESERVED_31_24_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1RSR0 */
#define DDR_PHY_DX1RSR0(t)        (t + 0x8d0)

#define DDR_PHY_DX1RSR0_DX1RSR0_QSGERR(x)        ((x) & GENMASK(15, 0))
#define DDR_PHY_DX1RSR0_DX1RSR0_QSGERR_M         GENMASK(15, 0)
#define DDR_PHY_DX1RSR0_DX1RSR0_QSGERR_X(x)      ((x) & GENMASK(15, 0))

#define DDR_PHY_DX1RSR0_DX1RSR0_X4QSGERR(x)      (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX1RSR0_DX1RSR0_X4QSGERR_M       GENMASK(31, 16)
#define DDR_PHY_DX1RSR0_DX1RSR0_X4QSGERR_X(x)    (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1RSR1 */
#define DDR_PHY_DX1RSR1(t)        (t + 0x8d4)

#define DDR_PHY_DX1RSR1_DX1RSR1_RDLVLERR(x)      ((x) & GENMASK(15, 0))
#define DDR_PHY_DX1RSR1_DX1RSR1_RDLVLERR_M       GENMASK(15, 0)
#define DDR_PHY_DX1RSR1_DX1RSR1_RDLVLERR_X(x)    ((x) & GENMASK(15, 0))

#define DDR_PHY_DX1RSR1_DX1RSR1_X4RDLVLERR(x)    (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX1RSR1_DX1RSR1_X4RDLVLERR_M     GENMASK(31, 16)
#define DDR_PHY_DX1RSR1_DX1RSR1_X4RDLVLERR_X(x)  (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1RSR2 */
#define DDR_PHY_DX1RSR2(t)        (t + 0x8d8)

#define DDR_PHY_DX1RSR2_DX1RSR2_WLAWN(x)         ((x) & GENMASK(15, 0))
#define DDR_PHY_DX1RSR2_DX1RSR2_WLAWN_M          GENMASK(15, 0)
#define DDR_PHY_DX1RSR2_DX1RSR2_WLAWN_X(x)       ((x) & GENMASK(15, 0))

#define DDR_PHY_DX1RSR2_DX1RSR2_X4WLAWN(x)       (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX1RSR2_DX1RSR2_X4WLAWN_M        GENMASK(31, 16)
#define DDR_PHY_DX1RSR2_DX1RSR2_X4WLAWN_X(x)     (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1RSR3 */
#define DDR_PHY_DX1RSR3(t)        (t + 0x8dc)

#define DDR_PHY_DX1RSR3_DX1RSR3_WLAERR(x)        ((x) & GENMASK(15, 0))
#define DDR_PHY_DX1RSR3_DX1RSR3_WLAERR_M         GENMASK(15, 0)
#define DDR_PHY_DX1RSR3_DX1RSR3_WLAERR_X(x)      ((x) & GENMASK(15, 0))

#define DDR_PHY_DX1RSR3_DX1RSR3_X4WLAERR(x)      (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX1RSR3_DX1RSR3_X4WLAERR_M       GENMASK(31, 16)
#define DDR_PHY_DX1RSR3_DX1RSR3_X4WLAERR_X(x)    (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1GSR0 */
#define DDR_PHY_DX1GSR0(t)        (t + 0x8e0)

#define DDR_PHY_DX1GSR0_DX1GSR0_WDQCAL(x)        ((x) & GENMASK(0, 0))
#define DDR_PHY_DX1GSR0_DX1GSR0_WDQCAL_M         GENMASK(0, 0)
#define DDR_PHY_DX1GSR0_DX1GSR0_WDQCAL_X(x)      ((x) & GENMASK(0, 0))

#define DDR_PHY_DX1GSR0_DX1GSR0_RDQSCAL(x)       (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX1GSR0_DX1GSR0_RDQSCAL_M        GENMASK(1, 1)
#define DDR_PHY_DX1GSR0_DX1GSR0_RDQSCAL_X(x)     (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX1GSR0_DX1GSR0_RDQSNCAL(x)      (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX1GSR0_DX1GSR0_RDQSNCAL_M       GENMASK(2, 2)
#define DDR_PHY_DX1GSR0_DX1GSR0_RDQSNCAL_X(x)    (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX1GSR0_DX1GSR0_GDQSCAL(x)       (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX1GSR0_DX1GSR0_GDQSCAL_M        GENMASK(3, 3)
#define DDR_PHY_DX1GSR0_DX1GSR0_GDQSCAL_X(x)     (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX1GSR0_DX1GSR0_WLCAL(x)         (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX1GSR0_DX1GSR0_WLCAL_M          GENMASK(4, 4)
#define DDR_PHY_DX1GSR0_DX1GSR0_WLCAL_X(x)       (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX1GSR0_DX1GSR0_WLDONE(x)        (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX1GSR0_DX1GSR0_WLDONE_M         GENMASK(5, 5)
#define DDR_PHY_DX1GSR0_DX1GSR0_WLDONE_X(x)      (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX1GSR0_DX1GSR0_WLERR(x)         (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX1GSR0_DX1GSR0_WLERR_M          GENMASK(6, 6)
#define DDR_PHY_DX1GSR0_DX1GSR0_WLERR_X(x)       (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX1GSR0_DX1GSR0_WLPRD(x)         (((x) << 7) & GENMASK(15, 7))
#define DDR_PHY_DX1GSR0_DX1GSR0_WLPRD_M          GENMASK(15, 7)
#define DDR_PHY_DX1GSR0_DX1GSR0_WLPRD_X(x)       (((x) & GENMASK(15, 7)) >> 7)

#define DDR_PHY_DX1GSR0_DX1GSR0_DPLOCK(x)        (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX1GSR0_DX1GSR0_DPLOCK_M         GENMASK(16, 16)
#define DDR_PHY_DX1GSR0_DX1GSR0_DPLOCK_X(x)      (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX1GSR0_DX1GSR0_GDQSPRD(x)       (((x) << 17) & GENMASK(25, 17))
#define DDR_PHY_DX1GSR0_DX1GSR0_GDQSPRD_M        GENMASK(25, 17)
#define DDR_PHY_DX1GSR0_DX1GSR0_GDQSPRD_X(x)     (((x) & GENMASK(25, 17)) >> 17)

#define DDR_PHY_DX1GSR0_DX1GSR0_WLWN(x)          (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_DX1GSR0_DX1GSR0_WLWN_M           GENMASK(26, 26)
#define DDR_PHY_DX1GSR0_DX1GSR0_WLWN_X(x)        (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_DX1GSR0_DX1GSR0_RESERVED_29_27(x)\
	(((x) << 27) & GENMASK(29, 27))
#define DDR_PHY_DX1GSR0_DX1GSR0_RESERVED_29_27_M GENMASK(29, 27)
#define DDR_PHY_DX1GSR0_DX1GSR0_RESERVED_29_27_X(x)\
	(((x) & GENMASK(29, 27)) >> 27)

#define DDR_PHY_DX1GSR0_DX1GSR0_WLDQ(x)          (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX1GSR0_DX1GSR0_WLDQ_M           GENMASK(30, 30)
#define DDR_PHY_DX1GSR0_DX1GSR0_WLDQ_X(x)        (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX1GSR0_DX1GSR0_RESERVED_31(x)   (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX1GSR0_DX1GSR0_RESERVED_31_M    GENMASK(31, 31)
#define DDR_PHY_DX1GSR0_DX1GSR0_RESERVED_31_X(x) (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1GSR1 */
#define DDR_PHY_DX1GSR1(t)        (t + 0x8e4)

#define DDR_PHY_DX1GSR1_DX1GSR1_DLTDONE(x)       ((x) & GENMASK(0, 0))
#define DDR_PHY_DX1GSR1_DX1GSR1_DLTDONE_M        GENMASK(0, 0)
#define DDR_PHY_DX1GSR1_DX1GSR1_DLTDONE_X(x)     ((x) & GENMASK(0, 0))

#define DDR_PHY_DX1GSR1_DX1GSR1_DLTCODE(x)       (((x) << 1) & GENMASK(24, 1))
#define DDR_PHY_DX1GSR1_DX1GSR1_DLTCODE_M        GENMASK(24, 1)
#define DDR_PHY_DX1GSR1_DX1GSR1_DLTCODE_X(x)     (((x) & GENMASK(24, 1)) >> 1)

#define DDR_PHY_DX1GSR1_DX1GSR1_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX1GSR1_DX1GSR1_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX1GSR1_DX1GSR1_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1GSR2 */
#define DDR_PHY_DX1GSR2(t)        (t + 0x8e8)

#define DDR_PHY_DX1GSR2_DX1GSR2_RDERR(x)         ((x) & GENMASK(0, 0))
#define DDR_PHY_DX1GSR2_DX1GSR2_RDERR_M          GENMASK(0, 0)
#define DDR_PHY_DX1GSR2_DX1GSR2_RDERR_X(x)       ((x) & GENMASK(0, 0))

#define DDR_PHY_DX1GSR2_DX1GSR2_RDWN(x)          (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX1GSR2_DX1GSR2_RDWN_M           GENMASK(1, 1)
#define DDR_PHY_DX1GSR2_DX1GSR2_RDWN_X(x)        (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX1GSR2_DX1GSR2_WDERR(x)         (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX1GSR2_DX1GSR2_WDERR_M          GENMASK(2, 2)
#define DDR_PHY_DX1GSR2_DX1GSR2_WDERR_X(x)       (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX1GSR2_DX1GSR2_WDWN(x)          (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX1GSR2_DX1GSR2_WDWN_M           GENMASK(3, 3)
#define DDR_PHY_DX1GSR2_DX1GSR2_WDWN_X(x)        (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX1GSR2_DX1GSR2_REERR(x)         (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX1GSR2_DX1GSR2_REERR_M          GENMASK(4, 4)
#define DDR_PHY_DX1GSR2_DX1GSR2_REERR_X(x)       (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX1GSR2_DX1GSR2_REWN(x)          (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX1GSR2_DX1GSR2_REWN_M           GENMASK(5, 5)
#define DDR_PHY_DX1GSR2_DX1GSR2_REWN_X(x)        (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX1GSR2_DX1GSR2_WEERR(x)         (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX1GSR2_DX1GSR2_WEERR_M          GENMASK(6, 6)
#define DDR_PHY_DX1GSR2_DX1GSR2_WEERR_X(x)       (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX1GSR2_DX1GSR2_WEWN(x)          (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_DX1GSR2_DX1GSR2_WEWN_M           GENMASK(7, 7)
#define DDR_PHY_DX1GSR2_DX1GSR2_WEWN_X(x)        (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_DX1GSR2_DX1GSR2_ESTAT(x)         (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX1GSR2_DX1GSR2_ESTAT_M          GENMASK(11, 8)
#define DDR_PHY_DX1GSR2_DX1GSR2_ESTAT_X(x)       (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX1GSR2_DX1GSR2_DBDQ(x)          (((x) << 12) & GENMASK(19, 12))
#define DDR_PHY_DX1GSR2_DX1GSR2_DBDQ_M           GENMASK(19, 12)
#define DDR_PHY_DX1GSR2_DX1GSR2_DBDQ_X(x)        (((x) & GENMASK(19, 12)) >> 12)

#define DDR_PHY_DX1GSR2_DX1GSR2_SRDERR(x)        (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX1GSR2_DX1GSR2_SRDERR_M         GENMASK(20, 20)
#define DDR_PHY_DX1GSR2_DX1GSR2_SRDERR_X(x)      (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX1GSR2_DX1GSR2_RESERVED_21(x)   (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX1GSR2_DX1GSR2_RESERVED_21_M    GENMASK(21, 21)
#define DDR_PHY_DX1GSR2_DX1GSR2_RESERVED_21_X(x) (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX1GSR2_DX1GSR2_GSDQSCAL(x)      (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX1GSR2_DX1GSR2_GSDQSCAL_M       GENMASK(22, 22)
#define DDR_PHY_DX1GSR2_DX1GSR2_GSDQSCAL_X(x)    (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX1GSR2_DX1GSR2_GSDQSPRD(x)      (((x) << 23) & GENMASK(31, 23))
#define DDR_PHY_DX1GSR2_DX1GSR2_GSDQSPRD_M       GENMASK(31, 23)
#define DDR_PHY_DX1GSR2_DX1GSR2_GSDQSPRD_X(x)    (((x) & GENMASK(31, 23)) >> 23)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1GSR3 */
#define DDR_PHY_DX1GSR3(t)        (t + 0x8ec)

#define DDR_PHY_DX1GSR3_DX1GSR3_SRDPC(x)         ((x) & GENMASK(1, 0))
#define DDR_PHY_DX1GSR3_DX1GSR3_SRDPC_M          GENMASK(1, 0)
#define DDR_PHY_DX1GSR3_DX1GSR3_SRDPC_X(x)       ((x) & GENMASK(1, 0))

#define DDR_PHY_DX1GSR3_DX1GSR3_RESERVED_7_2(x)  (((x) << 2) & GENMASK(7, 2))
#define DDR_PHY_DX1GSR3_DX1GSR3_RESERVED_7_2_M   GENMASK(7, 2)
#define DDR_PHY_DX1GSR3_DX1GSR3_RESERVED_7_2_X(x) (((x) & GENMASK(7, 2)) >> 2)

#define DDR_PHY_DX1GSR3_DX1GSR3_HVERR(x)         (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX1GSR3_DX1GSR3_HVERR_M          GENMASK(11, 8)
#define DDR_PHY_DX1GSR3_DX1GSR3_HVERR_X(x)       (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX1GSR3_DX1GSR3_HVWRN(x)         (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_DX1GSR3_DX1GSR3_HVWRN_M          GENMASK(15, 12)
#define DDR_PHY_DX1GSR3_DX1GSR3_HVWRN_X(x)       (((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_DX1GSR3_DX1GSR3_DVERR(x)         (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DX1GSR3_DX1GSR3_DVERR_M          GENMASK(19, 16)
#define DDR_PHY_DX1GSR3_DX1GSR3_DVERR_X(x)       (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DX1GSR3_DX1GSR3_DVWRN(x)         (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX1GSR3_DX1GSR3_DVWRN_M          GENMASK(23, 20)
#define DDR_PHY_DX1GSR3_DX1GSR3_DVWRN_X(x)       (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX1GSR3_DX1GSR3_ESTAT(x)         (((x) << 24) & GENMASK(26, 24))
#define DDR_PHY_DX1GSR3_DX1GSR3_ESTAT_M          GENMASK(26, 24)
#define DDR_PHY_DX1GSR3_DX1GSR3_ESTAT_X(x)       (((x) & GENMASK(26, 24)) >> 24)

#define DDR_PHY_DX1GSR3_DX1GSR3_RESERVED_31_27(x)\
	(((x) << 27) & GENMASK(31, 27))
#define DDR_PHY_DX1GSR3_DX1GSR3_RESERVED_31_27_M GENMASK(31, 27)
#define DDR_PHY_DX1GSR3_DX1GSR3_RESERVED_31_27_X(x)\
	(((x) & GENMASK(31, 27)) >> 27)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1GSR4 */
#define DDR_PHY_DX1GSR4(t)        (t + 0x8f0)

#define DDR_PHY_DX1GSR4_DX1GSR4_X4WDQCAL(x)      ((x) & GENMASK(0, 0))
#define DDR_PHY_DX1GSR4_DX1GSR4_X4WDQCAL_M       GENMASK(0, 0)
#define DDR_PHY_DX1GSR4_DX1GSR4_X4WDQCAL_X(x)    ((x) & GENMASK(0, 0))

#define DDR_PHY_DX1GSR4_DX1GSR4_X4RDQSCAL(x)     (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX1GSR4_DX1GSR4_X4RDQSCAL_M      GENMASK(1, 1)
#define DDR_PHY_DX1GSR4_DX1GSR4_X4RDQSCAL_X(x)   (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX1GSR4_DX1GSR4_X4RDQSNCAL(x)    (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX1GSR4_DX1GSR4_X4RDQSNCAL_M     GENMASK(2, 2)
#define DDR_PHY_DX1GSR4_DX1GSR4_X4RDQSNCAL_X(x)  (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX1GSR4_DX1GSR4_X4GDQSCAL(x)     (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX1GSR4_DX1GSR4_X4GDQSCAL_M      GENMASK(3, 3)
#define DDR_PHY_DX1GSR4_DX1GSR4_X4GDQSCAL_X(x)   (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX1GSR4_DX1GSR4_X4WLCAL(x)       (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX1GSR4_DX1GSR4_X4WLCAL_M        GENMASK(4, 4)
#define DDR_PHY_DX1GSR4_DX1GSR4_X4WLCAL_X(x)     (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX1GSR4_DX1GSR4_X4WLDONE(x)      (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX1GSR4_DX1GSR4_X4WLDONE_M       GENMASK(5, 5)
#define DDR_PHY_DX1GSR4_DX1GSR4_X4WLDONE_X(x)    (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX1GSR4_DX1GSR4_X4WLERR(x)       (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX1GSR4_DX1GSR4_X4WLERR_M        GENMASK(6, 6)
#define DDR_PHY_DX1GSR4_DX1GSR4_X4WLERR_X(x)     (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX1GSR4_DX1GSR4_X4WLPRD(x)       (((x) << 7) & GENMASK(15, 7))
#define DDR_PHY_DX1GSR4_DX1GSR4_X4WLPRD_M        GENMASK(15, 7)
#define DDR_PHY_DX1GSR4_DX1GSR4_X4WLPRD_X(x)     (((x) & GENMASK(15, 7)) >> 7)

#define DDR_PHY_DX1GSR4_DX1GSR4_X4DPLOCK(x)      (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX1GSR4_DX1GSR4_X4DPLOCK_M       GENMASK(16, 16)
#define DDR_PHY_DX1GSR4_DX1GSR4_X4DPLOCK_X(x)    (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX1GSR4_DX1GSR4_X4GDQSPRD(x)     (((x) << 17) & GENMASK(25, 17))
#define DDR_PHY_DX1GSR4_DX1GSR4_X4GDQSPRD_M      GENMASK(25, 17)
#define DDR_PHY_DX1GSR4_DX1GSR4_X4GDQSPRD_X(x)   (((x) & GENMASK(25, 17)) >> 17)

#define DDR_PHY_DX1GSR4_DX1GSR4_X4WLWN(x)        (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_DX1GSR4_DX1GSR4_X4WLWN_M         GENMASK(26, 26)
#define DDR_PHY_DX1GSR4_DX1GSR4_X4WLWN_X(x)      (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_DX1GSR4_DX1GSR4_RESERVED_29_27(x)\
	(((x) << 27) & GENMASK(29, 27))
#define DDR_PHY_DX1GSR4_DX1GSR4_RESERVED_29_27_M GENMASK(29, 27)
#define DDR_PHY_DX1GSR4_DX1GSR4_RESERVED_29_27_X(x)\
	(((x) & GENMASK(29, 27)) >> 27)

#define DDR_PHY_DX1GSR4_DX1GSR4_X4WLDQ(x)        (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX1GSR4_DX1GSR4_X4WLDQ_M         GENMASK(30, 30)
#define DDR_PHY_DX1GSR4_DX1GSR4_X4WLDQ_X(x)      (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX1GSR4_DX1GSR4_RESERVED_31(x)   (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX1GSR4_DX1GSR4_RESERVED_31_M    GENMASK(31, 31)
#define DDR_PHY_DX1GSR4_DX1GSR4_RESERVED_31_X(x) (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1GSR5 */
#define DDR_PHY_DX1GSR5(t)        (t + 0x8f4)

#define DDR_PHY_DX1GSR5_DX1GSR5_X4RDERR(x)       ((x) & GENMASK(0, 0))
#define DDR_PHY_DX1GSR5_DX1GSR5_X4RDERR_M        GENMASK(0, 0)
#define DDR_PHY_DX1GSR5_DX1GSR5_X4RDERR_X(x)     ((x) & GENMASK(0, 0))

#define DDR_PHY_DX1GSR5_DX1GSR5_X4RDWN(x)        (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX1GSR5_DX1GSR5_X4RDWN_M         GENMASK(1, 1)
#define DDR_PHY_DX1GSR5_DX1GSR5_X4RDWN_X(x)      (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX1GSR5_DX1GSR5_X4WDERR(x)       (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX1GSR5_DX1GSR5_X4WDERR_M        GENMASK(2, 2)
#define DDR_PHY_DX1GSR5_DX1GSR5_X4WDERR_X(x)     (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX1GSR5_DX1GSR5_X4WDWN(x)        (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX1GSR5_DX1GSR5_X4WDWN_M         GENMASK(3, 3)
#define DDR_PHY_DX1GSR5_DX1GSR5_X4WDWN_X(x)      (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX1GSR5_DX1GSR5_X4REERR(x)       (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX1GSR5_DX1GSR5_X4REERR_M        GENMASK(4, 4)
#define DDR_PHY_DX1GSR5_DX1GSR5_X4REERR_X(x)     (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX1GSR5_DX1GSR5_X4REWN(x)        (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX1GSR5_DX1GSR5_X4REWN_M         GENMASK(5, 5)
#define DDR_PHY_DX1GSR5_DX1GSR5_X4REWN_X(x)      (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX1GSR5_DX1GSR5_X4WEERR(x)       (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX1GSR5_DX1GSR5_X4WEERR_M        GENMASK(6, 6)
#define DDR_PHY_DX1GSR5_DX1GSR5_X4WEERR_X(x)     (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX1GSR5_DX1GSR5_X4WEWN(x)        (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_DX1GSR5_DX1GSR5_X4WEWN_M         GENMASK(7, 7)
#define DDR_PHY_DX1GSR5_DX1GSR5_X4WEWN_X(x)      (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_DX1GSR5_DX1GSR5_X4ESTAT(x)       (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX1GSR5_DX1GSR5_X4ESTAT_M        GENMASK(11, 8)
#define DDR_PHY_DX1GSR5_DX1GSR5_X4ESTAT_X(x)     (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX1GSR5_DX1GSR5_RESERVED_19_12(x)\
	(((x) << 12) & GENMASK(19, 12))
#define DDR_PHY_DX1GSR5_DX1GSR5_RESERVED_19_12_M GENMASK(19, 12)
#define DDR_PHY_DX1GSR5_DX1GSR5_RESERVED_19_12_X(x)\
	(((x) & GENMASK(19, 12)) >> 12)

#define DDR_PHY_DX1GSR5_DX1GSR5_X4SRDERR(x)      (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX1GSR5_DX1GSR5_X4SRDERR_M       GENMASK(20, 20)
#define DDR_PHY_DX1GSR5_DX1GSR5_X4SRDERR_X(x)    (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX1GSR5_DX1GSR5_RESERVED_21(x)   (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX1GSR5_DX1GSR5_RESERVED_21_M    GENMASK(21, 21)
#define DDR_PHY_DX1GSR5_DX1GSR5_RESERVED_21_X(x) (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX1GSR5_DX1GSR5_X4GSDQSCAL(x)    (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX1GSR5_DX1GSR5_X4GSDQSCAL_M     GENMASK(22, 22)
#define DDR_PHY_DX1GSR5_DX1GSR5_X4GSDQSCAL_X(x)  (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX1GSR5_DX1GSR5_X4GSDQSPRD(x)    (((x) << 23) & GENMASK(31, 23))
#define DDR_PHY_DX1GSR5_DX1GSR5_X4GSDQSPRD_M     GENMASK(31, 23)
#define DDR_PHY_DX1GSR5_DX1GSR5_X4GSDQSPRD_X(x)  (((x) & GENMASK(31, 23)) >> 23)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX1GSR6 */
#define DDR_PHY_DX1GSR6(t)        (t + 0x8f8)

#define DDR_PHY_DX1GSR6_DX1GSR6_RESERVED_1_0(x)  ((x) & GENMASK(1, 0))
#define DDR_PHY_DX1GSR6_DX1GSR6_RESERVED_1_0_M   GENMASK(1, 0)
#define DDR_PHY_DX1GSR6_DX1GSR6_RESERVED_1_0_X(x) ((x) & GENMASK(1, 0))

#define DDR_PHY_DX1GSR6_DX1GSR6_X4SRDPC(x)       (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DX1GSR6_DX1GSR6_X4SRDPC_M        GENMASK(3, 2)
#define DDR_PHY_DX1GSR6_DX1GSR6_X4SRDPC_X(x)     (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DX1GSR6_DX1GSR6_RESERVED_7_4(x)  (((x) << 4) & GENMASK(7, 4))
#define DDR_PHY_DX1GSR6_DX1GSR6_RESERVED_7_4_M   GENMASK(7, 4)
#define DDR_PHY_DX1GSR6_DX1GSR6_RESERVED_7_4_X(x) (((x) & GENMASK(7, 4)) >> 4)

#define DDR_PHY_DX1GSR6_DX1GSR6_X4HVERR(x)       (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX1GSR6_DX1GSR6_X4HVERR_M        GENMASK(11, 8)
#define DDR_PHY_DX1GSR6_DX1GSR6_X4HVERR_X(x)     (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX1GSR6_DX1GSR6_X4HVWRN(x)       (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_DX1GSR6_DX1GSR6_X4HVWRN_M        GENMASK(15, 12)
#define DDR_PHY_DX1GSR6_DX1GSR6_X4HVWRN_X(x)     (((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_DX1GSR6_DX1GSR6_X4DVERR(x)       (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DX1GSR6_DX1GSR6_X4DVERR_M        GENMASK(19, 16)
#define DDR_PHY_DX1GSR6_DX1GSR6_X4DVERR_X(x)     (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DX1GSR6_DX1GSR6_X4DVWRN(x)       (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX1GSR6_DX1GSR6_X4DVWRN_M        GENMASK(23, 20)
#define DDR_PHY_DX1GSR6_DX1GSR6_X4DVWRN_X(x)     (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX1GSR6_DX1GSR6_RESERVED_31_24(x)\
	(((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_DX1GSR6_DX1GSR6_RESERVED_31_24_M GENMASK(31, 24)
#define DDR_PHY_DX1GSR6_DX1GSR6_RESERVED_31_24_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2GCR0 */
#define DDR_PHY_DX2GCR0(t)        (t + 0x900)

#define DDR_PHY_DX2GCR0_DX2GCR0_DXEN(x)          ((x) & GENMASK(0, 0))
#define DDR_PHY_DX2GCR0_DX2GCR0_DXEN_M           GENMASK(0, 0)
#define DDR_PHY_DX2GCR0_DX2GCR0_DXEN_X(x)        ((x) & GENMASK(0, 0))

#define DDR_PHY_DX2GCR0_DX2GCR0_DXIOM(x)         (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX2GCR0_DX2GCR0_DXIOM_M          GENMASK(1, 1)
#define DDR_PHY_DX2GCR0_DX2GCR0_DXIOM_X(x)       (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX2GCR0_DX2GCR0_DQSGOE(x)        (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX2GCR0_DX2GCR0_DQSGOE_M         GENMASK(2, 2)
#define DDR_PHY_DX2GCR0_DX2GCR0_DQSGOE_X(x)      (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX2GCR0_DX2GCR0_DQSGODT(x)       (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX2GCR0_DX2GCR0_DQSGODT_M        GENMASK(3, 3)
#define DDR_PHY_DX2GCR0_DX2GCR0_DQSGODT_X(x)     (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX2GCR0_DX2GCR0_RESERVED_4(x)    (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX2GCR0_DX2GCR0_RESERVED_4_M     GENMASK(4, 4)
#define DDR_PHY_DX2GCR0_DX2GCR0_RESERVED_4_X(x)  (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX2GCR0_DX2GCR0_DQSGPDR(x)       (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX2GCR0_DX2GCR0_DQSGPDR_M        GENMASK(5, 5)
#define DDR_PHY_DX2GCR0_DX2GCR0_DQSGPDR_X(x)     (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX2GCR0_DX2GCR0_RESERVED_6(x)    (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX2GCR0_DX2GCR0_RESERVED_6_M     GENMASK(6, 6)
#define DDR_PHY_DX2GCR0_DX2GCR0_RESERVED_6_X(x)  (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX2GCR0_DX2GCR0_PDRAL(x)         (((x) << 7) & GENMASK(8, 7))
#define DDR_PHY_DX2GCR0_DX2GCR0_PDRAL_M          GENMASK(8, 7)
#define DDR_PHY_DX2GCR0_DX2GCR0_PDRAL_X(x)       (((x) & GENMASK(8, 7)) >> 7)

#define DDR_PHY_DX2GCR0_DX2GCR0_RTTOH(x)         (((x) << 9) & GENMASK(10, 9))
#define DDR_PHY_DX2GCR0_DX2GCR0_RTTOH_M          GENMASK(10, 9)
#define DDR_PHY_DX2GCR0_DX2GCR0_RTTOH_X(x)       (((x) & GENMASK(10, 9)) >> 9)

#define DDR_PHY_DX2GCR0_DX2GCR0_RTTOAL(x)        (((x) << 11) & GENMASK(11, 11))
#define DDR_PHY_DX2GCR0_DX2GCR0_RTTOAL_M         GENMASK(11, 11)
#define DDR_PHY_DX2GCR0_DX2GCR0_RTTOAL_X(x)      (((x) & GENMASK(11, 11)) >> 11)

#define DDR_PHY_DX2GCR0_DX2GCR0_DQSSEPDR(x)      (((x) << 12) & GENMASK(12, 12))
#define DDR_PHY_DX2GCR0_DX2GCR0_DQSSEPDR_M       GENMASK(12, 12)
#define DDR_PHY_DX2GCR0_DX2GCR0_DQSSEPDR_X(x)    (((x) & GENMASK(12, 12)) >> 12)

#define DDR_PHY_DX2GCR0_DX2GCR0_DQSNSEPDR(x)     (((x) << 13) & GENMASK(13, 13))
#define DDR_PHY_DX2GCR0_DX2GCR0_DQSNSEPDR_M      GENMASK(13, 13)
#define DDR_PHY_DX2GCR0_DX2GCR0_DQSNSEPDR_X(x)   (((x) & GENMASK(13, 13)) >> 13)

#define DDR_PHY_DX2GCR0_DX2GCR0_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX2GCR0_DX2GCR0_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX2GCR0_DX2GCR0_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX2GCR0_DX2GCR0_PLLRST(x)        (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX2GCR0_DX2GCR0_PLLRST_M         GENMASK(16, 16)
#define DDR_PHY_DX2GCR0_DX2GCR0_PLLRST_X(x)      (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX2GCR0_DX2GCR0_PLLPD(x)         (((x) << 17) & GENMASK(17, 17))
#define DDR_PHY_DX2GCR0_DX2GCR0_PLLPD_M          GENMASK(17, 17)
#define DDR_PHY_DX2GCR0_DX2GCR0_PLLPD_X(x)       (((x) & GENMASK(17, 17)) >> 17)

#define DDR_PHY_DX2GCR0_DX2GCR0_GSHIFT(x)        (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_DX2GCR0_DX2GCR0_GSHIFT_M         GENMASK(18, 18)
#define DDR_PHY_DX2GCR0_DX2GCR0_GSHIFT_X(x)      (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_DX2GCR0_DX2GCR0_PLLBYP(x)        (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_DX2GCR0_DX2GCR0_PLLBYP_M         GENMASK(19, 19)
#define DDR_PHY_DX2GCR0_DX2GCR0_PLLBYP_X(x)      (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_DX2GCR0_DX2GCR0_RDDLY(x)         (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX2GCR0_DX2GCR0_RDDLY_M          GENMASK(23, 20)
#define DDR_PHY_DX2GCR0_DX2GCR0_RDDLY_X(x)       (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX2GCR0_DX2GCR0_RESERVED_29_24(x)\
	(((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX2GCR0_DX2GCR0_RESERVED_29_24_M GENMASK(29, 24)
#define DDR_PHY_DX2GCR0_DX2GCR0_RESERVED_29_24_X(x)\
	(((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX2GCR0_DX2GCR0_MDLEN(x)         (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX2GCR0_DX2GCR0_MDLEN_M          GENMASK(30, 30)
#define DDR_PHY_DX2GCR0_DX2GCR0_MDLEN_X(x)       (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX2GCR0_DX2GCR0_CALBYP(x)        (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX2GCR0_DX2GCR0_CALBYP_M         GENMASK(31, 31)
#define DDR_PHY_DX2GCR0_DX2GCR0_CALBYP_X(x)      (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2GCR1 */
#define DDR_PHY_DX2GCR1(t)        (t + 0x904)

#define DDR_PHY_DX2GCR1_DX2GCR1_RESERVED_15_0(x) ((x) & GENMASK(15, 0))
#define DDR_PHY_DX2GCR1_DX2GCR1_RESERVED_15_0_M  GENMASK(15, 0)
#define DDR_PHY_DX2GCR1_DX2GCR1_RESERVED_15_0_X(x) ((x) & GENMASK(15, 0))

#define DDR_PHY_DX2GCR1_DX2GCR1_DXPDRMODE(x)     (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX2GCR1_DX2GCR1_DXPDRMODE_M      GENMASK(31, 16)
#define DDR_PHY_DX2GCR1_DX2GCR1_DXPDRMODE_X(x)   (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2GCR2 */
#define DDR_PHY_DX2GCR2(t)        (t + 0x908)

#define DDR_PHY_DX2GCR2_DX2GCR2_DXTEMODE(x)      ((x) & GENMASK(15, 0))
#define DDR_PHY_DX2GCR2_DX2GCR2_DXTEMODE_M       GENMASK(15, 0)
#define DDR_PHY_DX2GCR2_DX2GCR2_DXTEMODE_X(x)    ((x) & GENMASK(15, 0))

#define DDR_PHY_DX2GCR2_DX2GCR2_DXOEMODE(x)      (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX2GCR2_DX2GCR2_DXOEMODE_M       GENMASK(31, 16)
#define DDR_PHY_DX2GCR2_DX2GCR2_DXOEMODE_X(x)    (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2GCR3 */
#define DDR_PHY_DX2GCR3(t)        (t + 0x90c)

#define DDR_PHY_DX2GCR3_DX2GCR3_RESERVED_1_0(x)  ((x) & GENMASK(1, 0))
#define DDR_PHY_DX2GCR3_DX2GCR3_RESERVED_1_0_M   GENMASK(1, 0)
#define DDR_PHY_DX2GCR3_DX2GCR3_RESERVED_1_0_X(x) ((x) & GENMASK(1, 0))

#define DDR_PHY_DX2GCR3_DX2GCR3_DSPDRMODE(x)     (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DX2GCR3_DX2GCR3_DSPDRMODE_M      GENMASK(3, 2)
#define DDR_PHY_DX2GCR3_DX2GCR3_DSPDRMODE_X(x)   (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DX2GCR3_DX2GCR3_DSTEMODE(x)      (((x) << 4) & GENMASK(5, 4))
#define DDR_PHY_DX2GCR3_DX2GCR3_DSTEMODE_M       GENMASK(5, 4)
#define DDR_PHY_DX2GCR3_DX2GCR3_DSTEMODE_X(x)    (((x) & GENMASK(5, 4)) >> 4)

#define DDR_PHY_DX2GCR3_DX2GCR3_DSOEMODE(x)      (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX2GCR3_DX2GCR3_DSOEMODE_M       GENMASK(7, 6)
#define DDR_PHY_DX2GCR3_DX2GCR3_DSOEMODE_X(x)    (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX2GCR3_DX2GCR3_RESERVED_9_8(x)  (((x) << 8) & GENMASK(9, 8))
#define DDR_PHY_DX2GCR3_DX2GCR3_RESERVED_9_8_M   GENMASK(9, 8)
#define DDR_PHY_DX2GCR3_DX2GCR3_RESERVED_9_8_X(x) (((x) & GENMASK(9, 8)) >> 8)

#define DDR_PHY_DX2GCR3_DX2GCR3_DMPDRMODE(x)     (((x) << 10) & GENMASK(11, 10))
#define DDR_PHY_DX2GCR3_DX2GCR3_DMPDRMODE_M      GENMASK(11, 10)
#define DDR_PHY_DX2GCR3_DX2GCR3_DMPDRMODE_X(x)   (((x) & GENMASK(11, 10)) >> 10)

#define DDR_PHY_DX2GCR3_DX2GCR3_DMTEMODE(x)      (((x) << 12) & GENMASK(13, 12))
#define DDR_PHY_DX2GCR3_DX2GCR3_DMTEMODE_M       GENMASK(13, 12)
#define DDR_PHY_DX2GCR3_DX2GCR3_DMTEMODE_X(x)    (((x) & GENMASK(13, 12)) >> 12)

#define DDR_PHY_DX2GCR3_DX2GCR3_DMOEMODE(x)      (((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX2GCR3_DX2GCR3_DMOEMODE_M       GENMASK(15, 14)
#define DDR_PHY_DX2GCR3_DX2GCR3_DMOEMODE_X(x)    (((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX2GCR3_DX2GCR3_RESERVED_17_16(x)\
	(((x) << 16) & GENMASK(17, 16))
#define DDR_PHY_DX2GCR3_DX2GCR3_RESERVED_17_16_M GENMASK(17, 16)
#define DDR_PHY_DX2GCR3_DX2GCR3_RESERVED_17_16_X(x)\
	(((x) & GENMASK(17, 16)) >> 16)

#define DDR_PHY_DX2GCR3_DX2GCR3_OEBVT(x)         (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_DX2GCR3_DX2GCR3_OEBVT_M          GENMASK(18, 18)
#define DDR_PHY_DX2GCR3_DX2GCR3_OEBVT_X(x)       (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_DX2GCR3_DX2GCR3_PDRBVT(x)        (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_DX2GCR3_DX2GCR3_PDRBVT_M         GENMASK(19, 19)
#define DDR_PHY_DX2GCR3_DX2GCR3_PDRBVT_X(x)      (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_DX2GCR3_DX2GCR3_TEBVT(x)         (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX2GCR3_DX2GCR3_TEBVT_M          GENMASK(20, 20)
#define DDR_PHY_DX2GCR3_DX2GCR3_TEBVT_X(x)       (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX2GCR3_DX2GCR3_WDSBVT(x)        (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX2GCR3_DX2GCR3_WDSBVT_M         GENMASK(21, 21)
#define DDR_PHY_DX2GCR3_DX2GCR3_WDSBVT_X(x)      (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX2GCR3_DX2GCR3_RDSBVT(x)        (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX2GCR3_DX2GCR3_RDSBVT_M         GENMASK(22, 22)
#define DDR_PHY_DX2GCR3_DX2GCR3_RDSBVT_X(x)      (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX2GCR3_DX2GCR3_RGSLVT(x)        (((x) << 23) & GENMASK(23, 23))
#define DDR_PHY_DX2GCR3_DX2GCR3_RGSLVT_M         GENMASK(23, 23)
#define DDR_PHY_DX2GCR3_DX2GCR3_RGSLVT_X(x)      (((x) & GENMASK(23, 23)) >> 23)

#define DDR_PHY_DX2GCR3_DX2GCR3_WLLVT(x)         (((x) << 24) & GENMASK(24, 24))
#define DDR_PHY_DX2GCR3_DX2GCR3_WLLVT_M          GENMASK(24, 24)
#define DDR_PHY_DX2GCR3_DX2GCR3_WLLVT_X(x)       (((x) & GENMASK(24, 24)) >> 24)

#define DDR_PHY_DX2GCR3_DX2GCR3_WDLVT(x)         (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_DX2GCR3_DX2GCR3_WDLVT_M          GENMASK(25, 25)
#define DDR_PHY_DX2GCR3_DX2GCR3_WDLVT_X(x)       (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_DX2GCR3_DX2GCR3_RDLVT(x)         (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_DX2GCR3_DX2GCR3_RDLVT_M          GENMASK(26, 26)
#define DDR_PHY_DX2GCR3_DX2GCR3_RDLVT_X(x)       (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_DX2GCR3_DX2GCR3_RGLVT(x)         (((x) << 27) & GENMASK(27, 27))
#define DDR_PHY_DX2GCR3_DX2GCR3_RGLVT_M          GENMASK(27, 27)
#define DDR_PHY_DX2GCR3_DX2GCR3_RGLVT_X(x)       (((x) & GENMASK(27, 27)) >> 27)

#define DDR_PHY_DX2GCR3_DX2GCR3_WDBVT(x)         (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_DX2GCR3_DX2GCR3_WDBVT_M          GENMASK(28, 28)
#define DDR_PHY_DX2GCR3_DX2GCR3_WDBVT_X(x)       (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_DX2GCR3_DX2GCR3_RDBVT(x)         (((x) << 29) & GENMASK(29, 29))
#define DDR_PHY_DX2GCR3_DX2GCR3_RDBVT_M          GENMASK(29, 29)
#define DDR_PHY_DX2GCR3_DX2GCR3_RDBVT_X(x)       (((x) & GENMASK(29, 29)) >> 29)

#define DDR_PHY_DX2GCR3_DX2GCR3_WDMBVT(x)        (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX2GCR3_DX2GCR3_WDMBVT_M         GENMASK(30, 30)
#define DDR_PHY_DX2GCR3_DX2GCR3_WDMBVT_X(x)      (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX2GCR3_DX2GCR3_RDMBVT(x)        (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX2GCR3_DX2GCR3_RDMBVT_M         GENMASK(31, 31)
#define DDR_PHY_DX2GCR3_DX2GCR3_RDMBVT_X(x)      (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2GCR4 */
#define DDR_PHY_DX2GCR4(t)        (t + 0x910)

#define DDR_PHY_DX2GCR4_DX2GCR4_DXREFIMON(x)     ((x) & GENMASK(1, 0))
#define DDR_PHY_DX2GCR4_DX2GCR4_DXREFIMON_M      GENMASK(1, 0)
#define DDR_PHY_DX2GCR4_DX2GCR4_DXREFIMON_X(x)   ((x) & GENMASK(1, 0))

#define DDR_PHY_DX2GCR4_DX2GCR4_DXREFIEN(x)      (((x) << 2) & GENMASK(5, 2))
#define DDR_PHY_DX2GCR4_DX2GCR4_DXREFIEN_M       GENMASK(5, 2)
#define DDR_PHY_DX2GCR4_DX2GCR4_DXREFIEN_X(x)    (((x) & GENMASK(5, 2)) >> 2)

#define DDR_PHY_DX2GCR4_DX2GCR4_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX2GCR4_DX2GCR4_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX2GCR4_DX2GCR4_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX2GCR4_DX2GCR4_DXREFSSEL(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX2GCR4_DX2GCR4_DXREFSSEL_M      GENMASK(13, 8)
#define DDR_PHY_DX2GCR4_DX2GCR4_DXREFSSEL_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX2GCR4_DX2GCR4_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX2GCR4_DX2GCR4_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX2GCR4_DX2GCR4_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX2GCR4_DX2GCR4_DXREFESEL(x)     (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX2GCR4_DX2GCR4_DXREFESEL_M      GENMASK(21, 16)
#define DDR_PHY_DX2GCR4_DX2GCR4_DXREFESEL_X(x)   (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX2GCR4_DX2GCR4_RESERVED_24_22(x)\
	(((x) << 22) & GENMASK(24, 22))
#define DDR_PHY_DX2GCR4_DX2GCR4_RESERVED_24_22_M GENMASK(24, 22)
#define DDR_PHY_DX2GCR4_DX2GCR4_RESERVED_24_22_X(x)\
	(((x) & GENMASK(24, 22)) >> 22)

#define DDR_PHY_DX2GCR4_DX2GCR4_DXREFSEN(x)      (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_DX2GCR4_DX2GCR4_DXREFSEN_M       GENMASK(25, 25)
#define DDR_PHY_DX2GCR4_DX2GCR4_DXREFSEN_X(x)    (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_DX2GCR4_DX2GCR4_DXREFEEN(x)      (((x) << 26) & GENMASK(27, 26))
#define DDR_PHY_DX2GCR4_DX2GCR4_DXREFEEN_M       GENMASK(27, 26)
#define DDR_PHY_DX2GCR4_DX2GCR4_DXREFEEN_X(x)    (((x) & GENMASK(27, 26)) >> 26)

#define DDR_PHY_DX2GCR4_DX2GCR4_DXREFPEN(x)      (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_DX2GCR4_DX2GCR4_DXREFPEN_M       GENMASK(28, 28)
#define DDR_PHY_DX2GCR4_DX2GCR4_DXREFPEN_X(x)    (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_DX2GCR4_DX2GCR4_DXREFIOM(x)      (((x) << 29) & GENMASK(31, 29))
#define DDR_PHY_DX2GCR4_DX2GCR4_DXREFIOM_M       GENMASK(31, 29)
#define DDR_PHY_DX2GCR4_DX2GCR4_DXREFIOM_X(x)    (((x) & GENMASK(31, 29)) >> 29)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2GCR5 */
#define DDR_PHY_DX2GCR5(t)        (t + 0x914)

#define DDR_PHY_DX2GCR5_DX2GCR5_DXREFISELR0(x)   ((x) & GENMASK(5, 0))
#define DDR_PHY_DX2GCR5_DX2GCR5_DXREFISELR0_M    GENMASK(5, 0)
#define DDR_PHY_DX2GCR5_DX2GCR5_DXREFISELR0_X(x) ((x) & GENMASK(5, 0))

#define DDR_PHY_DX2GCR5_DX2GCR5_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX2GCR5_DX2GCR5_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX2GCR5_DX2GCR5_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX2GCR5_DX2GCR5_DXREFISELR1(x)   (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX2GCR5_DX2GCR5_DXREFISELR1_M    GENMASK(13, 8)
#define DDR_PHY_DX2GCR5_DX2GCR5_DXREFISELR1_X(x) (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX2GCR5_DX2GCR5_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX2GCR5_DX2GCR5_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX2GCR5_DX2GCR5_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX2GCR5_DX2GCR5_DXREFISELR2(x)   (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX2GCR5_DX2GCR5_DXREFISELR2_M    GENMASK(21, 16)
#define DDR_PHY_DX2GCR5_DX2GCR5_DXREFISELR2_X(x) (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX2GCR5_DX2GCR5_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX2GCR5_DX2GCR5_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX2GCR5_DX2GCR5_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX2GCR5_DX2GCR5_DXREFISELR3(x)   (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX2GCR5_DX2GCR5_DXREFISELR3_M    GENMASK(29, 24)
#define DDR_PHY_DX2GCR5_DX2GCR5_DXREFISELR3_X(x) (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX2GCR5_DX2GCR5_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX2GCR5_DX2GCR5_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX2GCR5_DX2GCR5_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2GCR6 */
#define DDR_PHY_DX2GCR6(t)        (t + 0x918)

#define DDR_PHY_DX2GCR6_DX2GCR6_DXDQVREFR0(x)    ((x) & GENMASK(5, 0))
#define DDR_PHY_DX2GCR6_DX2GCR6_DXDQVREFR0_M     GENMASK(5, 0)
#define DDR_PHY_DX2GCR6_DX2GCR6_DXDQVREFR0_X(x)  ((x) & GENMASK(5, 0))

#define DDR_PHY_DX2GCR6_DX2GCR6_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX2GCR6_DX2GCR6_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX2GCR6_DX2GCR6_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX2GCR6_DX2GCR6_DXDQVREFR1(x)    (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX2GCR6_DX2GCR6_DXDQVREFR1_M     GENMASK(13, 8)
#define DDR_PHY_DX2GCR6_DX2GCR6_DXDQVREFR1_X(x)  (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX2GCR6_DX2GCR6_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX2GCR6_DX2GCR6_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX2GCR6_DX2GCR6_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX2GCR6_DX2GCR6_DXDQVREFR2(x)    (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX2GCR6_DX2GCR6_DXDQVREFR2_M     GENMASK(21, 16)
#define DDR_PHY_DX2GCR6_DX2GCR6_DXDQVREFR2_X(x)  (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX2GCR6_DX2GCR6_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX2GCR6_DX2GCR6_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX2GCR6_DX2GCR6_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX2GCR6_DX2GCR6_DXDQVREFR3(x)    (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX2GCR6_DX2GCR6_DXDQVREFR3_M     GENMASK(29, 24)
#define DDR_PHY_DX2GCR6_DX2GCR6_DXDQVREFR3_X(x)  (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX2GCR6_DX2GCR6_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX2GCR6_DX2GCR6_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX2GCR6_DX2GCR6_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2GCR7 */
#define DDR_PHY_DX2GCR7(t)        (t + 0x91c)

#define DDR_PHY_DX2GCR7_DX2GCR7_RESERVED_1_0(x)  ((x) & GENMASK(1, 0))
#define DDR_PHY_DX2GCR7_DX2GCR7_RESERVED_1_0_M   GENMASK(1, 0)
#define DDR_PHY_DX2GCR7_DX2GCR7_RESERVED_1_0_X(x) ((x) & GENMASK(1, 0))

#define DDR_PHY_DX2GCR7_DX2GCR7_X4DSPDRMODE(x)   (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DX2GCR7_DX2GCR7_X4DSPDRMODE_M    GENMASK(3, 2)
#define DDR_PHY_DX2GCR7_DX2GCR7_X4DSPDRMODE_X(x) (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DX2GCR7_DX2GCR7_X4DSTEMODE(x)    (((x) << 4) & GENMASK(5, 4))
#define DDR_PHY_DX2GCR7_DX2GCR7_X4DSTEMODE_M     GENMASK(5, 4)
#define DDR_PHY_DX2GCR7_DX2GCR7_X4DSTEMODE_X(x)  (((x) & GENMASK(5, 4)) >> 4)

#define DDR_PHY_DX2GCR7_DX2GCR7_X4DSOEMODE(x)    (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX2GCR7_DX2GCR7_X4DSOEMODE_M     GENMASK(7, 6)
#define DDR_PHY_DX2GCR7_DX2GCR7_X4DSOEMODE_X(x)  (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX2GCR7_DX2GCR7_RESERVED_9_8(x)  (((x) << 8) & GENMASK(9, 8))
#define DDR_PHY_DX2GCR7_DX2GCR7_RESERVED_9_8_M   GENMASK(9, 8)
#define DDR_PHY_DX2GCR7_DX2GCR7_RESERVED_9_8_X(x) (((x) & GENMASK(9, 8)) >> 8)

#define DDR_PHY_DX2GCR7_DX2GCR7_X4DXPDRMODE(x)   (((x) << 10) & GENMASK(11, 10))
#define DDR_PHY_DX2GCR7_DX2GCR7_X4DXPDRMODE_M    GENMASK(11, 10)
#define DDR_PHY_DX2GCR7_DX2GCR7_X4DXPDRMODE_X(x) (((x) & GENMASK(11, 10)) >> 10)

#define DDR_PHY_DX2GCR7_DX2GCR7_X4DXTEMODE(x)    (((x) << 12) & GENMASK(13, 12))
#define DDR_PHY_DX2GCR7_DX2GCR7_X4DXTEMODE_M     GENMASK(13, 12)
#define DDR_PHY_DX2GCR7_DX2GCR7_X4DXTEMODE_X(x)  (((x) & GENMASK(13, 12)) >> 12)

#define DDR_PHY_DX2GCR7_DX2GCR7_X4DXOEMODE(x)    (((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX2GCR7_DX2GCR7_X4DXOEMODE_M     GENMASK(15, 14)
#define DDR_PHY_DX2GCR7_DX2GCR7_X4DXOEMODE_X(x)  (((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX2GCR7_DX2GCR7_X4DQSGOE(x)      (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX2GCR7_DX2GCR7_X4DQSGOE_M       GENMASK(16, 16)
#define DDR_PHY_DX2GCR7_DX2GCR7_X4DQSGOE_X(x)    (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX2GCR7_DX2GCR7_X4DQSGODT(x)     (((x) << 17) & GENMASK(17, 17))
#define DDR_PHY_DX2GCR7_DX2GCR7_X4DQSGODT_M      GENMASK(17, 17)
#define DDR_PHY_DX2GCR7_DX2GCR7_X4DQSGODT_X(x)   (((x) & GENMASK(17, 17)) >> 17)

#define DDR_PHY_DX2GCR7_DX2GCR7_RESERVED_18(x)   (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_DX2GCR7_DX2GCR7_RESERVED_18_M    GENMASK(18, 18)
#define DDR_PHY_DX2GCR7_DX2GCR7_RESERVED_18_X(x) (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_DX2GCR7_DX2GCR7_X4DQSGPDR(x)     (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_DX2GCR7_DX2GCR7_X4DQSGPDR_M      GENMASK(19, 19)
#define DDR_PHY_DX2GCR7_DX2GCR7_X4DQSGPDR_X(x)   (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_DX2GCR7_DX2GCR7_RESERVED_20(x)   (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX2GCR7_DX2GCR7_RESERVED_20_M    GENMASK(20, 20)
#define DDR_PHY_DX2GCR7_DX2GCR7_RESERVED_20_X(x) (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX2GCR7_DX2GCR7_X4DQSSEPDR(x)    (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX2GCR7_DX2GCR7_X4DQSSEPDR_M     GENMASK(21, 21)
#define DDR_PHY_DX2GCR7_DX2GCR7_X4DQSSEPDR_X(x)  (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX2GCR7_DX2GCR7_X4DQSNSEPDR(x)   (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX2GCR7_DX2GCR7_X4DQSNSEPDR_M    GENMASK(22, 22)
#define DDR_PHY_DX2GCR7_DX2GCR7_X4DQSNSEPDR_X(x) (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX2GCR7_DX2GCR7_X4RTTOH(x)       (((x) << 23) & GENMASK(24, 23))
#define DDR_PHY_DX2GCR7_DX2GCR7_X4RTTOH_M        GENMASK(24, 23)
#define DDR_PHY_DX2GCR7_DX2GCR7_X4RTTOH_X(x)     (((x) & GENMASK(24, 23)) >> 23)

#define DDR_PHY_DX2GCR7_DX2GCR7_X4RTTOAL(x)      (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_DX2GCR7_DX2GCR7_X4RTTOAL_M       GENMASK(25, 25)
#define DDR_PHY_DX2GCR7_DX2GCR7_X4RTTOAL_X(x)    (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_DX2GCR7_DX2GCR7_X4RDDLY(x)       (((x) << 26) & GENMASK(29, 26))
#define DDR_PHY_DX2GCR7_DX2GCR7_X4RDDLY_M        GENMASK(29, 26)
#define DDR_PHY_DX2GCR7_DX2GCR7_X4RDDLY_X(x)     (((x) & GENMASK(29, 26)) >> 26)

#define DDR_PHY_DX2GCR7_DX2GCR7_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX2GCR7_DX2GCR7_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX2GCR7_DX2GCR7_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2GCR8 */
#define DDR_PHY_DX2GCR8(t)        (t + 0x920)

#define DDR_PHY_DX2GCR8_DX2GCR8_X4DXREFISELR0(x) ((x) & GENMASK(5, 0))
#define DDR_PHY_DX2GCR8_DX2GCR8_X4DXREFISELR0_M  GENMASK(5, 0)
#define DDR_PHY_DX2GCR8_DX2GCR8_X4DXREFISELR0_X(x) ((x) & GENMASK(5, 0))

#define DDR_PHY_DX2GCR8_DX2GCR8_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX2GCR8_DX2GCR8_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX2GCR8_DX2GCR8_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX2GCR8_DX2GCR8_X4DXREFISELR1(x) (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX2GCR8_DX2GCR8_X4DXREFISELR1_M  GENMASK(13, 8)
#define DDR_PHY_DX2GCR8_DX2GCR8_X4DXREFISELR1_X(x) (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX2GCR8_DX2GCR8_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX2GCR8_DX2GCR8_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX2GCR8_DX2GCR8_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX2GCR8_DX2GCR8_X4DXREFISELR2(x) (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX2GCR8_DX2GCR8_X4DXREFISELR2_M  GENMASK(21, 16)
#define DDR_PHY_DX2GCR8_DX2GCR8_X4DXREFISELR2_X(x)\
	(((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX2GCR8_DX2GCR8_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX2GCR8_DX2GCR8_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX2GCR8_DX2GCR8_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX2GCR8_DX2GCR8_X4DXREFISELR3(x) (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX2GCR8_DX2GCR8_X4DXREFISELR3_M  GENMASK(29, 24)
#define DDR_PHY_DX2GCR8_DX2GCR8_X4DXREFISELR3_X(x)\
	(((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX2GCR8_DX2GCR8_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX2GCR8_DX2GCR8_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX2GCR8_DX2GCR8_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2GCR9 */
#define DDR_PHY_DX2GCR9(t)        (t + 0x924)

#define DDR_PHY_DX2GCR9_DX2GCR9_X4DXDQVREFR0(x)  ((x) & GENMASK(5, 0))
#define DDR_PHY_DX2GCR9_DX2GCR9_X4DXDQVREFR0_M   GENMASK(5, 0)
#define DDR_PHY_DX2GCR9_DX2GCR9_X4DXDQVREFR0_X(x) ((x) & GENMASK(5, 0))

#define DDR_PHY_DX2GCR9_DX2GCR9_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX2GCR9_DX2GCR9_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX2GCR9_DX2GCR9_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX2GCR9_DX2GCR9_X4DXDQVREFR1(x)  (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX2GCR9_DX2GCR9_X4DXDQVREFR1_M   GENMASK(13, 8)
#define DDR_PHY_DX2GCR9_DX2GCR9_X4DXDQVREFR1_X(x) (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX2GCR9_DX2GCR9_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX2GCR9_DX2GCR9_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX2GCR9_DX2GCR9_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX2GCR9_DX2GCR9_X4DXDQVREFR2(x)  (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX2GCR9_DX2GCR9_X4DXDQVREFR2_M   GENMASK(21, 16)
#define DDR_PHY_DX2GCR9_DX2GCR9_X4DXDQVREFR2_X(x)\
	(((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX2GCR9_DX2GCR9_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX2GCR9_DX2GCR9_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX2GCR9_DX2GCR9_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX2GCR9_DX2GCR9_X4DXDQVREFR3(x)  (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX2GCR9_DX2GCR9_X4DXDQVREFR3_M   GENMASK(29, 24)
#define DDR_PHY_DX2GCR9_DX2GCR9_X4DXDQVREFR3_X(x)\
	(((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX2GCR9_DX2GCR9_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX2GCR9_DX2GCR9_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX2GCR9_DX2GCR9_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2BDLR0 */
#define DDR_PHY_DX2BDLR0(t)       (t + 0x940)

#define DDR_PHY_DX2BDLR0_DX2BDLR0_DQ0WBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX2BDLR0_DX2BDLR0_DQ0WBD_M       GENMASK(5, 0)
#define DDR_PHY_DX2BDLR0_DX2BDLR0_DQ0WBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX2BDLR0_DX2BDLR0_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX2BDLR0_DX2BDLR0_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX2BDLR0_DX2BDLR0_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX2BDLR0_DX2BDLR0_DQ1WBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX2BDLR0_DX2BDLR0_DQ1WBD_M       GENMASK(13, 8)
#define DDR_PHY_DX2BDLR0_DX2BDLR0_DQ1WBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX2BDLR0_DX2BDLR0_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX2BDLR0_DX2BDLR0_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX2BDLR0_DX2BDLR0_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX2BDLR0_DX2BDLR0_DQ2WBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX2BDLR0_DX2BDLR0_DQ2WBD_M       GENMASK(21, 16)
#define DDR_PHY_DX2BDLR0_DX2BDLR0_DQ2WBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX2BDLR0_DX2BDLR0_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX2BDLR0_DX2BDLR0_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX2BDLR0_DX2BDLR0_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX2BDLR0_DX2BDLR0_DQ3WBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX2BDLR0_DX2BDLR0_DQ3WBD_M       GENMASK(29, 24)
#define DDR_PHY_DX2BDLR0_DX2BDLR0_DQ3WBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX2BDLR0_DX2BDLR0_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX2BDLR0_DX2BDLR0_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX2BDLR0_DX2BDLR0_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2BDLR1 */
#define DDR_PHY_DX2BDLR1(t)       (t + 0x944)

#define DDR_PHY_DX2BDLR1_DX2BDLR1_DQ4WBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX2BDLR1_DX2BDLR1_DQ4WBD_M       GENMASK(5, 0)
#define DDR_PHY_DX2BDLR1_DX2BDLR1_DQ4WBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX2BDLR1_DX2BDLR1_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX2BDLR1_DX2BDLR1_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX2BDLR1_DX2BDLR1_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX2BDLR1_DX2BDLR1_DQ5WBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX2BDLR1_DX2BDLR1_DQ5WBD_M       GENMASK(13, 8)
#define DDR_PHY_DX2BDLR1_DX2BDLR1_DQ5WBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX2BDLR1_DX2BDLR1_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX2BDLR1_DX2BDLR1_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX2BDLR1_DX2BDLR1_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX2BDLR1_DX2BDLR1_DQ6WBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX2BDLR1_DX2BDLR1_DQ6WBD_M       GENMASK(21, 16)
#define DDR_PHY_DX2BDLR1_DX2BDLR1_DQ6WBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX2BDLR1_DX2BDLR1_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX2BDLR1_DX2BDLR1_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX2BDLR1_DX2BDLR1_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX2BDLR1_DX2BDLR1_DQ7WBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX2BDLR1_DX2BDLR1_DQ7WBD_M       GENMASK(29, 24)
#define DDR_PHY_DX2BDLR1_DX2BDLR1_DQ7WBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX2BDLR1_DX2BDLR1_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX2BDLR1_DX2BDLR1_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX2BDLR1_DX2BDLR1_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2BDLR2 */
#define DDR_PHY_DX2BDLR2(t)       (t + 0x948)

#define DDR_PHY_DX2BDLR2_DX2BDLR2_DMWBD(x)       ((x) & GENMASK(5, 0))
#define DDR_PHY_DX2BDLR2_DX2BDLR2_DMWBD_M        GENMASK(5, 0)
#define DDR_PHY_DX2BDLR2_DX2BDLR2_DMWBD_X(x)     ((x) & GENMASK(5, 0))

#define DDR_PHY_DX2BDLR2_DX2BDLR2_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX2BDLR2_DX2BDLR2_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX2BDLR2_DX2BDLR2_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX2BDLR2_DX2BDLR2_DSWBD(x)       (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX2BDLR2_DX2BDLR2_DSWBD_M        GENMASK(13, 8)
#define DDR_PHY_DX2BDLR2_DX2BDLR2_DSWBD_X(x)     (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX2BDLR2_DX2BDLR2_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX2BDLR2_DX2BDLR2_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX2BDLR2_DX2BDLR2_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX2BDLR2_DX2BDLR2_DSOEBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX2BDLR2_DX2BDLR2_DSOEBD_M       GENMASK(21, 16)
#define DDR_PHY_DX2BDLR2_DX2BDLR2_DSOEBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX2BDLR2_DX2BDLR2_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX2BDLR2_DX2BDLR2_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX2BDLR2_DX2BDLR2_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2BDLR3 */
#define DDR_PHY_DX2BDLR3(t)       (t + 0x950)

#define DDR_PHY_DX2BDLR3_DX2BDLR3_DQ0RBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX2BDLR3_DX2BDLR3_DQ0RBD_M       GENMASK(5, 0)
#define DDR_PHY_DX2BDLR3_DX2BDLR3_DQ0RBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX2BDLR3_DX2BDLR3_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX2BDLR3_DX2BDLR3_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX2BDLR3_DX2BDLR3_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX2BDLR3_DX2BDLR3_DQ1RBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX2BDLR3_DX2BDLR3_DQ1RBD_M       GENMASK(13, 8)
#define DDR_PHY_DX2BDLR3_DX2BDLR3_DQ1RBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX2BDLR3_DX2BDLR3_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX2BDLR3_DX2BDLR3_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX2BDLR3_DX2BDLR3_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX2BDLR3_DX2BDLR3_DQ2RBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX2BDLR3_DX2BDLR3_DQ2RBD_M       GENMASK(21, 16)
#define DDR_PHY_DX2BDLR3_DX2BDLR3_DQ2RBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX2BDLR3_DX2BDLR3_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX2BDLR3_DX2BDLR3_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX2BDLR3_DX2BDLR3_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX2BDLR3_DX2BDLR3_DQ3RBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX2BDLR3_DX2BDLR3_DQ3RBD_M       GENMASK(29, 24)
#define DDR_PHY_DX2BDLR3_DX2BDLR3_DQ3RBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX2BDLR3_DX2BDLR3_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX2BDLR3_DX2BDLR3_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX2BDLR3_DX2BDLR3_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2BDLR4 */
#define DDR_PHY_DX2BDLR4(t)       (t + 0x954)

#define DDR_PHY_DX2BDLR4_DX2BDLR4_DQ4RBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX2BDLR4_DX2BDLR4_DQ4RBD_M       GENMASK(5, 0)
#define DDR_PHY_DX2BDLR4_DX2BDLR4_DQ4RBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX2BDLR4_DX2BDLR4_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX2BDLR4_DX2BDLR4_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX2BDLR4_DX2BDLR4_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX2BDLR4_DX2BDLR4_DQ5RBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX2BDLR4_DX2BDLR4_DQ5RBD_M       GENMASK(13, 8)
#define DDR_PHY_DX2BDLR4_DX2BDLR4_DQ5RBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX2BDLR4_DX2BDLR4_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX2BDLR4_DX2BDLR4_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX2BDLR4_DX2BDLR4_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX2BDLR4_DX2BDLR4_DQ6RBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX2BDLR4_DX2BDLR4_DQ6RBD_M       GENMASK(21, 16)
#define DDR_PHY_DX2BDLR4_DX2BDLR4_DQ6RBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX2BDLR4_DX2BDLR4_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX2BDLR4_DX2BDLR4_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX2BDLR4_DX2BDLR4_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX2BDLR4_DX2BDLR4_DQ7RBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX2BDLR4_DX2BDLR4_DQ7RBD_M       GENMASK(29, 24)
#define DDR_PHY_DX2BDLR4_DX2BDLR4_DQ7RBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX2BDLR4_DX2BDLR4_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX2BDLR4_DX2BDLR4_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX2BDLR4_DX2BDLR4_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2BDLR5 */
#define DDR_PHY_DX2BDLR5(t)       (t + 0x958)

#define DDR_PHY_DX2BDLR5_DX2BDLR5_DMRBD(x)       ((x) & GENMASK(5, 0))
#define DDR_PHY_DX2BDLR5_DX2BDLR5_DMRBD_M        GENMASK(5, 0)
#define DDR_PHY_DX2BDLR5_DX2BDLR5_DMRBD_X(x)     ((x) & GENMASK(5, 0))

#define DDR_PHY_DX2BDLR5_DX2BDLR5_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX2BDLR5_DX2BDLR5_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX2BDLR5_DX2BDLR5_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX2BDLR5_DX2BDLR5_DSRBD(x)       (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX2BDLR5_DX2BDLR5_DSRBD_M        GENMASK(13, 8)
#define DDR_PHY_DX2BDLR5_DX2BDLR5_DSRBD_X(x)     (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX2BDLR5_DX2BDLR5_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX2BDLR5_DX2BDLR5_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX2BDLR5_DX2BDLR5_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX2BDLR5_DX2BDLR5_DSNRBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX2BDLR5_DX2BDLR5_DSNRBD_M       GENMASK(21, 16)
#define DDR_PHY_DX2BDLR5_DX2BDLR5_DSNRBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX2BDLR5_DX2BDLR5_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX2BDLR5_DX2BDLR5_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX2BDLR5_DX2BDLR5_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2BDLR6 */
#define DDR_PHY_DX2BDLR6(t)       (t + 0x960)

#define DDR_PHY_DX2BDLR6_DX2BDLR6_RESERVED_7_0(x) ((x) & GENMASK(7, 0))
#define DDR_PHY_DX2BDLR6_DX2BDLR6_RESERVED_7_0_M GENMASK(7, 0)
#define DDR_PHY_DX2BDLR6_DX2BDLR6_RESERVED_7_0_X(x) ((x) & GENMASK(7, 0))

#define DDR_PHY_DX2BDLR6_DX2BDLR6_PDRBD(x)       (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX2BDLR6_DX2BDLR6_PDRBD_M        GENMASK(13, 8)
#define DDR_PHY_DX2BDLR6_DX2BDLR6_PDRBD_X(x)     (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX2BDLR6_DX2BDLR6_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX2BDLR6_DX2BDLR6_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX2BDLR6_DX2BDLR6_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX2BDLR6_DX2BDLR6_TERBD(x)       (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX2BDLR6_DX2BDLR6_TERBD_M        GENMASK(21, 16)
#define DDR_PHY_DX2BDLR6_DX2BDLR6_TERBD_X(x)     (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX2BDLR6_DX2BDLR6_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX2BDLR6_DX2BDLR6_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX2BDLR6_DX2BDLR6_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2BDLR7 */
#define DDR_PHY_DX2BDLR7(t)       (t + 0x964)

#define DDR_PHY_DX2BDLR7_DX2BDLR7_X4DMWBD(x)     ((x) & GENMASK(5, 0))
#define DDR_PHY_DX2BDLR7_DX2BDLR7_X4DMWBD_M      GENMASK(5, 0)
#define DDR_PHY_DX2BDLR7_DX2BDLR7_X4DMWBD_X(x)   ((x) & GENMASK(5, 0))

#define DDR_PHY_DX2BDLR7_DX2BDLR7_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX2BDLR7_DX2BDLR7_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX2BDLR7_DX2BDLR7_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX2BDLR7_DX2BDLR7_X4DSWBD(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX2BDLR7_DX2BDLR7_X4DSWBD_M      GENMASK(13, 8)
#define DDR_PHY_DX2BDLR7_DX2BDLR7_X4DSWBD_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX2BDLR7_DX2BDLR7_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX2BDLR7_DX2BDLR7_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX2BDLR7_DX2BDLR7_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX2BDLR7_DX2BDLR7_X4DSOEBD(x)    (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX2BDLR7_DX2BDLR7_X4DSOEBD_M     GENMASK(21, 16)
#define DDR_PHY_DX2BDLR7_DX2BDLR7_X4DSOEBD_X(x)  (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX2BDLR7_DX2BDLR7_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX2BDLR7_DX2BDLR7_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX2BDLR7_DX2BDLR7_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2BDLR8 */
#define DDR_PHY_DX2BDLR8(t)       (t + 0x968)

#define DDR_PHY_DX2BDLR8_DX2BDLR8_X4DMRBD(x)     ((x) & GENMASK(5, 0))
#define DDR_PHY_DX2BDLR8_DX2BDLR8_X4DMRBD_M      GENMASK(5, 0)
#define DDR_PHY_DX2BDLR8_DX2BDLR8_X4DMRBD_X(x)   ((x) & GENMASK(5, 0))

#define DDR_PHY_DX2BDLR8_DX2BDLR8_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX2BDLR8_DX2BDLR8_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX2BDLR8_DX2BDLR8_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX2BDLR8_DX2BDLR8_X4DSRBD(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX2BDLR8_DX2BDLR8_X4DSRBD_M      GENMASK(13, 8)
#define DDR_PHY_DX2BDLR8_DX2BDLR8_X4DSRBD_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX2BDLR8_DX2BDLR8_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX2BDLR8_DX2BDLR8_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX2BDLR8_DX2BDLR8_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX2BDLR8_DX2BDLR8_X4DSNRBD(x)    (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX2BDLR8_DX2BDLR8_X4DSNRBD_M     GENMASK(21, 16)
#define DDR_PHY_DX2BDLR8_DX2BDLR8_X4DSNRBD_X(x)  (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX2BDLR8_DX2BDLR8_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX2BDLR8_DX2BDLR8_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX2BDLR8_DX2BDLR8_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2BDLR9 */
#define DDR_PHY_DX2BDLR9(t)       (t + 0x96c)

#define DDR_PHY_DX2BDLR9_DX2BDLR9_RESERVED_7_0(x) ((x) & GENMASK(7, 0))
#define DDR_PHY_DX2BDLR9_DX2BDLR9_RESERVED_7_0_M GENMASK(7, 0)
#define DDR_PHY_DX2BDLR9_DX2BDLR9_RESERVED_7_0_X(x) ((x) & GENMASK(7, 0))

#define DDR_PHY_DX2BDLR9_DX2BDLR9_X4PDRBD(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX2BDLR9_DX2BDLR9_X4PDRBD_M      GENMASK(13, 8)
#define DDR_PHY_DX2BDLR9_DX2BDLR9_X4PDRBD_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX2BDLR9_DX2BDLR9_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX2BDLR9_DX2BDLR9_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX2BDLR9_DX2BDLR9_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX2BDLR9_DX2BDLR9_X4TERBD(x)     (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX2BDLR9_DX2BDLR9_X4TERBD_M      GENMASK(21, 16)
#define DDR_PHY_DX2BDLR9_DX2BDLR9_X4TERBD_X(x)   (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX2BDLR9_DX2BDLR9_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX2BDLR9_DX2BDLR9_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX2BDLR9_DX2BDLR9_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2LCDLR0 */
#define DDR_PHY_DX2LCDLR0(t)      (t + 0x980)

#define DDR_PHY_DX2LCDLR0_DX2LCDLR0_WLD(x)       ((x) & GENMASK(8, 0))
#define DDR_PHY_DX2LCDLR0_DX2LCDLR0_WLD_M        GENMASK(8, 0)
#define DDR_PHY_DX2LCDLR0_DX2LCDLR0_WLD_X(x)     ((x) & GENMASK(8, 0))

#define DDR_PHY_DX2LCDLR0_DX2LCDLR0_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX2LCDLR0_DX2LCDLR0_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX2LCDLR0_DX2LCDLR0_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX2LCDLR0_DX2LCDLR0_X4WLD(x)     (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX2LCDLR0_DX2LCDLR0_X4WLD_M      GENMASK(24, 16)
#define DDR_PHY_DX2LCDLR0_DX2LCDLR0_X4WLD_X(x)   (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX2LCDLR0_DX2LCDLR0_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX2LCDLR0_DX2LCDLR0_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX2LCDLR0_DX2LCDLR0_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2LCDLR1 */
#define DDR_PHY_DX2LCDLR1(t)      (t + 0x984)

#define DDR_PHY_DX2LCDLR1_DX2LCDLR1_WDQD(x)      ((x) & GENMASK(8, 0))
#define DDR_PHY_DX2LCDLR1_DX2LCDLR1_WDQD_M       GENMASK(8, 0)
#define DDR_PHY_DX2LCDLR1_DX2LCDLR1_WDQD_X(x)    ((x) & GENMASK(8, 0))

#define DDR_PHY_DX2LCDLR1_DX2LCDLR1_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX2LCDLR1_DX2LCDLR1_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX2LCDLR1_DX2LCDLR1_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX2LCDLR1_DX2LCDLR1_X4WDQD(x)    (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX2LCDLR1_DX2LCDLR1_X4WDQD_M     GENMASK(24, 16)
#define DDR_PHY_DX2LCDLR1_DX2LCDLR1_X4WDQD_X(x)  (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX2LCDLR1_DX2LCDLR1_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX2LCDLR1_DX2LCDLR1_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX2LCDLR1_DX2LCDLR1_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2LCDLR2 */
#define DDR_PHY_DX2LCDLR2(t)      (t + 0x988)

#define DDR_PHY_DX2LCDLR2_DX2LCDLR2_DQSGD(x)     ((x) & GENMASK(8, 0))
#define DDR_PHY_DX2LCDLR2_DX2LCDLR2_DQSGD_M      GENMASK(8, 0)
#define DDR_PHY_DX2LCDLR2_DX2LCDLR2_DQSGD_X(x)   ((x) & GENMASK(8, 0))

#define DDR_PHY_DX2LCDLR2_DX2LCDLR2_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX2LCDLR2_DX2LCDLR2_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX2LCDLR2_DX2LCDLR2_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX2LCDLR2_DX2LCDLR2_X4DQSGD(x)   (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX2LCDLR2_DX2LCDLR2_X4DQSGD_M    GENMASK(24, 16)
#define DDR_PHY_DX2LCDLR2_DX2LCDLR2_X4DQSGD_X(x) (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX2LCDLR2_DX2LCDLR2_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX2LCDLR2_DX2LCDLR2_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX2LCDLR2_DX2LCDLR2_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2LCDLR3 */
#define DDR_PHY_DX2LCDLR3(t)      (t + 0x98c)

#define DDR_PHY_DX2LCDLR3_DX2LCDLR3_RDQSD(x)     ((x) & GENMASK(8, 0))
#define DDR_PHY_DX2LCDLR3_DX2LCDLR3_RDQSD_M      GENMASK(8, 0)
#define DDR_PHY_DX2LCDLR3_DX2LCDLR3_RDQSD_X(x)   ((x) & GENMASK(8, 0))

#define DDR_PHY_DX2LCDLR3_DX2LCDLR3_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX2LCDLR3_DX2LCDLR3_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX2LCDLR3_DX2LCDLR3_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX2LCDLR3_DX2LCDLR3_X4RDQSD(x)   (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX2LCDLR3_DX2LCDLR3_X4RDQSD_M    GENMASK(24, 16)
#define DDR_PHY_DX2LCDLR3_DX2LCDLR3_X4RDQSD_X(x) (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX2LCDLR3_DX2LCDLR3_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX2LCDLR3_DX2LCDLR3_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX2LCDLR3_DX2LCDLR3_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2LCDLR4 */
#define DDR_PHY_DX2LCDLR4(t)      (t + 0x990)

#define DDR_PHY_DX2LCDLR4_DX2LCDLR4_RDQSND(x)    ((x) & GENMASK(8, 0))
#define DDR_PHY_DX2LCDLR4_DX2LCDLR4_RDQSND_M     GENMASK(8, 0)
#define DDR_PHY_DX2LCDLR4_DX2LCDLR4_RDQSND_X(x)  ((x) & GENMASK(8, 0))

#define DDR_PHY_DX2LCDLR4_DX2LCDLR4_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX2LCDLR4_DX2LCDLR4_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX2LCDLR4_DX2LCDLR4_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX2LCDLR4_DX2LCDLR4_X4RDQSND(x)  (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX2LCDLR4_DX2LCDLR4_X4RDQSND_M   GENMASK(24, 16)
#define DDR_PHY_DX2LCDLR4_DX2LCDLR4_X4RDQSND_X(x)\
	(((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX2LCDLR4_DX2LCDLR4_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX2LCDLR4_DX2LCDLR4_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX2LCDLR4_DX2LCDLR4_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2LCDLR5 */
#define DDR_PHY_DX2LCDLR5(t)      (t + 0x994)

#define DDR_PHY_DX2LCDLR5_DX2LCDLR5_DQSGSD(x)    ((x) & GENMASK(8, 0))
#define DDR_PHY_DX2LCDLR5_DX2LCDLR5_DQSGSD_M     GENMASK(8, 0)
#define DDR_PHY_DX2LCDLR5_DX2LCDLR5_DQSGSD_X(x)  ((x) & GENMASK(8, 0))

#define DDR_PHY_DX2LCDLR5_DX2LCDLR5_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX2LCDLR5_DX2LCDLR5_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX2LCDLR5_DX2LCDLR5_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX2LCDLR5_DX2LCDLR5_X4DQSGSD(x)  (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX2LCDLR5_DX2LCDLR5_X4DQSGSD_M   GENMASK(24, 16)
#define DDR_PHY_DX2LCDLR5_DX2LCDLR5_X4DQSGSD_X(x)\
	(((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX2LCDLR5_DX2LCDLR5_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX2LCDLR5_DX2LCDLR5_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX2LCDLR5_DX2LCDLR5_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2MDLR0 */
#define DDR_PHY_DX2MDLR0(t)       (t + 0x9a0)

#define DDR_PHY_DX2MDLR0_DX2MDLR0_IPRD(x)        ((x) & GENMASK(8, 0))
#define DDR_PHY_DX2MDLR0_DX2MDLR0_IPRD_M         GENMASK(8, 0)
#define DDR_PHY_DX2MDLR0_DX2MDLR0_IPRD_X(x)      ((x) & GENMASK(8, 0))

#define DDR_PHY_DX2MDLR0_DX2MDLR0_RESERVED_15_9(x) (((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX2MDLR0_DX2MDLR0_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX2MDLR0_DX2MDLR0_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX2MDLR0_DX2MDLR0_TPRD(x)        (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX2MDLR0_DX2MDLR0_TPRD_M         GENMASK(24, 16)
#define DDR_PHY_DX2MDLR0_DX2MDLR0_TPRD_X(x)      (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX2MDLR0_DX2MDLR0_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX2MDLR0_DX2MDLR0_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX2MDLR0_DX2MDLR0_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2MDLR1 */
#define DDR_PHY_DX2MDLR1(t)       (t + 0x9a4)

#define DDR_PHY_DX2MDLR1_DX2MDLR1_MDLD(x)        ((x) & GENMASK(8, 0))
#define DDR_PHY_DX2MDLR1_DX2MDLR1_MDLD_M         GENMASK(8, 0)
#define DDR_PHY_DX2MDLR1_DX2MDLR1_MDLD_X(x)      ((x) & GENMASK(8, 0))

#define DDR_PHY_DX2MDLR1_DX2MDLR1_RESERVED_31_9(x) (((x) << 9) & GENMASK(31, 9))
#define DDR_PHY_DX2MDLR1_DX2MDLR1_RESERVED_31_9_M GENMASK(31, 9)
#define DDR_PHY_DX2MDLR1_DX2MDLR1_RESERVED_31_9_X(x)\
	(((x) & GENMASK(31, 9)) >> 9)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2GTR0 */
#define DDR_PHY_DX2GTR0(t)        (t + 0x9c0)

#define DDR_PHY_DX2GTR0_DX2GTR0_DGSL(x)          ((x) & GENMASK(4, 0))
#define DDR_PHY_DX2GTR0_DX2GTR0_DGSL_M           GENMASK(4, 0)
#define DDR_PHY_DX2GTR0_DX2GTR0_DGSL_X(x)        ((x) & GENMASK(4, 0))

#define DDR_PHY_DX2GTR0_DX2GTR0_RESERVED_7_5(x)  (((x) << 5) & GENMASK(7, 5))
#define DDR_PHY_DX2GTR0_DX2GTR0_RESERVED_7_5_M   GENMASK(7, 5)
#define DDR_PHY_DX2GTR0_DX2GTR0_RESERVED_7_5_X(x) (((x) & GENMASK(7, 5)) >> 5)

#define DDR_PHY_DX2GTR0_DX2GTR0_X4DGSL(x)        (((x) << 8) & GENMASK(12, 8))
#define DDR_PHY_DX2GTR0_DX2GTR0_X4DGSL_M         GENMASK(12, 8)
#define DDR_PHY_DX2GTR0_DX2GTR0_X4DGSL_X(x)      (((x) & GENMASK(12, 8)) >> 8)

#define DDR_PHY_DX2GTR0_DX2GTR0_RESERVED_15_13(x)\
	(((x) << 13) & GENMASK(15, 13))
#define DDR_PHY_DX2GTR0_DX2GTR0_RESERVED_15_13_M GENMASK(15, 13)
#define DDR_PHY_DX2GTR0_DX2GTR0_RESERVED_15_13_X(x)\
	(((x) & GENMASK(15, 13)) >> 13)

#define DDR_PHY_DX2GTR0_DX2GTR0_WLSL(x)          (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DX2GTR0_DX2GTR0_WLSL_M           GENMASK(19, 16)
#define DDR_PHY_DX2GTR0_DX2GTR0_WLSL_X(x)        (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DX2GTR0_DX2GTR0_X4WLSL(x)        (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX2GTR0_DX2GTR0_X4WLSL_M         GENMASK(23, 20)
#define DDR_PHY_DX2GTR0_DX2GTR0_X4WLSL_X(x)      (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX2GTR0_DX2GTR0_RESERVED_31_24(x)\
	(((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_DX2GTR0_DX2GTR0_RESERVED_31_24_M GENMASK(31, 24)
#define DDR_PHY_DX2GTR0_DX2GTR0_RESERVED_31_24_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2RSR0 */
#define DDR_PHY_DX2RSR0(t)        (t + 0x9d0)

#define DDR_PHY_DX2RSR0_DX2RSR0_QSGERR(x)        ((x) & GENMASK(15, 0))
#define DDR_PHY_DX2RSR0_DX2RSR0_QSGERR_M         GENMASK(15, 0)
#define DDR_PHY_DX2RSR0_DX2RSR0_QSGERR_X(x)      ((x) & GENMASK(15, 0))

#define DDR_PHY_DX2RSR0_DX2RSR0_X4QSGERR(x)      (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX2RSR0_DX2RSR0_X4QSGERR_M       GENMASK(31, 16)
#define DDR_PHY_DX2RSR0_DX2RSR0_X4QSGERR_X(x)    (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2RSR1 */
#define DDR_PHY_DX2RSR1(t)        (t + 0x9d4)

#define DDR_PHY_DX2RSR1_DX2RSR1_RDLVLERR(x)      ((x) & GENMASK(15, 0))
#define DDR_PHY_DX2RSR1_DX2RSR1_RDLVLERR_M       GENMASK(15, 0)
#define DDR_PHY_DX2RSR1_DX2RSR1_RDLVLERR_X(x)    ((x) & GENMASK(15, 0))

#define DDR_PHY_DX2RSR1_DX2RSR1_X4RDLVLERR(x)    (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX2RSR1_DX2RSR1_X4RDLVLERR_M     GENMASK(31, 16)
#define DDR_PHY_DX2RSR1_DX2RSR1_X4RDLVLERR_X(x)  (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2RSR2 */
#define DDR_PHY_DX2RSR2(t)        (t + 0x9d8)

#define DDR_PHY_DX2RSR2_DX2RSR2_WLAWN(x)         ((x) & GENMASK(15, 0))
#define DDR_PHY_DX2RSR2_DX2RSR2_WLAWN_M          GENMASK(15, 0)
#define DDR_PHY_DX2RSR2_DX2RSR2_WLAWN_X(x)       ((x) & GENMASK(15, 0))

#define DDR_PHY_DX2RSR2_DX2RSR2_X4WLAWN(x)       (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX2RSR2_DX2RSR2_X4WLAWN_M        GENMASK(31, 16)
#define DDR_PHY_DX2RSR2_DX2RSR2_X4WLAWN_X(x)     (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2RSR3 */
#define DDR_PHY_DX2RSR3(t)        (t + 0x9dc)

#define DDR_PHY_DX2RSR3_DX2RSR3_WLAERR(x)        ((x) & GENMASK(15, 0))
#define DDR_PHY_DX2RSR3_DX2RSR3_WLAERR_M         GENMASK(15, 0)
#define DDR_PHY_DX2RSR3_DX2RSR3_WLAERR_X(x)      ((x) & GENMASK(15, 0))

#define DDR_PHY_DX2RSR3_DX2RSR3_X4WLAERR(x)      (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX2RSR3_DX2RSR3_X4WLAERR_M       GENMASK(31, 16)
#define DDR_PHY_DX2RSR3_DX2RSR3_X4WLAERR_X(x)    (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2GSR0 */
#define DDR_PHY_DX2GSR0(t)        (t + 0x9e0)

#define DDR_PHY_DX2GSR0_DX2GSR0_WDQCAL(x)        ((x) & GENMASK(0, 0))
#define DDR_PHY_DX2GSR0_DX2GSR0_WDQCAL_M         GENMASK(0, 0)
#define DDR_PHY_DX2GSR0_DX2GSR0_WDQCAL_X(x)      ((x) & GENMASK(0, 0))

#define DDR_PHY_DX2GSR0_DX2GSR0_RDQSCAL(x)       (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX2GSR0_DX2GSR0_RDQSCAL_M        GENMASK(1, 1)
#define DDR_PHY_DX2GSR0_DX2GSR0_RDQSCAL_X(x)     (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX2GSR0_DX2GSR0_RDQSNCAL(x)      (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX2GSR0_DX2GSR0_RDQSNCAL_M       GENMASK(2, 2)
#define DDR_PHY_DX2GSR0_DX2GSR0_RDQSNCAL_X(x)    (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX2GSR0_DX2GSR0_GDQSCAL(x)       (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX2GSR0_DX2GSR0_GDQSCAL_M        GENMASK(3, 3)
#define DDR_PHY_DX2GSR0_DX2GSR0_GDQSCAL_X(x)     (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX2GSR0_DX2GSR0_WLCAL(x)         (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX2GSR0_DX2GSR0_WLCAL_M          GENMASK(4, 4)
#define DDR_PHY_DX2GSR0_DX2GSR0_WLCAL_X(x)       (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX2GSR0_DX2GSR0_WLDONE(x)        (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX2GSR0_DX2GSR0_WLDONE_M         GENMASK(5, 5)
#define DDR_PHY_DX2GSR0_DX2GSR0_WLDONE_X(x)      (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX2GSR0_DX2GSR0_WLERR(x)         (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX2GSR0_DX2GSR0_WLERR_M          GENMASK(6, 6)
#define DDR_PHY_DX2GSR0_DX2GSR0_WLERR_X(x)       (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX2GSR0_DX2GSR0_WLPRD(x)         (((x) << 7) & GENMASK(15, 7))
#define DDR_PHY_DX2GSR0_DX2GSR0_WLPRD_M          GENMASK(15, 7)
#define DDR_PHY_DX2GSR0_DX2GSR0_WLPRD_X(x)       (((x) & GENMASK(15, 7)) >> 7)

#define DDR_PHY_DX2GSR0_DX2GSR0_DPLOCK(x)        (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX2GSR0_DX2GSR0_DPLOCK_M         GENMASK(16, 16)
#define DDR_PHY_DX2GSR0_DX2GSR0_DPLOCK_X(x)      (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX2GSR0_DX2GSR0_GDQSPRD(x)       (((x) << 17) & GENMASK(25, 17))
#define DDR_PHY_DX2GSR0_DX2GSR0_GDQSPRD_M        GENMASK(25, 17)
#define DDR_PHY_DX2GSR0_DX2GSR0_GDQSPRD_X(x)     (((x) & GENMASK(25, 17)) >> 17)

#define DDR_PHY_DX2GSR0_DX2GSR0_WLWN(x)          (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_DX2GSR0_DX2GSR0_WLWN_M           GENMASK(26, 26)
#define DDR_PHY_DX2GSR0_DX2GSR0_WLWN_X(x)        (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_DX2GSR0_DX2GSR0_RESERVED_29_27(x)\
	(((x) << 27) & GENMASK(29, 27))
#define DDR_PHY_DX2GSR0_DX2GSR0_RESERVED_29_27_M GENMASK(29, 27)
#define DDR_PHY_DX2GSR0_DX2GSR0_RESERVED_29_27_X(x)\
	(((x) & GENMASK(29, 27)) >> 27)

#define DDR_PHY_DX2GSR0_DX2GSR0_WLDQ(x)          (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX2GSR0_DX2GSR0_WLDQ_M           GENMASK(30, 30)
#define DDR_PHY_DX2GSR0_DX2GSR0_WLDQ_X(x)        (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX2GSR0_DX2GSR0_RESERVED_31(x)   (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX2GSR0_DX2GSR0_RESERVED_31_M    GENMASK(31, 31)
#define DDR_PHY_DX2GSR0_DX2GSR0_RESERVED_31_X(x) (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2GSR1 */
#define DDR_PHY_DX2GSR1(t)        (t + 0x9e4)

#define DDR_PHY_DX2GSR1_DX2GSR1_DLTDONE(x)       ((x) & GENMASK(0, 0))
#define DDR_PHY_DX2GSR1_DX2GSR1_DLTDONE_M        GENMASK(0, 0)
#define DDR_PHY_DX2GSR1_DX2GSR1_DLTDONE_X(x)     ((x) & GENMASK(0, 0))

#define DDR_PHY_DX2GSR1_DX2GSR1_DLTCODE(x)       (((x) << 1) & GENMASK(24, 1))
#define DDR_PHY_DX2GSR1_DX2GSR1_DLTCODE_M        GENMASK(24, 1)
#define DDR_PHY_DX2GSR1_DX2GSR1_DLTCODE_X(x)     (((x) & GENMASK(24, 1)) >> 1)

#define DDR_PHY_DX2GSR1_DX2GSR1_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX2GSR1_DX2GSR1_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX2GSR1_DX2GSR1_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2GSR2 */
#define DDR_PHY_DX2GSR2(t)        (t + 0x9e8)

#define DDR_PHY_DX2GSR2_DX2GSR2_RDERR(x)         ((x) & GENMASK(0, 0))
#define DDR_PHY_DX2GSR2_DX2GSR2_RDERR_M          GENMASK(0, 0)
#define DDR_PHY_DX2GSR2_DX2GSR2_RDERR_X(x)       ((x) & GENMASK(0, 0))

#define DDR_PHY_DX2GSR2_DX2GSR2_RDWN(x)          (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX2GSR2_DX2GSR2_RDWN_M           GENMASK(1, 1)
#define DDR_PHY_DX2GSR2_DX2GSR2_RDWN_X(x)        (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX2GSR2_DX2GSR2_WDERR(x)         (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX2GSR2_DX2GSR2_WDERR_M          GENMASK(2, 2)
#define DDR_PHY_DX2GSR2_DX2GSR2_WDERR_X(x)       (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX2GSR2_DX2GSR2_WDWN(x)          (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX2GSR2_DX2GSR2_WDWN_M           GENMASK(3, 3)
#define DDR_PHY_DX2GSR2_DX2GSR2_WDWN_X(x)        (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX2GSR2_DX2GSR2_REERR(x)         (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX2GSR2_DX2GSR2_REERR_M          GENMASK(4, 4)
#define DDR_PHY_DX2GSR2_DX2GSR2_REERR_X(x)       (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX2GSR2_DX2GSR2_REWN(x)          (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX2GSR2_DX2GSR2_REWN_M           GENMASK(5, 5)
#define DDR_PHY_DX2GSR2_DX2GSR2_REWN_X(x)        (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX2GSR2_DX2GSR2_WEERR(x)         (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX2GSR2_DX2GSR2_WEERR_M          GENMASK(6, 6)
#define DDR_PHY_DX2GSR2_DX2GSR2_WEERR_X(x)       (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX2GSR2_DX2GSR2_WEWN(x)          (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_DX2GSR2_DX2GSR2_WEWN_M           GENMASK(7, 7)
#define DDR_PHY_DX2GSR2_DX2GSR2_WEWN_X(x)        (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_DX2GSR2_DX2GSR2_ESTAT(x)         (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX2GSR2_DX2GSR2_ESTAT_M          GENMASK(11, 8)
#define DDR_PHY_DX2GSR2_DX2GSR2_ESTAT_X(x)       (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX2GSR2_DX2GSR2_DBDQ(x)          (((x) << 12) & GENMASK(19, 12))
#define DDR_PHY_DX2GSR2_DX2GSR2_DBDQ_M           GENMASK(19, 12)
#define DDR_PHY_DX2GSR2_DX2GSR2_DBDQ_X(x)        (((x) & GENMASK(19, 12)) >> 12)

#define DDR_PHY_DX2GSR2_DX2GSR2_SRDERR(x)        (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX2GSR2_DX2GSR2_SRDERR_M         GENMASK(20, 20)
#define DDR_PHY_DX2GSR2_DX2GSR2_SRDERR_X(x)      (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX2GSR2_DX2GSR2_RESERVED_21(x)   (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX2GSR2_DX2GSR2_RESERVED_21_M    GENMASK(21, 21)
#define DDR_PHY_DX2GSR2_DX2GSR2_RESERVED_21_X(x) (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX2GSR2_DX2GSR2_GSDQSCAL(x)      (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX2GSR2_DX2GSR2_GSDQSCAL_M       GENMASK(22, 22)
#define DDR_PHY_DX2GSR2_DX2GSR2_GSDQSCAL_X(x)    (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX2GSR2_DX2GSR2_GSDQSPRD(x)      (((x) << 23) & GENMASK(31, 23))
#define DDR_PHY_DX2GSR2_DX2GSR2_GSDQSPRD_M       GENMASK(31, 23)
#define DDR_PHY_DX2GSR2_DX2GSR2_GSDQSPRD_X(x)    (((x) & GENMASK(31, 23)) >> 23)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2GSR3 */
#define DDR_PHY_DX2GSR3(t)        (t + 0x9ec)

#define DDR_PHY_DX2GSR3_DX2GSR3_SRDPC(x)         ((x) & GENMASK(1, 0))
#define DDR_PHY_DX2GSR3_DX2GSR3_SRDPC_M          GENMASK(1, 0)
#define DDR_PHY_DX2GSR3_DX2GSR3_SRDPC_X(x)       ((x) & GENMASK(1, 0))

#define DDR_PHY_DX2GSR3_DX2GSR3_RESERVED_7_2(x)  (((x) << 2) & GENMASK(7, 2))
#define DDR_PHY_DX2GSR3_DX2GSR3_RESERVED_7_2_M   GENMASK(7, 2)
#define DDR_PHY_DX2GSR3_DX2GSR3_RESERVED_7_2_X(x) (((x) & GENMASK(7, 2)) >> 2)

#define DDR_PHY_DX2GSR3_DX2GSR3_HVERR(x)         (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX2GSR3_DX2GSR3_HVERR_M          GENMASK(11, 8)
#define DDR_PHY_DX2GSR3_DX2GSR3_HVERR_X(x)       (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX2GSR3_DX2GSR3_HVWRN(x)         (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_DX2GSR3_DX2GSR3_HVWRN_M          GENMASK(15, 12)
#define DDR_PHY_DX2GSR3_DX2GSR3_HVWRN_X(x)       (((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_DX2GSR3_DX2GSR3_DVERR(x)         (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DX2GSR3_DX2GSR3_DVERR_M          GENMASK(19, 16)
#define DDR_PHY_DX2GSR3_DX2GSR3_DVERR_X(x)       (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DX2GSR3_DX2GSR3_DVWRN(x)         (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX2GSR3_DX2GSR3_DVWRN_M          GENMASK(23, 20)
#define DDR_PHY_DX2GSR3_DX2GSR3_DVWRN_X(x)       (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX2GSR3_DX2GSR3_ESTAT(x)         (((x) << 24) & GENMASK(26, 24))
#define DDR_PHY_DX2GSR3_DX2GSR3_ESTAT_M          GENMASK(26, 24)
#define DDR_PHY_DX2GSR3_DX2GSR3_ESTAT_X(x)       (((x) & GENMASK(26, 24)) >> 24)

#define DDR_PHY_DX2GSR3_DX2GSR3_RESERVED_31_27(x)\
	(((x) << 27) & GENMASK(31, 27))
#define DDR_PHY_DX2GSR3_DX2GSR3_RESERVED_31_27_M GENMASK(31, 27)
#define DDR_PHY_DX2GSR3_DX2GSR3_RESERVED_31_27_X(x)\
	(((x) & GENMASK(31, 27)) >> 27)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2GSR4 */
#define DDR_PHY_DX2GSR4(t)        (t + 0x9f0)

#define DDR_PHY_DX2GSR4_DX2GSR4_X4WDQCAL(x)      ((x) & GENMASK(0, 0))
#define DDR_PHY_DX2GSR4_DX2GSR4_X4WDQCAL_M       GENMASK(0, 0)
#define DDR_PHY_DX2GSR4_DX2GSR4_X4WDQCAL_X(x)    ((x) & GENMASK(0, 0))

#define DDR_PHY_DX2GSR4_DX2GSR4_X4RDQSCAL(x)     (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX2GSR4_DX2GSR4_X4RDQSCAL_M      GENMASK(1, 1)
#define DDR_PHY_DX2GSR4_DX2GSR4_X4RDQSCAL_X(x)   (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX2GSR4_DX2GSR4_X4RDQSNCAL(x)    (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX2GSR4_DX2GSR4_X4RDQSNCAL_M     GENMASK(2, 2)
#define DDR_PHY_DX2GSR4_DX2GSR4_X4RDQSNCAL_X(x)  (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX2GSR4_DX2GSR4_X4GDQSCAL(x)     (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX2GSR4_DX2GSR4_X4GDQSCAL_M      GENMASK(3, 3)
#define DDR_PHY_DX2GSR4_DX2GSR4_X4GDQSCAL_X(x)   (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX2GSR4_DX2GSR4_X4WLCAL(x)       (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX2GSR4_DX2GSR4_X4WLCAL_M        GENMASK(4, 4)
#define DDR_PHY_DX2GSR4_DX2GSR4_X4WLCAL_X(x)     (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX2GSR4_DX2GSR4_X4WLDONE(x)      (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX2GSR4_DX2GSR4_X4WLDONE_M       GENMASK(5, 5)
#define DDR_PHY_DX2GSR4_DX2GSR4_X4WLDONE_X(x)    (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX2GSR4_DX2GSR4_X4WLERR(x)       (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX2GSR4_DX2GSR4_X4WLERR_M        GENMASK(6, 6)
#define DDR_PHY_DX2GSR4_DX2GSR4_X4WLERR_X(x)     (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX2GSR4_DX2GSR4_X4WLPRD(x)       (((x) << 7) & GENMASK(15, 7))
#define DDR_PHY_DX2GSR4_DX2GSR4_X4WLPRD_M        GENMASK(15, 7)
#define DDR_PHY_DX2GSR4_DX2GSR4_X4WLPRD_X(x)     (((x) & GENMASK(15, 7)) >> 7)

#define DDR_PHY_DX2GSR4_DX2GSR4_X4DPLOCK(x)      (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX2GSR4_DX2GSR4_X4DPLOCK_M       GENMASK(16, 16)
#define DDR_PHY_DX2GSR4_DX2GSR4_X4DPLOCK_X(x)    (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX2GSR4_DX2GSR4_X4GDQSPRD(x)     (((x) << 17) & GENMASK(25, 17))
#define DDR_PHY_DX2GSR4_DX2GSR4_X4GDQSPRD_M      GENMASK(25, 17)
#define DDR_PHY_DX2GSR4_DX2GSR4_X4GDQSPRD_X(x)   (((x) & GENMASK(25, 17)) >> 17)

#define DDR_PHY_DX2GSR4_DX2GSR4_X4WLWN(x)        (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_DX2GSR4_DX2GSR4_X4WLWN_M         GENMASK(26, 26)
#define DDR_PHY_DX2GSR4_DX2GSR4_X4WLWN_X(x)      (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_DX2GSR4_DX2GSR4_RESERVED_29_27(x)\
	(((x) << 27) & GENMASK(29, 27))
#define DDR_PHY_DX2GSR4_DX2GSR4_RESERVED_29_27_M GENMASK(29, 27)
#define DDR_PHY_DX2GSR4_DX2GSR4_RESERVED_29_27_X(x)\
	(((x) & GENMASK(29, 27)) >> 27)

#define DDR_PHY_DX2GSR4_DX2GSR4_X4WLDQ(x)        (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX2GSR4_DX2GSR4_X4WLDQ_M         GENMASK(30, 30)
#define DDR_PHY_DX2GSR4_DX2GSR4_X4WLDQ_X(x)      (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX2GSR4_DX2GSR4_RESERVED_31(x)   (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX2GSR4_DX2GSR4_RESERVED_31_M    GENMASK(31, 31)
#define DDR_PHY_DX2GSR4_DX2GSR4_RESERVED_31_X(x) (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2GSR5 */
#define DDR_PHY_DX2GSR5(t)        (t + 0x9f4)

#define DDR_PHY_DX2GSR5_DX2GSR5_X4RDERR(x)       ((x) & GENMASK(0, 0))
#define DDR_PHY_DX2GSR5_DX2GSR5_X4RDERR_M        GENMASK(0, 0)
#define DDR_PHY_DX2GSR5_DX2GSR5_X4RDERR_X(x)     ((x) & GENMASK(0, 0))

#define DDR_PHY_DX2GSR5_DX2GSR5_X4RDWN(x)        (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX2GSR5_DX2GSR5_X4RDWN_M         GENMASK(1, 1)
#define DDR_PHY_DX2GSR5_DX2GSR5_X4RDWN_X(x)      (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX2GSR5_DX2GSR5_X4WDERR(x)       (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX2GSR5_DX2GSR5_X4WDERR_M        GENMASK(2, 2)
#define DDR_PHY_DX2GSR5_DX2GSR5_X4WDERR_X(x)     (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX2GSR5_DX2GSR5_X4WDWN(x)        (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX2GSR5_DX2GSR5_X4WDWN_M         GENMASK(3, 3)
#define DDR_PHY_DX2GSR5_DX2GSR5_X4WDWN_X(x)      (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX2GSR5_DX2GSR5_X4REERR(x)       (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX2GSR5_DX2GSR5_X4REERR_M        GENMASK(4, 4)
#define DDR_PHY_DX2GSR5_DX2GSR5_X4REERR_X(x)     (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX2GSR5_DX2GSR5_X4REWN(x)        (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX2GSR5_DX2GSR5_X4REWN_M         GENMASK(5, 5)
#define DDR_PHY_DX2GSR5_DX2GSR5_X4REWN_X(x)      (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX2GSR5_DX2GSR5_X4WEERR(x)       (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX2GSR5_DX2GSR5_X4WEERR_M        GENMASK(6, 6)
#define DDR_PHY_DX2GSR5_DX2GSR5_X4WEERR_X(x)     (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX2GSR5_DX2GSR5_X4WEWN(x)        (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_DX2GSR5_DX2GSR5_X4WEWN_M         GENMASK(7, 7)
#define DDR_PHY_DX2GSR5_DX2GSR5_X4WEWN_X(x)      (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_DX2GSR5_DX2GSR5_X4ESTAT(x)       (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX2GSR5_DX2GSR5_X4ESTAT_M        GENMASK(11, 8)
#define DDR_PHY_DX2GSR5_DX2GSR5_X4ESTAT_X(x)     (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX2GSR5_DX2GSR5_RESERVED_19_12(x)\
	(((x) << 12) & GENMASK(19, 12))
#define DDR_PHY_DX2GSR5_DX2GSR5_RESERVED_19_12_M GENMASK(19, 12)
#define DDR_PHY_DX2GSR5_DX2GSR5_RESERVED_19_12_X(x)\
	(((x) & GENMASK(19, 12)) >> 12)

#define DDR_PHY_DX2GSR5_DX2GSR5_X4SRDERR(x)      (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX2GSR5_DX2GSR5_X4SRDERR_M       GENMASK(20, 20)
#define DDR_PHY_DX2GSR5_DX2GSR5_X4SRDERR_X(x)    (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX2GSR5_DX2GSR5_RESERVED_21(x)   (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX2GSR5_DX2GSR5_RESERVED_21_M    GENMASK(21, 21)
#define DDR_PHY_DX2GSR5_DX2GSR5_RESERVED_21_X(x) (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX2GSR5_DX2GSR5_X4GSDQSCAL(x)    (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX2GSR5_DX2GSR5_X4GSDQSCAL_M     GENMASK(22, 22)
#define DDR_PHY_DX2GSR5_DX2GSR5_X4GSDQSCAL_X(x)  (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX2GSR5_DX2GSR5_X4GSDQSPRD(x)    (((x) << 23) & GENMASK(31, 23))
#define DDR_PHY_DX2GSR5_DX2GSR5_X4GSDQSPRD_M     GENMASK(31, 23)
#define DDR_PHY_DX2GSR5_DX2GSR5_X4GSDQSPRD_X(x)  (((x) & GENMASK(31, 23)) >> 23)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX2GSR6 */
#define DDR_PHY_DX2GSR6(t)        (t + 0x9f8)

#define DDR_PHY_DX2GSR6_DX2GSR6_RESERVED_1_0(x)  ((x) & GENMASK(1, 0))
#define DDR_PHY_DX2GSR6_DX2GSR6_RESERVED_1_0_M   GENMASK(1, 0)
#define DDR_PHY_DX2GSR6_DX2GSR6_RESERVED_1_0_X(x) ((x) & GENMASK(1, 0))

#define DDR_PHY_DX2GSR6_DX2GSR6_X4SRDPC(x)       (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DX2GSR6_DX2GSR6_X4SRDPC_M        GENMASK(3, 2)
#define DDR_PHY_DX2GSR6_DX2GSR6_X4SRDPC_X(x)     (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DX2GSR6_DX2GSR6_RESERVED_7_4(x)  (((x) << 4) & GENMASK(7, 4))
#define DDR_PHY_DX2GSR6_DX2GSR6_RESERVED_7_4_M   GENMASK(7, 4)
#define DDR_PHY_DX2GSR6_DX2GSR6_RESERVED_7_4_X(x) (((x) & GENMASK(7, 4)) >> 4)

#define DDR_PHY_DX2GSR6_DX2GSR6_X4HVERR(x)       (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX2GSR6_DX2GSR6_X4HVERR_M        GENMASK(11, 8)
#define DDR_PHY_DX2GSR6_DX2GSR6_X4HVERR_X(x)     (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX2GSR6_DX2GSR6_X4HVWRN(x)       (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_DX2GSR6_DX2GSR6_X4HVWRN_M        GENMASK(15, 12)
#define DDR_PHY_DX2GSR6_DX2GSR6_X4HVWRN_X(x)     (((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_DX2GSR6_DX2GSR6_X4DVERR(x)       (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DX2GSR6_DX2GSR6_X4DVERR_M        GENMASK(19, 16)
#define DDR_PHY_DX2GSR6_DX2GSR6_X4DVERR_X(x)     (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DX2GSR6_DX2GSR6_X4DVWRN(x)       (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX2GSR6_DX2GSR6_X4DVWRN_M        GENMASK(23, 20)
#define DDR_PHY_DX2GSR6_DX2GSR6_X4DVWRN_X(x)     (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX2GSR6_DX2GSR6_RESERVED_31_24(x)\
	(((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_DX2GSR6_DX2GSR6_RESERVED_31_24_M GENMASK(31, 24)
#define DDR_PHY_DX2GSR6_DX2GSR6_RESERVED_31_24_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3GCR0 */
#define DDR_PHY_DX3GCR0(t)        (t + 0xa00)

#define DDR_PHY_DX3GCR0_DX3GCR0_DXEN(x)          ((x) & GENMASK(0, 0))
#define DDR_PHY_DX3GCR0_DX3GCR0_DXEN_M           GENMASK(0, 0)
#define DDR_PHY_DX3GCR0_DX3GCR0_DXEN_X(x)        ((x) & GENMASK(0, 0))

#define DDR_PHY_DX3GCR0_DX3GCR0_DXIOM(x)         (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX3GCR0_DX3GCR0_DXIOM_M          GENMASK(1, 1)
#define DDR_PHY_DX3GCR0_DX3GCR0_DXIOM_X(x)       (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX3GCR0_DX3GCR0_DQSGOE(x)        (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX3GCR0_DX3GCR0_DQSGOE_M         GENMASK(2, 2)
#define DDR_PHY_DX3GCR0_DX3GCR0_DQSGOE_X(x)      (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX3GCR0_DX3GCR0_DQSGODT(x)       (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX3GCR0_DX3GCR0_DQSGODT_M        GENMASK(3, 3)
#define DDR_PHY_DX3GCR0_DX3GCR0_DQSGODT_X(x)     (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX3GCR0_DX3GCR0_RESERVED_4(x)    (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX3GCR0_DX3GCR0_RESERVED_4_M     GENMASK(4, 4)
#define DDR_PHY_DX3GCR0_DX3GCR0_RESERVED_4_X(x)  (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX3GCR0_DX3GCR0_DQSGPDR(x)       (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX3GCR0_DX3GCR0_DQSGPDR_M        GENMASK(5, 5)
#define DDR_PHY_DX3GCR0_DX3GCR0_DQSGPDR_X(x)     (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX3GCR0_DX3GCR0_RESERVED_6(x)    (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX3GCR0_DX3GCR0_RESERVED_6_M     GENMASK(6, 6)
#define DDR_PHY_DX3GCR0_DX3GCR0_RESERVED_6_X(x)  (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX3GCR0_DX3GCR0_PDRAL(x)         (((x) << 7) & GENMASK(8, 7))
#define DDR_PHY_DX3GCR0_DX3GCR0_PDRAL_M          GENMASK(8, 7)
#define DDR_PHY_DX3GCR0_DX3GCR0_PDRAL_X(x)       (((x) & GENMASK(8, 7)) >> 7)

#define DDR_PHY_DX3GCR0_DX3GCR0_RTTOH(x)         (((x) << 9) & GENMASK(10, 9))
#define DDR_PHY_DX3GCR0_DX3GCR0_RTTOH_M          GENMASK(10, 9)
#define DDR_PHY_DX3GCR0_DX3GCR0_RTTOH_X(x)       (((x) & GENMASK(10, 9)) >> 9)

#define DDR_PHY_DX3GCR0_DX3GCR0_RTTOAL(x)        (((x) << 11) & GENMASK(11, 11))
#define DDR_PHY_DX3GCR0_DX3GCR0_RTTOAL_M         GENMASK(11, 11)
#define DDR_PHY_DX3GCR0_DX3GCR0_RTTOAL_X(x)      (((x) & GENMASK(11, 11)) >> 11)

#define DDR_PHY_DX3GCR0_DX3GCR0_DQSSEPDR(x)      (((x) << 12) & GENMASK(12, 12))
#define DDR_PHY_DX3GCR0_DX3GCR0_DQSSEPDR_M       GENMASK(12, 12)
#define DDR_PHY_DX3GCR0_DX3GCR0_DQSSEPDR_X(x)    (((x) & GENMASK(12, 12)) >> 12)

#define DDR_PHY_DX3GCR0_DX3GCR0_DQSNSEPDR(x)     (((x) << 13) & GENMASK(13, 13))
#define DDR_PHY_DX3GCR0_DX3GCR0_DQSNSEPDR_M      GENMASK(13, 13)
#define DDR_PHY_DX3GCR0_DX3GCR0_DQSNSEPDR_X(x)   (((x) & GENMASK(13, 13)) >> 13)

#define DDR_PHY_DX3GCR0_DX3GCR0_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX3GCR0_DX3GCR0_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX3GCR0_DX3GCR0_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX3GCR0_DX3GCR0_PLLRST(x)        (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX3GCR0_DX3GCR0_PLLRST_M         GENMASK(16, 16)
#define DDR_PHY_DX3GCR0_DX3GCR0_PLLRST_X(x)      (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX3GCR0_DX3GCR0_PLLPD(x)         (((x) << 17) & GENMASK(17, 17))
#define DDR_PHY_DX3GCR0_DX3GCR0_PLLPD_M          GENMASK(17, 17)
#define DDR_PHY_DX3GCR0_DX3GCR0_PLLPD_X(x)       (((x) & GENMASK(17, 17)) >> 17)

#define DDR_PHY_DX3GCR0_DX3GCR0_GSHIFT(x)        (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_DX3GCR0_DX3GCR0_GSHIFT_M         GENMASK(18, 18)
#define DDR_PHY_DX3GCR0_DX3GCR0_GSHIFT_X(x)      (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_DX3GCR0_DX3GCR0_PLLBYP(x)        (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_DX3GCR0_DX3GCR0_PLLBYP_M         GENMASK(19, 19)
#define DDR_PHY_DX3GCR0_DX3GCR0_PLLBYP_X(x)      (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_DX3GCR0_DX3GCR0_RDDLY(x)         (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX3GCR0_DX3GCR0_RDDLY_M          GENMASK(23, 20)
#define DDR_PHY_DX3GCR0_DX3GCR0_RDDLY_X(x)       (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX3GCR0_DX3GCR0_RESERVED_29_24(x)\
	(((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX3GCR0_DX3GCR0_RESERVED_29_24_M GENMASK(29, 24)
#define DDR_PHY_DX3GCR0_DX3GCR0_RESERVED_29_24_X(x)\
	(((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX3GCR0_DX3GCR0_MDLEN(x)         (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX3GCR0_DX3GCR0_MDLEN_M          GENMASK(30, 30)
#define DDR_PHY_DX3GCR0_DX3GCR0_MDLEN_X(x)       (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX3GCR0_DX3GCR0_CALBYP(x)        (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX3GCR0_DX3GCR0_CALBYP_M         GENMASK(31, 31)
#define DDR_PHY_DX3GCR0_DX3GCR0_CALBYP_X(x)      (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3GCR1 */
#define DDR_PHY_DX3GCR1(t)        (t + 0xa04)

#define DDR_PHY_DX3GCR1_DX3GCR1_RESERVED_15_0(x) ((x) & GENMASK(15, 0))
#define DDR_PHY_DX3GCR1_DX3GCR1_RESERVED_15_0_M  GENMASK(15, 0)
#define DDR_PHY_DX3GCR1_DX3GCR1_RESERVED_15_0_X(x) ((x) & GENMASK(15, 0))

#define DDR_PHY_DX3GCR1_DX3GCR1_DXPDRMODE(x)     (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX3GCR1_DX3GCR1_DXPDRMODE_M      GENMASK(31, 16)
#define DDR_PHY_DX3GCR1_DX3GCR1_DXPDRMODE_X(x)   (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3GCR2 */
#define DDR_PHY_DX3GCR2(t)        (t + 0xa08)

#define DDR_PHY_DX3GCR2_DX3GCR2_DXTEMODE(x)      ((x) & GENMASK(15, 0))
#define DDR_PHY_DX3GCR2_DX3GCR2_DXTEMODE_M       GENMASK(15, 0)
#define DDR_PHY_DX3GCR2_DX3GCR2_DXTEMODE_X(x)    ((x) & GENMASK(15, 0))

#define DDR_PHY_DX3GCR2_DX3GCR2_DXOEMODE(x)      (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX3GCR2_DX3GCR2_DXOEMODE_M       GENMASK(31, 16)
#define DDR_PHY_DX3GCR2_DX3GCR2_DXOEMODE_X(x)    (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3GCR3 */
#define DDR_PHY_DX3GCR3(t)        (t + 0xa0c)

#define DDR_PHY_DX3GCR3_DX3GCR3_RESERVED_1_0(x)  ((x) & GENMASK(1, 0))
#define DDR_PHY_DX3GCR3_DX3GCR3_RESERVED_1_0_M   GENMASK(1, 0)
#define DDR_PHY_DX3GCR3_DX3GCR3_RESERVED_1_0_X(x) ((x) & GENMASK(1, 0))

#define DDR_PHY_DX3GCR3_DX3GCR3_DSPDRMODE(x)     (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DX3GCR3_DX3GCR3_DSPDRMODE_M      GENMASK(3, 2)
#define DDR_PHY_DX3GCR3_DX3GCR3_DSPDRMODE_X(x)   (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DX3GCR3_DX3GCR3_DSTEMODE(x)      (((x) << 4) & GENMASK(5, 4))
#define DDR_PHY_DX3GCR3_DX3GCR3_DSTEMODE_M       GENMASK(5, 4)
#define DDR_PHY_DX3GCR3_DX3GCR3_DSTEMODE_X(x)    (((x) & GENMASK(5, 4)) >> 4)

#define DDR_PHY_DX3GCR3_DX3GCR3_DSOEMODE(x)      (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX3GCR3_DX3GCR3_DSOEMODE_M       GENMASK(7, 6)
#define DDR_PHY_DX3GCR3_DX3GCR3_DSOEMODE_X(x)    (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX3GCR3_DX3GCR3_RESERVED_9_8(x)  (((x) << 8) & GENMASK(9, 8))
#define DDR_PHY_DX3GCR3_DX3GCR3_RESERVED_9_8_M   GENMASK(9, 8)
#define DDR_PHY_DX3GCR3_DX3GCR3_RESERVED_9_8_X(x) (((x) & GENMASK(9, 8)) >> 8)

#define DDR_PHY_DX3GCR3_DX3GCR3_DMPDRMODE(x)     (((x) << 10) & GENMASK(11, 10))
#define DDR_PHY_DX3GCR3_DX3GCR3_DMPDRMODE_M      GENMASK(11, 10)
#define DDR_PHY_DX3GCR3_DX3GCR3_DMPDRMODE_X(x)   (((x) & GENMASK(11, 10)) >> 10)

#define DDR_PHY_DX3GCR3_DX3GCR3_DMTEMODE(x)      (((x) << 12) & GENMASK(13, 12))
#define DDR_PHY_DX3GCR3_DX3GCR3_DMTEMODE_M       GENMASK(13, 12)
#define DDR_PHY_DX3GCR3_DX3GCR3_DMTEMODE_X(x)    (((x) & GENMASK(13, 12)) >> 12)

#define DDR_PHY_DX3GCR3_DX3GCR3_DMOEMODE(x)      (((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX3GCR3_DX3GCR3_DMOEMODE_M       GENMASK(15, 14)
#define DDR_PHY_DX3GCR3_DX3GCR3_DMOEMODE_X(x)    (((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX3GCR3_DX3GCR3_RESERVED_17_16(x)\
	(((x) << 16) & GENMASK(17, 16))
#define DDR_PHY_DX3GCR3_DX3GCR3_RESERVED_17_16_M GENMASK(17, 16)
#define DDR_PHY_DX3GCR3_DX3GCR3_RESERVED_17_16_X(x)\
	(((x) & GENMASK(17, 16)) >> 16)

#define DDR_PHY_DX3GCR3_DX3GCR3_OEBVT(x)         (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_DX3GCR3_DX3GCR3_OEBVT_M          GENMASK(18, 18)
#define DDR_PHY_DX3GCR3_DX3GCR3_OEBVT_X(x)       (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_DX3GCR3_DX3GCR3_PDRBVT(x)        (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_DX3GCR3_DX3GCR3_PDRBVT_M         GENMASK(19, 19)
#define DDR_PHY_DX3GCR3_DX3GCR3_PDRBVT_X(x)      (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_DX3GCR3_DX3GCR3_TEBVT(x)         (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX3GCR3_DX3GCR3_TEBVT_M          GENMASK(20, 20)
#define DDR_PHY_DX3GCR3_DX3GCR3_TEBVT_X(x)       (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX3GCR3_DX3GCR3_WDSBVT(x)        (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX3GCR3_DX3GCR3_WDSBVT_M         GENMASK(21, 21)
#define DDR_PHY_DX3GCR3_DX3GCR3_WDSBVT_X(x)      (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX3GCR3_DX3GCR3_RDSBVT(x)        (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX3GCR3_DX3GCR3_RDSBVT_M         GENMASK(22, 22)
#define DDR_PHY_DX3GCR3_DX3GCR3_RDSBVT_X(x)      (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX3GCR3_DX3GCR3_RGSLVT(x)        (((x) << 23) & GENMASK(23, 23))
#define DDR_PHY_DX3GCR3_DX3GCR3_RGSLVT_M         GENMASK(23, 23)
#define DDR_PHY_DX3GCR3_DX3GCR3_RGSLVT_X(x)      (((x) & GENMASK(23, 23)) >> 23)

#define DDR_PHY_DX3GCR3_DX3GCR3_WLLVT(x)         (((x) << 24) & GENMASK(24, 24))
#define DDR_PHY_DX3GCR3_DX3GCR3_WLLVT_M          GENMASK(24, 24)
#define DDR_PHY_DX3GCR3_DX3GCR3_WLLVT_X(x)       (((x) & GENMASK(24, 24)) >> 24)

#define DDR_PHY_DX3GCR3_DX3GCR3_WDLVT(x)         (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_DX3GCR3_DX3GCR3_WDLVT_M          GENMASK(25, 25)
#define DDR_PHY_DX3GCR3_DX3GCR3_WDLVT_X(x)       (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_DX3GCR3_DX3GCR3_RDLVT(x)         (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_DX3GCR3_DX3GCR3_RDLVT_M          GENMASK(26, 26)
#define DDR_PHY_DX3GCR3_DX3GCR3_RDLVT_X(x)       (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_DX3GCR3_DX3GCR3_RGLVT(x)         (((x) << 27) & GENMASK(27, 27))
#define DDR_PHY_DX3GCR3_DX3GCR3_RGLVT_M          GENMASK(27, 27)
#define DDR_PHY_DX3GCR3_DX3GCR3_RGLVT_X(x)       (((x) & GENMASK(27, 27)) >> 27)

#define DDR_PHY_DX3GCR3_DX3GCR3_WDBVT(x)         (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_DX3GCR3_DX3GCR3_WDBVT_M          GENMASK(28, 28)
#define DDR_PHY_DX3GCR3_DX3GCR3_WDBVT_X(x)       (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_DX3GCR3_DX3GCR3_RDBVT(x)         (((x) << 29) & GENMASK(29, 29))
#define DDR_PHY_DX3GCR3_DX3GCR3_RDBVT_M          GENMASK(29, 29)
#define DDR_PHY_DX3GCR3_DX3GCR3_RDBVT_X(x)       (((x) & GENMASK(29, 29)) >> 29)

#define DDR_PHY_DX3GCR3_DX3GCR3_WDMBVT(x)        (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX3GCR3_DX3GCR3_WDMBVT_M         GENMASK(30, 30)
#define DDR_PHY_DX3GCR3_DX3GCR3_WDMBVT_X(x)      (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX3GCR3_DX3GCR3_RDMBVT(x)        (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX3GCR3_DX3GCR3_RDMBVT_M         GENMASK(31, 31)
#define DDR_PHY_DX3GCR3_DX3GCR3_RDMBVT_X(x)      (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3GCR4 */
#define DDR_PHY_DX3GCR4(t)        (t + 0xa10)

#define DDR_PHY_DX3GCR4_DX3GCR4_DXREFIMON(x)     ((x) & GENMASK(1, 0))
#define DDR_PHY_DX3GCR4_DX3GCR4_DXREFIMON_M      GENMASK(1, 0)
#define DDR_PHY_DX3GCR4_DX3GCR4_DXREFIMON_X(x)   ((x) & GENMASK(1, 0))

#define DDR_PHY_DX3GCR4_DX3GCR4_DXREFIEN(x)      (((x) << 2) & GENMASK(5, 2))
#define DDR_PHY_DX3GCR4_DX3GCR4_DXREFIEN_M       GENMASK(5, 2)
#define DDR_PHY_DX3GCR4_DX3GCR4_DXREFIEN_X(x)    (((x) & GENMASK(5, 2)) >> 2)

#define DDR_PHY_DX3GCR4_DX3GCR4_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX3GCR4_DX3GCR4_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX3GCR4_DX3GCR4_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX3GCR4_DX3GCR4_DXREFSSEL(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX3GCR4_DX3GCR4_DXREFSSEL_M      GENMASK(13, 8)
#define DDR_PHY_DX3GCR4_DX3GCR4_DXREFSSEL_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX3GCR4_DX3GCR4_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX3GCR4_DX3GCR4_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX3GCR4_DX3GCR4_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX3GCR4_DX3GCR4_DXREFESEL(x)     (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX3GCR4_DX3GCR4_DXREFESEL_M      GENMASK(21, 16)
#define DDR_PHY_DX3GCR4_DX3GCR4_DXREFESEL_X(x)   (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX3GCR4_DX3GCR4_RESERVED_24_22(x)\
	(((x) << 22) & GENMASK(24, 22))
#define DDR_PHY_DX3GCR4_DX3GCR4_RESERVED_24_22_M GENMASK(24, 22)
#define DDR_PHY_DX3GCR4_DX3GCR4_RESERVED_24_22_X(x)\
	(((x) & GENMASK(24, 22)) >> 22)

#define DDR_PHY_DX3GCR4_DX3GCR4_DXREFSEN(x)      (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_DX3GCR4_DX3GCR4_DXREFSEN_M       GENMASK(25, 25)
#define DDR_PHY_DX3GCR4_DX3GCR4_DXREFSEN_X(x)    (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_DX3GCR4_DX3GCR4_DXREFEEN(x)      (((x) << 26) & GENMASK(27, 26))
#define DDR_PHY_DX3GCR4_DX3GCR4_DXREFEEN_M       GENMASK(27, 26)
#define DDR_PHY_DX3GCR4_DX3GCR4_DXREFEEN_X(x)    (((x) & GENMASK(27, 26)) >> 26)

#define DDR_PHY_DX3GCR4_DX3GCR4_DXREFPEN(x)      (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_DX3GCR4_DX3GCR4_DXREFPEN_M       GENMASK(28, 28)
#define DDR_PHY_DX3GCR4_DX3GCR4_DXREFPEN_X(x)    (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_DX3GCR4_DX3GCR4_DXREFIOM(x)      (((x) << 29) & GENMASK(31, 29))
#define DDR_PHY_DX3GCR4_DX3GCR4_DXREFIOM_M       GENMASK(31, 29)
#define DDR_PHY_DX3GCR4_DX3GCR4_DXREFIOM_X(x)    (((x) & GENMASK(31, 29)) >> 29)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3GCR5 */
#define DDR_PHY_DX3GCR5(t)        (t + 0xa14)

#define DDR_PHY_DX3GCR5_DX3GCR5_DXREFISELR0(x)   ((x) & GENMASK(5, 0))
#define DDR_PHY_DX3GCR5_DX3GCR5_DXREFISELR0_M    GENMASK(5, 0)
#define DDR_PHY_DX3GCR5_DX3GCR5_DXREFISELR0_X(x) ((x) & GENMASK(5, 0))

#define DDR_PHY_DX3GCR5_DX3GCR5_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX3GCR5_DX3GCR5_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX3GCR5_DX3GCR5_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX3GCR5_DX3GCR5_DXREFISELR1(x)   (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX3GCR5_DX3GCR5_DXREFISELR1_M    GENMASK(13, 8)
#define DDR_PHY_DX3GCR5_DX3GCR5_DXREFISELR1_X(x) (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX3GCR5_DX3GCR5_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX3GCR5_DX3GCR5_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX3GCR5_DX3GCR5_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX3GCR5_DX3GCR5_DXREFISELR2(x)   (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX3GCR5_DX3GCR5_DXREFISELR2_M    GENMASK(21, 16)
#define DDR_PHY_DX3GCR5_DX3GCR5_DXREFISELR2_X(x) (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX3GCR5_DX3GCR5_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX3GCR5_DX3GCR5_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX3GCR5_DX3GCR5_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX3GCR5_DX3GCR5_DXREFISELR3(x)   (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX3GCR5_DX3GCR5_DXREFISELR3_M    GENMASK(29, 24)
#define DDR_PHY_DX3GCR5_DX3GCR5_DXREFISELR3_X(x) (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX3GCR5_DX3GCR5_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX3GCR5_DX3GCR5_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX3GCR5_DX3GCR5_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3GCR6 */
#define DDR_PHY_DX3GCR6(t)        (t + 0xa18)

#define DDR_PHY_DX3GCR6_DX3GCR6_DXDQVREFR0(x)    ((x) & GENMASK(5, 0))
#define DDR_PHY_DX3GCR6_DX3GCR6_DXDQVREFR0_M     GENMASK(5, 0)
#define DDR_PHY_DX3GCR6_DX3GCR6_DXDQVREFR0_X(x)  ((x) & GENMASK(5, 0))

#define DDR_PHY_DX3GCR6_DX3GCR6_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX3GCR6_DX3GCR6_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX3GCR6_DX3GCR6_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX3GCR6_DX3GCR6_DXDQVREFR1(x)    (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX3GCR6_DX3GCR6_DXDQVREFR1_M     GENMASK(13, 8)
#define DDR_PHY_DX3GCR6_DX3GCR6_DXDQVREFR1_X(x)  (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX3GCR6_DX3GCR6_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX3GCR6_DX3GCR6_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX3GCR6_DX3GCR6_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX3GCR6_DX3GCR6_DXDQVREFR2(x)    (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX3GCR6_DX3GCR6_DXDQVREFR2_M     GENMASK(21, 16)
#define DDR_PHY_DX3GCR6_DX3GCR6_DXDQVREFR2_X(x)  (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX3GCR6_DX3GCR6_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX3GCR6_DX3GCR6_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX3GCR6_DX3GCR6_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX3GCR6_DX3GCR6_DXDQVREFR3(x)    (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX3GCR6_DX3GCR6_DXDQVREFR3_M     GENMASK(29, 24)
#define DDR_PHY_DX3GCR6_DX3GCR6_DXDQVREFR3_X(x)  (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX3GCR6_DX3GCR6_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX3GCR6_DX3GCR6_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX3GCR6_DX3GCR6_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3GCR7 */
#define DDR_PHY_DX3GCR7(t)        (t + 0xa1c)

#define DDR_PHY_DX3GCR7_DX3GCR7_RESERVED_1_0(x)  ((x) & GENMASK(1, 0))
#define DDR_PHY_DX3GCR7_DX3GCR7_RESERVED_1_0_M   GENMASK(1, 0)
#define DDR_PHY_DX3GCR7_DX3GCR7_RESERVED_1_0_X(x) ((x) & GENMASK(1, 0))

#define DDR_PHY_DX3GCR7_DX3GCR7_X4DSPDRMODE(x)   (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DX3GCR7_DX3GCR7_X4DSPDRMODE_M    GENMASK(3, 2)
#define DDR_PHY_DX3GCR7_DX3GCR7_X4DSPDRMODE_X(x) (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DX3GCR7_DX3GCR7_X4DSTEMODE(x)    (((x) << 4) & GENMASK(5, 4))
#define DDR_PHY_DX3GCR7_DX3GCR7_X4DSTEMODE_M     GENMASK(5, 4)
#define DDR_PHY_DX3GCR7_DX3GCR7_X4DSTEMODE_X(x)  (((x) & GENMASK(5, 4)) >> 4)

#define DDR_PHY_DX3GCR7_DX3GCR7_X4DSOEMODE(x)    (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX3GCR7_DX3GCR7_X4DSOEMODE_M     GENMASK(7, 6)
#define DDR_PHY_DX3GCR7_DX3GCR7_X4DSOEMODE_X(x)  (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX3GCR7_DX3GCR7_RESERVED_9_8(x)  (((x) << 8) & GENMASK(9, 8))
#define DDR_PHY_DX3GCR7_DX3GCR7_RESERVED_9_8_M   GENMASK(9, 8)
#define DDR_PHY_DX3GCR7_DX3GCR7_RESERVED_9_8_X(x) (((x) & GENMASK(9, 8)) >> 8)

#define DDR_PHY_DX3GCR7_DX3GCR7_X4DXPDRMODE(x)   (((x) << 10) & GENMASK(11, 10))
#define DDR_PHY_DX3GCR7_DX3GCR7_X4DXPDRMODE_M    GENMASK(11, 10)
#define DDR_PHY_DX3GCR7_DX3GCR7_X4DXPDRMODE_X(x) (((x) & GENMASK(11, 10)) >> 10)

#define DDR_PHY_DX3GCR7_DX3GCR7_X4DXTEMODE(x)    (((x) << 12) & GENMASK(13, 12))
#define DDR_PHY_DX3GCR7_DX3GCR7_X4DXTEMODE_M     GENMASK(13, 12)
#define DDR_PHY_DX3GCR7_DX3GCR7_X4DXTEMODE_X(x)  (((x) & GENMASK(13, 12)) >> 12)

#define DDR_PHY_DX3GCR7_DX3GCR7_X4DXOEMODE(x)    (((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX3GCR7_DX3GCR7_X4DXOEMODE_M     GENMASK(15, 14)
#define DDR_PHY_DX3GCR7_DX3GCR7_X4DXOEMODE_X(x)  (((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX3GCR7_DX3GCR7_X4DQSGOE(x)      (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX3GCR7_DX3GCR7_X4DQSGOE_M       GENMASK(16, 16)
#define DDR_PHY_DX3GCR7_DX3GCR7_X4DQSGOE_X(x)    (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX3GCR7_DX3GCR7_X4DQSGODT(x)     (((x) << 17) & GENMASK(17, 17))
#define DDR_PHY_DX3GCR7_DX3GCR7_X4DQSGODT_M      GENMASK(17, 17)
#define DDR_PHY_DX3GCR7_DX3GCR7_X4DQSGODT_X(x)   (((x) & GENMASK(17, 17)) >> 17)

#define DDR_PHY_DX3GCR7_DX3GCR7_RESERVED_18(x)   (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_DX3GCR7_DX3GCR7_RESERVED_18_M    GENMASK(18, 18)
#define DDR_PHY_DX3GCR7_DX3GCR7_RESERVED_18_X(x) (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_DX3GCR7_DX3GCR7_X4DQSGPDR(x)     (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_DX3GCR7_DX3GCR7_X4DQSGPDR_M      GENMASK(19, 19)
#define DDR_PHY_DX3GCR7_DX3GCR7_X4DQSGPDR_X(x)   (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_DX3GCR7_DX3GCR7_RESERVED_20(x)   (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX3GCR7_DX3GCR7_RESERVED_20_M    GENMASK(20, 20)
#define DDR_PHY_DX3GCR7_DX3GCR7_RESERVED_20_X(x) (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX3GCR7_DX3GCR7_X4DQSSEPDR(x)    (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX3GCR7_DX3GCR7_X4DQSSEPDR_M     GENMASK(21, 21)
#define DDR_PHY_DX3GCR7_DX3GCR7_X4DQSSEPDR_X(x)  (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX3GCR7_DX3GCR7_X4DQSNSEPDR(x)   (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX3GCR7_DX3GCR7_X4DQSNSEPDR_M    GENMASK(22, 22)
#define DDR_PHY_DX3GCR7_DX3GCR7_X4DQSNSEPDR_X(x) (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX3GCR7_DX3GCR7_X4RTTOH(x)       (((x) << 23) & GENMASK(24, 23))
#define DDR_PHY_DX3GCR7_DX3GCR7_X4RTTOH_M        GENMASK(24, 23)
#define DDR_PHY_DX3GCR7_DX3GCR7_X4RTTOH_X(x)     (((x) & GENMASK(24, 23)) >> 23)

#define DDR_PHY_DX3GCR7_DX3GCR7_X4RTTOAL(x)      (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_DX3GCR7_DX3GCR7_X4RTTOAL_M       GENMASK(25, 25)
#define DDR_PHY_DX3GCR7_DX3GCR7_X4RTTOAL_X(x)    (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_DX3GCR7_DX3GCR7_X4RDDLY(x)       (((x) << 26) & GENMASK(29, 26))
#define DDR_PHY_DX3GCR7_DX3GCR7_X4RDDLY_M        GENMASK(29, 26)
#define DDR_PHY_DX3GCR7_DX3GCR7_X4RDDLY_X(x)     (((x) & GENMASK(29, 26)) >> 26)

#define DDR_PHY_DX3GCR7_DX3GCR7_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX3GCR7_DX3GCR7_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX3GCR7_DX3GCR7_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3GCR8 */
#define DDR_PHY_DX3GCR8(t)        (t + 0xa20)

#define DDR_PHY_DX3GCR8_DX3GCR8_X4DXREFISELR0(x) ((x) & GENMASK(5, 0))
#define DDR_PHY_DX3GCR8_DX3GCR8_X4DXREFISELR0_M  GENMASK(5, 0)
#define DDR_PHY_DX3GCR8_DX3GCR8_X4DXREFISELR0_X(x) ((x) & GENMASK(5, 0))

#define DDR_PHY_DX3GCR8_DX3GCR8_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX3GCR8_DX3GCR8_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX3GCR8_DX3GCR8_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX3GCR8_DX3GCR8_X4DXREFISELR1(x) (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX3GCR8_DX3GCR8_X4DXREFISELR1_M  GENMASK(13, 8)
#define DDR_PHY_DX3GCR8_DX3GCR8_X4DXREFISELR1_X(x) (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX3GCR8_DX3GCR8_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX3GCR8_DX3GCR8_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX3GCR8_DX3GCR8_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX3GCR8_DX3GCR8_X4DXREFISELR2(x) (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX3GCR8_DX3GCR8_X4DXREFISELR2_M  GENMASK(21, 16)
#define DDR_PHY_DX3GCR8_DX3GCR8_X4DXREFISELR2_X(x)\
	(((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX3GCR8_DX3GCR8_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX3GCR8_DX3GCR8_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX3GCR8_DX3GCR8_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX3GCR8_DX3GCR8_X4DXREFISELR3(x) (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX3GCR8_DX3GCR8_X4DXREFISELR3_M  GENMASK(29, 24)
#define DDR_PHY_DX3GCR8_DX3GCR8_X4DXREFISELR3_X(x)\
	(((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX3GCR8_DX3GCR8_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX3GCR8_DX3GCR8_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX3GCR8_DX3GCR8_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3GCR9 */
#define DDR_PHY_DX3GCR9(t)        (t + 0xa24)

#define DDR_PHY_DX3GCR9_DX3GCR9_X4DXDQVREFR0(x)  ((x) & GENMASK(5, 0))
#define DDR_PHY_DX3GCR9_DX3GCR9_X4DXDQVREFR0_M   GENMASK(5, 0)
#define DDR_PHY_DX3GCR9_DX3GCR9_X4DXDQVREFR0_X(x) ((x) & GENMASK(5, 0))

#define DDR_PHY_DX3GCR9_DX3GCR9_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX3GCR9_DX3GCR9_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX3GCR9_DX3GCR9_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX3GCR9_DX3GCR9_X4DXDQVREFR1(x)  (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX3GCR9_DX3GCR9_X4DXDQVREFR1_M   GENMASK(13, 8)
#define DDR_PHY_DX3GCR9_DX3GCR9_X4DXDQVREFR1_X(x) (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX3GCR9_DX3GCR9_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX3GCR9_DX3GCR9_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX3GCR9_DX3GCR9_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX3GCR9_DX3GCR9_X4DXDQVREFR2(x)  (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX3GCR9_DX3GCR9_X4DXDQVREFR2_M   GENMASK(21, 16)
#define DDR_PHY_DX3GCR9_DX3GCR9_X4DXDQVREFR2_X(x)\
	(((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX3GCR9_DX3GCR9_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX3GCR9_DX3GCR9_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX3GCR9_DX3GCR9_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX3GCR9_DX3GCR9_X4DXDQVREFR3(x)  (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX3GCR9_DX3GCR9_X4DXDQVREFR3_M   GENMASK(29, 24)
#define DDR_PHY_DX3GCR9_DX3GCR9_X4DXDQVREFR3_X(x)\
	(((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX3GCR9_DX3GCR9_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX3GCR9_DX3GCR9_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX3GCR9_DX3GCR9_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3BDLR0 */
#define DDR_PHY_DX3BDLR0(t)       (t + 0xa40)

#define DDR_PHY_DX3BDLR0_DX3BDLR0_DQ0WBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX3BDLR0_DX3BDLR0_DQ0WBD_M       GENMASK(5, 0)
#define DDR_PHY_DX3BDLR0_DX3BDLR0_DQ0WBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX3BDLR0_DX3BDLR0_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX3BDLR0_DX3BDLR0_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX3BDLR0_DX3BDLR0_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX3BDLR0_DX3BDLR0_DQ1WBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX3BDLR0_DX3BDLR0_DQ1WBD_M       GENMASK(13, 8)
#define DDR_PHY_DX3BDLR0_DX3BDLR0_DQ1WBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX3BDLR0_DX3BDLR0_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX3BDLR0_DX3BDLR0_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX3BDLR0_DX3BDLR0_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX3BDLR0_DX3BDLR0_DQ2WBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX3BDLR0_DX3BDLR0_DQ2WBD_M       GENMASK(21, 16)
#define DDR_PHY_DX3BDLR0_DX3BDLR0_DQ2WBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX3BDLR0_DX3BDLR0_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX3BDLR0_DX3BDLR0_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX3BDLR0_DX3BDLR0_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX3BDLR0_DX3BDLR0_DQ3WBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX3BDLR0_DX3BDLR0_DQ3WBD_M       GENMASK(29, 24)
#define DDR_PHY_DX3BDLR0_DX3BDLR0_DQ3WBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX3BDLR0_DX3BDLR0_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX3BDLR0_DX3BDLR0_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX3BDLR0_DX3BDLR0_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3BDLR1 */
#define DDR_PHY_DX3BDLR1(t)       (t + 0xa44)

#define DDR_PHY_DX3BDLR1_DX3BDLR1_DQ4WBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX3BDLR1_DX3BDLR1_DQ4WBD_M       GENMASK(5, 0)
#define DDR_PHY_DX3BDLR1_DX3BDLR1_DQ4WBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX3BDLR1_DX3BDLR1_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX3BDLR1_DX3BDLR1_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX3BDLR1_DX3BDLR1_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX3BDLR1_DX3BDLR1_DQ5WBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX3BDLR1_DX3BDLR1_DQ5WBD_M       GENMASK(13, 8)
#define DDR_PHY_DX3BDLR1_DX3BDLR1_DQ5WBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX3BDLR1_DX3BDLR1_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX3BDLR1_DX3BDLR1_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX3BDLR1_DX3BDLR1_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX3BDLR1_DX3BDLR1_DQ6WBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX3BDLR1_DX3BDLR1_DQ6WBD_M       GENMASK(21, 16)
#define DDR_PHY_DX3BDLR1_DX3BDLR1_DQ6WBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX3BDLR1_DX3BDLR1_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX3BDLR1_DX3BDLR1_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX3BDLR1_DX3BDLR1_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX3BDLR1_DX3BDLR1_DQ7WBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX3BDLR1_DX3BDLR1_DQ7WBD_M       GENMASK(29, 24)
#define DDR_PHY_DX3BDLR1_DX3BDLR1_DQ7WBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX3BDLR1_DX3BDLR1_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX3BDLR1_DX3BDLR1_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX3BDLR1_DX3BDLR1_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3BDLR2 */
#define DDR_PHY_DX3BDLR2(t)       (t + 0xa48)

#define DDR_PHY_DX3BDLR2_DX3BDLR2_DMWBD(x)       ((x) & GENMASK(5, 0))
#define DDR_PHY_DX3BDLR2_DX3BDLR2_DMWBD_M        GENMASK(5, 0)
#define DDR_PHY_DX3BDLR2_DX3BDLR2_DMWBD_X(x)     ((x) & GENMASK(5, 0))

#define DDR_PHY_DX3BDLR2_DX3BDLR2_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX3BDLR2_DX3BDLR2_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX3BDLR2_DX3BDLR2_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX3BDLR2_DX3BDLR2_DSWBD(x)       (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX3BDLR2_DX3BDLR2_DSWBD_M        GENMASK(13, 8)
#define DDR_PHY_DX3BDLR2_DX3BDLR2_DSWBD_X(x)     (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX3BDLR2_DX3BDLR2_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX3BDLR2_DX3BDLR2_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX3BDLR2_DX3BDLR2_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX3BDLR2_DX3BDLR2_DSOEBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX3BDLR2_DX3BDLR2_DSOEBD_M       GENMASK(21, 16)
#define DDR_PHY_DX3BDLR2_DX3BDLR2_DSOEBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX3BDLR2_DX3BDLR2_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX3BDLR2_DX3BDLR2_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX3BDLR2_DX3BDLR2_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3BDLR3 */
#define DDR_PHY_DX3BDLR3(t)       (t + 0xa50)

#define DDR_PHY_DX3BDLR3_DX3BDLR3_DQ0RBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX3BDLR3_DX3BDLR3_DQ0RBD_M       GENMASK(5, 0)
#define DDR_PHY_DX3BDLR3_DX3BDLR3_DQ0RBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX3BDLR3_DX3BDLR3_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX3BDLR3_DX3BDLR3_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX3BDLR3_DX3BDLR3_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX3BDLR3_DX3BDLR3_DQ1RBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX3BDLR3_DX3BDLR3_DQ1RBD_M       GENMASK(13, 8)
#define DDR_PHY_DX3BDLR3_DX3BDLR3_DQ1RBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX3BDLR3_DX3BDLR3_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX3BDLR3_DX3BDLR3_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX3BDLR3_DX3BDLR3_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX3BDLR3_DX3BDLR3_DQ2RBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX3BDLR3_DX3BDLR3_DQ2RBD_M       GENMASK(21, 16)
#define DDR_PHY_DX3BDLR3_DX3BDLR3_DQ2RBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX3BDLR3_DX3BDLR3_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX3BDLR3_DX3BDLR3_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX3BDLR3_DX3BDLR3_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX3BDLR3_DX3BDLR3_DQ3RBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX3BDLR3_DX3BDLR3_DQ3RBD_M       GENMASK(29, 24)
#define DDR_PHY_DX3BDLR3_DX3BDLR3_DQ3RBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX3BDLR3_DX3BDLR3_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX3BDLR3_DX3BDLR3_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX3BDLR3_DX3BDLR3_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3BDLR4 */
#define DDR_PHY_DX3BDLR4(t)       (t + 0xa54)

#define DDR_PHY_DX3BDLR4_DX3BDLR4_DQ4RBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX3BDLR4_DX3BDLR4_DQ4RBD_M       GENMASK(5, 0)
#define DDR_PHY_DX3BDLR4_DX3BDLR4_DQ4RBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX3BDLR4_DX3BDLR4_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX3BDLR4_DX3BDLR4_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX3BDLR4_DX3BDLR4_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX3BDLR4_DX3BDLR4_DQ5RBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX3BDLR4_DX3BDLR4_DQ5RBD_M       GENMASK(13, 8)
#define DDR_PHY_DX3BDLR4_DX3BDLR4_DQ5RBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX3BDLR4_DX3BDLR4_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX3BDLR4_DX3BDLR4_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX3BDLR4_DX3BDLR4_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX3BDLR4_DX3BDLR4_DQ6RBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX3BDLR4_DX3BDLR4_DQ6RBD_M       GENMASK(21, 16)
#define DDR_PHY_DX3BDLR4_DX3BDLR4_DQ6RBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX3BDLR4_DX3BDLR4_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX3BDLR4_DX3BDLR4_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX3BDLR4_DX3BDLR4_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX3BDLR4_DX3BDLR4_DQ7RBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX3BDLR4_DX3BDLR4_DQ7RBD_M       GENMASK(29, 24)
#define DDR_PHY_DX3BDLR4_DX3BDLR4_DQ7RBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX3BDLR4_DX3BDLR4_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX3BDLR4_DX3BDLR4_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX3BDLR4_DX3BDLR4_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3BDLR5 */
#define DDR_PHY_DX3BDLR5(t)       (t + 0xa58)

#define DDR_PHY_DX3BDLR5_DX3BDLR5_DMRBD(x)       ((x) & GENMASK(5, 0))
#define DDR_PHY_DX3BDLR5_DX3BDLR5_DMRBD_M        GENMASK(5, 0)
#define DDR_PHY_DX3BDLR5_DX3BDLR5_DMRBD_X(x)     ((x) & GENMASK(5, 0))

#define DDR_PHY_DX3BDLR5_DX3BDLR5_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX3BDLR5_DX3BDLR5_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX3BDLR5_DX3BDLR5_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX3BDLR5_DX3BDLR5_DSRBD(x)       (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX3BDLR5_DX3BDLR5_DSRBD_M        GENMASK(13, 8)
#define DDR_PHY_DX3BDLR5_DX3BDLR5_DSRBD_X(x)     (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX3BDLR5_DX3BDLR5_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX3BDLR5_DX3BDLR5_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX3BDLR5_DX3BDLR5_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX3BDLR5_DX3BDLR5_DSNRBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX3BDLR5_DX3BDLR5_DSNRBD_M       GENMASK(21, 16)
#define DDR_PHY_DX3BDLR5_DX3BDLR5_DSNRBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX3BDLR5_DX3BDLR5_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX3BDLR5_DX3BDLR5_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX3BDLR5_DX3BDLR5_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3BDLR6 */
#define DDR_PHY_DX3BDLR6(t)       (t + 0xa60)

#define DDR_PHY_DX3BDLR6_DX3BDLR6_RESERVED_7_0(x) ((x) & GENMASK(7, 0))
#define DDR_PHY_DX3BDLR6_DX3BDLR6_RESERVED_7_0_M GENMASK(7, 0)
#define DDR_PHY_DX3BDLR6_DX3BDLR6_RESERVED_7_0_X(x) ((x) & GENMASK(7, 0))

#define DDR_PHY_DX3BDLR6_DX3BDLR6_PDRBD(x)       (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX3BDLR6_DX3BDLR6_PDRBD_M        GENMASK(13, 8)
#define DDR_PHY_DX3BDLR6_DX3BDLR6_PDRBD_X(x)     (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX3BDLR6_DX3BDLR6_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX3BDLR6_DX3BDLR6_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX3BDLR6_DX3BDLR6_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX3BDLR6_DX3BDLR6_TERBD(x)       (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX3BDLR6_DX3BDLR6_TERBD_M        GENMASK(21, 16)
#define DDR_PHY_DX3BDLR6_DX3BDLR6_TERBD_X(x)     (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX3BDLR6_DX3BDLR6_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX3BDLR6_DX3BDLR6_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX3BDLR6_DX3BDLR6_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3BDLR7 */
#define DDR_PHY_DX3BDLR7(t)       (t + 0xa64)

#define DDR_PHY_DX3BDLR7_DX3BDLR7_X4DMWBD(x)     ((x) & GENMASK(5, 0))
#define DDR_PHY_DX3BDLR7_DX3BDLR7_X4DMWBD_M      GENMASK(5, 0)
#define DDR_PHY_DX3BDLR7_DX3BDLR7_X4DMWBD_X(x)   ((x) & GENMASK(5, 0))

#define DDR_PHY_DX3BDLR7_DX3BDLR7_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX3BDLR7_DX3BDLR7_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX3BDLR7_DX3BDLR7_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX3BDLR7_DX3BDLR7_X4DSWBD(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX3BDLR7_DX3BDLR7_X4DSWBD_M      GENMASK(13, 8)
#define DDR_PHY_DX3BDLR7_DX3BDLR7_X4DSWBD_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX3BDLR7_DX3BDLR7_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX3BDLR7_DX3BDLR7_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX3BDLR7_DX3BDLR7_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX3BDLR7_DX3BDLR7_X4DSOEBD(x)    (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX3BDLR7_DX3BDLR7_X4DSOEBD_M     GENMASK(21, 16)
#define DDR_PHY_DX3BDLR7_DX3BDLR7_X4DSOEBD_X(x)  (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX3BDLR7_DX3BDLR7_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX3BDLR7_DX3BDLR7_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX3BDLR7_DX3BDLR7_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3BDLR8 */
#define DDR_PHY_DX3BDLR8(t)       (t + 0xa68)

#define DDR_PHY_DX3BDLR8_DX3BDLR8_X4DMRBD(x)     ((x) & GENMASK(5, 0))
#define DDR_PHY_DX3BDLR8_DX3BDLR8_X4DMRBD_M      GENMASK(5, 0)
#define DDR_PHY_DX3BDLR8_DX3BDLR8_X4DMRBD_X(x)   ((x) & GENMASK(5, 0))

#define DDR_PHY_DX3BDLR8_DX3BDLR8_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX3BDLR8_DX3BDLR8_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX3BDLR8_DX3BDLR8_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX3BDLR8_DX3BDLR8_X4DSRBD(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX3BDLR8_DX3BDLR8_X4DSRBD_M      GENMASK(13, 8)
#define DDR_PHY_DX3BDLR8_DX3BDLR8_X4DSRBD_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX3BDLR8_DX3BDLR8_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX3BDLR8_DX3BDLR8_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX3BDLR8_DX3BDLR8_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX3BDLR8_DX3BDLR8_X4DSNRBD(x)    (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX3BDLR8_DX3BDLR8_X4DSNRBD_M     GENMASK(21, 16)
#define DDR_PHY_DX3BDLR8_DX3BDLR8_X4DSNRBD_X(x)  (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX3BDLR8_DX3BDLR8_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX3BDLR8_DX3BDLR8_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX3BDLR8_DX3BDLR8_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3BDLR9 */
#define DDR_PHY_DX3BDLR9(t)       (t + 0xa6c)

#define DDR_PHY_DX3BDLR9_DX3BDLR9_RESERVED_7_0(x) ((x) & GENMASK(7, 0))
#define DDR_PHY_DX3BDLR9_DX3BDLR9_RESERVED_7_0_M GENMASK(7, 0)
#define DDR_PHY_DX3BDLR9_DX3BDLR9_RESERVED_7_0_X(x) ((x) & GENMASK(7, 0))

#define DDR_PHY_DX3BDLR9_DX3BDLR9_X4PDRBD(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX3BDLR9_DX3BDLR9_X4PDRBD_M      GENMASK(13, 8)
#define DDR_PHY_DX3BDLR9_DX3BDLR9_X4PDRBD_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX3BDLR9_DX3BDLR9_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX3BDLR9_DX3BDLR9_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX3BDLR9_DX3BDLR9_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX3BDLR9_DX3BDLR9_X4TERBD(x)     (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX3BDLR9_DX3BDLR9_X4TERBD_M      GENMASK(21, 16)
#define DDR_PHY_DX3BDLR9_DX3BDLR9_X4TERBD_X(x)   (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX3BDLR9_DX3BDLR9_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX3BDLR9_DX3BDLR9_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX3BDLR9_DX3BDLR9_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3LCDLR0 */
#define DDR_PHY_DX3LCDLR0(t)      (t + 0xa80)

#define DDR_PHY_DX3LCDLR0_DX3LCDLR0_WLD(x)       ((x) & GENMASK(8, 0))
#define DDR_PHY_DX3LCDLR0_DX3LCDLR0_WLD_M        GENMASK(8, 0)
#define DDR_PHY_DX3LCDLR0_DX3LCDLR0_WLD_X(x)     ((x) & GENMASK(8, 0))

#define DDR_PHY_DX3LCDLR0_DX3LCDLR0_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX3LCDLR0_DX3LCDLR0_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX3LCDLR0_DX3LCDLR0_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX3LCDLR0_DX3LCDLR0_X4WLD(x)     (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX3LCDLR0_DX3LCDLR0_X4WLD_M      GENMASK(24, 16)
#define DDR_PHY_DX3LCDLR0_DX3LCDLR0_X4WLD_X(x)   (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX3LCDLR0_DX3LCDLR0_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX3LCDLR0_DX3LCDLR0_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX3LCDLR0_DX3LCDLR0_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3LCDLR1 */
#define DDR_PHY_DX3LCDLR1(t)      (t + 0xa84)

#define DDR_PHY_DX3LCDLR1_DX3LCDLR1_WDQD(x)      ((x) & GENMASK(8, 0))
#define DDR_PHY_DX3LCDLR1_DX3LCDLR1_WDQD_M       GENMASK(8, 0)
#define DDR_PHY_DX3LCDLR1_DX3LCDLR1_WDQD_X(x)    ((x) & GENMASK(8, 0))

#define DDR_PHY_DX3LCDLR1_DX3LCDLR1_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX3LCDLR1_DX3LCDLR1_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX3LCDLR1_DX3LCDLR1_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX3LCDLR1_DX3LCDLR1_X4WDQD(x)    (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX3LCDLR1_DX3LCDLR1_X4WDQD_M     GENMASK(24, 16)
#define DDR_PHY_DX3LCDLR1_DX3LCDLR1_X4WDQD_X(x)  (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX3LCDLR1_DX3LCDLR1_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX3LCDLR1_DX3LCDLR1_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX3LCDLR1_DX3LCDLR1_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3LCDLR2 */
#define DDR_PHY_DX3LCDLR2(t)      (t + 0xa88)

#define DDR_PHY_DX3LCDLR2_DX3LCDLR2_DQSGD(x)     ((x) & GENMASK(8, 0))
#define DDR_PHY_DX3LCDLR2_DX3LCDLR2_DQSGD_M      GENMASK(8, 0)
#define DDR_PHY_DX3LCDLR2_DX3LCDLR2_DQSGD_X(x)   ((x) & GENMASK(8, 0))

#define DDR_PHY_DX3LCDLR2_DX3LCDLR2_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX3LCDLR2_DX3LCDLR2_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX3LCDLR2_DX3LCDLR2_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX3LCDLR2_DX3LCDLR2_X4DQSGD(x)   (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX3LCDLR2_DX3LCDLR2_X4DQSGD_M    GENMASK(24, 16)
#define DDR_PHY_DX3LCDLR2_DX3LCDLR2_X4DQSGD_X(x) (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX3LCDLR2_DX3LCDLR2_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX3LCDLR2_DX3LCDLR2_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX3LCDLR2_DX3LCDLR2_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3LCDLR3 */
#define DDR_PHY_DX3LCDLR3(t)      (t + 0xa8c)

#define DDR_PHY_DX3LCDLR3_DX3LCDLR3_RDQSD(x)     ((x) & GENMASK(8, 0))
#define DDR_PHY_DX3LCDLR3_DX3LCDLR3_RDQSD_M      GENMASK(8, 0)
#define DDR_PHY_DX3LCDLR3_DX3LCDLR3_RDQSD_X(x)   ((x) & GENMASK(8, 0))

#define DDR_PHY_DX3LCDLR3_DX3LCDLR3_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX3LCDLR3_DX3LCDLR3_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX3LCDLR3_DX3LCDLR3_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX3LCDLR3_DX3LCDLR3_X4RDQSD(x)   (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX3LCDLR3_DX3LCDLR3_X4RDQSD_M    GENMASK(24, 16)
#define DDR_PHY_DX3LCDLR3_DX3LCDLR3_X4RDQSD_X(x) (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX3LCDLR3_DX3LCDLR3_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX3LCDLR3_DX3LCDLR3_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX3LCDLR3_DX3LCDLR3_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3LCDLR4 */
#define DDR_PHY_DX3LCDLR4(t)      (t + 0xa90)

#define DDR_PHY_DX3LCDLR4_DX3LCDLR4_RDQSND(x)    ((x) & GENMASK(8, 0))
#define DDR_PHY_DX3LCDLR4_DX3LCDLR4_RDQSND_M     GENMASK(8, 0)
#define DDR_PHY_DX3LCDLR4_DX3LCDLR4_RDQSND_X(x)  ((x) & GENMASK(8, 0))

#define DDR_PHY_DX3LCDLR4_DX3LCDLR4_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX3LCDLR4_DX3LCDLR4_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX3LCDLR4_DX3LCDLR4_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX3LCDLR4_DX3LCDLR4_X4RDQSND(x)  (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX3LCDLR4_DX3LCDLR4_X4RDQSND_M   GENMASK(24, 16)
#define DDR_PHY_DX3LCDLR4_DX3LCDLR4_X4RDQSND_X(x)\
	(((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX3LCDLR4_DX3LCDLR4_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX3LCDLR4_DX3LCDLR4_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX3LCDLR4_DX3LCDLR4_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3LCDLR5 */
#define DDR_PHY_DX3LCDLR5(t)      (t + 0xa94)

#define DDR_PHY_DX3LCDLR5_DX3LCDLR5_DQSGSD(x)    ((x) & GENMASK(8, 0))
#define DDR_PHY_DX3LCDLR5_DX3LCDLR5_DQSGSD_M     GENMASK(8, 0)
#define DDR_PHY_DX3LCDLR5_DX3LCDLR5_DQSGSD_X(x)  ((x) & GENMASK(8, 0))

#define DDR_PHY_DX3LCDLR5_DX3LCDLR5_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX3LCDLR5_DX3LCDLR5_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX3LCDLR5_DX3LCDLR5_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX3LCDLR5_DX3LCDLR5_X4DQSGSD(x)  (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX3LCDLR5_DX3LCDLR5_X4DQSGSD_M   GENMASK(24, 16)
#define DDR_PHY_DX3LCDLR5_DX3LCDLR5_X4DQSGSD_X(x)\
	(((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX3LCDLR5_DX3LCDLR5_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX3LCDLR5_DX3LCDLR5_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX3LCDLR5_DX3LCDLR5_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3MDLR0 */
#define DDR_PHY_DX3MDLR0(t)       (t + 0xaa0)

#define DDR_PHY_DX3MDLR0_DX3MDLR0_IPRD(x)        ((x) & GENMASK(8, 0))
#define DDR_PHY_DX3MDLR0_DX3MDLR0_IPRD_M         GENMASK(8, 0)
#define DDR_PHY_DX3MDLR0_DX3MDLR0_IPRD_X(x)      ((x) & GENMASK(8, 0))

#define DDR_PHY_DX3MDLR0_DX3MDLR0_RESERVED_15_9(x) (((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX3MDLR0_DX3MDLR0_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX3MDLR0_DX3MDLR0_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX3MDLR0_DX3MDLR0_TPRD(x)        (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX3MDLR0_DX3MDLR0_TPRD_M         GENMASK(24, 16)
#define DDR_PHY_DX3MDLR0_DX3MDLR0_TPRD_X(x)      (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX3MDLR0_DX3MDLR0_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX3MDLR0_DX3MDLR0_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX3MDLR0_DX3MDLR0_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3MDLR1 */
#define DDR_PHY_DX3MDLR1(t)       (t + 0xaa4)

#define DDR_PHY_DX3MDLR1_DX3MDLR1_MDLD(x)        ((x) & GENMASK(8, 0))
#define DDR_PHY_DX3MDLR1_DX3MDLR1_MDLD_M         GENMASK(8, 0)
#define DDR_PHY_DX3MDLR1_DX3MDLR1_MDLD_X(x)      ((x) & GENMASK(8, 0))

#define DDR_PHY_DX3MDLR1_DX3MDLR1_RESERVED_31_9(x) (((x) << 9) & GENMASK(31, 9))
#define DDR_PHY_DX3MDLR1_DX3MDLR1_RESERVED_31_9_M GENMASK(31, 9)
#define DDR_PHY_DX3MDLR1_DX3MDLR1_RESERVED_31_9_X(x)\
	(((x) & GENMASK(31, 9)) >> 9)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3GTR0 */
#define DDR_PHY_DX3GTR0(t)        (t + 0xac0)

#define DDR_PHY_DX3GTR0_DX3GTR0_DGSL(x)          ((x) & GENMASK(4, 0))
#define DDR_PHY_DX3GTR0_DX3GTR0_DGSL_M           GENMASK(4, 0)
#define DDR_PHY_DX3GTR0_DX3GTR0_DGSL_X(x)        ((x) & GENMASK(4, 0))

#define DDR_PHY_DX3GTR0_DX3GTR0_RESERVED_7_5(x)  (((x) << 5) & GENMASK(7, 5))
#define DDR_PHY_DX3GTR0_DX3GTR0_RESERVED_7_5_M   GENMASK(7, 5)
#define DDR_PHY_DX3GTR0_DX3GTR0_RESERVED_7_5_X(x) (((x) & GENMASK(7, 5)) >> 5)

#define DDR_PHY_DX3GTR0_DX3GTR0_X4DGSL(x)        (((x) << 8) & GENMASK(12, 8))
#define DDR_PHY_DX3GTR0_DX3GTR0_X4DGSL_M         GENMASK(12, 8)
#define DDR_PHY_DX3GTR0_DX3GTR0_X4DGSL_X(x)      (((x) & GENMASK(12, 8)) >> 8)

#define DDR_PHY_DX3GTR0_DX3GTR0_RESERVED_15_13(x)\
	(((x) << 13) & GENMASK(15, 13))
#define DDR_PHY_DX3GTR0_DX3GTR0_RESERVED_15_13_M GENMASK(15, 13)
#define DDR_PHY_DX3GTR0_DX3GTR0_RESERVED_15_13_X(x)\
	(((x) & GENMASK(15, 13)) >> 13)

#define DDR_PHY_DX3GTR0_DX3GTR0_WLSL(x)          (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DX3GTR0_DX3GTR0_WLSL_M           GENMASK(19, 16)
#define DDR_PHY_DX3GTR0_DX3GTR0_WLSL_X(x)        (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DX3GTR0_DX3GTR0_X4WLSL(x)        (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX3GTR0_DX3GTR0_X4WLSL_M         GENMASK(23, 20)
#define DDR_PHY_DX3GTR0_DX3GTR0_X4WLSL_X(x)      (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX3GTR0_DX3GTR0_RESERVED_31_24(x)\
	(((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_DX3GTR0_DX3GTR0_RESERVED_31_24_M GENMASK(31, 24)
#define DDR_PHY_DX3GTR0_DX3GTR0_RESERVED_31_24_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3RSR0 */
#define DDR_PHY_DX3RSR0(t)        (t + 0xad0)

#define DDR_PHY_DX3RSR0_DX3RSR0_QSGERR(x)        ((x) & GENMASK(15, 0))
#define DDR_PHY_DX3RSR0_DX3RSR0_QSGERR_M         GENMASK(15, 0)
#define DDR_PHY_DX3RSR0_DX3RSR0_QSGERR_X(x)      ((x) & GENMASK(15, 0))

#define DDR_PHY_DX3RSR0_DX3RSR0_X4QSGERR(x)      (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX3RSR0_DX3RSR0_X4QSGERR_M       GENMASK(31, 16)
#define DDR_PHY_DX3RSR0_DX3RSR0_X4QSGERR_X(x)    (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3RSR1 */
#define DDR_PHY_DX3RSR1(t)        (t + 0xad4)

#define DDR_PHY_DX3RSR1_DX3RSR1_RDLVLERR(x)      ((x) & GENMASK(15, 0))
#define DDR_PHY_DX3RSR1_DX3RSR1_RDLVLERR_M       GENMASK(15, 0)
#define DDR_PHY_DX3RSR1_DX3RSR1_RDLVLERR_X(x)    ((x) & GENMASK(15, 0))

#define DDR_PHY_DX3RSR1_DX3RSR1_X4RDLVLERR(x)    (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX3RSR1_DX3RSR1_X4RDLVLERR_M     GENMASK(31, 16)
#define DDR_PHY_DX3RSR1_DX3RSR1_X4RDLVLERR_X(x)  (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3RSR2 */
#define DDR_PHY_DX3RSR2(t)        (t + 0xad8)

#define DDR_PHY_DX3RSR2_DX3RSR2_WLAWN(x)         ((x) & GENMASK(15, 0))
#define DDR_PHY_DX3RSR2_DX3RSR2_WLAWN_M          GENMASK(15, 0)
#define DDR_PHY_DX3RSR2_DX3RSR2_WLAWN_X(x)       ((x) & GENMASK(15, 0))

#define DDR_PHY_DX3RSR2_DX3RSR2_X4WLAWN(x)       (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX3RSR2_DX3RSR2_X4WLAWN_M        GENMASK(31, 16)
#define DDR_PHY_DX3RSR2_DX3RSR2_X4WLAWN_X(x)     (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3RSR3 */
#define DDR_PHY_DX3RSR3(t)        (t + 0xadc)

#define DDR_PHY_DX3RSR3_DX3RSR3_WLAERR(x)        ((x) & GENMASK(15, 0))
#define DDR_PHY_DX3RSR3_DX3RSR3_WLAERR_M         GENMASK(15, 0)
#define DDR_PHY_DX3RSR3_DX3RSR3_WLAERR_X(x)      ((x) & GENMASK(15, 0))

#define DDR_PHY_DX3RSR3_DX3RSR3_X4WLAERR(x)      (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX3RSR3_DX3RSR3_X4WLAERR_M       GENMASK(31, 16)
#define DDR_PHY_DX3RSR3_DX3RSR3_X4WLAERR_X(x)    (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3GSR0 */
#define DDR_PHY_DX3GSR0(t)        (t + 0xae0)

#define DDR_PHY_DX3GSR0_DX3GSR0_WDQCAL(x)        ((x) & GENMASK(0, 0))
#define DDR_PHY_DX3GSR0_DX3GSR0_WDQCAL_M         GENMASK(0, 0)
#define DDR_PHY_DX3GSR0_DX3GSR0_WDQCAL_X(x)      ((x) & GENMASK(0, 0))

#define DDR_PHY_DX3GSR0_DX3GSR0_RDQSCAL(x)       (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX3GSR0_DX3GSR0_RDQSCAL_M        GENMASK(1, 1)
#define DDR_PHY_DX3GSR0_DX3GSR0_RDQSCAL_X(x)     (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX3GSR0_DX3GSR0_RDQSNCAL(x)      (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX3GSR0_DX3GSR0_RDQSNCAL_M       GENMASK(2, 2)
#define DDR_PHY_DX3GSR0_DX3GSR0_RDQSNCAL_X(x)    (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX3GSR0_DX3GSR0_GDQSCAL(x)       (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX3GSR0_DX3GSR0_GDQSCAL_M        GENMASK(3, 3)
#define DDR_PHY_DX3GSR0_DX3GSR0_GDQSCAL_X(x)     (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX3GSR0_DX3GSR0_WLCAL(x)         (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX3GSR0_DX3GSR0_WLCAL_M          GENMASK(4, 4)
#define DDR_PHY_DX3GSR0_DX3GSR0_WLCAL_X(x)       (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX3GSR0_DX3GSR0_WLDONE(x)        (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX3GSR0_DX3GSR0_WLDONE_M         GENMASK(5, 5)
#define DDR_PHY_DX3GSR0_DX3GSR0_WLDONE_X(x)      (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX3GSR0_DX3GSR0_WLERR(x)         (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX3GSR0_DX3GSR0_WLERR_M          GENMASK(6, 6)
#define DDR_PHY_DX3GSR0_DX3GSR0_WLERR_X(x)       (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX3GSR0_DX3GSR0_WLPRD(x)         (((x) << 7) & GENMASK(15, 7))
#define DDR_PHY_DX3GSR0_DX3GSR0_WLPRD_M          GENMASK(15, 7)
#define DDR_PHY_DX3GSR0_DX3GSR0_WLPRD_X(x)       (((x) & GENMASK(15, 7)) >> 7)

#define DDR_PHY_DX3GSR0_DX3GSR0_DPLOCK(x)        (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX3GSR0_DX3GSR0_DPLOCK_M         GENMASK(16, 16)
#define DDR_PHY_DX3GSR0_DX3GSR0_DPLOCK_X(x)      (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX3GSR0_DX3GSR0_GDQSPRD(x)       (((x) << 17) & GENMASK(25, 17))
#define DDR_PHY_DX3GSR0_DX3GSR0_GDQSPRD_M        GENMASK(25, 17)
#define DDR_PHY_DX3GSR0_DX3GSR0_GDQSPRD_X(x)     (((x) & GENMASK(25, 17)) >> 17)

#define DDR_PHY_DX3GSR0_DX3GSR0_WLWN(x)          (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_DX3GSR0_DX3GSR0_WLWN_M           GENMASK(26, 26)
#define DDR_PHY_DX3GSR0_DX3GSR0_WLWN_X(x)        (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_DX3GSR0_DX3GSR0_RESERVED_29_27(x)\
	(((x) << 27) & GENMASK(29, 27))
#define DDR_PHY_DX3GSR0_DX3GSR0_RESERVED_29_27_M GENMASK(29, 27)
#define DDR_PHY_DX3GSR0_DX3GSR0_RESERVED_29_27_X(x)\
	(((x) & GENMASK(29, 27)) >> 27)

#define DDR_PHY_DX3GSR0_DX3GSR0_WLDQ(x)          (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX3GSR0_DX3GSR0_WLDQ_M           GENMASK(30, 30)
#define DDR_PHY_DX3GSR0_DX3GSR0_WLDQ_X(x)        (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX3GSR0_DX3GSR0_RESERVED_31(x)   (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX3GSR0_DX3GSR0_RESERVED_31_M    GENMASK(31, 31)
#define DDR_PHY_DX3GSR0_DX3GSR0_RESERVED_31_X(x) (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3GSR1 */
#define DDR_PHY_DX3GSR1(t)        (t + 0xae4)

#define DDR_PHY_DX3GSR1_DX3GSR1_DLTDONE(x)       ((x) & GENMASK(0, 0))
#define DDR_PHY_DX3GSR1_DX3GSR1_DLTDONE_M        GENMASK(0, 0)
#define DDR_PHY_DX3GSR1_DX3GSR1_DLTDONE_X(x)     ((x) & GENMASK(0, 0))

#define DDR_PHY_DX3GSR1_DX3GSR1_DLTCODE(x)       (((x) << 1) & GENMASK(24, 1))
#define DDR_PHY_DX3GSR1_DX3GSR1_DLTCODE_M        GENMASK(24, 1)
#define DDR_PHY_DX3GSR1_DX3GSR1_DLTCODE_X(x)     (((x) & GENMASK(24, 1)) >> 1)

#define DDR_PHY_DX3GSR1_DX3GSR1_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX3GSR1_DX3GSR1_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX3GSR1_DX3GSR1_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3GSR2 */
#define DDR_PHY_DX3GSR2(t)        (t + 0xae8)

#define DDR_PHY_DX3GSR2_DX3GSR2_RDERR(x)         ((x) & GENMASK(0, 0))
#define DDR_PHY_DX3GSR2_DX3GSR2_RDERR_M          GENMASK(0, 0)
#define DDR_PHY_DX3GSR2_DX3GSR2_RDERR_X(x)       ((x) & GENMASK(0, 0))

#define DDR_PHY_DX3GSR2_DX3GSR2_RDWN(x)          (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX3GSR2_DX3GSR2_RDWN_M           GENMASK(1, 1)
#define DDR_PHY_DX3GSR2_DX3GSR2_RDWN_X(x)        (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX3GSR2_DX3GSR2_WDERR(x)         (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX3GSR2_DX3GSR2_WDERR_M          GENMASK(2, 2)
#define DDR_PHY_DX3GSR2_DX3GSR2_WDERR_X(x)       (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX3GSR2_DX3GSR2_WDWN(x)          (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX3GSR2_DX3GSR2_WDWN_M           GENMASK(3, 3)
#define DDR_PHY_DX3GSR2_DX3GSR2_WDWN_X(x)        (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX3GSR2_DX3GSR2_REERR(x)         (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX3GSR2_DX3GSR2_REERR_M          GENMASK(4, 4)
#define DDR_PHY_DX3GSR2_DX3GSR2_REERR_X(x)       (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX3GSR2_DX3GSR2_REWN(x)          (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX3GSR2_DX3GSR2_REWN_M           GENMASK(5, 5)
#define DDR_PHY_DX3GSR2_DX3GSR2_REWN_X(x)        (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX3GSR2_DX3GSR2_WEERR(x)         (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX3GSR2_DX3GSR2_WEERR_M          GENMASK(6, 6)
#define DDR_PHY_DX3GSR2_DX3GSR2_WEERR_X(x)       (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX3GSR2_DX3GSR2_WEWN(x)          (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_DX3GSR2_DX3GSR2_WEWN_M           GENMASK(7, 7)
#define DDR_PHY_DX3GSR2_DX3GSR2_WEWN_X(x)        (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_DX3GSR2_DX3GSR2_ESTAT(x)         (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX3GSR2_DX3GSR2_ESTAT_M          GENMASK(11, 8)
#define DDR_PHY_DX3GSR2_DX3GSR2_ESTAT_X(x)       (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX3GSR2_DX3GSR2_DBDQ(x)          (((x) << 12) & GENMASK(19, 12))
#define DDR_PHY_DX3GSR2_DX3GSR2_DBDQ_M           GENMASK(19, 12)
#define DDR_PHY_DX3GSR2_DX3GSR2_DBDQ_X(x)        (((x) & GENMASK(19, 12)) >> 12)

#define DDR_PHY_DX3GSR2_DX3GSR2_SRDERR(x)        (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX3GSR2_DX3GSR2_SRDERR_M         GENMASK(20, 20)
#define DDR_PHY_DX3GSR2_DX3GSR2_SRDERR_X(x)      (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX3GSR2_DX3GSR2_RESERVED_21(x)   (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX3GSR2_DX3GSR2_RESERVED_21_M    GENMASK(21, 21)
#define DDR_PHY_DX3GSR2_DX3GSR2_RESERVED_21_X(x) (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX3GSR2_DX3GSR2_GSDQSCAL(x)      (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX3GSR2_DX3GSR2_GSDQSCAL_M       GENMASK(22, 22)
#define DDR_PHY_DX3GSR2_DX3GSR2_GSDQSCAL_X(x)    (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX3GSR2_DX3GSR2_GSDQSPRD(x)      (((x) << 23) & GENMASK(31, 23))
#define DDR_PHY_DX3GSR2_DX3GSR2_GSDQSPRD_M       GENMASK(31, 23)
#define DDR_PHY_DX3GSR2_DX3GSR2_GSDQSPRD_X(x)    (((x) & GENMASK(31, 23)) >> 23)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3GSR3 */
#define DDR_PHY_DX3GSR3(t)        (t + 0xaec)

#define DDR_PHY_DX3GSR3_DX3GSR3_SRDPC(x)         ((x) & GENMASK(1, 0))
#define DDR_PHY_DX3GSR3_DX3GSR3_SRDPC_M          GENMASK(1, 0)
#define DDR_PHY_DX3GSR3_DX3GSR3_SRDPC_X(x)       ((x) & GENMASK(1, 0))

#define DDR_PHY_DX3GSR3_DX3GSR3_RESERVED_7_2(x)  (((x) << 2) & GENMASK(7, 2))
#define DDR_PHY_DX3GSR3_DX3GSR3_RESERVED_7_2_M   GENMASK(7, 2)
#define DDR_PHY_DX3GSR3_DX3GSR3_RESERVED_7_2_X(x) (((x) & GENMASK(7, 2)) >> 2)

#define DDR_PHY_DX3GSR3_DX3GSR3_HVERR(x)         (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX3GSR3_DX3GSR3_HVERR_M          GENMASK(11, 8)
#define DDR_PHY_DX3GSR3_DX3GSR3_HVERR_X(x)       (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX3GSR3_DX3GSR3_HVWRN(x)         (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_DX3GSR3_DX3GSR3_HVWRN_M          GENMASK(15, 12)
#define DDR_PHY_DX3GSR3_DX3GSR3_HVWRN_X(x)       (((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_DX3GSR3_DX3GSR3_DVERR(x)         (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DX3GSR3_DX3GSR3_DVERR_M          GENMASK(19, 16)
#define DDR_PHY_DX3GSR3_DX3GSR3_DVERR_X(x)       (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DX3GSR3_DX3GSR3_DVWRN(x)         (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX3GSR3_DX3GSR3_DVWRN_M          GENMASK(23, 20)
#define DDR_PHY_DX3GSR3_DX3GSR3_DVWRN_X(x)       (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX3GSR3_DX3GSR3_ESTAT(x)         (((x) << 24) & GENMASK(26, 24))
#define DDR_PHY_DX3GSR3_DX3GSR3_ESTAT_M          GENMASK(26, 24)
#define DDR_PHY_DX3GSR3_DX3GSR3_ESTAT_X(x)       (((x) & GENMASK(26, 24)) >> 24)

#define DDR_PHY_DX3GSR3_DX3GSR3_RESERVED_31_27(x)\
	(((x) << 27) & GENMASK(31, 27))
#define DDR_PHY_DX3GSR3_DX3GSR3_RESERVED_31_27_M GENMASK(31, 27)
#define DDR_PHY_DX3GSR3_DX3GSR3_RESERVED_31_27_X(x)\
	(((x) & GENMASK(31, 27)) >> 27)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3GSR4 */
#define DDR_PHY_DX3GSR4(t)        (t + 0xaf0)

#define DDR_PHY_DX3GSR4_DX3GSR4_X4WDQCAL(x)      ((x) & GENMASK(0, 0))
#define DDR_PHY_DX3GSR4_DX3GSR4_X4WDQCAL_M       GENMASK(0, 0)
#define DDR_PHY_DX3GSR4_DX3GSR4_X4WDQCAL_X(x)    ((x) & GENMASK(0, 0))

#define DDR_PHY_DX3GSR4_DX3GSR4_X4RDQSCAL(x)     (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX3GSR4_DX3GSR4_X4RDQSCAL_M      GENMASK(1, 1)
#define DDR_PHY_DX3GSR4_DX3GSR4_X4RDQSCAL_X(x)   (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX3GSR4_DX3GSR4_X4RDQSNCAL(x)    (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX3GSR4_DX3GSR4_X4RDQSNCAL_M     GENMASK(2, 2)
#define DDR_PHY_DX3GSR4_DX3GSR4_X4RDQSNCAL_X(x)  (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX3GSR4_DX3GSR4_X4GDQSCAL(x)     (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX3GSR4_DX3GSR4_X4GDQSCAL_M      GENMASK(3, 3)
#define DDR_PHY_DX3GSR4_DX3GSR4_X4GDQSCAL_X(x)   (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX3GSR4_DX3GSR4_X4WLCAL(x)       (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX3GSR4_DX3GSR4_X4WLCAL_M        GENMASK(4, 4)
#define DDR_PHY_DX3GSR4_DX3GSR4_X4WLCAL_X(x)     (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX3GSR4_DX3GSR4_X4WLDONE(x)      (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX3GSR4_DX3GSR4_X4WLDONE_M       GENMASK(5, 5)
#define DDR_PHY_DX3GSR4_DX3GSR4_X4WLDONE_X(x)    (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX3GSR4_DX3GSR4_X4WLERR(x)       (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX3GSR4_DX3GSR4_X4WLERR_M        GENMASK(6, 6)
#define DDR_PHY_DX3GSR4_DX3GSR4_X4WLERR_X(x)     (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX3GSR4_DX3GSR4_X4WLPRD(x)       (((x) << 7) & GENMASK(15, 7))
#define DDR_PHY_DX3GSR4_DX3GSR4_X4WLPRD_M        GENMASK(15, 7)
#define DDR_PHY_DX3GSR4_DX3GSR4_X4WLPRD_X(x)     (((x) & GENMASK(15, 7)) >> 7)

#define DDR_PHY_DX3GSR4_DX3GSR4_X4DPLOCK(x)      (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX3GSR4_DX3GSR4_X4DPLOCK_M       GENMASK(16, 16)
#define DDR_PHY_DX3GSR4_DX3GSR4_X4DPLOCK_X(x)    (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX3GSR4_DX3GSR4_X4GDQSPRD(x)     (((x) << 17) & GENMASK(25, 17))
#define DDR_PHY_DX3GSR4_DX3GSR4_X4GDQSPRD_M      GENMASK(25, 17)
#define DDR_PHY_DX3GSR4_DX3GSR4_X4GDQSPRD_X(x)   (((x) & GENMASK(25, 17)) >> 17)

#define DDR_PHY_DX3GSR4_DX3GSR4_X4WLWN(x)        (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_DX3GSR4_DX3GSR4_X4WLWN_M         GENMASK(26, 26)
#define DDR_PHY_DX3GSR4_DX3GSR4_X4WLWN_X(x)      (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_DX3GSR4_DX3GSR4_RESERVED_29_27(x)\
	(((x) << 27) & GENMASK(29, 27))
#define DDR_PHY_DX3GSR4_DX3GSR4_RESERVED_29_27_M GENMASK(29, 27)
#define DDR_PHY_DX3GSR4_DX3GSR4_RESERVED_29_27_X(x)\
	(((x) & GENMASK(29, 27)) >> 27)

#define DDR_PHY_DX3GSR4_DX3GSR4_X4WLDQ(x)        (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX3GSR4_DX3GSR4_X4WLDQ_M         GENMASK(30, 30)
#define DDR_PHY_DX3GSR4_DX3GSR4_X4WLDQ_X(x)      (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX3GSR4_DX3GSR4_RESERVED_31(x)   (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX3GSR4_DX3GSR4_RESERVED_31_M    GENMASK(31, 31)
#define DDR_PHY_DX3GSR4_DX3GSR4_RESERVED_31_X(x) (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3GSR5 */
#define DDR_PHY_DX3GSR5(t)        (t + 0xaf4)

#define DDR_PHY_DX3GSR5_DX3GSR5_X4RDERR(x)       ((x) & GENMASK(0, 0))
#define DDR_PHY_DX3GSR5_DX3GSR5_X4RDERR_M        GENMASK(0, 0)
#define DDR_PHY_DX3GSR5_DX3GSR5_X4RDERR_X(x)     ((x) & GENMASK(0, 0))

#define DDR_PHY_DX3GSR5_DX3GSR5_X4RDWN(x)        (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX3GSR5_DX3GSR5_X4RDWN_M         GENMASK(1, 1)
#define DDR_PHY_DX3GSR5_DX3GSR5_X4RDWN_X(x)      (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX3GSR5_DX3GSR5_X4WDERR(x)       (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX3GSR5_DX3GSR5_X4WDERR_M        GENMASK(2, 2)
#define DDR_PHY_DX3GSR5_DX3GSR5_X4WDERR_X(x)     (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX3GSR5_DX3GSR5_X4WDWN(x)        (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX3GSR5_DX3GSR5_X4WDWN_M         GENMASK(3, 3)
#define DDR_PHY_DX3GSR5_DX3GSR5_X4WDWN_X(x)      (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX3GSR5_DX3GSR5_X4REERR(x)       (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX3GSR5_DX3GSR5_X4REERR_M        GENMASK(4, 4)
#define DDR_PHY_DX3GSR5_DX3GSR5_X4REERR_X(x)     (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX3GSR5_DX3GSR5_X4REWN(x)        (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX3GSR5_DX3GSR5_X4REWN_M         GENMASK(5, 5)
#define DDR_PHY_DX3GSR5_DX3GSR5_X4REWN_X(x)      (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX3GSR5_DX3GSR5_X4WEERR(x)       (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX3GSR5_DX3GSR5_X4WEERR_M        GENMASK(6, 6)
#define DDR_PHY_DX3GSR5_DX3GSR5_X4WEERR_X(x)     (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX3GSR5_DX3GSR5_X4WEWN(x)        (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_DX3GSR5_DX3GSR5_X4WEWN_M         GENMASK(7, 7)
#define DDR_PHY_DX3GSR5_DX3GSR5_X4WEWN_X(x)      (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_DX3GSR5_DX3GSR5_X4ESTAT(x)       (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX3GSR5_DX3GSR5_X4ESTAT_M        GENMASK(11, 8)
#define DDR_PHY_DX3GSR5_DX3GSR5_X4ESTAT_X(x)     (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX3GSR5_DX3GSR5_RESERVED_19_12(x)\
	(((x) << 12) & GENMASK(19, 12))
#define DDR_PHY_DX3GSR5_DX3GSR5_RESERVED_19_12_M GENMASK(19, 12)
#define DDR_PHY_DX3GSR5_DX3GSR5_RESERVED_19_12_X(x)\
	(((x) & GENMASK(19, 12)) >> 12)

#define DDR_PHY_DX3GSR5_DX3GSR5_X4SRDERR(x)      (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX3GSR5_DX3GSR5_X4SRDERR_M       GENMASK(20, 20)
#define DDR_PHY_DX3GSR5_DX3GSR5_X4SRDERR_X(x)    (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX3GSR5_DX3GSR5_RESERVED_21(x)   (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX3GSR5_DX3GSR5_RESERVED_21_M    GENMASK(21, 21)
#define DDR_PHY_DX3GSR5_DX3GSR5_RESERVED_21_X(x) (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX3GSR5_DX3GSR5_X4GSDQSCAL(x)    (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX3GSR5_DX3GSR5_X4GSDQSCAL_M     GENMASK(22, 22)
#define DDR_PHY_DX3GSR5_DX3GSR5_X4GSDQSCAL_X(x)  (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX3GSR5_DX3GSR5_X4GSDQSPRD(x)    (((x) << 23) & GENMASK(31, 23))
#define DDR_PHY_DX3GSR5_DX3GSR5_X4GSDQSPRD_M     GENMASK(31, 23)
#define DDR_PHY_DX3GSR5_DX3GSR5_X4GSDQSPRD_X(x)  (((x) & GENMASK(31, 23)) >> 23)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX3GSR6 */
#define DDR_PHY_DX3GSR6(t)        (t + 0xaf8)

#define DDR_PHY_DX3GSR6_DX3GSR6_RESERVED_1_0(x)  ((x) & GENMASK(1, 0))
#define DDR_PHY_DX3GSR6_DX3GSR6_RESERVED_1_0_M   GENMASK(1, 0)
#define DDR_PHY_DX3GSR6_DX3GSR6_RESERVED_1_0_X(x) ((x) & GENMASK(1, 0))

#define DDR_PHY_DX3GSR6_DX3GSR6_X4SRDPC(x)       (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DX3GSR6_DX3GSR6_X4SRDPC_M        GENMASK(3, 2)
#define DDR_PHY_DX3GSR6_DX3GSR6_X4SRDPC_X(x)     (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DX3GSR6_DX3GSR6_RESERVED_7_4(x)  (((x) << 4) & GENMASK(7, 4))
#define DDR_PHY_DX3GSR6_DX3GSR6_RESERVED_7_4_M   GENMASK(7, 4)
#define DDR_PHY_DX3GSR6_DX3GSR6_RESERVED_7_4_X(x) (((x) & GENMASK(7, 4)) >> 4)

#define DDR_PHY_DX3GSR6_DX3GSR6_X4HVERR(x)       (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX3GSR6_DX3GSR6_X4HVERR_M        GENMASK(11, 8)
#define DDR_PHY_DX3GSR6_DX3GSR6_X4HVERR_X(x)     (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX3GSR6_DX3GSR6_X4HVWRN(x)       (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_DX3GSR6_DX3GSR6_X4HVWRN_M        GENMASK(15, 12)
#define DDR_PHY_DX3GSR6_DX3GSR6_X4HVWRN_X(x)     (((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_DX3GSR6_DX3GSR6_X4DVERR(x)       (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DX3GSR6_DX3GSR6_X4DVERR_M        GENMASK(19, 16)
#define DDR_PHY_DX3GSR6_DX3GSR6_X4DVERR_X(x)     (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DX3GSR6_DX3GSR6_X4DVWRN(x)       (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX3GSR6_DX3GSR6_X4DVWRN_M        GENMASK(23, 20)
#define DDR_PHY_DX3GSR6_DX3GSR6_X4DVWRN_X(x)     (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX3GSR6_DX3GSR6_RESERVED_31_24(x)\
	(((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_DX3GSR6_DX3GSR6_RESERVED_31_24_M GENMASK(31, 24)
#define DDR_PHY_DX3GSR6_DX3GSR6_RESERVED_31_24_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4GCR0 */
#define DDR_PHY_DX4GCR0(t)        (t + 0xb00)

#define DDR_PHY_DX4GCR0_DX4GCR0_DXEN(x)          ((x) & GENMASK(0, 0))
#define DDR_PHY_DX4GCR0_DX4GCR0_DXEN_M           GENMASK(0, 0)
#define DDR_PHY_DX4GCR0_DX4GCR0_DXEN_X(x)        ((x) & GENMASK(0, 0))

#define DDR_PHY_DX4GCR0_DX4GCR0_DXIOM(x)         (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX4GCR0_DX4GCR0_DXIOM_M          GENMASK(1, 1)
#define DDR_PHY_DX4GCR0_DX4GCR0_DXIOM_X(x)       (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX4GCR0_DX4GCR0_DQSGOE(x)        (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX4GCR0_DX4GCR0_DQSGOE_M         GENMASK(2, 2)
#define DDR_PHY_DX4GCR0_DX4GCR0_DQSGOE_X(x)      (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX4GCR0_DX4GCR0_DQSGODT(x)       (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX4GCR0_DX4GCR0_DQSGODT_M        GENMASK(3, 3)
#define DDR_PHY_DX4GCR0_DX4GCR0_DQSGODT_X(x)     (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX4GCR0_DX4GCR0_RESERVED_4(x)    (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX4GCR0_DX4GCR0_RESERVED_4_M     GENMASK(4, 4)
#define DDR_PHY_DX4GCR0_DX4GCR0_RESERVED_4_X(x)  (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX4GCR0_DX4GCR0_DQSGPDR(x)       (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX4GCR0_DX4GCR0_DQSGPDR_M        GENMASK(5, 5)
#define DDR_PHY_DX4GCR0_DX4GCR0_DQSGPDR_X(x)     (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX4GCR0_DX4GCR0_RESERVED_6(x)    (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX4GCR0_DX4GCR0_RESERVED_6_M     GENMASK(6, 6)
#define DDR_PHY_DX4GCR0_DX4GCR0_RESERVED_6_X(x)  (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX4GCR0_DX4GCR0_PDRAL(x)         (((x) << 7) & GENMASK(8, 7))
#define DDR_PHY_DX4GCR0_DX4GCR0_PDRAL_M          GENMASK(8, 7)
#define DDR_PHY_DX4GCR0_DX4GCR0_PDRAL_X(x)       (((x) & GENMASK(8, 7)) >> 7)

#define DDR_PHY_DX4GCR0_DX4GCR0_RTTOH(x)         (((x) << 9) & GENMASK(10, 9))
#define DDR_PHY_DX4GCR0_DX4GCR0_RTTOH_M          GENMASK(10, 9)
#define DDR_PHY_DX4GCR0_DX4GCR0_RTTOH_X(x)       (((x) & GENMASK(10, 9)) >> 9)

#define DDR_PHY_DX4GCR0_DX4GCR0_RTTOAL(x)        (((x) << 11) & GENMASK(11, 11))
#define DDR_PHY_DX4GCR0_DX4GCR0_RTTOAL_M         GENMASK(11, 11)
#define DDR_PHY_DX4GCR0_DX4GCR0_RTTOAL_X(x)      (((x) & GENMASK(11, 11)) >> 11)

#define DDR_PHY_DX4GCR0_DX4GCR0_DQSSEPDR(x)      (((x) << 12) & GENMASK(12, 12))
#define DDR_PHY_DX4GCR0_DX4GCR0_DQSSEPDR_M       GENMASK(12, 12)
#define DDR_PHY_DX4GCR0_DX4GCR0_DQSSEPDR_X(x)    (((x) & GENMASK(12, 12)) >> 12)

#define DDR_PHY_DX4GCR0_DX4GCR0_DQSNSEPDR(x)     (((x) << 13) & GENMASK(13, 13))
#define DDR_PHY_DX4GCR0_DX4GCR0_DQSNSEPDR_M      GENMASK(13, 13)
#define DDR_PHY_DX4GCR0_DX4GCR0_DQSNSEPDR_X(x)   (((x) & GENMASK(13, 13)) >> 13)

#define DDR_PHY_DX4GCR0_DX4GCR0_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX4GCR0_DX4GCR0_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX4GCR0_DX4GCR0_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX4GCR0_DX4GCR0_PLLRST(x)        (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX4GCR0_DX4GCR0_PLLRST_M         GENMASK(16, 16)
#define DDR_PHY_DX4GCR0_DX4GCR0_PLLRST_X(x)      (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX4GCR0_DX4GCR0_PLLPD(x)         (((x) << 17) & GENMASK(17, 17))
#define DDR_PHY_DX4GCR0_DX4GCR0_PLLPD_M          GENMASK(17, 17)
#define DDR_PHY_DX4GCR0_DX4GCR0_PLLPD_X(x)       (((x) & GENMASK(17, 17)) >> 17)

#define DDR_PHY_DX4GCR0_DX4GCR0_GSHIFT(x)        (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_DX4GCR0_DX4GCR0_GSHIFT_M         GENMASK(18, 18)
#define DDR_PHY_DX4GCR0_DX4GCR0_GSHIFT_X(x)      (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_DX4GCR0_DX4GCR0_PLLBYP(x)        (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_DX4GCR0_DX4GCR0_PLLBYP_M         GENMASK(19, 19)
#define DDR_PHY_DX4GCR0_DX4GCR0_PLLBYP_X(x)      (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_DX4GCR0_DX4GCR0_RDDLY(x)         (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX4GCR0_DX4GCR0_RDDLY_M          GENMASK(23, 20)
#define DDR_PHY_DX4GCR0_DX4GCR0_RDDLY_X(x)       (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX4GCR0_DX4GCR0_RESERVED_29_24(x)\
	(((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX4GCR0_DX4GCR0_RESERVED_29_24_M GENMASK(29, 24)
#define DDR_PHY_DX4GCR0_DX4GCR0_RESERVED_29_24_X(x)\
	(((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX4GCR0_DX4GCR0_MDLEN(x)         (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX4GCR0_DX4GCR0_MDLEN_M          GENMASK(30, 30)
#define DDR_PHY_DX4GCR0_DX4GCR0_MDLEN_X(x)       (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX4GCR0_DX4GCR0_CALBYP(x)        (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX4GCR0_DX4GCR0_CALBYP_M         GENMASK(31, 31)
#define DDR_PHY_DX4GCR0_DX4GCR0_CALBYP_X(x)      (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4GCR1 */
#define DDR_PHY_DX4GCR1(t)        (t + 0xb04)

#define DDR_PHY_DX4GCR1_DX4GCR1_RESERVED_15_0(x) ((x) & GENMASK(15, 0))
#define DDR_PHY_DX4GCR1_DX4GCR1_RESERVED_15_0_M  GENMASK(15, 0)
#define DDR_PHY_DX4GCR1_DX4GCR1_RESERVED_15_0_X(x) ((x) & GENMASK(15, 0))

#define DDR_PHY_DX4GCR1_DX4GCR1_DXPDRMODE(x)     (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX4GCR1_DX4GCR1_DXPDRMODE_M      GENMASK(31, 16)
#define DDR_PHY_DX4GCR1_DX4GCR1_DXPDRMODE_X(x)   (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4GCR2 */
#define DDR_PHY_DX4GCR2(t)        (t + 0xb08)

#define DDR_PHY_DX4GCR2_DX4GCR2_DXTEMODE(x)      ((x) & GENMASK(15, 0))
#define DDR_PHY_DX4GCR2_DX4GCR2_DXTEMODE_M       GENMASK(15, 0)
#define DDR_PHY_DX4GCR2_DX4GCR2_DXTEMODE_X(x)    ((x) & GENMASK(15, 0))

#define DDR_PHY_DX4GCR2_DX4GCR2_DXOEMODE(x)      (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX4GCR2_DX4GCR2_DXOEMODE_M       GENMASK(31, 16)
#define DDR_PHY_DX4GCR2_DX4GCR2_DXOEMODE_X(x)    (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4GCR3 */
#define DDR_PHY_DX4GCR3(t)        (t + 0xb0c)

#define DDR_PHY_DX4GCR3_DX4GCR3_RESERVED_1_0(x)  ((x) & GENMASK(1, 0))
#define DDR_PHY_DX4GCR3_DX4GCR3_RESERVED_1_0_M   GENMASK(1, 0)
#define DDR_PHY_DX4GCR3_DX4GCR3_RESERVED_1_0_X(x) ((x) & GENMASK(1, 0))

#define DDR_PHY_DX4GCR3_DX4GCR3_DSPDRMODE(x)     (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DX4GCR3_DX4GCR3_DSPDRMODE_M      GENMASK(3, 2)
#define DDR_PHY_DX4GCR3_DX4GCR3_DSPDRMODE_X(x)   (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DX4GCR3_DX4GCR3_DSTEMODE(x)      (((x) << 4) & GENMASK(5, 4))
#define DDR_PHY_DX4GCR3_DX4GCR3_DSTEMODE_M       GENMASK(5, 4)
#define DDR_PHY_DX4GCR3_DX4GCR3_DSTEMODE_X(x)    (((x) & GENMASK(5, 4)) >> 4)

#define DDR_PHY_DX4GCR3_DX4GCR3_DSOEMODE(x)      (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX4GCR3_DX4GCR3_DSOEMODE_M       GENMASK(7, 6)
#define DDR_PHY_DX4GCR3_DX4GCR3_DSOEMODE_X(x)    (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX4GCR3_DX4GCR3_RESERVED_9_8(x)  (((x) << 8) & GENMASK(9, 8))
#define DDR_PHY_DX4GCR3_DX4GCR3_RESERVED_9_8_M   GENMASK(9, 8)
#define DDR_PHY_DX4GCR3_DX4GCR3_RESERVED_9_8_X(x) (((x) & GENMASK(9, 8)) >> 8)

#define DDR_PHY_DX4GCR3_DX4GCR3_DMPDRMODE(x)     (((x) << 10) & GENMASK(11, 10))
#define DDR_PHY_DX4GCR3_DX4GCR3_DMPDRMODE_M      GENMASK(11, 10)
#define DDR_PHY_DX4GCR3_DX4GCR3_DMPDRMODE_X(x)   (((x) & GENMASK(11, 10)) >> 10)

#define DDR_PHY_DX4GCR3_DX4GCR3_DMTEMODE(x)      (((x) << 12) & GENMASK(13, 12))
#define DDR_PHY_DX4GCR3_DX4GCR3_DMTEMODE_M       GENMASK(13, 12)
#define DDR_PHY_DX4GCR3_DX4GCR3_DMTEMODE_X(x)    (((x) & GENMASK(13, 12)) >> 12)

#define DDR_PHY_DX4GCR3_DX4GCR3_DMOEMODE(x)      (((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX4GCR3_DX4GCR3_DMOEMODE_M       GENMASK(15, 14)
#define DDR_PHY_DX4GCR3_DX4GCR3_DMOEMODE_X(x)    (((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX4GCR3_DX4GCR3_RESERVED_17_16(x)\
	(((x) << 16) & GENMASK(17, 16))
#define DDR_PHY_DX4GCR3_DX4GCR3_RESERVED_17_16_M GENMASK(17, 16)
#define DDR_PHY_DX4GCR3_DX4GCR3_RESERVED_17_16_X(x)\
	(((x) & GENMASK(17, 16)) >> 16)

#define DDR_PHY_DX4GCR3_DX4GCR3_OEBVT(x)         (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_DX4GCR3_DX4GCR3_OEBVT_M          GENMASK(18, 18)
#define DDR_PHY_DX4GCR3_DX4GCR3_OEBVT_X(x)       (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_DX4GCR3_DX4GCR3_PDRBVT(x)        (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_DX4GCR3_DX4GCR3_PDRBVT_M         GENMASK(19, 19)
#define DDR_PHY_DX4GCR3_DX4GCR3_PDRBVT_X(x)      (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_DX4GCR3_DX4GCR3_TEBVT(x)         (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX4GCR3_DX4GCR3_TEBVT_M          GENMASK(20, 20)
#define DDR_PHY_DX4GCR3_DX4GCR3_TEBVT_X(x)       (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX4GCR3_DX4GCR3_WDSBVT(x)        (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX4GCR3_DX4GCR3_WDSBVT_M         GENMASK(21, 21)
#define DDR_PHY_DX4GCR3_DX4GCR3_WDSBVT_X(x)      (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX4GCR3_DX4GCR3_RDSBVT(x)        (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX4GCR3_DX4GCR3_RDSBVT_M         GENMASK(22, 22)
#define DDR_PHY_DX4GCR3_DX4GCR3_RDSBVT_X(x)      (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX4GCR3_DX4GCR3_RGSLVT(x)        (((x) << 23) & GENMASK(23, 23))
#define DDR_PHY_DX4GCR3_DX4GCR3_RGSLVT_M         GENMASK(23, 23)
#define DDR_PHY_DX4GCR3_DX4GCR3_RGSLVT_X(x)      (((x) & GENMASK(23, 23)) >> 23)

#define DDR_PHY_DX4GCR3_DX4GCR3_WLLVT(x)         (((x) << 24) & GENMASK(24, 24))
#define DDR_PHY_DX4GCR3_DX4GCR3_WLLVT_M          GENMASK(24, 24)
#define DDR_PHY_DX4GCR3_DX4GCR3_WLLVT_X(x)       (((x) & GENMASK(24, 24)) >> 24)

#define DDR_PHY_DX4GCR3_DX4GCR3_WDLVT(x)         (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_DX4GCR3_DX4GCR3_WDLVT_M          GENMASK(25, 25)
#define DDR_PHY_DX4GCR3_DX4GCR3_WDLVT_X(x)       (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_DX4GCR3_DX4GCR3_RDLVT(x)         (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_DX4GCR3_DX4GCR3_RDLVT_M          GENMASK(26, 26)
#define DDR_PHY_DX4GCR3_DX4GCR3_RDLVT_X(x)       (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_DX4GCR3_DX4GCR3_RGLVT(x)         (((x) << 27) & GENMASK(27, 27))
#define DDR_PHY_DX4GCR3_DX4GCR3_RGLVT_M          GENMASK(27, 27)
#define DDR_PHY_DX4GCR3_DX4GCR3_RGLVT_X(x)       (((x) & GENMASK(27, 27)) >> 27)

#define DDR_PHY_DX4GCR3_DX4GCR3_WDBVT(x)         (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_DX4GCR3_DX4GCR3_WDBVT_M          GENMASK(28, 28)
#define DDR_PHY_DX4GCR3_DX4GCR3_WDBVT_X(x)       (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_DX4GCR3_DX4GCR3_RDBVT(x)         (((x) << 29) & GENMASK(29, 29))
#define DDR_PHY_DX4GCR3_DX4GCR3_RDBVT_M          GENMASK(29, 29)
#define DDR_PHY_DX4GCR3_DX4GCR3_RDBVT_X(x)       (((x) & GENMASK(29, 29)) >> 29)

#define DDR_PHY_DX4GCR3_DX4GCR3_WDMBVT(x)        (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX4GCR3_DX4GCR3_WDMBVT_M         GENMASK(30, 30)
#define DDR_PHY_DX4GCR3_DX4GCR3_WDMBVT_X(x)      (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX4GCR3_DX4GCR3_RDMBVT(x)        (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX4GCR3_DX4GCR3_RDMBVT_M         GENMASK(31, 31)
#define DDR_PHY_DX4GCR3_DX4GCR3_RDMBVT_X(x)      (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4GCR4 */
#define DDR_PHY_DX4GCR4(t)        (t + 0xb10)

#define DDR_PHY_DX4GCR4_DX4GCR4_DXREFIMON(x)     ((x) & GENMASK(1, 0))
#define DDR_PHY_DX4GCR4_DX4GCR4_DXREFIMON_M      GENMASK(1, 0)
#define DDR_PHY_DX4GCR4_DX4GCR4_DXREFIMON_X(x)   ((x) & GENMASK(1, 0))

#define DDR_PHY_DX4GCR4_DX4GCR4_DXREFIEN(x)      (((x) << 2) & GENMASK(5, 2))
#define DDR_PHY_DX4GCR4_DX4GCR4_DXREFIEN_M       GENMASK(5, 2)
#define DDR_PHY_DX4GCR4_DX4GCR4_DXREFIEN_X(x)    (((x) & GENMASK(5, 2)) >> 2)

#define DDR_PHY_DX4GCR4_DX4GCR4_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX4GCR4_DX4GCR4_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX4GCR4_DX4GCR4_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX4GCR4_DX4GCR4_DXREFSSEL(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX4GCR4_DX4GCR4_DXREFSSEL_M      GENMASK(13, 8)
#define DDR_PHY_DX4GCR4_DX4GCR4_DXREFSSEL_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX4GCR4_DX4GCR4_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX4GCR4_DX4GCR4_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX4GCR4_DX4GCR4_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX4GCR4_DX4GCR4_DXREFESEL(x)     (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX4GCR4_DX4GCR4_DXREFESEL_M      GENMASK(21, 16)
#define DDR_PHY_DX4GCR4_DX4GCR4_DXREFESEL_X(x)   (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX4GCR4_DX4GCR4_RESERVED_24_22(x)\
	(((x) << 22) & GENMASK(24, 22))
#define DDR_PHY_DX4GCR4_DX4GCR4_RESERVED_24_22_M GENMASK(24, 22)
#define DDR_PHY_DX4GCR4_DX4GCR4_RESERVED_24_22_X(x)\
	(((x) & GENMASK(24, 22)) >> 22)

#define DDR_PHY_DX4GCR4_DX4GCR4_DXREFSEN(x)      (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_DX4GCR4_DX4GCR4_DXREFSEN_M       GENMASK(25, 25)
#define DDR_PHY_DX4GCR4_DX4GCR4_DXREFSEN_X(x)    (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_DX4GCR4_DX4GCR4_DXREFEEN(x)      (((x) << 26) & GENMASK(27, 26))
#define DDR_PHY_DX4GCR4_DX4GCR4_DXREFEEN_M       GENMASK(27, 26)
#define DDR_PHY_DX4GCR4_DX4GCR4_DXREFEEN_X(x)    (((x) & GENMASK(27, 26)) >> 26)

#define DDR_PHY_DX4GCR4_DX4GCR4_DXREFPEN(x)      (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_DX4GCR4_DX4GCR4_DXREFPEN_M       GENMASK(28, 28)
#define DDR_PHY_DX4GCR4_DX4GCR4_DXREFPEN_X(x)    (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_DX4GCR4_DX4GCR4_DXREFIOM(x)      (((x) << 29) & GENMASK(31, 29))
#define DDR_PHY_DX4GCR4_DX4GCR4_DXREFIOM_M       GENMASK(31, 29)
#define DDR_PHY_DX4GCR4_DX4GCR4_DXREFIOM_X(x)    (((x) & GENMASK(31, 29)) >> 29)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4GCR5 */
#define DDR_PHY_DX4GCR5(t)        (t + 0xb14)

#define DDR_PHY_DX4GCR5_DX4GCR5_DXREFISELR0(x)   ((x) & GENMASK(5, 0))
#define DDR_PHY_DX4GCR5_DX4GCR5_DXREFISELR0_M    GENMASK(5, 0)
#define DDR_PHY_DX4GCR5_DX4GCR5_DXREFISELR0_X(x) ((x) & GENMASK(5, 0))

#define DDR_PHY_DX4GCR5_DX4GCR5_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX4GCR5_DX4GCR5_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX4GCR5_DX4GCR5_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX4GCR5_DX4GCR5_DXREFISELR1(x)   (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX4GCR5_DX4GCR5_DXREFISELR1_M    GENMASK(13, 8)
#define DDR_PHY_DX4GCR5_DX4GCR5_DXREFISELR1_X(x) (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX4GCR5_DX4GCR5_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX4GCR5_DX4GCR5_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX4GCR5_DX4GCR5_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX4GCR5_DX4GCR5_DXREFISELR2(x)   (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX4GCR5_DX4GCR5_DXREFISELR2_M    GENMASK(21, 16)
#define DDR_PHY_DX4GCR5_DX4GCR5_DXREFISELR2_X(x) (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX4GCR5_DX4GCR5_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX4GCR5_DX4GCR5_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX4GCR5_DX4GCR5_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX4GCR5_DX4GCR5_DXREFISELR3(x)   (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX4GCR5_DX4GCR5_DXREFISELR3_M    GENMASK(29, 24)
#define DDR_PHY_DX4GCR5_DX4GCR5_DXREFISELR3_X(x) (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX4GCR5_DX4GCR5_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX4GCR5_DX4GCR5_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX4GCR5_DX4GCR5_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4GCR6 */
#define DDR_PHY_DX4GCR6(t)        (t + 0xb18)

#define DDR_PHY_DX4GCR6_DX4GCR6_DXDQVREFR0(x)    ((x) & GENMASK(5, 0))
#define DDR_PHY_DX4GCR6_DX4GCR6_DXDQVREFR0_M     GENMASK(5, 0)
#define DDR_PHY_DX4GCR6_DX4GCR6_DXDQVREFR0_X(x)  ((x) & GENMASK(5, 0))

#define DDR_PHY_DX4GCR6_DX4GCR6_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX4GCR6_DX4GCR6_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX4GCR6_DX4GCR6_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX4GCR6_DX4GCR6_DXDQVREFR1(x)    (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX4GCR6_DX4GCR6_DXDQVREFR1_M     GENMASK(13, 8)
#define DDR_PHY_DX4GCR6_DX4GCR6_DXDQVREFR1_X(x)  (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX4GCR6_DX4GCR6_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX4GCR6_DX4GCR6_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX4GCR6_DX4GCR6_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX4GCR6_DX4GCR6_DXDQVREFR2(x)    (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX4GCR6_DX4GCR6_DXDQVREFR2_M     GENMASK(21, 16)
#define DDR_PHY_DX4GCR6_DX4GCR6_DXDQVREFR2_X(x)  (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX4GCR6_DX4GCR6_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX4GCR6_DX4GCR6_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX4GCR6_DX4GCR6_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX4GCR6_DX4GCR6_DXDQVREFR3(x)    (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX4GCR6_DX4GCR6_DXDQVREFR3_M     GENMASK(29, 24)
#define DDR_PHY_DX4GCR6_DX4GCR6_DXDQVREFR3_X(x)  (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX4GCR6_DX4GCR6_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX4GCR6_DX4GCR6_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX4GCR6_DX4GCR6_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4GCR7 */
#define DDR_PHY_DX4GCR7(t)        (t + 0xb1c)

#define DDR_PHY_DX4GCR7_DX4GCR7_RESERVED_1_0(x)  ((x) & GENMASK(1, 0))
#define DDR_PHY_DX4GCR7_DX4GCR7_RESERVED_1_0_M   GENMASK(1, 0)
#define DDR_PHY_DX4GCR7_DX4GCR7_RESERVED_1_0_X(x) ((x) & GENMASK(1, 0))

#define DDR_PHY_DX4GCR7_DX4GCR7_X4DSPDRMODE(x)   (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DX4GCR7_DX4GCR7_X4DSPDRMODE_M    GENMASK(3, 2)
#define DDR_PHY_DX4GCR7_DX4GCR7_X4DSPDRMODE_X(x) (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DX4GCR7_DX4GCR7_X4DSTEMODE(x)    (((x) << 4) & GENMASK(5, 4))
#define DDR_PHY_DX4GCR7_DX4GCR7_X4DSTEMODE_M     GENMASK(5, 4)
#define DDR_PHY_DX4GCR7_DX4GCR7_X4DSTEMODE_X(x)  (((x) & GENMASK(5, 4)) >> 4)

#define DDR_PHY_DX4GCR7_DX4GCR7_X4DSOEMODE(x)    (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX4GCR7_DX4GCR7_X4DSOEMODE_M     GENMASK(7, 6)
#define DDR_PHY_DX4GCR7_DX4GCR7_X4DSOEMODE_X(x)  (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX4GCR7_DX4GCR7_RESERVED_9_8(x)  (((x) << 8) & GENMASK(9, 8))
#define DDR_PHY_DX4GCR7_DX4GCR7_RESERVED_9_8_M   GENMASK(9, 8)
#define DDR_PHY_DX4GCR7_DX4GCR7_RESERVED_9_8_X(x) (((x) & GENMASK(9, 8)) >> 8)

#define DDR_PHY_DX4GCR7_DX4GCR7_X4DXPDRMODE(x)   (((x) << 10) & GENMASK(11, 10))
#define DDR_PHY_DX4GCR7_DX4GCR7_X4DXPDRMODE_M    GENMASK(11, 10)
#define DDR_PHY_DX4GCR7_DX4GCR7_X4DXPDRMODE_X(x) (((x) & GENMASK(11, 10)) >> 10)

#define DDR_PHY_DX4GCR7_DX4GCR7_X4DXTEMODE(x)    (((x) << 12) & GENMASK(13, 12))
#define DDR_PHY_DX4GCR7_DX4GCR7_X4DXTEMODE_M     GENMASK(13, 12)
#define DDR_PHY_DX4GCR7_DX4GCR7_X4DXTEMODE_X(x)  (((x) & GENMASK(13, 12)) >> 12)

#define DDR_PHY_DX4GCR7_DX4GCR7_X4DXOEMODE(x)    (((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX4GCR7_DX4GCR7_X4DXOEMODE_M     GENMASK(15, 14)
#define DDR_PHY_DX4GCR7_DX4GCR7_X4DXOEMODE_X(x)  (((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX4GCR7_DX4GCR7_X4DQSGOE(x)      (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX4GCR7_DX4GCR7_X4DQSGOE_M       GENMASK(16, 16)
#define DDR_PHY_DX4GCR7_DX4GCR7_X4DQSGOE_X(x)    (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX4GCR7_DX4GCR7_X4DQSGODT(x)     (((x) << 17) & GENMASK(17, 17))
#define DDR_PHY_DX4GCR7_DX4GCR7_X4DQSGODT_M      GENMASK(17, 17)
#define DDR_PHY_DX4GCR7_DX4GCR7_X4DQSGODT_X(x)   (((x) & GENMASK(17, 17)) >> 17)

#define DDR_PHY_DX4GCR7_DX4GCR7_RESERVED_18(x)   (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_DX4GCR7_DX4GCR7_RESERVED_18_M    GENMASK(18, 18)
#define DDR_PHY_DX4GCR7_DX4GCR7_RESERVED_18_X(x) (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_DX4GCR7_DX4GCR7_X4DQSGPDR(x)     (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_DX4GCR7_DX4GCR7_X4DQSGPDR_M      GENMASK(19, 19)
#define DDR_PHY_DX4GCR7_DX4GCR7_X4DQSGPDR_X(x)   (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_DX4GCR7_DX4GCR7_RESERVED_20(x)   (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX4GCR7_DX4GCR7_RESERVED_20_M    GENMASK(20, 20)
#define DDR_PHY_DX4GCR7_DX4GCR7_RESERVED_20_X(x) (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX4GCR7_DX4GCR7_X4DQSSEPDR(x)    (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX4GCR7_DX4GCR7_X4DQSSEPDR_M     GENMASK(21, 21)
#define DDR_PHY_DX4GCR7_DX4GCR7_X4DQSSEPDR_X(x)  (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX4GCR7_DX4GCR7_X4DQSNSEPDR(x)   (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX4GCR7_DX4GCR7_X4DQSNSEPDR_M    GENMASK(22, 22)
#define DDR_PHY_DX4GCR7_DX4GCR7_X4DQSNSEPDR_X(x) (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX4GCR7_DX4GCR7_X4RTTOH(x)       (((x) << 23) & GENMASK(24, 23))
#define DDR_PHY_DX4GCR7_DX4GCR7_X4RTTOH_M        GENMASK(24, 23)
#define DDR_PHY_DX4GCR7_DX4GCR7_X4RTTOH_X(x)     (((x) & GENMASK(24, 23)) >> 23)

#define DDR_PHY_DX4GCR7_DX4GCR7_X4RTTOAL(x)      (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_DX4GCR7_DX4GCR7_X4RTTOAL_M       GENMASK(25, 25)
#define DDR_PHY_DX4GCR7_DX4GCR7_X4RTTOAL_X(x)    (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_DX4GCR7_DX4GCR7_X4RDDLY(x)       (((x) << 26) & GENMASK(29, 26))
#define DDR_PHY_DX4GCR7_DX4GCR7_X4RDDLY_M        GENMASK(29, 26)
#define DDR_PHY_DX4GCR7_DX4GCR7_X4RDDLY_X(x)     (((x) & GENMASK(29, 26)) >> 26)

#define DDR_PHY_DX4GCR7_DX4GCR7_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX4GCR7_DX4GCR7_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX4GCR7_DX4GCR7_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4GCR8 */
#define DDR_PHY_DX4GCR8(t)        (t + 0xb20)

#define DDR_PHY_DX4GCR8_DX4GCR8_X4DXREFISELR0(x) ((x) & GENMASK(5, 0))
#define DDR_PHY_DX4GCR8_DX4GCR8_X4DXREFISELR0_M  GENMASK(5, 0)
#define DDR_PHY_DX4GCR8_DX4GCR8_X4DXREFISELR0_X(x) ((x) & GENMASK(5, 0))

#define DDR_PHY_DX4GCR8_DX4GCR8_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX4GCR8_DX4GCR8_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX4GCR8_DX4GCR8_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX4GCR8_DX4GCR8_X4DXREFISELR1(x) (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX4GCR8_DX4GCR8_X4DXREFISELR1_M  GENMASK(13, 8)
#define DDR_PHY_DX4GCR8_DX4GCR8_X4DXREFISELR1_X(x) (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX4GCR8_DX4GCR8_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX4GCR8_DX4GCR8_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX4GCR8_DX4GCR8_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX4GCR8_DX4GCR8_X4DXREFISELR2(x) (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX4GCR8_DX4GCR8_X4DXREFISELR2_M  GENMASK(21, 16)
#define DDR_PHY_DX4GCR8_DX4GCR8_X4DXREFISELR2_X(x)\
	(((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX4GCR8_DX4GCR8_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX4GCR8_DX4GCR8_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX4GCR8_DX4GCR8_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX4GCR8_DX4GCR8_X4DXREFISELR3(x) (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX4GCR8_DX4GCR8_X4DXREFISELR3_M  GENMASK(29, 24)
#define DDR_PHY_DX4GCR8_DX4GCR8_X4DXREFISELR3_X(x)\
	(((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX4GCR8_DX4GCR8_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX4GCR8_DX4GCR8_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX4GCR8_DX4GCR8_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4GCR9 */
#define DDR_PHY_DX4GCR9(t)        (t + 0xb24)

#define DDR_PHY_DX4GCR9_DX4GCR9_X4DXDQVREFR0(x)  ((x) & GENMASK(5, 0))
#define DDR_PHY_DX4GCR9_DX4GCR9_X4DXDQVREFR0_M   GENMASK(5, 0)
#define DDR_PHY_DX4GCR9_DX4GCR9_X4DXDQVREFR0_X(x) ((x) & GENMASK(5, 0))

#define DDR_PHY_DX4GCR9_DX4GCR9_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX4GCR9_DX4GCR9_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX4GCR9_DX4GCR9_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX4GCR9_DX4GCR9_X4DXDQVREFR1(x)  (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX4GCR9_DX4GCR9_X4DXDQVREFR1_M   GENMASK(13, 8)
#define DDR_PHY_DX4GCR9_DX4GCR9_X4DXDQVREFR1_X(x) (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX4GCR9_DX4GCR9_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX4GCR9_DX4GCR9_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX4GCR9_DX4GCR9_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX4GCR9_DX4GCR9_X4DXDQVREFR2(x)  (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX4GCR9_DX4GCR9_X4DXDQVREFR2_M   GENMASK(21, 16)
#define DDR_PHY_DX4GCR9_DX4GCR9_X4DXDQVREFR2_X(x)\
	(((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX4GCR9_DX4GCR9_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX4GCR9_DX4GCR9_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX4GCR9_DX4GCR9_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX4GCR9_DX4GCR9_X4DXDQVREFR3(x)  (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX4GCR9_DX4GCR9_X4DXDQVREFR3_M   GENMASK(29, 24)
#define DDR_PHY_DX4GCR9_DX4GCR9_X4DXDQVREFR3_X(x)\
	(((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX4GCR9_DX4GCR9_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX4GCR9_DX4GCR9_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX4GCR9_DX4GCR9_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4BDLR0 */
#define DDR_PHY_DX4BDLR0(t)       (t + 0xb40)

#define DDR_PHY_DX4BDLR0_DX4BDLR0_DQ0WBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX4BDLR0_DX4BDLR0_DQ0WBD_M       GENMASK(5, 0)
#define DDR_PHY_DX4BDLR0_DX4BDLR0_DQ0WBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX4BDLR0_DX4BDLR0_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX4BDLR0_DX4BDLR0_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX4BDLR0_DX4BDLR0_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX4BDLR0_DX4BDLR0_DQ1WBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX4BDLR0_DX4BDLR0_DQ1WBD_M       GENMASK(13, 8)
#define DDR_PHY_DX4BDLR0_DX4BDLR0_DQ1WBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX4BDLR0_DX4BDLR0_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX4BDLR0_DX4BDLR0_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX4BDLR0_DX4BDLR0_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX4BDLR0_DX4BDLR0_DQ2WBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX4BDLR0_DX4BDLR0_DQ2WBD_M       GENMASK(21, 16)
#define DDR_PHY_DX4BDLR0_DX4BDLR0_DQ2WBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX4BDLR0_DX4BDLR0_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX4BDLR0_DX4BDLR0_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX4BDLR0_DX4BDLR0_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX4BDLR0_DX4BDLR0_DQ3WBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX4BDLR0_DX4BDLR0_DQ3WBD_M       GENMASK(29, 24)
#define DDR_PHY_DX4BDLR0_DX4BDLR0_DQ3WBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX4BDLR0_DX4BDLR0_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX4BDLR0_DX4BDLR0_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX4BDLR0_DX4BDLR0_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4BDLR1 */
#define DDR_PHY_DX4BDLR1(t)       (t + 0xb44)

#define DDR_PHY_DX4BDLR1_DX4BDLR1_DQ4WBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX4BDLR1_DX4BDLR1_DQ4WBD_M       GENMASK(5, 0)
#define DDR_PHY_DX4BDLR1_DX4BDLR1_DQ4WBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX4BDLR1_DX4BDLR1_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX4BDLR1_DX4BDLR1_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX4BDLR1_DX4BDLR1_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX4BDLR1_DX4BDLR1_DQ5WBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX4BDLR1_DX4BDLR1_DQ5WBD_M       GENMASK(13, 8)
#define DDR_PHY_DX4BDLR1_DX4BDLR1_DQ5WBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX4BDLR1_DX4BDLR1_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX4BDLR1_DX4BDLR1_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX4BDLR1_DX4BDLR1_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX4BDLR1_DX4BDLR1_DQ6WBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX4BDLR1_DX4BDLR1_DQ6WBD_M       GENMASK(21, 16)
#define DDR_PHY_DX4BDLR1_DX4BDLR1_DQ6WBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX4BDLR1_DX4BDLR1_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX4BDLR1_DX4BDLR1_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX4BDLR1_DX4BDLR1_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX4BDLR1_DX4BDLR1_DQ7WBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX4BDLR1_DX4BDLR1_DQ7WBD_M       GENMASK(29, 24)
#define DDR_PHY_DX4BDLR1_DX4BDLR1_DQ7WBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX4BDLR1_DX4BDLR1_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX4BDLR1_DX4BDLR1_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX4BDLR1_DX4BDLR1_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4BDLR2 */
#define DDR_PHY_DX4BDLR2(t)       (t + 0xb48)

#define DDR_PHY_DX4BDLR2_DX4BDLR2_DMWBD(x)       ((x) & GENMASK(5, 0))
#define DDR_PHY_DX4BDLR2_DX4BDLR2_DMWBD_M        GENMASK(5, 0)
#define DDR_PHY_DX4BDLR2_DX4BDLR2_DMWBD_X(x)     ((x) & GENMASK(5, 0))

#define DDR_PHY_DX4BDLR2_DX4BDLR2_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX4BDLR2_DX4BDLR2_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX4BDLR2_DX4BDLR2_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX4BDLR2_DX4BDLR2_DSWBD(x)       (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX4BDLR2_DX4BDLR2_DSWBD_M        GENMASK(13, 8)
#define DDR_PHY_DX4BDLR2_DX4BDLR2_DSWBD_X(x)     (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX4BDLR2_DX4BDLR2_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX4BDLR2_DX4BDLR2_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX4BDLR2_DX4BDLR2_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX4BDLR2_DX4BDLR2_DSOEBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX4BDLR2_DX4BDLR2_DSOEBD_M       GENMASK(21, 16)
#define DDR_PHY_DX4BDLR2_DX4BDLR2_DSOEBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX4BDLR2_DX4BDLR2_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX4BDLR2_DX4BDLR2_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX4BDLR2_DX4BDLR2_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4BDLR3 */
#define DDR_PHY_DX4BDLR3(t)       (t + 0xb50)

#define DDR_PHY_DX4BDLR3_DX4BDLR3_DQ0RBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX4BDLR3_DX4BDLR3_DQ0RBD_M       GENMASK(5, 0)
#define DDR_PHY_DX4BDLR3_DX4BDLR3_DQ0RBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX4BDLR3_DX4BDLR3_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX4BDLR3_DX4BDLR3_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX4BDLR3_DX4BDLR3_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX4BDLR3_DX4BDLR3_DQ1RBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX4BDLR3_DX4BDLR3_DQ1RBD_M       GENMASK(13, 8)
#define DDR_PHY_DX4BDLR3_DX4BDLR3_DQ1RBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX4BDLR3_DX4BDLR3_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX4BDLR3_DX4BDLR3_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX4BDLR3_DX4BDLR3_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX4BDLR3_DX4BDLR3_DQ2RBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX4BDLR3_DX4BDLR3_DQ2RBD_M       GENMASK(21, 16)
#define DDR_PHY_DX4BDLR3_DX4BDLR3_DQ2RBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX4BDLR3_DX4BDLR3_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX4BDLR3_DX4BDLR3_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX4BDLR3_DX4BDLR3_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX4BDLR3_DX4BDLR3_DQ3RBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX4BDLR3_DX4BDLR3_DQ3RBD_M       GENMASK(29, 24)
#define DDR_PHY_DX4BDLR3_DX4BDLR3_DQ3RBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX4BDLR3_DX4BDLR3_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX4BDLR3_DX4BDLR3_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX4BDLR3_DX4BDLR3_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4BDLR4 */
#define DDR_PHY_DX4BDLR4(t)       (t + 0xb54)

#define DDR_PHY_DX4BDLR4_DX4BDLR4_DQ4RBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX4BDLR4_DX4BDLR4_DQ4RBD_M       GENMASK(5, 0)
#define DDR_PHY_DX4BDLR4_DX4BDLR4_DQ4RBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX4BDLR4_DX4BDLR4_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX4BDLR4_DX4BDLR4_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX4BDLR4_DX4BDLR4_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX4BDLR4_DX4BDLR4_DQ5RBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX4BDLR4_DX4BDLR4_DQ5RBD_M       GENMASK(13, 8)
#define DDR_PHY_DX4BDLR4_DX4BDLR4_DQ5RBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX4BDLR4_DX4BDLR4_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX4BDLR4_DX4BDLR4_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX4BDLR4_DX4BDLR4_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX4BDLR4_DX4BDLR4_DQ6RBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX4BDLR4_DX4BDLR4_DQ6RBD_M       GENMASK(21, 16)
#define DDR_PHY_DX4BDLR4_DX4BDLR4_DQ6RBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX4BDLR4_DX4BDLR4_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX4BDLR4_DX4BDLR4_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX4BDLR4_DX4BDLR4_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX4BDLR4_DX4BDLR4_DQ7RBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX4BDLR4_DX4BDLR4_DQ7RBD_M       GENMASK(29, 24)
#define DDR_PHY_DX4BDLR4_DX4BDLR4_DQ7RBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX4BDLR4_DX4BDLR4_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX4BDLR4_DX4BDLR4_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX4BDLR4_DX4BDLR4_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4BDLR5 */
#define DDR_PHY_DX4BDLR5(t)       (t + 0xb58)

#define DDR_PHY_DX4BDLR5_DX4BDLR5_DMRBD(x)       ((x) & GENMASK(5, 0))
#define DDR_PHY_DX4BDLR5_DX4BDLR5_DMRBD_M        GENMASK(5, 0)
#define DDR_PHY_DX4BDLR5_DX4BDLR5_DMRBD_X(x)     ((x) & GENMASK(5, 0))

#define DDR_PHY_DX4BDLR5_DX4BDLR5_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX4BDLR5_DX4BDLR5_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX4BDLR5_DX4BDLR5_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX4BDLR5_DX4BDLR5_DSRBD(x)       (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX4BDLR5_DX4BDLR5_DSRBD_M        GENMASK(13, 8)
#define DDR_PHY_DX4BDLR5_DX4BDLR5_DSRBD_X(x)     (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX4BDLR5_DX4BDLR5_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX4BDLR5_DX4BDLR5_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX4BDLR5_DX4BDLR5_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX4BDLR5_DX4BDLR5_DSNRBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX4BDLR5_DX4BDLR5_DSNRBD_M       GENMASK(21, 16)
#define DDR_PHY_DX4BDLR5_DX4BDLR5_DSNRBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX4BDLR5_DX4BDLR5_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX4BDLR5_DX4BDLR5_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX4BDLR5_DX4BDLR5_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4BDLR6 */
#define DDR_PHY_DX4BDLR6(t)       (t + 0xb60)

#define DDR_PHY_DX4BDLR6_DX4BDLR6_RESERVED_7_0(x) ((x) & GENMASK(7, 0))
#define DDR_PHY_DX4BDLR6_DX4BDLR6_RESERVED_7_0_M GENMASK(7, 0)
#define DDR_PHY_DX4BDLR6_DX4BDLR6_RESERVED_7_0_X(x) ((x) & GENMASK(7, 0))

#define DDR_PHY_DX4BDLR6_DX4BDLR6_PDRBD(x)       (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX4BDLR6_DX4BDLR6_PDRBD_M        GENMASK(13, 8)
#define DDR_PHY_DX4BDLR6_DX4BDLR6_PDRBD_X(x)     (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX4BDLR6_DX4BDLR6_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX4BDLR6_DX4BDLR6_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX4BDLR6_DX4BDLR6_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX4BDLR6_DX4BDLR6_TERBD(x)       (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX4BDLR6_DX4BDLR6_TERBD_M        GENMASK(21, 16)
#define DDR_PHY_DX4BDLR6_DX4BDLR6_TERBD_X(x)     (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX4BDLR6_DX4BDLR6_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX4BDLR6_DX4BDLR6_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX4BDLR6_DX4BDLR6_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4BDLR7 */
#define DDR_PHY_DX4BDLR7(t)       (t + 0xb64)

#define DDR_PHY_DX4BDLR7_DX4BDLR7_X4DMWBD(x)     ((x) & GENMASK(5, 0))
#define DDR_PHY_DX4BDLR7_DX4BDLR7_X4DMWBD_M      GENMASK(5, 0)
#define DDR_PHY_DX4BDLR7_DX4BDLR7_X4DMWBD_X(x)   ((x) & GENMASK(5, 0))

#define DDR_PHY_DX4BDLR7_DX4BDLR7_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX4BDLR7_DX4BDLR7_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX4BDLR7_DX4BDLR7_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX4BDLR7_DX4BDLR7_X4DSWBD(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX4BDLR7_DX4BDLR7_X4DSWBD_M      GENMASK(13, 8)
#define DDR_PHY_DX4BDLR7_DX4BDLR7_X4DSWBD_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX4BDLR7_DX4BDLR7_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX4BDLR7_DX4BDLR7_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX4BDLR7_DX4BDLR7_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX4BDLR7_DX4BDLR7_X4DSOEBD(x)    (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX4BDLR7_DX4BDLR7_X4DSOEBD_M     GENMASK(21, 16)
#define DDR_PHY_DX4BDLR7_DX4BDLR7_X4DSOEBD_X(x)  (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX4BDLR7_DX4BDLR7_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX4BDLR7_DX4BDLR7_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX4BDLR7_DX4BDLR7_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4BDLR8 */
#define DDR_PHY_DX4BDLR8(t)       (t + 0xb68)

#define DDR_PHY_DX4BDLR8_DX4BDLR8_X4DMRBD(x)     ((x) & GENMASK(5, 0))
#define DDR_PHY_DX4BDLR8_DX4BDLR8_X4DMRBD_M      GENMASK(5, 0)
#define DDR_PHY_DX4BDLR8_DX4BDLR8_X4DMRBD_X(x)   ((x) & GENMASK(5, 0))

#define DDR_PHY_DX4BDLR8_DX4BDLR8_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX4BDLR8_DX4BDLR8_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX4BDLR8_DX4BDLR8_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX4BDLR8_DX4BDLR8_X4DSRBD(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX4BDLR8_DX4BDLR8_X4DSRBD_M      GENMASK(13, 8)
#define DDR_PHY_DX4BDLR8_DX4BDLR8_X4DSRBD_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX4BDLR8_DX4BDLR8_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX4BDLR8_DX4BDLR8_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX4BDLR8_DX4BDLR8_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX4BDLR8_DX4BDLR8_X4DSNRBD(x)    (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX4BDLR8_DX4BDLR8_X4DSNRBD_M     GENMASK(21, 16)
#define DDR_PHY_DX4BDLR8_DX4BDLR8_X4DSNRBD_X(x)  (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX4BDLR8_DX4BDLR8_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX4BDLR8_DX4BDLR8_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX4BDLR8_DX4BDLR8_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4BDLR9 */
#define DDR_PHY_DX4BDLR9(t)       (t + 0xb6c)

#define DDR_PHY_DX4BDLR9_DX4BDLR9_RESERVED_7_0(x) ((x) & GENMASK(7, 0))
#define DDR_PHY_DX4BDLR9_DX4BDLR9_RESERVED_7_0_M GENMASK(7, 0)
#define DDR_PHY_DX4BDLR9_DX4BDLR9_RESERVED_7_0_X(x) ((x) & GENMASK(7, 0))

#define DDR_PHY_DX4BDLR9_DX4BDLR9_X4PDRBD(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX4BDLR9_DX4BDLR9_X4PDRBD_M      GENMASK(13, 8)
#define DDR_PHY_DX4BDLR9_DX4BDLR9_X4PDRBD_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX4BDLR9_DX4BDLR9_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX4BDLR9_DX4BDLR9_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX4BDLR9_DX4BDLR9_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX4BDLR9_DX4BDLR9_X4TERBD(x)     (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX4BDLR9_DX4BDLR9_X4TERBD_M      GENMASK(21, 16)
#define DDR_PHY_DX4BDLR9_DX4BDLR9_X4TERBD_X(x)   (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX4BDLR9_DX4BDLR9_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX4BDLR9_DX4BDLR9_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX4BDLR9_DX4BDLR9_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4LCDLR0 */
#define DDR_PHY_DX4LCDLR0(t)      (t + 0xb80)

#define DDR_PHY_DX4LCDLR0_DX4LCDLR0_WLD(x)       ((x) & GENMASK(8, 0))
#define DDR_PHY_DX4LCDLR0_DX4LCDLR0_WLD_M        GENMASK(8, 0)
#define DDR_PHY_DX4LCDLR0_DX4LCDLR0_WLD_X(x)     ((x) & GENMASK(8, 0))

#define DDR_PHY_DX4LCDLR0_DX4LCDLR0_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX4LCDLR0_DX4LCDLR0_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX4LCDLR0_DX4LCDLR0_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX4LCDLR0_DX4LCDLR0_X4WLD(x)     (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX4LCDLR0_DX4LCDLR0_X4WLD_M      GENMASK(24, 16)
#define DDR_PHY_DX4LCDLR0_DX4LCDLR0_X4WLD_X(x)   (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX4LCDLR0_DX4LCDLR0_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX4LCDLR0_DX4LCDLR0_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX4LCDLR0_DX4LCDLR0_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4LCDLR1 */
#define DDR_PHY_DX4LCDLR1(t)      (t + 0xb84)

#define DDR_PHY_DX4LCDLR1_DX4LCDLR1_WDQD(x)      ((x) & GENMASK(8, 0))
#define DDR_PHY_DX4LCDLR1_DX4LCDLR1_WDQD_M       GENMASK(8, 0)
#define DDR_PHY_DX4LCDLR1_DX4LCDLR1_WDQD_X(x)    ((x) & GENMASK(8, 0))

#define DDR_PHY_DX4LCDLR1_DX4LCDLR1_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX4LCDLR1_DX4LCDLR1_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX4LCDLR1_DX4LCDLR1_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX4LCDLR1_DX4LCDLR1_X4WDQD(x)    (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX4LCDLR1_DX4LCDLR1_X4WDQD_M     GENMASK(24, 16)
#define DDR_PHY_DX4LCDLR1_DX4LCDLR1_X4WDQD_X(x)  (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX4LCDLR1_DX4LCDLR1_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX4LCDLR1_DX4LCDLR1_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX4LCDLR1_DX4LCDLR1_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4LCDLR2 */
#define DDR_PHY_DX4LCDLR2(t)      (t + 0xb88)

#define DDR_PHY_DX4LCDLR2_DX4LCDLR2_DQSGD(x)     ((x) & GENMASK(8, 0))
#define DDR_PHY_DX4LCDLR2_DX4LCDLR2_DQSGD_M      GENMASK(8, 0)
#define DDR_PHY_DX4LCDLR2_DX4LCDLR2_DQSGD_X(x)   ((x) & GENMASK(8, 0))

#define DDR_PHY_DX4LCDLR2_DX4LCDLR2_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX4LCDLR2_DX4LCDLR2_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX4LCDLR2_DX4LCDLR2_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX4LCDLR2_DX4LCDLR2_X4DQSGD(x)   (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX4LCDLR2_DX4LCDLR2_X4DQSGD_M    GENMASK(24, 16)
#define DDR_PHY_DX4LCDLR2_DX4LCDLR2_X4DQSGD_X(x) (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX4LCDLR2_DX4LCDLR2_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX4LCDLR2_DX4LCDLR2_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX4LCDLR2_DX4LCDLR2_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4LCDLR3 */
#define DDR_PHY_DX4LCDLR3(t)      (t + 0xb8c)

#define DDR_PHY_DX4LCDLR3_DX4LCDLR3_RDQSD(x)     ((x) & GENMASK(8, 0))
#define DDR_PHY_DX4LCDLR3_DX4LCDLR3_RDQSD_M      GENMASK(8, 0)
#define DDR_PHY_DX4LCDLR3_DX4LCDLR3_RDQSD_X(x)   ((x) & GENMASK(8, 0))

#define DDR_PHY_DX4LCDLR3_DX4LCDLR3_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX4LCDLR3_DX4LCDLR3_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX4LCDLR3_DX4LCDLR3_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX4LCDLR3_DX4LCDLR3_X4RDQSD(x)   (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX4LCDLR3_DX4LCDLR3_X4RDQSD_M    GENMASK(24, 16)
#define DDR_PHY_DX4LCDLR3_DX4LCDLR3_X4RDQSD_X(x) (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX4LCDLR3_DX4LCDLR3_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX4LCDLR3_DX4LCDLR3_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX4LCDLR3_DX4LCDLR3_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4LCDLR4 */
#define DDR_PHY_DX4LCDLR4(t)      (t + 0xb90)

#define DDR_PHY_DX4LCDLR4_DX4LCDLR4_RDQSND(x)    ((x) & GENMASK(8, 0))
#define DDR_PHY_DX4LCDLR4_DX4LCDLR4_RDQSND_M     GENMASK(8, 0)
#define DDR_PHY_DX4LCDLR4_DX4LCDLR4_RDQSND_X(x)  ((x) & GENMASK(8, 0))

#define DDR_PHY_DX4LCDLR4_DX4LCDLR4_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX4LCDLR4_DX4LCDLR4_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX4LCDLR4_DX4LCDLR4_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX4LCDLR4_DX4LCDLR4_X4RDQSND(x)  (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX4LCDLR4_DX4LCDLR4_X4RDQSND_M   GENMASK(24, 16)
#define DDR_PHY_DX4LCDLR4_DX4LCDLR4_X4RDQSND_X(x)\
	(((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX4LCDLR4_DX4LCDLR4_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX4LCDLR4_DX4LCDLR4_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX4LCDLR4_DX4LCDLR4_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4LCDLR5 */
#define DDR_PHY_DX4LCDLR5(t)      (t + 0xb94)

#define DDR_PHY_DX4LCDLR5_DX4LCDLR5_DQSGSD(x)    ((x) & GENMASK(8, 0))
#define DDR_PHY_DX4LCDLR5_DX4LCDLR5_DQSGSD_M     GENMASK(8, 0)
#define DDR_PHY_DX4LCDLR5_DX4LCDLR5_DQSGSD_X(x)  ((x) & GENMASK(8, 0))

#define DDR_PHY_DX4LCDLR5_DX4LCDLR5_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX4LCDLR5_DX4LCDLR5_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX4LCDLR5_DX4LCDLR5_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX4LCDLR5_DX4LCDLR5_X4DQSGSD(x)  (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX4LCDLR5_DX4LCDLR5_X4DQSGSD_M   GENMASK(24, 16)
#define DDR_PHY_DX4LCDLR5_DX4LCDLR5_X4DQSGSD_X(x)\
	(((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX4LCDLR5_DX4LCDLR5_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX4LCDLR5_DX4LCDLR5_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX4LCDLR5_DX4LCDLR5_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4MDLR0 */
#define DDR_PHY_DX4MDLR0(t)       (t + 0xba0)

#define DDR_PHY_DX4MDLR0_DX4MDLR0_IPRD(x)        ((x) & GENMASK(8, 0))
#define DDR_PHY_DX4MDLR0_DX4MDLR0_IPRD_M         GENMASK(8, 0)
#define DDR_PHY_DX4MDLR0_DX4MDLR0_IPRD_X(x)      ((x) & GENMASK(8, 0))

#define DDR_PHY_DX4MDLR0_DX4MDLR0_RESERVED_15_9(x) (((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX4MDLR0_DX4MDLR0_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX4MDLR0_DX4MDLR0_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX4MDLR0_DX4MDLR0_TPRD(x)        (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX4MDLR0_DX4MDLR0_TPRD_M         GENMASK(24, 16)
#define DDR_PHY_DX4MDLR0_DX4MDLR0_TPRD_X(x)      (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX4MDLR0_DX4MDLR0_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX4MDLR0_DX4MDLR0_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX4MDLR0_DX4MDLR0_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4MDLR1 */
#define DDR_PHY_DX4MDLR1(t)       (t + 0xba4)

#define DDR_PHY_DX4MDLR1_DX4MDLR1_MDLD(x)        ((x) & GENMASK(8, 0))
#define DDR_PHY_DX4MDLR1_DX4MDLR1_MDLD_M         GENMASK(8, 0)
#define DDR_PHY_DX4MDLR1_DX4MDLR1_MDLD_X(x)      ((x) & GENMASK(8, 0))

#define DDR_PHY_DX4MDLR1_DX4MDLR1_RESERVED_31_9(x) (((x) << 9) & GENMASK(31, 9))
#define DDR_PHY_DX4MDLR1_DX4MDLR1_RESERVED_31_9_M GENMASK(31, 9)
#define DDR_PHY_DX4MDLR1_DX4MDLR1_RESERVED_31_9_X(x)\
	(((x) & GENMASK(31, 9)) >> 9)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4GTR0 */
#define DDR_PHY_DX4GTR0(t)        (t + 0xbc0)

#define DDR_PHY_DX4GTR0_DX4GTR0_DGSL(x)          ((x) & GENMASK(4, 0))
#define DDR_PHY_DX4GTR0_DX4GTR0_DGSL_M           GENMASK(4, 0)
#define DDR_PHY_DX4GTR0_DX4GTR0_DGSL_X(x)        ((x) & GENMASK(4, 0))

#define DDR_PHY_DX4GTR0_DX4GTR0_RESERVED_7_5(x)  (((x) << 5) & GENMASK(7, 5))
#define DDR_PHY_DX4GTR0_DX4GTR0_RESERVED_7_5_M   GENMASK(7, 5)
#define DDR_PHY_DX4GTR0_DX4GTR0_RESERVED_7_5_X(x) (((x) & GENMASK(7, 5)) >> 5)

#define DDR_PHY_DX4GTR0_DX4GTR0_X4DGSL(x)        (((x) << 8) & GENMASK(12, 8))
#define DDR_PHY_DX4GTR0_DX4GTR0_X4DGSL_M         GENMASK(12, 8)
#define DDR_PHY_DX4GTR0_DX4GTR0_X4DGSL_X(x)      (((x) & GENMASK(12, 8)) >> 8)

#define DDR_PHY_DX4GTR0_DX4GTR0_RESERVED_15_13(x)\
	(((x) << 13) & GENMASK(15, 13))
#define DDR_PHY_DX4GTR0_DX4GTR0_RESERVED_15_13_M GENMASK(15, 13)
#define DDR_PHY_DX4GTR0_DX4GTR0_RESERVED_15_13_X(x)\
	(((x) & GENMASK(15, 13)) >> 13)

#define DDR_PHY_DX4GTR0_DX4GTR0_WLSL(x)          (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DX4GTR0_DX4GTR0_WLSL_M           GENMASK(19, 16)
#define DDR_PHY_DX4GTR0_DX4GTR0_WLSL_X(x)        (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DX4GTR0_DX4GTR0_X4WLSL(x)        (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX4GTR0_DX4GTR0_X4WLSL_M         GENMASK(23, 20)
#define DDR_PHY_DX4GTR0_DX4GTR0_X4WLSL_X(x)      (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX4GTR0_DX4GTR0_RESERVED_31_24(x)\
	(((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_DX4GTR0_DX4GTR0_RESERVED_31_24_M GENMASK(31, 24)
#define DDR_PHY_DX4GTR0_DX4GTR0_RESERVED_31_24_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4RSR0 */
#define DDR_PHY_DX4RSR0(t)        (t + 0xbd0)

#define DDR_PHY_DX4RSR0_DX4RSR0_QSGERR(x)        ((x) & GENMASK(15, 0))
#define DDR_PHY_DX4RSR0_DX4RSR0_QSGERR_M         GENMASK(15, 0)
#define DDR_PHY_DX4RSR0_DX4RSR0_QSGERR_X(x)      ((x) & GENMASK(15, 0))

#define DDR_PHY_DX4RSR0_DX4RSR0_X4QSGERR(x)      (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX4RSR0_DX4RSR0_X4QSGERR_M       GENMASK(31, 16)
#define DDR_PHY_DX4RSR0_DX4RSR0_X4QSGERR_X(x)    (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4RSR1 */
#define DDR_PHY_DX4RSR1(t)        (t + 0xbd4)

#define DDR_PHY_DX4RSR1_DX4RSR1_RDLVLERR(x)      ((x) & GENMASK(15, 0))
#define DDR_PHY_DX4RSR1_DX4RSR1_RDLVLERR_M       GENMASK(15, 0)
#define DDR_PHY_DX4RSR1_DX4RSR1_RDLVLERR_X(x)    ((x) & GENMASK(15, 0))

#define DDR_PHY_DX4RSR1_DX4RSR1_X4RDLVLERR(x)    (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX4RSR1_DX4RSR1_X4RDLVLERR_M     GENMASK(31, 16)
#define DDR_PHY_DX4RSR1_DX4RSR1_X4RDLVLERR_X(x)  (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4RSR2 */
#define DDR_PHY_DX4RSR2(t)        (t + 0xbd8)

#define DDR_PHY_DX4RSR2_DX4RSR2_WLAWN(x)         ((x) & GENMASK(15, 0))
#define DDR_PHY_DX4RSR2_DX4RSR2_WLAWN_M          GENMASK(15, 0)
#define DDR_PHY_DX4RSR2_DX4RSR2_WLAWN_X(x)       ((x) & GENMASK(15, 0))

#define DDR_PHY_DX4RSR2_DX4RSR2_X4WLAWN(x)       (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX4RSR2_DX4RSR2_X4WLAWN_M        GENMASK(31, 16)
#define DDR_PHY_DX4RSR2_DX4RSR2_X4WLAWN_X(x)     (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4RSR3 */
#define DDR_PHY_DX4RSR3(t)        (t + 0xbdc)

#define DDR_PHY_DX4RSR3_DX4RSR3_WLAERR(x)        ((x) & GENMASK(15, 0))
#define DDR_PHY_DX4RSR3_DX4RSR3_WLAERR_M         GENMASK(15, 0)
#define DDR_PHY_DX4RSR3_DX4RSR3_WLAERR_X(x)      ((x) & GENMASK(15, 0))

#define DDR_PHY_DX4RSR3_DX4RSR3_X4WLAERR(x)      (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX4RSR3_DX4RSR3_X4WLAERR_M       GENMASK(31, 16)
#define DDR_PHY_DX4RSR3_DX4RSR3_X4WLAERR_X(x)    (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4GSR0 */
#define DDR_PHY_DX4GSR0(t)        (t + 0xbe0)

#define DDR_PHY_DX4GSR0_DX4GSR0_WDQCAL(x)        ((x) & GENMASK(0, 0))
#define DDR_PHY_DX4GSR0_DX4GSR0_WDQCAL_M         GENMASK(0, 0)
#define DDR_PHY_DX4GSR0_DX4GSR0_WDQCAL_X(x)      ((x) & GENMASK(0, 0))

#define DDR_PHY_DX4GSR0_DX4GSR0_RDQSCAL(x)       (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX4GSR0_DX4GSR0_RDQSCAL_M        GENMASK(1, 1)
#define DDR_PHY_DX4GSR0_DX4GSR0_RDQSCAL_X(x)     (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX4GSR0_DX4GSR0_RDQSNCAL(x)      (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX4GSR0_DX4GSR0_RDQSNCAL_M       GENMASK(2, 2)
#define DDR_PHY_DX4GSR0_DX4GSR0_RDQSNCAL_X(x)    (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX4GSR0_DX4GSR0_GDQSCAL(x)       (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX4GSR0_DX4GSR0_GDQSCAL_M        GENMASK(3, 3)
#define DDR_PHY_DX4GSR0_DX4GSR0_GDQSCAL_X(x)     (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX4GSR0_DX4GSR0_WLCAL(x)         (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX4GSR0_DX4GSR0_WLCAL_M          GENMASK(4, 4)
#define DDR_PHY_DX4GSR0_DX4GSR0_WLCAL_X(x)       (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX4GSR0_DX4GSR0_WLDONE(x)        (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX4GSR0_DX4GSR0_WLDONE_M         GENMASK(5, 5)
#define DDR_PHY_DX4GSR0_DX4GSR0_WLDONE_X(x)      (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX4GSR0_DX4GSR0_WLERR(x)         (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX4GSR0_DX4GSR0_WLERR_M          GENMASK(6, 6)
#define DDR_PHY_DX4GSR0_DX4GSR0_WLERR_X(x)       (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX4GSR0_DX4GSR0_WLPRD(x)         (((x) << 7) & GENMASK(15, 7))
#define DDR_PHY_DX4GSR0_DX4GSR0_WLPRD_M          GENMASK(15, 7)
#define DDR_PHY_DX4GSR0_DX4GSR0_WLPRD_X(x)       (((x) & GENMASK(15, 7)) >> 7)

#define DDR_PHY_DX4GSR0_DX4GSR0_DPLOCK(x)        (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX4GSR0_DX4GSR0_DPLOCK_M         GENMASK(16, 16)
#define DDR_PHY_DX4GSR0_DX4GSR0_DPLOCK_X(x)      (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX4GSR0_DX4GSR0_GDQSPRD(x)       (((x) << 17) & GENMASK(25, 17))
#define DDR_PHY_DX4GSR0_DX4GSR0_GDQSPRD_M        GENMASK(25, 17)
#define DDR_PHY_DX4GSR0_DX4GSR0_GDQSPRD_X(x)     (((x) & GENMASK(25, 17)) >> 17)

#define DDR_PHY_DX4GSR0_DX4GSR0_WLWN(x)          (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_DX4GSR0_DX4GSR0_WLWN_M           GENMASK(26, 26)
#define DDR_PHY_DX4GSR0_DX4GSR0_WLWN_X(x)        (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_DX4GSR0_DX4GSR0_RESERVED_29_27(x)\
	(((x) << 27) & GENMASK(29, 27))
#define DDR_PHY_DX4GSR0_DX4GSR0_RESERVED_29_27_M GENMASK(29, 27)
#define DDR_PHY_DX4GSR0_DX4GSR0_RESERVED_29_27_X(x)\
	(((x) & GENMASK(29, 27)) >> 27)

#define DDR_PHY_DX4GSR0_DX4GSR0_WLDQ(x)          (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX4GSR0_DX4GSR0_WLDQ_M           GENMASK(30, 30)
#define DDR_PHY_DX4GSR0_DX4GSR0_WLDQ_X(x)        (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX4GSR0_DX4GSR0_RESERVED_31(x)   (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX4GSR0_DX4GSR0_RESERVED_31_M    GENMASK(31, 31)
#define DDR_PHY_DX4GSR0_DX4GSR0_RESERVED_31_X(x) (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4GSR1 */
#define DDR_PHY_DX4GSR1(t)        (t + 0xbe4)

#define DDR_PHY_DX4GSR1_DX4GSR1_DLTDONE(x)       ((x) & GENMASK(0, 0))
#define DDR_PHY_DX4GSR1_DX4GSR1_DLTDONE_M        GENMASK(0, 0)
#define DDR_PHY_DX4GSR1_DX4GSR1_DLTDONE_X(x)     ((x) & GENMASK(0, 0))

#define DDR_PHY_DX4GSR1_DX4GSR1_DLTCODE(x)       (((x) << 1) & GENMASK(24, 1))
#define DDR_PHY_DX4GSR1_DX4GSR1_DLTCODE_M        GENMASK(24, 1)
#define DDR_PHY_DX4GSR1_DX4GSR1_DLTCODE_X(x)     (((x) & GENMASK(24, 1)) >> 1)

#define DDR_PHY_DX4GSR1_DX4GSR1_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX4GSR1_DX4GSR1_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX4GSR1_DX4GSR1_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4GSR2 */
#define DDR_PHY_DX4GSR2(t)        (t + 0xbe8)

#define DDR_PHY_DX4GSR2_DX4GSR2_RDERR(x)         ((x) & GENMASK(0, 0))
#define DDR_PHY_DX4GSR2_DX4GSR2_RDERR_M          GENMASK(0, 0)
#define DDR_PHY_DX4GSR2_DX4GSR2_RDERR_X(x)       ((x) & GENMASK(0, 0))

#define DDR_PHY_DX4GSR2_DX4GSR2_RDWN(x)          (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX4GSR2_DX4GSR2_RDWN_M           GENMASK(1, 1)
#define DDR_PHY_DX4GSR2_DX4GSR2_RDWN_X(x)        (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX4GSR2_DX4GSR2_WDERR(x)         (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX4GSR2_DX4GSR2_WDERR_M          GENMASK(2, 2)
#define DDR_PHY_DX4GSR2_DX4GSR2_WDERR_X(x)       (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX4GSR2_DX4GSR2_WDWN(x)          (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX4GSR2_DX4GSR2_WDWN_M           GENMASK(3, 3)
#define DDR_PHY_DX4GSR2_DX4GSR2_WDWN_X(x)        (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX4GSR2_DX4GSR2_REERR(x)         (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX4GSR2_DX4GSR2_REERR_M          GENMASK(4, 4)
#define DDR_PHY_DX4GSR2_DX4GSR2_REERR_X(x)       (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX4GSR2_DX4GSR2_REWN(x)          (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX4GSR2_DX4GSR2_REWN_M           GENMASK(5, 5)
#define DDR_PHY_DX4GSR2_DX4GSR2_REWN_X(x)        (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX4GSR2_DX4GSR2_WEERR(x)         (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX4GSR2_DX4GSR2_WEERR_M          GENMASK(6, 6)
#define DDR_PHY_DX4GSR2_DX4GSR2_WEERR_X(x)       (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX4GSR2_DX4GSR2_WEWN(x)          (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_DX4GSR2_DX4GSR2_WEWN_M           GENMASK(7, 7)
#define DDR_PHY_DX4GSR2_DX4GSR2_WEWN_X(x)        (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_DX4GSR2_DX4GSR2_ESTAT(x)         (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX4GSR2_DX4GSR2_ESTAT_M          GENMASK(11, 8)
#define DDR_PHY_DX4GSR2_DX4GSR2_ESTAT_X(x)       (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX4GSR2_DX4GSR2_DBDQ(x)          (((x) << 12) & GENMASK(19, 12))
#define DDR_PHY_DX4GSR2_DX4GSR2_DBDQ_M           GENMASK(19, 12)
#define DDR_PHY_DX4GSR2_DX4GSR2_DBDQ_X(x)        (((x) & GENMASK(19, 12)) >> 12)

#define DDR_PHY_DX4GSR2_DX4GSR2_SRDERR(x)        (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX4GSR2_DX4GSR2_SRDERR_M         GENMASK(20, 20)
#define DDR_PHY_DX4GSR2_DX4GSR2_SRDERR_X(x)      (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX4GSR2_DX4GSR2_RESERVED_21(x)   (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX4GSR2_DX4GSR2_RESERVED_21_M    GENMASK(21, 21)
#define DDR_PHY_DX4GSR2_DX4GSR2_RESERVED_21_X(x) (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX4GSR2_DX4GSR2_GSDQSCAL(x)      (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX4GSR2_DX4GSR2_GSDQSCAL_M       GENMASK(22, 22)
#define DDR_PHY_DX4GSR2_DX4GSR2_GSDQSCAL_X(x)    (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX4GSR2_DX4GSR2_GSDQSPRD(x)      (((x) << 23) & GENMASK(31, 23))
#define DDR_PHY_DX4GSR2_DX4GSR2_GSDQSPRD_M       GENMASK(31, 23)
#define DDR_PHY_DX4GSR2_DX4GSR2_GSDQSPRD_X(x)    (((x) & GENMASK(31, 23)) >> 23)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4GSR3 */
#define DDR_PHY_DX4GSR3(t)        (t + 0xbec)

#define DDR_PHY_DX4GSR3_DX4GSR3_SRDPC(x)         ((x) & GENMASK(1, 0))
#define DDR_PHY_DX4GSR3_DX4GSR3_SRDPC_M          GENMASK(1, 0)
#define DDR_PHY_DX4GSR3_DX4GSR3_SRDPC_X(x)       ((x) & GENMASK(1, 0))

#define DDR_PHY_DX4GSR3_DX4GSR3_RESERVED_7_2(x)  (((x) << 2) & GENMASK(7, 2))
#define DDR_PHY_DX4GSR3_DX4GSR3_RESERVED_7_2_M   GENMASK(7, 2)
#define DDR_PHY_DX4GSR3_DX4GSR3_RESERVED_7_2_X(x) (((x) & GENMASK(7, 2)) >> 2)

#define DDR_PHY_DX4GSR3_DX4GSR3_HVERR(x)         (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX4GSR3_DX4GSR3_HVERR_M          GENMASK(11, 8)
#define DDR_PHY_DX4GSR3_DX4GSR3_HVERR_X(x)       (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX4GSR3_DX4GSR3_HVWRN(x)         (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_DX4GSR3_DX4GSR3_HVWRN_M          GENMASK(15, 12)
#define DDR_PHY_DX4GSR3_DX4GSR3_HVWRN_X(x)       (((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_DX4GSR3_DX4GSR3_DVERR(x)         (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DX4GSR3_DX4GSR3_DVERR_M          GENMASK(19, 16)
#define DDR_PHY_DX4GSR3_DX4GSR3_DVERR_X(x)       (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DX4GSR3_DX4GSR3_DVWRN(x)         (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX4GSR3_DX4GSR3_DVWRN_M          GENMASK(23, 20)
#define DDR_PHY_DX4GSR3_DX4GSR3_DVWRN_X(x)       (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX4GSR3_DX4GSR3_ESTAT(x)         (((x) << 24) & GENMASK(26, 24))
#define DDR_PHY_DX4GSR3_DX4GSR3_ESTAT_M          GENMASK(26, 24)
#define DDR_PHY_DX4GSR3_DX4GSR3_ESTAT_X(x)       (((x) & GENMASK(26, 24)) >> 24)

#define DDR_PHY_DX4GSR3_DX4GSR3_RESERVED_31_27(x)\
	(((x) << 27) & GENMASK(31, 27))
#define DDR_PHY_DX4GSR3_DX4GSR3_RESERVED_31_27_M GENMASK(31, 27)
#define DDR_PHY_DX4GSR3_DX4GSR3_RESERVED_31_27_X(x)\
	(((x) & GENMASK(31, 27)) >> 27)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4GSR4 */
#define DDR_PHY_DX4GSR4(t)        (t + 0xbf0)

#define DDR_PHY_DX4GSR4_DX4GSR4_X4WDQCAL(x)      ((x) & GENMASK(0, 0))
#define DDR_PHY_DX4GSR4_DX4GSR4_X4WDQCAL_M       GENMASK(0, 0)
#define DDR_PHY_DX4GSR4_DX4GSR4_X4WDQCAL_X(x)    ((x) & GENMASK(0, 0))

#define DDR_PHY_DX4GSR4_DX4GSR4_X4RDQSCAL(x)     (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX4GSR4_DX4GSR4_X4RDQSCAL_M      GENMASK(1, 1)
#define DDR_PHY_DX4GSR4_DX4GSR4_X4RDQSCAL_X(x)   (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX4GSR4_DX4GSR4_X4RDQSNCAL(x)    (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX4GSR4_DX4GSR4_X4RDQSNCAL_M     GENMASK(2, 2)
#define DDR_PHY_DX4GSR4_DX4GSR4_X4RDQSNCAL_X(x)  (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX4GSR4_DX4GSR4_X4GDQSCAL(x)     (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX4GSR4_DX4GSR4_X4GDQSCAL_M      GENMASK(3, 3)
#define DDR_PHY_DX4GSR4_DX4GSR4_X4GDQSCAL_X(x)   (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX4GSR4_DX4GSR4_X4WLCAL(x)       (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX4GSR4_DX4GSR4_X4WLCAL_M        GENMASK(4, 4)
#define DDR_PHY_DX4GSR4_DX4GSR4_X4WLCAL_X(x)     (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX4GSR4_DX4GSR4_X4WLDONE(x)      (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX4GSR4_DX4GSR4_X4WLDONE_M       GENMASK(5, 5)
#define DDR_PHY_DX4GSR4_DX4GSR4_X4WLDONE_X(x)    (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX4GSR4_DX4GSR4_X4WLERR(x)       (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX4GSR4_DX4GSR4_X4WLERR_M        GENMASK(6, 6)
#define DDR_PHY_DX4GSR4_DX4GSR4_X4WLERR_X(x)     (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX4GSR4_DX4GSR4_X4WLPRD(x)       (((x) << 7) & GENMASK(15, 7))
#define DDR_PHY_DX4GSR4_DX4GSR4_X4WLPRD_M        GENMASK(15, 7)
#define DDR_PHY_DX4GSR4_DX4GSR4_X4WLPRD_X(x)     (((x) & GENMASK(15, 7)) >> 7)

#define DDR_PHY_DX4GSR4_DX4GSR4_X4DPLOCK(x)      (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX4GSR4_DX4GSR4_X4DPLOCK_M       GENMASK(16, 16)
#define DDR_PHY_DX4GSR4_DX4GSR4_X4DPLOCK_X(x)    (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX4GSR4_DX4GSR4_X4GDQSPRD(x)     (((x) << 17) & GENMASK(25, 17))
#define DDR_PHY_DX4GSR4_DX4GSR4_X4GDQSPRD_M      GENMASK(25, 17)
#define DDR_PHY_DX4GSR4_DX4GSR4_X4GDQSPRD_X(x)   (((x) & GENMASK(25, 17)) >> 17)

#define DDR_PHY_DX4GSR4_DX4GSR4_X4WLWN(x)        (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_DX4GSR4_DX4GSR4_X4WLWN_M         GENMASK(26, 26)
#define DDR_PHY_DX4GSR4_DX4GSR4_X4WLWN_X(x)      (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_DX4GSR4_DX4GSR4_RESERVED_29_27(x)\
	(((x) << 27) & GENMASK(29, 27))
#define DDR_PHY_DX4GSR4_DX4GSR4_RESERVED_29_27_M GENMASK(29, 27)
#define DDR_PHY_DX4GSR4_DX4GSR4_RESERVED_29_27_X(x)\
	(((x) & GENMASK(29, 27)) >> 27)

#define DDR_PHY_DX4GSR4_DX4GSR4_X4WLDQ(x)        (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX4GSR4_DX4GSR4_X4WLDQ_M         GENMASK(30, 30)
#define DDR_PHY_DX4GSR4_DX4GSR4_X4WLDQ_X(x)      (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX4GSR4_DX4GSR4_RESERVED_31(x)   (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX4GSR4_DX4GSR4_RESERVED_31_M    GENMASK(31, 31)
#define DDR_PHY_DX4GSR4_DX4GSR4_RESERVED_31_X(x) (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4GSR5 */
#define DDR_PHY_DX4GSR5(t)        (t + 0xbf4)

#define DDR_PHY_DX4GSR5_DX4GSR5_X4RDERR(x)       ((x) & GENMASK(0, 0))
#define DDR_PHY_DX4GSR5_DX4GSR5_X4RDERR_M        GENMASK(0, 0)
#define DDR_PHY_DX4GSR5_DX4GSR5_X4RDERR_X(x)     ((x) & GENMASK(0, 0))

#define DDR_PHY_DX4GSR5_DX4GSR5_X4RDWN(x)        (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX4GSR5_DX4GSR5_X4RDWN_M         GENMASK(1, 1)
#define DDR_PHY_DX4GSR5_DX4GSR5_X4RDWN_X(x)      (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX4GSR5_DX4GSR5_X4WDERR(x)       (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX4GSR5_DX4GSR5_X4WDERR_M        GENMASK(2, 2)
#define DDR_PHY_DX4GSR5_DX4GSR5_X4WDERR_X(x)     (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX4GSR5_DX4GSR5_X4WDWN(x)        (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX4GSR5_DX4GSR5_X4WDWN_M         GENMASK(3, 3)
#define DDR_PHY_DX4GSR5_DX4GSR5_X4WDWN_X(x)      (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX4GSR5_DX4GSR5_X4REERR(x)       (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX4GSR5_DX4GSR5_X4REERR_M        GENMASK(4, 4)
#define DDR_PHY_DX4GSR5_DX4GSR5_X4REERR_X(x)     (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX4GSR5_DX4GSR5_X4REWN(x)        (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX4GSR5_DX4GSR5_X4REWN_M         GENMASK(5, 5)
#define DDR_PHY_DX4GSR5_DX4GSR5_X4REWN_X(x)      (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX4GSR5_DX4GSR5_X4WEERR(x)       (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX4GSR5_DX4GSR5_X4WEERR_M        GENMASK(6, 6)
#define DDR_PHY_DX4GSR5_DX4GSR5_X4WEERR_X(x)     (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX4GSR5_DX4GSR5_X4WEWN(x)        (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_DX4GSR5_DX4GSR5_X4WEWN_M         GENMASK(7, 7)
#define DDR_PHY_DX4GSR5_DX4GSR5_X4WEWN_X(x)      (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_DX4GSR5_DX4GSR5_X4ESTAT(x)       (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX4GSR5_DX4GSR5_X4ESTAT_M        GENMASK(11, 8)
#define DDR_PHY_DX4GSR5_DX4GSR5_X4ESTAT_X(x)     (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX4GSR5_DX4GSR5_RESERVED_19_12(x)\
	(((x) << 12) & GENMASK(19, 12))
#define DDR_PHY_DX4GSR5_DX4GSR5_RESERVED_19_12_M GENMASK(19, 12)
#define DDR_PHY_DX4GSR5_DX4GSR5_RESERVED_19_12_X(x)\
	(((x) & GENMASK(19, 12)) >> 12)

#define DDR_PHY_DX4GSR5_DX4GSR5_X4SRDERR(x)      (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX4GSR5_DX4GSR5_X4SRDERR_M       GENMASK(20, 20)
#define DDR_PHY_DX4GSR5_DX4GSR5_X4SRDERR_X(x)    (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX4GSR5_DX4GSR5_RESERVED_21(x)   (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX4GSR5_DX4GSR5_RESERVED_21_M    GENMASK(21, 21)
#define DDR_PHY_DX4GSR5_DX4GSR5_RESERVED_21_X(x) (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX4GSR5_DX4GSR5_X4GSDQSCAL(x)    (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX4GSR5_DX4GSR5_X4GSDQSCAL_M     GENMASK(22, 22)
#define DDR_PHY_DX4GSR5_DX4GSR5_X4GSDQSCAL_X(x)  (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX4GSR5_DX4GSR5_X4GSDQSPRD(x)    (((x) << 23) & GENMASK(31, 23))
#define DDR_PHY_DX4GSR5_DX4GSR5_X4GSDQSPRD_M     GENMASK(31, 23)
#define DDR_PHY_DX4GSR5_DX4GSR5_X4GSDQSPRD_X(x)  (((x) & GENMASK(31, 23)) >> 23)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX4GSR6 */
#define DDR_PHY_DX4GSR6(t)        (t + 0xbf8)

#define DDR_PHY_DX4GSR6_DX4GSR6_RESERVED_1_0(x)  ((x) & GENMASK(1, 0))
#define DDR_PHY_DX4GSR6_DX4GSR6_RESERVED_1_0_M   GENMASK(1, 0)
#define DDR_PHY_DX4GSR6_DX4GSR6_RESERVED_1_0_X(x) ((x) & GENMASK(1, 0))

#define DDR_PHY_DX4GSR6_DX4GSR6_X4SRDPC(x)       (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DX4GSR6_DX4GSR6_X4SRDPC_M        GENMASK(3, 2)
#define DDR_PHY_DX4GSR6_DX4GSR6_X4SRDPC_X(x)     (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DX4GSR6_DX4GSR6_RESERVED_7_4(x)  (((x) << 4) & GENMASK(7, 4))
#define DDR_PHY_DX4GSR6_DX4GSR6_RESERVED_7_4_M   GENMASK(7, 4)
#define DDR_PHY_DX4GSR6_DX4GSR6_RESERVED_7_4_X(x) (((x) & GENMASK(7, 4)) >> 4)

#define DDR_PHY_DX4GSR6_DX4GSR6_X4HVERR(x)       (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX4GSR6_DX4GSR6_X4HVERR_M        GENMASK(11, 8)
#define DDR_PHY_DX4GSR6_DX4GSR6_X4HVERR_X(x)     (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX4GSR6_DX4GSR6_X4HVWRN(x)       (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_DX4GSR6_DX4GSR6_X4HVWRN_M        GENMASK(15, 12)
#define DDR_PHY_DX4GSR6_DX4GSR6_X4HVWRN_X(x)     (((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_DX4GSR6_DX4GSR6_X4DVERR(x)       (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DX4GSR6_DX4GSR6_X4DVERR_M        GENMASK(19, 16)
#define DDR_PHY_DX4GSR6_DX4GSR6_X4DVERR_X(x)     (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DX4GSR6_DX4GSR6_X4DVWRN(x)       (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX4GSR6_DX4GSR6_X4DVWRN_M        GENMASK(23, 20)
#define DDR_PHY_DX4GSR6_DX4GSR6_X4DVWRN_X(x)     (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX4GSR6_DX4GSR6_RESERVED_31_24(x)\
	(((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_DX4GSR6_DX4GSR6_RESERVED_31_24_M GENMASK(31, 24)
#define DDR_PHY_DX4GSR6_DX4GSR6_RESERVED_31_24_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5GCR0 */
#define DDR_PHY_DX5GCR0(t)        (t + 0xc00)

#define DDR_PHY_DX5GCR0_DX5GCR0_DXEN(x)          ((x) & GENMASK(0, 0))
#define DDR_PHY_DX5GCR0_DX5GCR0_DXEN_M           GENMASK(0, 0)
#define DDR_PHY_DX5GCR0_DX5GCR0_DXEN_X(x)        ((x) & GENMASK(0, 0))

#define DDR_PHY_DX5GCR0_DX5GCR0_DXIOM(x)         (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX5GCR0_DX5GCR0_DXIOM_M          GENMASK(1, 1)
#define DDR_PHY_DX5GCR0_DX5GCR0_DXIOM_X(x)       (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX5GCR0_DX5GCR0_DQSGOE(x)        (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX5GCR0_DX5GCR0_DQSGOE_M         GENMASK(2, 2)
#define DDR_PHY_DX5GCR0_DX5GCR0_DQSGOE_X(x)      (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX5GCR0_DX5GCR0_DQSGODT(x)       (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX5GCR0_DX5GCR0_DQSGODT_M        GENMASK(3, 3)
#define DDR_PHY_DX5GCR0_DX5GCR0_DQSGODT_X(x)     (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX5GCR0_DX5GCR0_RESERVED_4(x)    (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX5GCR0_DX5GCR0_RESERVED_4_M     GENMASK(4, 4)
#define DDR_PHY_DX5GCR0_DX5GCR0_RESERVED_4_X(x)  (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX5GCR0_DX5GCR0_DQSGPDR(x)       (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX5GCR0_DX5GCR0_DQSGPDR_M        GENMASK(5, 5)
#define DDR_PHY_DX5GCR0_DX5GCR0_DQSGPDR_X(x)     (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX5GCR0_DX5GCR0_RESERVED_6(x)    (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX5GCR0_DX5GCR0_RESERVED_6_M     GENMASK(6, 6)
#define DDR_PHY_DX5GCR0_DX5GCR0_RESERVED_6_X(x)  (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX5GCR0_DX5GCR0_PDRAL(x)         (((x) << 7) & GENMASK(8, 7))
#define DDR_PHY_DX5GCR0_DX5GCR0_PDRAL_M          GENMASK(8, 7)
#define DDR_PHY_DX5GCR0_DX5GCR0_PDRAL_X(x)       (((x) & GENMASK(8, 7)) >> 7)

#define DDR_PHY_DX5GCR0_DX5GCR0_RTTOH(x)         (((x) << 9) & GENMASK(10, 9))
#define DDR_PHY_DX5GCR0_DX5GCR0_RTTOH_M          GENMASK(10, 9)
#define DDR_PHY_DX5GCR0_DX5GCR0_RTTOH_X(x)       (((x) & GENMASK(10, 9)) >> 9)

#define DDR_PHY_DX5GCR0_DX5GCR0_RTTOAL(x)        (((x) << 11) & GENMASK(11, 11))
#define DDR_PHY_DX5GCR0_DX5GCR0_RTTOAL_M         GENMASK(11, 11)
#define DDR_PHY_DX5GCR0_DX5GCR0_RTTOAL_X(x)      (((x) & GENMASK(11, 11)) >> 11)

#define DDR_PHY_DX5GCR0_DX5GCR0_DQSSEPDR(x)      (((x) << 12) & GENMASK(12, 12))
#define DDR_PHY_DX5GCR0_DX5GCR0_DQSSEPDR_M       GENMASK(12, 12)
#define DDR_PHY_DX5GCR0_DX5GCR0_DQSSEPDR_X(x)    (((x) & GENMASK(12, 12)) >> 12)

#define DDR_PHY_DX5GCR0_DX5GCR0_DQSNSEPDR(x)     (((x) << 13) & GENMASK(13, 13))
#define DDR_PHY_DX5GCR0_DX5GCR0_DQSNSEPDR_M      GENMASK(13, 13)
#define DDR_PHY_DX5GCR0_DX5GCR0_DQSNSEPDR_X(x)   (((x) & GENMASK(13, 13)) >> 13)

#define DDR_PHY_DX5GCR0_DX5GCR0_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX5GCR0_DX5GCR0_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX5GCR0_DX5GCR0_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX5GCR0_DX5GCR0_PLLRST(x)        (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX5GCR0_DX5GCR0_PLLRST_M         GENMASK(16, 16)
#define DDR_PHY_DX5GCR0_DX5GCR0_PLLRST_X(x)      (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX5GCR0_DX5GCR0_PLLPD(x)         (((x) << 17) & GENMASK(17, 17))
#define DDR_PHY_DX5GCR0_DX5GCR0_PLLPD_M          GENMASK(17, 17)
#define DDR_PHY_DX5GCR0_DX5GCR0_PLLPD_X(x)       (((x) & GENMASK(17, 17)) >> 17)

#define DDR_PHY_DX5GCR0_DX5GCR0_GSHIFT(x)        (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_DX5GCR0_DX5GCR0_GSHIFT_M         GENMASK(18, 18)
#define DDR_PHY_DX5GCR0_DX5GCR0_GSHIFT_X(x)      (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_DX5GCR0_DX5GCR0_PLLBYP(x)        (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_DX5GCR0_DX5GCR0_PLLBYP_M         GENMASK(19, 19)
#define DDR_PHY_DX5GCR0_DX5GCR0_PLLBYP_X(x)      (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_DX5GCR0_DX5GCR0_RDDLY(x)         (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX5GCR0_DX5GCR0_RDDLY_M          GENMASK(23, 20)
#define DDR_PHY_DX5GCR0_DX5GCR0_RDDLY_X(x)       (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX5GCR0_DX5GCR0_RESERVED_29_24(x)\
	(((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX5GCR0_DX5GCR0_RESERVED_29_24_M GENMASK(29, 24)
#define DDR_PHY_DX5GCR0_DX5GCR0_RESERVED_29_24_X(x)\
	(((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX5GCR0_DX5GCR0_MDLEN(x)         (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX5GCR0_DX5GCR0_MDLEN_M          GENMASK(30, 30)
#define DDR_PHY_DX5GCR0_DX5GCR0_MDLEN_X(x)       (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX5GCR0_DX5GCR0_CALBYP(x)        (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX5GCR0_DX5GCR0_CALBYP_M         GENMASK(31, 31)
#define DDR_PHY_DX5GCR0_DX5GCR0_CALBYP_X(x)      (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5GCR1 */
#define DDR_PHY_DX5GCR1(t)        (t + 0xc04)

#define DDR_PHY_DX5GCR1_DX5GCR1_RESERVED_15_0(x) ((x) & GENMASK(15, 0))
#define DDR_PHY_DX5GCR1_DX5GCR1_RESERVED_15_0_M  GENMASK(15, 0)
#define DDR_PHY_DX5GCR1_DX5GCR1_RESERVED_15_0_X(x) ((x) & GENMASK(15, 0))

#define DDR_PHY_DX5GCR1_DX5GCR1_DXPDRMODE(x)     (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX5GCR1_DX5GCR1_DXPDRMODE_M      GENMASK(31, 16)
#define DDR_PHY_DX5GCR1_DX5GCR1_DXPDRMODE_X(x)   (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5GCR2 */
#define DDR_PHY_DX5GCR2(t)        (t + 0xc08)

#define DDR_PHY_DX5GCR2_DX5GCR2_DXTEMODE(x)      ((x) & GENMASK(15, 0))
#define DDR_PHY_DX5GCR2_DX5GCR2_DXTEMODE_M       GENMASK(15, 0)
#define DDR_PHY_DX5GCR2_DX5GCR2_DXTEMODE_X(x)    ((x) & GENMASK(15, 0))

#define DDR_PHY_DX5GCR2_DX5GCR2_DXOEMODE(x)      (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX5GCR2_DX5GCR2_DXOEMODE_M       GENMASK(31, 16)
#define DDR_PHY_DX5GCR2_DX5GCR2_DXOEMODE_X(x)    (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5GCR3 */
#define DDR_PHY_DX5GCR3(t)        (t + 0xc0c)

#define DDR_PHY_DX5GCR3_DX5GCR3_RESERVED_1_0(x)  ((x) & GENMASK(1, 0))
#define DDR_PHY_DX5GCR3_DX5GCR3_RESERVED_1_0_M   GENMASK(1, 0)
#define DDR_PHY_DX5GCR3_DX5GCR3_RESERVED_1_0_X(x) ((x) & GENMASK(1, 0))

#define DDR_PHY_DX5GCR3_DX5GCR3_DSPDRMODE(x)     (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DX5GCR3_DX5GCR3_DSPDRMODE_M      GENMASK(3, 2)
#define DDR_PHY_DX5GCR3_DX5GCR3_DSPDRMODE_X(x)   (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DX5GCR3_DX5GCR3_DSTEMODE(x)      (((x) << 4) & GENMASK(5, 4))
#define DDR_PHY_DX5GCR3_DX5GCR3_DSTEMODE_M       GENMASK(5, 4)
#define DDR_PHY_DX5GCR3_DX5GCR3_DSTEMODE_X(x)    (((x) & GENMASK(5, 4)) >> 4)

#define DDR_PHY_DX5GCR3_DX5GCR3_DSOEMODE(x)      (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX5GCR3_DX5GCR3_DSOEMODE_M       GENMASK(7, 6)
#define DDR_PHY_DX5GCR3_DX5GCR3_DSOEMODE_X(x)    (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX5GCR3_DX5GCR3_RESERVED_9_8(x)  (((x) << 8) & GENMASK(9, 8))
#define DDR_PHY_DX5GCR3_DX5GCR3_RESERVED_9_8_M   GENMASK(9, 8)
#define DDR_PHY_DX5GCR3_DX5GCR3_RESERVED_9_8_X(x) (((x) & GENMASK(9, 8)) >> 8)

#define DDR_PHY_DX5GCR3_DX5GCR3_DMPDRMODE(x)     (((x) << 10) & GENMASK(11, 10))
#define DDR_PHY_DX5GCR3_DX5GCR3_DMPDRMODE_M      GENMASK(11, 10)
#define DDR_PHY_DX5GCR3_DX5GCR3_DMPDRMODE_X(x)   (((x) & GENMASK(11, 10)) >> 10)

#define DDR_PHY_DX5GCR3_DX5GCR3_DMTEMODE(x)      (((x) << 12) & GENMASK(13, 12))
#define DDR_PHY_DX5GCR3_DX5GCR3_DMTEMODE_M       GENMASK(13, 12)
#define DDR_PHY_DX5GCR3_DX5GCR3_DMTEMODE_X(x)    (((x) & GENMASK(13, 12)) >> 12)

#define DDR_PHY_DX5GCR3_DX5GCR3_DMOEMODE(x)      (((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX5GCR3_DX5GCR3_DMOEMODE_M       GENMASK(15, 14)
#define DDR_PHY_DX5GCR3_DX5GCR3_DMOEMODE_X(x)    (((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX5GCR3_DX5GCR3_RESERVED_17_16(x)\
	(((x) << 16) & GENMASK(17, 16))
#define DDR_PHY_DX5GCR3_DX5GCR3_RESERVED_17_16_M GENMASK(17, 16)
#define DDR_PHY_DX5GCR3_DX5GCR3_RESERVED_17_16_X(x)\
	(((x) & GENMASK(17, 16)) >> 16)

#define DDR_PHY_DX5GCR3_DX5GCR3_OEBVT(x)         (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_DX5GCR3_DX5GCR3_OEBVT_M          GENMASK(18, 18)
#define DDR_PHY_DX5GCR3_DX5GCR3_OEBVT_X(x)       (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_DX5GCR3_DX5GCR3_PDRBVT(x)        (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_DX5GCR3_DX5GCR3_PDRBVT_M         GENMASK(19, 19)
#define DDR_PHY_DX5GCR3_DX5GCR3_PDRBVT_X(x)      (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_DX5GCR3_DX5GCR3_TEBVT(x)         (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX5GCR3_DX5GCR3_TEBVT_M          GENMASK(20, 20)
#define DDR_PHY_DX5GCR3_DX5GCR3_TEBVT_X(x)       (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX5GCR3_DX5GCR3_WDSBVT(x)        (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX5GCR3_DX5GCR3_WDSBVT_M         GENMASK(21, 21)
#define DDR_PHY_DX5GCR3_DX5GCR3_WDSBVT_X(x)      (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX5GCR3_DX5GCR3_RDSBVT(x)        (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX5GCR3_DX5GCR3_RDSBVT_M         GENMASK(22, 22)
#define DDR_PHY_DX5GCR3_DX5GCR3_RDSBVT_X(x)      (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX5GCR3_DX5GCR3_RGSLVT(x)        (((x) << 23) & GENMASK(23, 23))
#define DDR_PHY_DX5GCR3_DX5GCR3_RGSLVT_M         GENMASK(23, 23)
#define DDR_PHY_DX5GCR3_DX5GCR3_RGSLVT_X(x)      (((x) & GENMASK(23, 23)) >> 23)

#define DDR_PHY_DX5GCR3_DX5GCR3_WLLVT(x)         (((x) << 24) & GENMASK(24, 24))
#define DDR_PHY_DX5GCR3_DX5GCR3_WLLVT_M          GENMASK(24, 24)
#define DDR_PHY_DX5GCR3_DX5GCR3_WLLVT_X(x)       (((x) & GENMASK(24, 24)) >> 24)

#define DDR_PHY_DX5GCR3_DX5GCR3_WDLVT(x)         (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_DX5GCR3_DX5GCR3_WDLVT_M          GENMASK(25, 25)
#define DDR_PHY_DX5GCR3_DX5GCR3_WDLVT_X(x)       (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_DX5GCR3_DX5GCR3_RDLVT(x)         (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_DX5GCR3_DX5GCR3_RDLVT_M          GENMASK(26, 26)
#define DDR_PHY_DX5GCR3_DX5GCR3_RDLVT_X(x)       (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_DX5GCR3_DX5GCR3_RGLVT(x)         (((x) << 27) & GENMASK(27, 27))
#define DDR_PHY_DX5GCR3_DX5GCR3_RGLVT_M          GENMASK(27, 27)
#define DDR_PHY_DX5GCR3_DX5GCR3_RGLVT_X(x)       (((x) & GENMASK(27, 27)) >> 27)

#define DDR_PHY_DX5GCR3_DX5GCR3_WDBVT(x)         (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_DX5GCR3_DX5GCR3_WDBVT_M          GENMASK(28, 28)
#define DDR_PHY_DX5GCR3_DX5GCR3_WDBVT_X(x)       (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_DX5GCR3_DX5GCR3_RDBVT(x)         (((x) << 29) & GENMASK(29, 29))
#define DDR_PHY_DX5GCR3_DX5GCR3_RDBVT_M          GENMASK(29, 29)
#define DDR_PHY_DX5GCR3_DX5GCR3_RDBVT_X(x)       (((x) & GENMASK(29, 29)) >> 29)

#define DDR_PHY_DX5GCR3_DX5GCR3_WDMBVT(x)        (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX5GCR3_DX5GCR3_WDMBVT_M         GENMASK(30, 30)
#define DDR_PHY_DX5GCR3_DX5GCR3_WDMBVT_X(x)      (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX5GCR3_DX5GCR3_RDMBVT(x)        (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX5GCR3_DX5GCR3_RDMBVT_M         GENMASK(31, 31)
#define DDR_PHY_DX5GCR3_DX5GCR3_RDMBVT_X(x)      (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5GCR4 */
#define DDR_PHY_DX5GCR4(t)        (t + 0xc10)

#define DDR_PHY_DX5GCR4_DX5GCR4_DXREFIMON(x)     ((x) & GENMASK(1, 0))
#define DDR_PHY_DX5GCR4_DX5GCR4_DXREFIMON_M      GENMASK(1, 0)
#define DDR_PHY_DX5GCR4_DX5GCR4_DXREFIMON_X(x)   ((x) & GENMASK(1, 0))

#define DDR_PHY_DX5GCR4_DX5GCR4_DXREFIEN(x)      (((x) << 2) & GENMASK(5, 2))
#define DDR_PHY_DX5GCR4_DX5GCR4_DXREFIEN_M       GENMASK(5, 2)
#define DDR_PHY_DX5GCR4_DX5GCR4_DXREFIEN_X(x)    (((x) & GENMASK(5, 2)) >> 2)

#define DDR_PHY_DX5GCR4_DX5GCR4_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX5GCR4_DX5GCR4_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX5GCR4_DX5GCR4_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX5GCR4_DX5GCR4_DXREFSSEL(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX5GCR4_DX5GCR4_DXREFSSEL_M      GENMASK(13, 8)
#define DDR_PHY_DX5GCR4_DX5GCR4_DXREFSSEL_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX5GCR4_DX5GCR4_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX5GCR4_DX5GCR4_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX5GCR4_DX5GCR4_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX5GCR4_DX5GCR4_DXREFESEL(x)     (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX5GCR4_DX5GCR4_DXREFESEL_M      GENMASK(21, 16)
#define DDR_PHY_DX5GCR4_DX5GCR4_DXREFESEL_X(x)   (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX5GCR4_DX5GCR4_RESERVED_24_22(x)\
	(((x) << 22) & GENMASK(24, 22))
#define DDR_PHY_DX5GCR4_DX5GCR4_RESERVED_24_22_M GENMASK(24, 22)
#define DDR_PHY_DX5GCR4_DX5GCR4_RESERVED_24_22_X(x)\
	(((x) & GENMASK(24, 22)) >> 22)

#define DDR_PHY_DX5GCR4_DX5GCR4_DXREFSEN(x)      (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_DX5GCR4_DX5GCR4_DXREFSEN_M       GENMASK(25, 25)
#define DDR_PHY_DX5GCR4_DX5GCR4_DXREFSEN_X(x)    (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_DX5GCR4_DX5GCR4_DXREFEEN(x)      (((x) << 26) & GENMASK(27, 26))
#define DDR_PHY_DX5GCR4_DX5GCR4_DXREFEEN_M       GENMASK(27, 26)
#define DDR_PHY_DX5GCR4_DX5GCR4_DXREFEEN_X(x)    (((x) & GENMASK(27, 26)) >> 26)

#define DDR_PHY_DX5GCR4_DX5GCR4_DXREFPEN(x)      (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_DX5GCR4_DX5GCR4_DXREFPEN_M       GENMASK(28, 28)
#define DDR_PHY_DX5GCR4_DX5GCR4_DXREFPEN_X(x)    (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_DX5GCR4_DX5GCR4_DXREFIOM(x)      (((x) << 29) & GENMASK(31, 29))
#define DDR_PHY_DX5GCR4_DX5GCR4_DXREFIOM_M       GENMASK(31, 29)
#define DDR_PHY_DX5GCR4_DX5GCR4_DXREFIOM_X(x)    (((x) & GENMASK(31, 29)) >> 29)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5GCR5 */
#define DDR_PHY_DX5GCR5(t)        (t + 0xc14)

#define DDR_PHY_DX5GCR5_DX5GCR5_DXREFISELR0(x)   ((x) & GENMASK(5, 0))
#define DDR_PHY_DX5GCR5_DX5GCR5_DXREFISELR0_M    GENMASK(5, 0)
#define DDR_PHY_DX5GCR5_DX5GCR5_DXREFISELR0_X(x) ((x) & GENMASK(5, 0))

#define DDR_PHY_DX5GCR5_DX5GCR5_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX5GCR5_DX5GCR5_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX5GCR5_DX5GCR5_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX5GCR5_DX5GCR5_DXREFISELR1(x)   (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX5GCR5_DX5GCR5_DXREFISELR1_M    GENMASK(13, 8)
#define DDR_PHY_DX5GCR5_DX5GCR5_DXREFISELR1_X(x) (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX5GCR5_DX5GCR5_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX5GCR5_DX5GCR5_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX5GCR5_DX5GCR5_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX5GCR5_DX5GCR5_DXREFISELR2(x)   (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX5GCR5_DX5GCR5_DXREFISELR2_M    GENMASK(21, 16)
#define DDR_PHY_DX5GCR5_DX5GCR5_DXREFISELR2_X(x) (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX5GCR5_DX5GCR5_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX5GCR5_DX5GCR5_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX5GCR5_DX5GCR5_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX5GCR5_DX5GCR5_DXREFISELR3(x)   (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX5GCR5_DX5GCR5_DXREFISELR3_M    GENMASK(29, 24)
#define DDR_PHY_DX5GCR5_DX5GCR5_DXREFISELR3_X(x) (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX5GCR5_DX5GCR5_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX5GCR5_DX5GCR5_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX5GCR5_DX5GCR5_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5GCR6 */
#define DDR_PHY_DX5GCR6(t)        (t + 0xc18)

#define DDR_PHY_DX5GCR6_DX5GCR6_DXDQVREFR0(x)    ((x) & GENMASK(5, 0))
#define DDR_PHY_DX5GCR6_DX5GCR6_DXDQVREFR0_M     GENMASK(5, 0)
#define DDR_PHY_DX5GCR6_DX5GCR6_DXDQVREFR0_X(x)  ((x) & GENMASK(5, 0))

#define DDR_PHY_DX5GCR6_DX5GCR6_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX5GCR6_DX5GCR6_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX5GCR6_DX5GCR6_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX5GCR6_DX5GCR6_DXDQVREFR1(x)    (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX5GCR6_DX5GCR6_DXDQVREFR1_M     GENMASK(13, 8)
#define DDR_PHY_DX5GCR6_DX5GCR6_DXDQVREFR1_X(x)  (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX5GCR6_DX5GCR6_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX5GCR6_DX5GCR6_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX5GCR6_DX5GCR6_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX5GCR6_DX5GCR6_DXDQVREFR2(x)    (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX5GCR6_DX5GCR6_DXDQVREFR2_M     GENMASK(21, 16)
#define DDR_PHY_DX5GCR6_DX5GCR6_DXDQVREFR2_X(x)  (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX5GCR6_DX5GCR6_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX5GCR6_DX5GCR6_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX5GCR6_DX5GCR6_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX5GCR6_DX5GCR6_DXDQVREFR3(x)    (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX5GCR6_DX5GCR6_DXDQVREFR3_M     GENMASK(29, 24)
#define DDR_PHY_DX5GCR6_DX5GCR6_DXDQVREFR3_X(x)  (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX5GCR6_DX5GCR6_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX5GCR6_DX5GCR6_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX5GCR6_DX5GCR6_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5GCR7 */
#define DDR_PHY_DX5GCR7(t)        (t + 0xc1c)

#define DDR_PHY_DX5GCR7_DX5GCR7_RESERVED_1_0(x)  ((x) & GENMASK(1, 0))
#define DDR_PHY_DX5GCR7_DX5GCR7_RESERVED_1_0_M   GENMASK(1, 0)
#define DDR_PHY_DX5GCR7_DX5GCR7_RESERVED_1_0_X(x) ((x) & GENMASK(1, 0))

#define DDR_PHY_DX5GCR7_DX5GCR7_X4DSPDRMODE(x)   (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DX5GCR7_DX5GCR7_X4DSPDRMODE_M    GENMASK(3, 2)
#define DDR_PHY_DX5GCR7_DX5GCR7_X4DSPDRMODE_X(x) (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DX5GCR7_DX5GCR7_X4DSTEMODE(x)    (((x) << 4) & GENMASK(5, 4))
#define DDR_PHY_DX5GCR7_DX5GCR7_X4DSTEMODE_M     GENMASK(5, 4)
#define DDR_PHY_DX5GCR7_DX5GCR7_X4DSTEMODE_X(x)  (((x) & GENMASK(5, 4)) >> 4)

#define DDR_PHY_DX5GCR7_DX5GCR7_X4DSOEMODE(x)    (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX5GCR7_DX5GCR7_X4DSOEMODE_M     GENMASK(7, 6)
#define DDR_PHY_DX5GCR7_DX5GCR7_X4DSOEMODE_X(x)  (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX5GCR7_DX5GCR7_RESERVED_9_8(x)  (((x) << 8) & GENMASK(9, 8))
#define DDR_PHY_DX5GCR7_DX5GCR7_RESERVED_9_8_M   GENMASK(9, 8)
#define DDR_PHY_DX5GCR7_DX5GCR7_RESERVED_9_8_X(x) (((x) & GENMASK(9, 8)) >> 8)

#define DDR_PHY_DX5GCR7_DX5GCR7_X4DXPDRMODE(x)   (((x) << 10) & GENMASK(11, 10))
#define DDR_PHY_DX5GCR7_DX5GCR7_X4DXPDRMODE_M    GENMASK(11, 10)
#define DDR_PHY_DX5GCR7_DX5GCR7_X4DXPDRMODE_X(x) (((x) & GENMASK(11, 10)) >> 10)

#define DDR_PHY_DX5GCR7_DX5GCR7_X4DXTEMODE(x)    (((x) << 12) & GENMASK(13, 12))
#define DDR_PHY_DX5GCR7_DX5GCR7_X4DXTEMODE_M     GENMASK(13, 12)
#define DDR_PHY_DX5GCR7_DX5GCR7_X4DXTEMODE_X(x)  (((x) & GENMASK(13, 12)) >> 12)

#define DDR_PHY_DX5GCR7_DX5GCR7_X4DXOEMODE(x)    (((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX5GCR7_DX5GCR7_X4DXOEMODE_M     GENMASK(15, 14)
#define DDR_PHY_DX5GCR7_DX5GCR7_X4DXOEMODE_X(x)  (((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX5GCR7_DX5GCR7_X4DQSGOE(x)      (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX5GCR7_DX5GCR7_X4DQSGOE_M       GENMASK(16, 16)
#define DDR_PHY_DX5GCR7_DX5GCR7_X4DQSGOE_X(x)    (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX5GCR7_DX5GCR7_X4DQSGODT(x)     (((x) << 17) & GENMASK(17, 17))
#define DDR_PHY_DX5GCR7_DX5GCR7_X4DQSGODT_M      GENMASK(17, 17)
#define DDR_PHY_DX5GCR7_DX5GCR7_X4DQSGODT_X(x)   (((x) & GENMASK(17, 17)) >> 17)

#define DDR_PHY_DX5GCR7_DX5GCR7_RESERVED_18(x)   (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_DX5GCR7_DX5GCR7_RESERVED_18_M    GENMASK(18, 18)
#define DDR_PHY_DX5GCR7_DX5GCR7_RESERVED_18_X(x) (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_DX5GCR7_DX5GCR7_X4DQSGPDR(x)     (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_DX5GCR7_DX5GCR7_X4DQSGPDR_M      GENMASK(19, 19)
#define DDR_PHY_DX5GCR7_DX5GCR7_X4DQSGPDR_X(x)   (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_DX5GCR7_DX5GCR7_RESERVED_20(x)   (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX5GCR7_DX5GCR7_RESERVED_20_M    GENMASK(20, 20)
#define DDR_PHY_DX5GCR7_DX5GCR7_RESERVED_20_X(x) (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX5GCR7_DX5GCR7_X4DQSSEPDR(x)    (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX5GCR7_DX5GCR7_X4DQSSEPDR_M     GENMASK(21, 21)
#define DDR_PHY_DX5GCR7_DX5GCR7_X4DQSSEPDR_X(x)  (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX5GCR7_DX5GCR7_X4DQSNSEPDR(x)   (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX5GCR7_DX5GCR7_X4DQSNSEPDR_M    GENMASK(22, 22)
#define DDR_PHY_DX5GCR7_DX5GCR7_X4DQSNSEPDR_X(x) (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX5GCR7_DX5GCR7_X4RTTOH(x)       (((x) << 23) & GENMASK(24, 23))
#define DDR_PHY_DX5GCR7_DX5GCR7_X4RTTOH_M        GENMASK(24, 23)
#define DDR_PHY_DX5GCR7_DX5GCR7_X4RTTOH_X(x)     (((x) & GENMASK(24, 23)) >> 23)

#define DDR_PHY_DX5GCR7_DX5GCR7_X4RTTOAL(x)      (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_DX5GCR7_DX5GCR7_X4RTTOAL_M       GENMASK(25, 25)
#define DDR_PHY_DX5GCR7_DX5GCR7_X4RTTOAL_X(x)    (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_DX5GCR7_DX5GCR7_X4RDDLY(x)       (((x) << 26) & GENMASK(29, 26))
#define DDR_PHY_DX5GCR7_DX5GCR7_X4RDDLY_M        GENMASK(29, 26)
#define DDR_PHY_DX5GCR7_DX5GCR7_X4RDDLY_X(x)     (((x) & GENMASK(29, 26)) >> 26)

#define DDR_PHY_DX5GCR7_DX5GCR7_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX5GCR7_DX5GCR7_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX5GCR7_DX5GCR7_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5GCR8 */
#define DDR_PHY_DX5GCR8(t)        (t + 0xc20)

#define DDR_PHY_DX5GCR8_DX5GCR8_X4DXREFISELR0(x) ((x) & GENMASK(5, 0))
#define DDR_PHY_DX5GCR8_DX5GCR8_X4DXREFISELR0_M  GENMASK(5, 0)
#define DDR_PHY_DX5GCR8_DX5GCR8_X4DXREFISELR0_X(x) ((x) & GENMASK(5, 0))

#define DDR_PHY_DX5GCR8_DX5GCR8_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX5GCR8_DX5GCR8_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX5GCR8_DX5GCR8_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX5GCR8_DX5GCR8_X4DXREFISELR1(x) (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX5GCR8_DX5GCR8_X4DXREFISELR1_M  GENMASK(13, 8)
#define DDR_PHY_DX5GCR8_DX5GCR8_X4DXREFISELR1_X(x) (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX5GCR8_DX5GCR8_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX5GCR8_DX5GCR8_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX5GCR8_DX5GCR8_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX5GCR8_DX5GCR8_X4DXREFISELR2(x) (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX5GCR8_DX5GCR8_X4DXREFISELR2_M  GENMASK(21, 16)
#define DDR_PHY_DX5GCR8_DX5GCR8_X4DXREFISELR2_X(x)\
	(((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX5GCR8_DX5GCR8_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX5GCR8_DX5GCR8_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX5GCR8_DX5GCR8_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX5GCR8_DX5GCR8_X4DXREFISELR3(x) (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX5GCR8_DX5GCR8_X4DXREFISELR3_M  GENMASK(29, 24)
#define DDR_PHY_DX5GCR8_DX5GCR8_X4DXREFISELR3_X(x)\
	(((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX5GCR8_DX5GCR8_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX5GCR8_DX5GCR8_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX5GCR8_DX5GCR8_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5GCR9 */
#define DDR_PHY_DX5GCR9(t)        (t + 0xc24)

#define DDR_PHY_DX5GCR9_DX5GCR9_X4DXDQVREFR0(x)  ((x) & GENMASK(5, 0))
#define DDR_PHY_DX5GCR9_DX5GCR9_X4DXDQVREFR0_M   GENMASK(5, 0)
#define DDR_PHY_DX5GCR9_DX5GCR9_X4DXDQVREFR0_X(x) ((x) & GENMASK(5, 0))

#define DDR_PHY_DX5GCR9_DX5GCR9_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX5GCR9_DX5GCR9_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX5GCR9_DX5GCR9_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX5GCR9_DX5GCR9_X4DXDQVREFR1(x)  (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX5GCR9_DX5GCR9_X4DXDQVREFR1_M   GENMASK(13, 8)
#define DDR_PHY_DX5GCR9_DX5GCR9_X4DXDQVREFR1_X(x) (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX5GCR9_DX5GCR9_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX5GCR9_DX5GCR9_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX5GCR9_DX5GCR9_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX5GCR9_DX5GCR9_X4DXDQVREFR2(x)  (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX5GCR9_DX5GCR9_X4DXDQVREFR2_M   GENMASK(21, 16)
#define DDR_PHY_DX5GCR9_DX5GCR9_X4DXDQVREFR2_X(x)\
	(((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX5GCR9_DX5GCR9_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX5GCR9_DX5GCR9_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX5GCR9_DX5GCR9_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX5GCR9_DX5GCR9_X4DXDQVREFR3(x)  (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX5GCR9_DX5GCR9_X4DXDQVREFR3_M   GENMASK(29, 24)
#define DDR_PHY_DX5GCR9_DX5GCR9_X4DXDQVREFR3_X(x)\
	(((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX5GCR9_DX5GCR9_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX5GCR9_DX5GCR9_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX5GCR9_DX5GCR9_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5BDLR0 */
#define DDR_PHY_DX5BDLR0(t)       (t + 0xc40)

#define DDR_PHY_DX5BDLR0_DX5BDLR0_DQ0WBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX5BDLR0_DX5BDLR0_DQ0WBD_M       GENMASK(5, 0)
#define DDR_PHY_DX5BDLR0_DX5BDLR0_DQ0WBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX5BDLR0_DX5BDLR0_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX5BDLR0_DX5BDLR0_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX5BDLR0_DX5BDLR0_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX5BDLR0_DX5BDLR0_DQ1WBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX5BDLR0_DX5BDLR0_DQ1WBD_M       GENMASK(13, 8)
#define DDR_PHY_DX5BDLR0_DX5BDLR0_DQ1WBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX5BDLR0_DX5BDLR0_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX5BDLR0_DX5BDLR0_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX5BDLR0_DX5BDLR0_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX5BDLR0_DX5BDLR0_DQ2WBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX5BDLR0_DX5BDLR0_DQ2WBD_M       GENMASK(21, 16)
#define DDR_PHY_DX5BDLR0_DX5BDLR0_DQ2WBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX5BDLR0_DX5BDLR0_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX5BDLR0_DX5BDLR0_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX5BDLR0_DX5BDLR0_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX5BDLR0_DX5BDLR0_DQ3WBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX5BDLR0_DX5BDLR0_DQ3WBD_M       GENMASK(29, 24)
#define DDR_PHY_DX5BDLR0_DX5BDLR0_DQ3WBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX5BDLR0_DX5BDLR0_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX5BDLR0_DX5BDLR0_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX5BDLR0_DX5BDLR0_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5BDLR1 */
#define DDR_PHY_DX5BDLR1(t)       (t + 0xc44)

#define DDR_PHY_DX5BDLR1_DX5BDLR1_DQ4WBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX5BDLR1_DX5BDLR1_DQ4WBD_M       GENMASK(5, 0)
#define DDR_PHY_DX5BDLR1_DX5BDLR1_DQ4WBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX5BDLR1_DX5BDLR1_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX5BDLR1_DX5BDLR1_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX5BDLR1_DX5BDLR1_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX5BDLR1_DX5BDLR1_DQ5WBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX5BDLR1_DX5BDLR1_DQ5WBD_M       GENMASK(13, 8)
#define DDR_PHY_DX5BDLR1_DX5BDLR1_DQ5WBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX5BDLR1_DX5BDLR1_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX5BDLR1_DX5BDLR1_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX5BDLR1_DX5BDLR1_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX5BDLR1_DX5BDLR1_DQ6WBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX5BDLR1_DX5BDLR1_DQ6WBD_M       GENMASK(21, 16)
#define DDR_PHY_DX5BDLR1_DX5BDLR1_DQ6WBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX5BDLR1_DX5BDLR1_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX5BDLR1_DX5BDLR1_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX5BDLR1_DX5BDLR1_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX5BDLR1_DX5BDLR1_DQ7WBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX5BDLR1_DX5BDLR1_DQ7WBD_M       GENMASK(29, 24)
#define DDR_PHY_DX5BDLR1_DX5BDLR1_DQ7WBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX5BDLR1_DX5BDLR1_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX5BDLR1_DX5BDLR1_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX5BDLR1_DX5BDLR1_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5BDLR2 */
#define DDR_PHY_DX5BDLR2(t)       (t + 0xc48)

#define DDR_PHY_DX5BDLR2_DX5BDLR2_DMWBD(x)       ((x) & GENMASK(5, 0))
#define DDR_PHY_DX5BDLR2_DX5BDLR2_DMWBD_M        GENMASK(5, 0)
#define DDR_PHY_DX5BDLR2_DX5BDLR2_DMWBD_X(x)     ((x) & GENMASK(5, 0))

#define DDR_PHY_DX5BDLR2_DX5BDLR2_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX5BDLR2_DX5BDLR2_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX5BDLR2_DX5BDLR2_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX5BDLR2_DX5BDLR2_DSWBD(x)       (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX5BDLR2_DX5BDLR2_DSWBD_M        GENMASK(13, 8)
#define DDR_PHY_DX5BDLR2_DX5BDLR2_DSWBD_X(x)     (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX5BDLR2_DX5BDLR2_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX5BDLR2_DX5BDLR2_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX5BDLR2_DX5BDLR2_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX5BDLR2_DX5BDLR2_DSOEBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX5BDLR2_DX5BDLR2_DSOEBD_M       GENMASK(21, 16)
#define DDR_PHY_DX5BDLR2_DX5BDLR2_DSOEBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX5BDLR2_DX5BDLR2_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX5BDLR2_DX5BDLR2_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX5BDLR2_DX5BDLR2_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5BDLR3 */
#define DDR_PHY_DX5BDLR3(t)       (t + 0xc50)

#define DDR_PHY_DX5BDLR3_DX5BDLR3_DQ0RBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX5BDLR3_DX5BDLR3_DQ0RBD_M       GENMASK(5, 0)
#define DDR_PHY_DX5BDLR3_DX5BDLR3_DQ0RBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX5BDLR3_DX5BDLR3_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX5BDLR3_DX5BDLR3_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX5BDLR3_DX5BDLR3_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX5BDLR3_DX5BDLR3_DQ1RBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX5BDLR3_DX5BDLR3_DQ1RBD_M       GENMASK(13, 8)
#define DDR_PHY_DX5BDLR3_DX5BDLR3_DQ1RBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX5BDLR3_DX5BDLR3_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX5BDLR3_DX5BDLR3_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX5BDLR3_DX5BDLR3_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX5BDLR3_DX5BDLR3_DQ2RBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX5BDLR3_DX5BDLR3_DQ2RBD_M       GENMASK(21, 16)
#define DDR_PHY_DX5BDLR3_DX5BDLR3_DQ2RBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX5BDLR3_DX5BDLR3_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX5BDLR3_DX5BDLR3_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX5BDLR3_DX5BDLR3_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX5BDLR3_DX5BDLR3_DQ3RBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX5BDLR3_DX5BDLR3_DQ3RBD_M       GENMASK(29, 24)
#define DDR_PHY_DX5BDLR3_DX5BDLR3_DQ3RBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX5BDLR3_DX5BDLR3_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX5BDLR3_DX5BDLR3_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX5BDLR3_DX5BDLR3_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5BDLR4 */
#define DDR_PHY_DX5BDLR4(t)       (t + 0xc54)

#define DDR_PHY_DX5BDLR4_DX5BDLR4_DQ4RBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX5BDLR4_DX5BDLR4_DQ4RBD_M       GENMASK(5, 0)
#define DDR_PHY_DX5BDLR4_DX5BDLR4_DQ4RBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX5BDLR4_DX5BDLR4_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX5BDLR4_DX5BDLR4_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX5BDLR4_DX5BDLR4_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX5BDLR4_DX5BDLR4_DQ5RBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX5BDLR4_DX5BDLR4_DQ5RBD_M       GENMASK(13, 8)
#define DDR_PHY_DX5BDLR4_DX5BDLR4_DQ5RBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX5BDLR4_DX5BDLR4_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX5BDLR4_DX5BDLR4_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX5BDLR4_DX5BDLR4_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX5BDLR4_DX5BDLR4_DQ6RBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX5BDLR4_DX5BDLR4_DQ6RBD_M       GENMASK(21, 16)
#define DDR_PHY_DX5BDLR4_DX5BDLR4_DQ6RBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX5BDLR4_DX5BDLR4_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX5BDLR4_DX5BDLR4_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX5BDLR4_DX5BDLR4_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX5BDLR4_DX5BDLR4_DQ7RBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX5BDLR4_DX5BDLR4_DQ7RBD_M       GENMASK(29, 24)
#define DDR_PHY_DX5BDLR4_DX5BDLR4_DQ7RBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX5BDLR4_DX5BDLR4_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX5BDLR4_DX5BDLR4_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX5BDLR4_DX5BDLR4_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5BDLR5 */
#define DDR_PHY_DX5BDLR5(t)       (t + 0xc58)

#define DDR_PHY_DX5BDLR5_DX5BDLR5_DMRBD(x)       ((x) & GENMASK(5, 0))
#define DDR_PHY_DX5BDLR5_DX5BDLR5_DMRBD_M        GENMASK(5, 0)
#define DDR_PHY_DX5BDLR5_DX5BDLR5_DMRBD_X(x)     ((x) & GENMASK(5, 0))

#define DDR_PHY_DX5BDLR5_DX5BDLR5_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX5BDLR5_DX5BDLR5_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX5BDLR5_DX5BDLR5_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX5BDLR5_DX5BDLR5_DSRBD(x)       (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX5BDLR5_DX5BDLR5_DSRBD_M        GENMASK(13, 8)
#define DDR_PHY_DX5BDLR5_DX5BDLR5_DSRBD_X(x)     (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX5BDLR5_DX5BDLR5_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX5BDLR5_DX5BDLR5_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX5BDLR5_DX5BDLR5_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX5BDLR5_DX5BDLR5_DSNRBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX5BDLR5_DX5BDLR5_DSNRBD_M       GENMASK(21, 16)
#define DDR_PHY_DX5BDLR5_DX5BDLR5_DSNRBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX5BDLR5_DX5BDLR5_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX5BDLR5_DX5BDLR5_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX5BDLR5_DX5BDLR5_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5BDLR6 */
#define DDR_PHY_DX5BDLR6(t)       (t + 0xc60)

#define DDR_PHY_DX5BDLR6_DX5BDLR6_RESERVED_7_0(x) ((x) & GENMASK(7, 0))
#define DDR_PHY_DX5BDLR6_DX5BDLR6_RESERVED_7_0_M GENMASK(7, 0)
#define DDR_PHY_DX5BDLR6_DX5BDLR6_RESERVED_7_0_X(x) ((x) & GENMASK(7, 0))

#define DDR_PHY_DX5BDLR6_DX5BDLR6_PDRBD(x)       (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX5BDLR6_DX5BDLR6_PDRBD_M        GENMASK(13, 8)
#define DDR_PHY_DX5BDLR6_DX5BDLR6_PDRBD_X(x)     (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX5BDLR6_DX5BDLR6_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX5BDLR6_DX5BDLR6_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX5BDLR6_DX5BDLR6_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX5BDLR6_DX5BDLR6_TERBD(x)       (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX5BDLR6_DX5BDLR6_TERBD_M        GENMASK(21, 16)
#define DDR_PHY_DX5BDLR6_DX5BDLR6_TERBD_X(x)     (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX5BDLR6_DX5BDLR6_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX5BDLR6_DX5BDLR6_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX5BDLR6_DX5BDLR6_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5BDLR7 */
#define DDR_PHY_DX5BDLR7(t)       (t + 0xc64)

#define DDR_PHY_DX5BDLR7_DX5BDLR7_X4DMWBD(x)     ((x) & GENMASK(5, 0))
#define DDR_PHY_DX5BDLR7_DX5BDLR7_X4DMWBD_M      GENMASK(5, 0)
#define DDR_PHY_DX5BDLR7_DX5BDLR7_X4DMWBD_X(x)   ((x) & GENMASK(5, 0))

#define DDR_PHY_DX5BDLR7_DX5BDLR7_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX5BDLR7_DX5BDLR7_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX5BDLR7_DX5BDLR7_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX5BDLR7_DX5BDLR7_X4DSWBD(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX5BDLR7_DX5BDLR7_X4DSWBD_M      GENMASK(13, 8)
#define DDR_PHY_DX5BDLR7_DX5BDLR7_X4DSWBD_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX5BDLR7_DX5BDLR7_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX5BDLR7_DX5BDLR7_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX5BDLR7_DX5BDLR7_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX5BDLR7_DX5BDLR7_X4DSOEBD(x)    (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX5BDLR7_DX5BDLR7_X4DSOEBD_M     GENMASK(21, 16)
#define DDR_PHY_DX5BDLR7_DX5BDLR7_X4DSOEBD_X(x)  (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX5BDLR7_DX5BDLR7_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX5BDLR7_DX5BDLR7_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX5BDLR7_DX5BDLR7_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5BDLR8 */
#define DDR_PHY_DX5BDLR8(t)       (t + 0xc68)

#define DDR_PHY_DX5BDLR8_DX5BDLR8_X4DMRBD(x)     ((x) & GENMASK(5, 0))
#define DDR_PHY_DX5BDLR8_DX5BDLR8_X4DMRBD_M      GENMASK(5, 0)
#define DDR_PHY_DX5BDLR8_DX5BDLR8_X4DMRBD_X(x)   ((x) & GENMASK(5, 0))

#define DDR_PHY_DX5BDLR8_DX5BDLR8_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX5BDLR8_DX5BDLR8_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX5BDLR8_DX5BDLR8_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX5BDLR8_DX5BDLR8_X4DSRBD(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX5BDLR8_DX5BDLR8_X4DSRBD_M      GENMASK(13, 8)
#define DDR_PHY_DX5BDLR8_DX5BDLR8_X4DSRBD_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX5BDLR8_DX5BDLR8_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX5BDLR8_DX5BDLR8_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX5BDLR8_DX5BDLR8_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX5BDLR8_DX5BDLR8_X4DSNRBD(x)    (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX5BDLR8_DX5BDLR8_X4DSNRBD_M     GENMASK(21, 16)
#define DDR_PHY_DX5BDLR8_DX5BDLR8_X4DSNRBD_X(x)  (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX5BDLR8_DX5BDLR8_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX5BDLR8_DX5BDLR8_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX5BDLR8_DX5BDLR8_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5BDLR9 */
#define DDR_PHY_DX5BDLR9(t)       (t + 0xc6c)

#define DDR_PHY_DX5BDLR9_DX5BDLR9_RESERVED_7_0(x) ((x) & GENMASK(7, 0))
#define DDR_PHY_DX5BDLR9_DX5BDLR9_RESERVED_7_0_M GENMASK(7, 0)
#define DDR_PHY_DX5BDLR9_DX5BDLR9_RESERVED_7_0_X(x) ((x) & GENMASK(7, 0))

#define DDR_PHY_DX5BDLR9_DX5BDLR9_X4PDRBD(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX5BDLR9_DX5BDLR9_X4PDRBD_M      GENMASK(13, 8)
#define DDR_PHY_DX5BDLR9_DX5BDLR9_X4PDRBD_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX5BDLR9_DX5BDLR9_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX5BDLR9_DX5BDLR9_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX5BDLR9_DX5BDLR9_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX5BDLR9_DX5BDLR9_X4TERBD(x)     (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX5BDLR9_DX5BDLR9_X4TERBD_M      GENMASK(21, 16)
#define DDR_PHY_DX5BDLR9_DX5BDLR9_X4TERBD_X(x)   (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX5BDLR9_DX5BDLR9_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX5BDLR9_DX5BDLR9_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX5BDLR9_DX5BDLR9_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5LCDLR0 */
#define DDR_PHY_DX5LCDLR0(t)      (t + 0xc80)

#define DDR_PHY_DX5LCDLR0_DX5LCDLR0_WLD(x)       ((x) & GENMASK(8, 0))
#define DDR_PHY_DX5LCDLR0_DX5LCDLR0_WLD_M        GENMASK(8, 0)
#define DDR_PHY_DX5LCDLR0_DX5LCDLR0_WLD_X(x)     ((x) & GENMASK(8, 0))

#define DDR_PHY_DX5LCDLR0_DX5LCDLR0_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX5LCDLR0_DX5LCDLR0_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX5LCDLR0_DX5LCDLR0_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX5LCDLR0_DX5LCDLR0_X4WLD(x)     (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX5LCDLR0_DX5LCDLR0_X4WLD_M      GENMASK(24, 16)
#define DDR_PHY_DX5LCDLR0_DX5LCDLR0_X4WLD_X(x)   (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX5LCDLR0_DX5LCDLR0_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX5LCDLR0_DX5LCDLR0_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX5LCDLR0_DX5LCDLR0_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5LCDLR1 */
#define DDR_PHY_DX5LCDLR1(t)      (t + 0xc84)

#define DDR_PHY_DX5LCDLR1_DX5LCDLR1_WDQD(x)      ((x) & GENMASK(8, 0))
#define DDR_PHY_DX5LCDLR1_DX5LCDLR1_WDQD_M       GENMASK(8, 0)
#define DDR_PHY_DX5LCDLR1_DX5LCDLR1_WDQD_X(x)    ((x) & GENMASK(8, 0))

#define DDR_PHY_DX5LCDLR1_DX5LCDLR1_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX5LCDLR1_DX5LCDLR1_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX5LCDLR1_DX5LCDLR1_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX5LCDLR1_DX5LCDLR1_X4WDQD(x)    (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX5LCDLR1_DX5LCDLR1_X4WDQD_M     GENMASK(24, 16)
#define DDR_PHY_DX5LCDLR1_DX5LCDLR1_X4WDQD_X(x)  (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX5LCDLR1_DX5LCDLR1_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX5LCDLR1_DX5LCDLR1_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX5LCDLR1_DX5LCDLR1_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5LCDLR2 */
#define DDR_PHY_DX5LCDLR2(t)      (t + 0xc88)

#define DDR_PHY_DX5LCDLR2_DX5LCDLR2_DQSGD(x)     ((x) & GENMASK(8, 0))
#define DDR_PHY_DX5LCDLR2_DX5LCDLR2_DQSGD_M      GENMASK(8, 0)
#define DDR_PHY_DX5LCDLR2_DX5LCDLR2_DQSGD_X(x)   ((x) & GENMASK(8, 0))

#define DDR_PHY_DX5LCDLR2_DX5LCDLR2_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX5LCDLR2_DX5LCDLR2_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX5LCDLR2_DX5LCDLR2_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX5LCDLR2_DX5LCDLR2_X4DQSGD(x)   (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX5LCDLR2_DX5LCDLR2_X4DQSGD_M    GENMASK(24, 16)
#define DDR_PHY_DX5LCDLR2_DX5LCDLR2_X4DQSGD_X(x) (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX5LCDLR2_DX5LCDLR2_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX5LCDLR2_DX5LCDLR2_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX5LCDLR2_DX5LCDLR2_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5LCDLR3 */
#define DDR_PHY_DX5LCDLR3(t)      (t + 0xc8c)

#define DDR_PHY_DX5LCDLR3_DX5LCDLR3_RDQSD(x)     ((x) & GENMASK(8, 0))
#define DDR_PHY_DX5LCDLR3_DX5LCDLR3_RDQSD_M      GENMASK(8, 0)
#define DDR_PHY_DX5LCDLR3_DX5LCDLR3_RDQSD_X(x)   ((x) & GENMASK(8, 0))

#define DDR_PHY_DX5LCDLR3_DX5LCDLR3_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX5LCDLR3_DX5LCDLR3_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX5LCDLR3_DX5LCDLR3_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX5LCDLR3_DX5LCDLR3_X4RDQSD(x)   (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX5LCDLR3_DX5LCDLR3_X4RDQSD_M    GENMASK(24, 16)
#define DDR_PHY_DX5LCDLR3_DX5LCDLR3_X4RDQSD_X(x) (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX5LCDLR3_DX5LCDLR3_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX5LCDLR3_DX5LCDLR3_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX5LCDLR3_DX5LCDLR3_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5LCDLR4 */
#define DDR_PHY_DX5LCDLR4(t)      (t + 0xc90)

#define DDR_PHY_DX5LCDLR4_DX5LCDLR4_RDQSND(x)    ((x) & GENMASK(8, 0))
#define DDR_PHY_DX5LCDLR4_DX5LCDLR4_RDQSND_M     GENMASK(8, 0)
#define DDR_PHY_DX5LCDLR4_DX5LCDLR4_RDQSND_X(x)  ((x) & GENMASK(8, 0))

#define DDR_PHY_DX5LCDLR4_DX5LCDLR4_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX5LCDLR4_DX5LCDLR4_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX5LCDLR4_DX5LCDLR4_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX5LCDLR4_DX5LCDLR4_X4RDQSND(x)  (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX5LCDLR4_DX5LCDLR4_X4RDQSND_M   GENMASK(24, 16)
#define DDR_PHY_DX5LCDLR4_DX5LCDLR4_X4RDQSND_X(x)\
	(((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX5LCDLR4_DX5LCDLR4_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX5LCDLR4_DX5LCDLR4_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX5LCDLR4_DX5LCDLR4_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5LCDLR5 */
#define DDR_PHY_DX5LCDLR5(t)      (t + 0xc94)

#define DDR_PHY_DX5LCDLR5_DX5LCDLR5_DQSGSD(x)    ((x) & GENMASK(8, 0))
#define DDR_PHY_DX5LCDLR5_DX5LCDLR5_DQSGSD_M     GENMASK(8, 0)
#define DDR_PHY_DX5LCDLR5_DX5LCDLR5_DQSGSD_X(x)  ((x) & GENMASK(8, 0))

#define DDR_PHY_DX5LCDLR5_DX5LCDLR5_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX5LCDLR5_DX5LCDLR5_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX5LCDLR5_DX5LCDLR5_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX5LCDLR5_DX5LCDLR5_X4DQSGSD(x)  (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX5LCDLR5_DX5LCDLR5_X4DQSGSD_M   GENMASK(24, 16)
#define DDR_PHY_DX5LCDLR5_DX5LCDLR5_X4DQSGSD_X(x)\
	(((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX5LCDLR5_DX5LCDLR5_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX5LCDLR5_DX5LCDLR5_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX5LCDLR5_DX5LCDLR5_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5MDLR0 */
#define DDR_PHY_DX5MDLR0(t)       (t + 0xca0)

#define DDR_PHY_DX5MDLR0_DX5MDLR0_IPRD(x)        ((x) & GENMASK(8, 0))
#define DDR_PHY_DX5MDLR0_DX5MDLR0_IPRD_M         GENMASK(8, 0)
#define DDR_PHY_DX5MDLR0_DX5MDLR0_IPRD_X(x)      ((x) & GENMASK(8, 0))

#define DDR_PHY_DX5MDLR0_DX5MDLR0_RESERVED_15_9(x) (((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX5MDLR0_DX5MDLR0_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX5MDLR0_DX5MDLR0_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX5MDLR0_DX5MDLR0_TPRD(x)        (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX5MDLR0_DX5MDLR0_TPRD_M         GENMASK(24, 16)
#define DDR_PHY_DX5MDLR0_DX5MDLR0_TPRD_X(x)      (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX5MDLR0_DX5MDLR0_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX5MDLR0_DX5MDLR0_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX5MDLR0_DX5MDLR0_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5MDLR1 */
#define DDR_PHY_DX5MDLR1(t)       (t + 0xca4)

#define DDR_PHY_DX5MDLR1_DX5MDLR1_MDLD(x)        ((x) & GENMASK(8, 0))
#define DDR_PHY_DX5MDLR1_DX5MDLR1_MDLD_M         GENMASK(8, 0)
#define DDR_PHY_DX5MDLR1_DX5MDLR1_MDLD_X(x)      ((x) & GENMASK(8, 0))

#define DDR_PHY_DX5MDLR1_DX5MDLR1_RESERVED_31_9(x) (((x) << 9) & GENMASK(31, 9))
#define DDR_PHY_DX5MDLR1_DX5MDLR1_RESERVED_31_9_M GENMASK(31, 9)
#define DDR_PHY_DX5MDLR1_DX5MDLR1_RESERVED_31_9_X(x)\
	(((x) & GENMASK(31, 9)) >> 9)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5GTR0 */
#define DDR_PHY_DX5GTR0(t)        (t + 0xcc0)

#define DDR_PHY_DX5GTR0_DX5GTR0_DGSL(x)          ((x) & GENMASK(4, 0))
#define DDR_PHY_DX5GTR0_DX5GTR0_DGSL_M           GENMASK(4, 0)
#define DDR_PHY_DX5GTR0_DX5GTR0_DGSL_X(x)        ((x) & GENMASK(4, 0))

#define DDR_PHY_DX5GTR0_DX5GTR0_RESERVED_7_5(x)  (((x) << 5) & GENMASK(7, 5))
#define DDR_PHY_DX5GTR0_DX5GTR0_RESERVED_7_5_M   GENMASK(7, 5)
#define DDR_PHY_DX5GTR0_DX5GTR0_RESERVED_7_5_X(x) (((x) & GENMASK(7, 5)) >> 5)

#define DDR_PHY_DX5GTR0_DX5GTR0_X4DGSL(x)        (((x) << 8) & GENMASK(12, 8))
#define DDR_PHY_DX5GTR0_DX5GTR0_X4DGSL_M         GENMASK(12, 8)
#define DDR_PHY_DX5GTR0_DX5GTR0_X4DGSL_X(x)      (((x) & GENMASK(12, 8)) >> 8)

#define DDR_PHY_DX5GTR0_DX5GTR0_RESERVED_15_13(x)\
	(((x) << 13) & GENMASK(15, 13))
#define DDR_PHY_DX5GTR0_DX5GTR0_RESERVED_15_13_M GENMASK(15, 13)
#define DDR_PHY_DX5GTR0_DX5GTR0_RESERVED_15_13_X(x)\
	(((x) & GENMASK(15, 13)) >> 13)

#define DDR_PHY_DX5GTR0_DX5GTR0_WLSL(x)          (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DX5GTR0_DX5GTR0_WLSL_M           GENMASK(19, 16)
#define DDR_PHY_DX5GTR0_DX5GTR0_WLSL_X(x)        (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DX5GTR0_DX5GTR0_X4WLSL(x)        (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX5GTR0_DX5GTR0_X4WLSL_M         GENMASK(23, 20)
#define DDR_PHY_DX5GTR0_DX5GTR0_X4WLSL_X(x)      (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX5GTR0_DX5GTR0_RESERVED_31_24(x)\
	(((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_DX5GTR0_DX5GTR0_RESERVED_31_24_M GENMASK(31, 24)
#define DDR_PHY_DX5GTR0_DX5GTR0_RESERVED_31_24_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5RSR0 */
#define DDR_PHY_DX5RSR0(t)        (t + 0xcd0)

#define DDR_PHY_DX5RSR0_DX5RSR0_QSGERR(x)        ((x) & GENMASK(15, 0))
#define DDR_PHY_DX5RSR0_DX5RSR0_QSGERR_M         GENMASK(15, 0)
#define DDR_PHY_DX5RSR0_DX5RSR0_QSGERR_X(x)      ((x) & GENMASK(15, 0))

#define DDR_PHY_DX5RSR0_DX5RSR0_X4QSGERR(x)      (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX5RSR0_DX5RSR0_X4QSGERR_M       GENMASK(31, 16)
#define DDR_PHY_DX5RSR0_DX5RSR0_X4QSGERR_X(x)    (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5RSR1 */
#define DDR_PHY_DX5RSR1(t)        (t + 0xcd4)

#define DDR_PHY_DX5RSR1_DX5RSR1_RDLVLERR(x)      ((x) & GENMASK(15, 0))
#define DDR_PHY_DX5RSR1_DX5RSR1_RDLVLERR_M       GENMASK(15, 0)
#define DDR_PHY_DX5RSR1_DX5RSR1_RDLVLERR_X(x)    ((x) & GENMASK(15, 0))

#define DDR_PHY_DX5RSR1_DX5RSR1_X4RDLVLERR(x)    (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX5RSR1_DX5RSR1_X4RDLVLERR_M     GENMASK(31, 16)
#define DDR_PHY_DX5RSR1_DX5RSR1_X4RDLVLERR_X(x)  (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5RSR2 */
#define DDR_PHY_DX5RSR2(t)        (t + 0xcd8)

#define DDR_PHY_DX5RSR2_DX5RSR2_WLAWN(x)         ((x) & GENMASK(15, 0))
#define DDR_PHY_DX5RSR2_DX5RSR2_WLAWN_M          GENMASK(15, 0)
#define DDR_PHY_DX5RSR2_DX5RSR2_WLAWN_X(x)       ((x) & GENMASK(15, 0))

#define DDR_PHY_DX5RSR2_DX5RSR2_X4WLAWN(x)       (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX5RSR2_DX5RSR2_X4WLAWN_M        GENMASK(31, 16)
#define DDR_PHY_DX5RSR2_DX5RSR2_X4WLAWN_X(x)     (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5RSR3 */
#define DDR_PHY_DX5RSR3(t)        (t + 0xcdc)

#define DDR_PHY_DX5RSR3_DX5RSR3_WLAERR(x)        ((x) & GENMASK(15, 0))
#define DDR_PHY_DX5RSR3_DX5RSR3_WLAERR_M         GENMASK(15, 0)
#define DDR_PHY_DX5RSR3_DX5RSR3_WLAERR_X(x)      ((x) & GENMASK(15, 0))

#define DDR_PHY_DX5RSR3_DX5RSR3_X4WLAERR(x)      (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX5RSR3_DX5RSR3_X4WLAERR_M       GENMASK(31, 16)
#define DDR_PHY_DX5RSR3_DX5RSR3_X4WLAERR_X(x)    (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5GSR0 */
#define DDR_PHY_DX5GSR0(t)        (t + 0xce0)

#define DDR_PHY_DX5GSR0_DX5GSR0_WDQCAL(x)        ((x) & GENMASK(0, 0))
#define DDR_PHY_DX5GSR0_DX5GSR0_WDQCAL_M         GENMASK(0, 0)
#define DDR_PHY_DX5GSR0_DX5GSR0_WDQCAL_X(x)      ((x) & GENMASK(0, 0))

#define DDR_PHY_DX5GSR0_DX5GSR0_RDQSCAL(x)       (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX5GSR0_DX5GSR0_RDQSCAL_M        GENMASK(1, 1)
#define DDR_PHY_DX5GSR0_DX5GSR0_RDQSCAL_X(x)     (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX5GSR0_DX5GSR0_RDQSNCAL(x)      (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX5GSR0_DX5GSR0_RDQSNCAL_M       GENMASK(2, 2)
#define DDR_PHY_DX5GSR0_DX5GSR0_RDQSNCAL_X(x)    (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX5GSR0_DX5GSR0_GDQSCAL(x)       (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX5GSR0_DX5GSR0_GDQSCAL_M        GENMASK(3, 3)
#define DDR_PHY_DX5GSR0_DX5GSR0_GDQSCAL_X(x)     (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX5GSR0_DX5GSR0_WLCAL(x)         (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX5GSR0_DX5GSR0_WLCAL_M          GENMASK(4, 4)
#define DDR_PHY_DX5GSR0_DX5GSR0_WLCAL_X(x)       (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX5GSR0_DX5GSR0_WLDONE(x)        (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX5GSR0_DX5GSR0_WLDONE_M         GENMASK(5, 5)
#define DDR_PHY_DX5GSR0_DX5GSR0_WLDONE_X(x)      (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX5GSR0_DX5GSR0_WLERR(x)         (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX5GSR0_DX5GSR0_WLERR_M          GENMASK(6, 6)
#define DDR_PHY_DX5GSR0_DX5GSR0_WLERR_X(x)       (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX5GSR0_DX5GSR0_WLPRD(x)         (((x) << 7) & GENMASK(15, 7))
#define DDR_PHY_DX5GSR0_DX5GSR0_WLPRD_M          GENMASK(15, 7)
#define DDR_PHY_DX5GSR0_DX5GSR0_WLPRD_X(x)       (((x) & GENMASK(15, 7)) >> 7)

#define DDR_PHY_DX5GSR0_DX5GSR0_DPLOCK(x)        (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX5GSR0_DX5GSR0_DPLOCK_M         GENMASK(16, 16)
#define DDR_PHY_DX5GSR0_DX5GSR0_DPLOCK_X(x)      (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX5GSR0_DX5GSR0_GDQSPRD(x)       (((x) << 17) & GENMASK(25, 17))
#define DDR_PHY_DX5GSR0_DX5GSR0_GDQSPRD_M        GENMASK(25, 17)
#define DDR_PHY_DX5GSR0_DX5GSR0_GDQSPRD_X(x)     (((x) & GENMASK(25, 17)) >> 17)

#define DDR_PHY_DX5GSR0_DX5GSR0_WLWN(x)          (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_DX5GSR0_DX5GSR0_WLWN_M           GENMASK(26, 26)
#define DDR_PHY_DX5GSR0_DX5GSR0_WLWN_X(x)        (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_DX5GSR0_DX5GSR0_RESERVED_29_27(x)\
	(((x) << 27) & GENMASK(29, 27))
#define DDR_PHY_DX5GSR0_DX5GSR0_RESERVED_29_27_M GENMASK(29, 27)
#define DDR_PHY_DX5GSR0_DX5GSR0_RESERVED_29_27_X(x)\
	(((x) & GENMASK(29, 27)) >> 27)

#define DDR_PHY_DX5GSR0_DX5GSR0_WLDQ(x)          (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX5GSR0_DX5GSR0_WLDQ_M           GENMASK(30, 30)
#define DDR_PHY_DX5GSR0_DX5GSR0_WLDQ_X(x)        (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX5GSR0_DX5GSR0_RESERVED_31(x)   (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX5GSR0_DX5GSR0_RESERVED_31_M    GENMASK(31, 31)
#define DDR_PHY_DX5GSR0_DX5GSR0_RESERVED_31_X(x) (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5GSR1 */
#define DDR_PHY_DX5GSR1(t)        (t + 0xce4)

#define DDR_PHY_DX5GSR1_DX5GSR1_DLTDONE(x)       ((x) & GENMASK(0, 0))
#define DDR_PHY_DX5GSR1_DX5GSR1_DLTDONE_M        GENMASK(0, 0)
#define DDR_PHY_DX5GSR1_DX5GSR1_DLTDONE_X(x)     ((x) & GENMASK(0, 0))

#define DDR_PHY_DX5GSR1_DX5GSR1_DLTCODE(x)       (((x) << 1) & GENMASK(24, 1))
#define DDR_PHY_DX5GSR1_DX5GSR1_DLTCODE_M        GENMASK(24, 1)
#define DDR_PHY_DX5GSR1_DX5GSR1_DLTCODE_X(x)     (((x) & GENMASK(24, 1)) >> 1)

#define DDR_PHY_DX5GSR1_DX5GSR1_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX5GSR1_DX5GSR1_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX5GSR1_DX5GSR1_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5GSR2 */
#define DDR_PHY_DX5GSR2(t)        (t + 0xce8)

#define DDR_PHY_DX5GSR2_DX5GSR2_RDERR(x)         ((x) & GENMASK(0, 0))
#define DDR_PHY_DX5GSR2_DX5GSR2_RDERR_M          GENMASK(0, 0)
#define DDR_PHY_DX5GSR2_DX5GSR2_RDERR_X(x)       ((x) & GENMASK(0, 0))

#define DDR_PHY_DX5GSR2_DX5GSR2_RDWN(x)          (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX5GSR2_DX5GSR2_RDWN_M           GENMASK(1, 1)
#define DDR_PHY_DX5GSR2_DX5GSR2_RDWN_X(x)        (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX5GSR2_DX5GSR2_WDERR(x)         (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX5GSR2_DX5GSR2_WDERR_M          GENMASK(2, 2)
#define DDR_PHY_DX5GSR2_DX5GSR2_WDERR_X(x)       (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX5GSR2_DX5GSR2_WDWN(x)          (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX5GSR2_DX5GSR2_WDWN_M           GENMASK(3, 3)
#define DDR_PHY_DX5GSR2_DX5GSR2_WDWN_X(x)        (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX5GSR2_DX5GSR2_REERR(x)         (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX5GSR2_DX5GSR2_REERR_M          GENMASK(4, 4)
#define DDR_PHY_DX5GSR2_DX5GSR2_REERR_X(x)       (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX5GSR2_DX5GSR2_REWN(x)          (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX5GSR2_DX5GSR2_REWN_M           GENMASK(5, 5)
#define DDR_PHY_DX5GSR2_DX5GSR2_REWN_X(x)        (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX5GSR2_DX5GSR2_WEERR(x)         (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX5GSR2_DX5GSR2_WEERR_M          GENMASK(6, 6)
#define DDR_PHY_DX5GSR2_DX5GSR2_WEERR_X(x)       (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX5GSR2_DX5GSR2_WEWN(x)          (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_DX5GSR2_DX5GSR2_WEWN_M           GENMASK(7, 7)
#define DDR_PHY_DX5GSR2_DX5GSR2_WEWN_X(x)        (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_DX5GSR2_DX5GSR2_ESTAT(x)         (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX5GSR2_DX5GSR2_ESTAT_M          GENMASK(11, 8)
#define DDR_PHY_DX5GSR2_DX5GSR2_ESTAT_X(x)       (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX5GSR2_DX5GSR2_DBDQ(x)          (((x) << 12) & GENMASK(19, 12))
#define DDR_PHY_DX5GSR2_DX5GSR2_DBDQ_M           GENMASK(19, 12)
#define DDR_PHY_DX5GSR2_DX5GSR2_DBDQ_X(x)        (((x) & GENMASK(19, 12)) >> 12)

#define DDR_PHY_DX5GSR2_DX5GSR2_SRDERR(x)        (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX5GSR2_DX5GSR2_SRDERR_M         GENMASK(20, 20)
#define DDR_PHY_DX5GSR2_DX5GSR2_SRDERR_X(x)      (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX5GSR2_DX5GSR2_RESERVED_21(x)   (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX5GSR2_DX5GSR2_RESERVED_21_M    GENMASK(21, 21)
#define DDR_PHY_DX5GSR2_DX5GSR2_RESERVED_21_X(x) (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX5GSR2_DX5GSR2_GSDQSCAL(x)      (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX5GSR2_DX5GSR2_GSDQSCAL_M       GENMASK(22, 22)
#define DDR_PHY_DX5GSR2_DX5GSR2_GSDQSCAL_X(x)    (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX5GSR2_DX5GSR2_GSDQSPRD(x)      (((x) << 23) & GENMASK(31, 23))
#define DDR_PHY_DX5GSR2_DX5GSR2_GSDQSPRD_M       GENMASK(31, 23)
#define DDR_PHY_DX5GSR2_DX5GSR2_GSDQSPRD_X(x)    (((x) & GENMASK(31, 23)) >> 23)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5GSR3 */
#define DDR_PHY_DX5GSR3(t)        (t + 0xcec)

#define DDR_PHY_DX5GSR3_DX5GSR3_SRDPC(x)         ((x) & GENMASK(1, 0))
#define DDR_PHY_DX5GSR3_DX5GSR3_SRDPC_M          GENMASK(1, 0)
#define DDR_PHY_DX5GSR3_DX5GSR3_SRDPC_X(x)       ((x) & GENMASK(1, 0))

#define DDR_PHY_DX5GSR3_DX5GSR3_RESERVED_7_2(x)  (((x) << 2) & GENMASK(7, 2))
#define DDR_PHY_DX5GSR3_DX5GSR3_RESERVED_7_2_M   GENMASK(7, 2)
#define DDR_PHY_DX5GSR3_DX5GSR3_RESERVED_7_2_X(x) (((x) & GENMASK(7, 2)) >> 2)

#define DDR_PHY_DX5GSR3_DX5GSR3_HVERR(x)         (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX5GSR3_DX5GSR3_HVERR_M          GENMASK(11, 8)
#define DDR_PHY_DX5GSR3_DX5GSR3_HVERR_X(x)       (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX5GSR3_DX5GSR3_HVWRN(x)         (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_DX5GSR3_DX5GSR3_HVWRN_M          GENMASK(15, 12)
#define DDR_PHY_DX5GSR3_DX5GSR3_HVWRN_X(x)       (((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_DX5GSR3_DX5GSR3_DVERR(x)         (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DX5GSR3_DX5GSR3_DVERR_M          GENMASK(19, 16)
#define DDR_PHY_DX5GSR3_DX5GSR3_DVERR_X(x)       (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DX5GSR3_DX5GSR3_DVWRN(x)         (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX5GSR3_DX5GSR3_DVWRN_M          GENMASK(23, 20)
#define DDR_PHY_DX5GSR3_DX5GSR3_DVWRN_X(x)       (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX5GSR3_DX5GSR3_ESTAT(x)         (((x) << 24) & GENMASK(26, 24))
#define DDR_PHY_DX5GSR3_DX5GSR3_ESTAT_M          GENMASK(26, 24)
#define DDR_PHY_DX5GSR3_DX5GSR3_ESTAT_X(x)       (((x) & GENMASK(26, 24)) >> 24)

#define DDR_PHY_DX5GSR3_DX5GSR3_RESERVED_31_27(x)\
	(((x) << 27) & GENMASK(31, 27))
#define DDR_PHY_DX5GSR3_DX5GSR3_RESERVED_31_27_M GENMASK(31, 27)
#define DDR_PHY_DX5GSR3_DX5GSR3_RESERVED_31_27_X(x)\
	(((x) & GENMASK(31, 27)) >> 27)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5GSR4 */
#define DDR_PHY_DX5GSR4(t)        (t + 0xcf0)

#define DDR_PHY_DX5GSR4_DX5GSR4_X4WDQCAL(x)      ((x) & GENMASK(0, 0))
#define DDR_PHY_DX5GSR4_DX5GSR4_X4WDQCAL_M       GENMASK(0, 0)
#define DDR_PHY_DX5GSR4_DX5GSR4_X4WDQCAL_X(x)    ((x) & GENMASK(0, 0))

#define DDR_PHY_DX5GSR4_DX5GSR4_X4RDQSCAL(x)     (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX5GSR4_DX5GSR4_X4RDQSCAL_M      GENMASK(1, 1)
#define DDR_PHY_DX5GSR4_DX5GSR4_X4RDQSCAL_X(x)   (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX5GSR4_DX5GSR4_X4RDQSNCAL(x)    (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX5GSR4_DX5GSR4_X4RDQSNCAL_M     GENMASK(2, 2)
#define DDR_PHY_DX5GSR4_DX5GSR4_X4RDQSNCAL_X(x)  (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX5GSR4_DX5GSR4_X4GDQSCAL(x)     (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX5GSR4_DX5GSR4_X4GDQSCAL_M      GENMASK(3, 3)
#define DDR_PHY_DX5GSR4_DX5GSR4_X4GDQSCAL_X(x)   (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX5GSR4_DX5GSR4_X4WLCAL(x)       (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX5GSR4_DX5GSR4_X4WLCAL_M        GENMASK(4, 4)
#define DDR_PHY_DX5GSR4_DX5GSR4_X4WLCAL_X(x)     (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX5GSR4_DX5GSR4_X4WLDONE(x)      (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX5GSR4_DX5GSR4_X4WLDONE_M       GENMASK(5, 5)
#define DDR_PHY_DX5GSR4_DX5GSR4_X4WLDONE_X(x)    (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX5GSR4_DX5GSR4_X4WLERR(x)       (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX5GSR4_DX5GSR4_X4WLERR_M        GENMASK(6, 6)
#define DDR_PHY_DX5GSR4_DX5GSR4_X4WLERR_X(x)     (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX5GSR4_DX5GSR4_X4WLPRD(x)       (((x) << 7) & GENMASK(15, 7))
#define DDR_PHY_DX5GSR4_DX5GSR4_X4WLPRD_M        GENMASK(15, 7)
#define DDR_PHY_DX5GSR4_DX5GSR4_X4WLPRD_X(x)     (((x) & GENMASK(15, 7)) >> 7)

#define DDR_PHY_DX5GSR4_DX5GSR4_X4DPLOCK(x)      (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX5GSR4_DX5GSR4_X4DPLOCK_M       GENMASK(16, 16)
#define DDR_PHY_DX5GSR4_DX5GSR4_X4DPLOCK_X(x)    (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX5GSR4_DX5GSR4_X4GDQSPRD(x)     (((x) << 17) & GENMASK(25, 17))
#define DDR_PHY_DX5GSR4_DX5GSR4_X4GDQSPRD_M      GENMASK(25, 17)
#define DDR_PHY_DX5GSR4_DX5GSR4_X4GDQSPRD_X(x)   (((x) & GENMASK(25, 17)) >> 17)

#define DDR_PHY_DX5GSR4_DX5GSR4_X4WLWN(x)        (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_DX5GSR4_DX5GSR4_X4WLWN_M         GENMASK(26, 26)
#define DDR_PHY_DX5GSR4_DX5GSR4_X4WLWN_X(x)      (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_DX5GSR4_DX5GSR4_RESERVED_29_27(x)\
	(((x) << 27) & GENMASK(29, 27))
#define DDR_PHY_DX5GSR4_DX5GSR4_RESERVED_29_27_M GENMASK(29, 27)
#define DDR_PHY_DX5GSR4_DX5GSR4_RESERVED_29_27_X(x)\
	(((x) & GENMASK(29, 27)) >> 27)

#define DDR_PHY_DX5GSR4_DX5GSR4_X4WLDQ(x)        (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX5GSR4_DX5GSR4_X4WLDQ_M         GENMASK(30, 30)
#define DDR_PHY_DX5GSR4_DX5GSR4_X4WLDQ_X(x)      (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX5GSR4_DX5GSR4_RESERVED_31(x)   (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX5GSR4_DX5GSR4_RESERVED_31_M    GENMASK(31, 31)
#define DDR_PHY_DX5GSR4_DX5GSR4_RESERVED_31_X(x) (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5GSR5 */
#define DDR_PHY_DX5GSR5(t)        (t + 0xcf4)

#define DDR_PHY_DX5GSR5_DX5GSR5_X4RDERR(x)       ((x) & GENMASK(0, 0))
#define DDR_PHY_DX5GSR5_DX5GSR5_X4RDERR_M        GENMASK(0, 0)
#define DDR_PHY_DX5GSR5_DX5GSR5_X4RDERR_X(x)     ((x) & GENMASK(0, 0))

#define DDR_PHY_DX5GSR5_DX5GSR5_X4RDWN(x)        (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX5GSR5_DX5GSR5_X4RDWN_M         GENMASK(1, 1)
#define DDR_PHY_DX5GSR5_DX5GSR5_X4RDWN_X(x)      (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX5GSR5_DX5GSR5_X4WDERR(x)       (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX5GSR5_DX5GSR5_X4WDERR_M        GENMASK(2, 2)
#define DDR_PHY_DX5GSR5_DX5GSR5_X4WDERR_X(x)     (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX5GSR5_DX5GSR5_X4WDWN(x)        (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX5GSR5_DX5GSR5_X4WDWN_M         GENMASK(3, 3)
#define DDR_PHY_DX5GSR5_DX5GSR5_X4WDWN_X(x)      (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX5GSR5_DX5GSR5_X4REERR(x)       (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX5GSR5_DX5GSR5_X4REERR_M        GENMASK(4, 4)
#define DDR_PHY_DX5GSR5_DX5GSR5_X4REERR_X(x)     (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX5GSR5_DX5GSR5_X4REWN(x)        (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX5GSR5_DX5GSR5_X4REWN_M         GENMASK(5, 5)
#define DDR_PHY_DX5GSR5_DX5GSR5_X4REWN_X(x)      (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX5GSR5_DX5GSR5_X4WEERR(x)       (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX5GSR5_DX5GSR5_X4WEERR_M        GENMASK(6, 6)
#define DDR_PHY_DX5GSR5_DX5GSR5_X4WEERR_X(x)     (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX5GSR5_DX5GSR5_X4WEWN(x)        (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_DX5GSR5_DX5GSR5_X4WEWN_M         GENMASK(7, 7)
#define DDR_PHY_DX5GSR5_DX5GSR5_X4WEWN_X(x)      (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_DX5GSR5_DX5GSR5_X4ESTAT(x)       (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX5GSR5_DX5GSR5_X4ESTAT_M        GENMASK(11, 8)
#define DDR_PHY_DX5GSR5_DX5GSR5_X4ESTAT_X(x)     (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX5GSR5_DX5GSR5_RESERVED_19_12(x)\
	(((x) << 12) & GENMASK(19, 12))
#define DDR_PHY_DX5GSR5_DX5GSR5_RESERVED_19_12_M GENMASK(19, 12)
#define DDR_PHY_DX5GSR5_DX5GSR5_RESERVED_19_12_X(x)\
	(((x) & GENMASK(19, 12)) >> 12)

#define DDR_PHY_DX5GSR5_DX5GSR5_X4SRDERR(x)      (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX5GSR5_DX5GSR5_X4SRDERR_M       GENMASK(20, 20)
#define DDR_PHY_DX5GSR5_DX5GSR5_X4SRDERR_X(x)    (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX5GSR5_DX5GSR5_RESERVED_21(x)   (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX5GSR5_DX5GSR5_RESERVED_21_M    GENMASK(21, 21)
#define DDR_PHY_DX5GSR5_DX5GSR5_RESERVED_21_X(x) (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX5GSR5_DX5GSR5_X4GSDQSCAL(x)    (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX5GSR5_DX5GSR5_X4GSDQSCAL_M     GENMASK(22, 22)
#define DDR_PHY_DX5GSR5_DX5GSR5_X4GSDQSCAL_X(x)  (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX5GSR5_DX5GSR5_X4GSDQSPRD(x)    (((x) << 23) & GENMASK(31, 23))
#define DDR_PHY_DX5GSR5_DX5GSR5_X4GSDQSPRD_M     GENMASK(31, 23)
#define DDR_PHY_DX5GSR5_DX5GSR5_X4GSDQSPRD_X(x)  (((x) & GENMASK(31, 23)) >> 23)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX5GSR6 */
#define DDR_PHY_DX5GSR6(t)        (t + 0xcf8)

#define DDR_PHY_DX5GSR6_DX5GSR6_RESERVED_1_0(x)  ((x) & GENMASK(1, 0))
#define DDR_PHY_DX5GSR6_DX5GSR6_RESERVED_1_0_M   GENMASK(1, 0)
#define DDR_PHY_DX5GSR6_DX5GSR6_RESERVED_1_0_X(x) ((x) & GENMASK(1, 0))

#define DDR_PHY_DX5GSR6_DX5GSR6_X4SRDPC(x)       (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DX5GSR6_DX5GSR6_X4SRDPC_M        GENMASK(3, 2)
#define DDR_PHY_DX5GSR6_DX5GSR6_X4SRDPC_X(x)     (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DX5GSR6_DX5GSR6_RESERVED_7_4(x)  (((x) << 4) & GENMASK(7, 4))
#define DDR_PHY_DX5GSR6_DX5GSR6_RESERVED_7_4_M   GENMASK(7, 4)
#define DDR_PHY_DX5GSR6_DX5GSR6_RESERVED_7_4_X(x) (((x) & GENMASK(7, 4)) >> 4)

#define DDR_PHY_DX5GSR6_DX5GSR6_X4HVERR(x)       (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX5GSR6_DX5GSR6_X4HVERR_M        GENMASK(11, 8)
#define DDR_PHY_DX5GSR6_DX5GSR6_X4HVERR_X(x)     (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX5GSR6_DX5GSR6_X4HVWRN(x)       (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_DX5GSR6_DX5GSR6_X4HVWRN_M        GENMASK(15, 12)
#define DDR_PHY_DX5GSR6_DX5GSR6_X4HVWRN_X(x)     (((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_DX5GSR6_DX5GSR6_X4DVERR(x)       (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DX5GSR6_DX5GSR6_X4DVERR_M        GENMASK(19, 16)
#define DDR_PHY_DX5GSR6_DX5GSR6_X4DVERR_X(x)     (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DX5GSR6_DX5GSR6_X4DVWRN(x)       (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX5GSR6_DX5GSR6_X4DVWRN_M        GENMASK(23, 20)
#define DDR_PHY_DX5GSR6_DX5GSR6_X4DVWRN_X(x)     (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX5GSR6_DX5GSR6_RESERVED_31_24(x)\
	(((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_DX5GSR6_DX5GSR6_RESERVED_31_24_M GENMASK(31, 24)
#define DDR_PHY_DX5GSR6_DX5GSR6_RESERVED_31_24_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6GCR0 */
#define DDR_PHY_DX6GCR0(t)        (t + 0xd00)

#define DDR_PHY_DX6GCR0_DX6GCR0_DXEN(x)          ((x) & GENMASK(0, 0))
#define DDR_PHY_DX6GCR0_DX6GCR0_DXEN_M           GENMASK(0, 0)
#define DDR_PHY_DX6GCR0_DX6GCR0_DXEN_X(x)        ((x) & GENMASK(0, 0))

#define DDR_PHY_DX6GCR0_DX6GCR0_DXIOM(x)         (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX6GCR0_DX6GCR0_DXIOM_M          GENMASK(1, 1)
#define DDR_PHY_DX6GCR0_DX6GCR0_DXIOM_X(x)       (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX6GCR0_DX6GCR0_DQSGOE(x)        (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX6GCR0_DX6GCR0_DQSGOE_M         GENMASK(2, 2)
#define DDR_PHY_DX6GCR0_DX6GCR0_DQSGOE_X(x)      (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX6GCR0_DX6GCR0_DQSGODT(x)       (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX6GCR0_DX6GCR0_DQSGODT_M        GENMASK(3, 3)
#define DDR_PHY_DX6GCR0_DX6GCR0_DQSGODT_X(x)     (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX6GCR0_DX6GCR0_RESERVED_4(x)    (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX6GCR0_DX6GCR0_RESERVED_4_M     GENMASK(4, 4)
#define DDR_PHY_DX6GCR0_DX6GCR0_RESERVED_4_X(x)  (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX6GCR0_DX6GCR0_DQSGPDR(x)       (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX6GCR0_DX6GCR0_DQSGPDR_M        GENMASK(5, 5)
#define DDR_PHY_DX6GCR0_DX6GCR0_DQSGPDR_X(x)     (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX6GCR0_DX6GCR0_RESERVED_6(x)    (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX6GCR0_DX6GCR0_RESERVED_6_M     GENMASK(6, 6)
#define DDR_PHY_DX6GCR0_DX6GCR0_RESERVED_6_X(x)  (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX6GCR0_DX6GCR0_PDRAL(x)         (((x) << 7) & GENMASK(8, 7))
#define DDR_PHY_DX6GCR0_DX6GCR0_PDRAL_M          GENMASK(8, 7)
#define DDR_PHY_DX6GCR0_DX6GCR0_PDRAL_X(x)       (((x) & GENMASK(8, 7)) >> 7)

#define DDR_PHY_DX6GCR0_DX6GCR0_RTTOH(x)         (((x) << 9) & GENMASK(10, 9))
#define DDR_PHY_DX6GCR0_DX6GCR0_RTTOH_M          GENMASK(10, 9)
#define DDR_PHY_DX6GCR0_DX6GCR0_RTTOH_X(x)       (((x) & GENMASK(10, 9)) >> 9)

#define DDR_PHY_DX6GCR0_DX6GCR0_RTTOAL(x)        (((x) << 11) & GENMASK(11, 11))
#define DDR_PHY_DX6GCR0_DX6GCR0_RTTOAL_M         GENMASK(11, 11)
#define DDR_PHY_DX6GCR0_DX6GCR0_RTTOAL_X(x)      (((x) & GENMASK(11, 11)) >> 11)

#define DDR_PHY_DX6GCR0_DX6GCR0_DQSSEPDR(x)      (((x) << 12) & GENMASK(12, 12))
#define DDR_PHY_DX6GCR0_DX6GCR0_DQSSEPDR_M       GENMASK(12, 12)
#define DDR_PHY_DX6GCR0_DX6GCR0_DQSSEPDR_X(x)    (((x) & GENMASK(12, 12)) >> 12)

#define DDR_PHY_DX6GCR0_DX6GCR0_DQSNSEPDR(x)     (((x) << 13) & GENMASK(13, 13))
#define DDR_PHY_DX6GCR0_DX6GCR0_DQSNSEPDR_M      GENMASK(13, 13)
#define DDR_PHY_DX6GCR0_DX6GCR0_DQSNSEPDR_X(x)   (((x) & GENMASK(13, 13)) >> 13)

#define DDR_PHY_DX6GCR0_DX6GCR0_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX6GCR0_DX6GCR0_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX6GCR0_DX6GCR0_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX6GCR0_DX6GCR0_PLLRST(x)        (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX6GCR0_DX6GCR0_PLLRST_M         GENMASK(16, 16)
#define DDR_PHY_DX6GCR0_DX6GCR0_PLLRST_X(x)      (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX6GCR0_DX6GCR0_PLLPD(x)         (((x) << 17) & GENMASK(17, 17))
#define DDR_PHY_DX6GCR0_DX6GCR0_PLLPD_M          GENMASK(17, 17)
#define DDR_PHY_DX6GCR0_DX6GCR0_PLLPD_X(x)       (((x) & GENMASK(17, 17)) >> 17)

#define DDR_PHY_DX6GCR0_DX6GCR0_GSHIFT(x)        (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_DX6GCR0_DX6GCR0_GSHIFT_M         GENMASK(18, 18)
#define DDR_PHY_DX6GCR0_DX6GCR0_GSHIFT_X(x)      (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_DX6GCR0_DX6GCR0_PLLBYP(x)        (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_DX6GCR0_DX6GCR0_PLLBYP_M         GENMASK(19, 19)
#define DDR_PHY_DX6GCR0_DX6GCR0_PLLBYP_X(x)      (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_DX6GCR0_DX6GCR0_RDDLY(x)         (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX6GCR0_DX6GCR0_RDDLY_M          GENMASK(23, 20)
#define DDR_PHY_DX6GCR0_DX6GCR0_RDDLY_X(x)       (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX6GCR0_DX6GCR0_RESERVED_29_24(x)\
	(((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX6GCR0_DX6GCR0_RESERVED_29_24_M GENMASK(29, 24)
#define DDR_PHY_DX6GCR0_DX6GCR0_RESERVED_29_24_X(x)\
	(((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX6GCR0_DX6GCR0_MDLEN(x)         (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX6GCR0_DX6GCR0_MDLEN_M          GENMASK(30, 30)
#define DDR_PHY_DX6GCR0_DX6GCR0_MDLEN_X(x)       (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX6GCR0_DX6GCR0_CALBYP(x)        (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX6GCR0_DX6GCR0_CALBYP_M         GENMASK(31, 31)
#define DDR_PHY_DX6GCR0_DX6GCR0_CALBYP_X(x)      (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6GCR1 */
#define DDR_PHY_DX6GCR1(t)        (t + 0xd04)

#define DDR_PHY_DX6GCR1_DX6GCR1_RESERVED_15_0(x) ((x) & GENMASK(15, 0))
#define DDR_PHY_DX6GCR1_DX6GCR1_RESERVED_15_0_M  GENMASK(15, 0)
#define DDR_PHY_DX6GCR1_DX6GCR1_RESERVED_15_0_X(x) ((x) & GENMASK(15, 0))

#define DDR_PHY_DX6GCR1_DX6GCR1_DXPDRMODE(x)     (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX6GCR1_DX6GCR1_DXPDRMODE_M      GENMASK(31, 16)
#define DDR_PHY_DX6GCR1_DX6GCR1_DXPDRMODE_X(x)   (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6GCR2 */
#define DDR_PHY_DX6GCR2(t)        (t + 0xd08)

#define DDR_PHY_DX6GCR2_DX6GCR2_DXTEMODE(x)      ((x) & GENMASK(15, 0))
#define DDR_PHY_DX6GCR2_DX6GCR2_DXTEMODE_M       GENMASK(15, 0)
#define DDR_PHY_DX6GCR2_DX6GCR2_DXTEMODE_X(x)    ((x) & GENMASK(15, 0))

#define DDR_PHY_DX6GCR2_DX6GCR2_DXOEMODE(x)      (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX6GCR2_DX6GCR2_DXOEMODE_M       GENMASK(31, 16)
#define DDR_PHY_DX6GCR2_DX6GCR2_DXOEMODE_X(x)    (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6GCR3 */
#define DDR_PHY_DX6GCR3(t)        (t + 0xd0c)

#define DDR_PHY_DX6GCR3_DX6GCR3_RESERVED_1_0(x)  ((x) & GENMASK(1, 0))
#define DDR_PHY_DX6GCR3_DX6GCR3_RESERVED_1_0_M   GENMASK(1, 0)
#define DDR_PHY_DX6GCR3_DX6GCR3_RESERVED_1_0_X(x) ((x) & GENMASK(1, 0))

#define DDR_PHY_DX6GCR3_DX6GCR3_DSPDRMODE(x)     (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DX6GCR3_DX6GCR3_DSPDRMODE_M      GENMASK(3, 2)
#define DDR_PHY_DX6GCR3_DX6GCR3_DSPDRMODE_X(x)   (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DX6GCR3_DX6GCR3_DSTEMODE(x)      (((x) << 4) & GENMASK(5, 4))
#define DDR_PHY_DX6GCR3_DX6GCR3_DSTEMODE_M       GENMASK(5, 4)
#define DDR_PHY_DX6GCR3_DX6GCR3_DSTEMODE_X(x)    (((x) & GENMASK(5, 4)) >> 4)

#define DDR_PHY_DX6GCR3_DX6GCR3_DSOEMODE(x)      (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX6GCR3_DX6GCR3_DSOEMODE_M       GENMASK(7, 6)
#define DDR_PHY_DX6GCR3_DX6GCR3_DSOEMODE_X(x)    (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX6GCR3_DX6GCR3_RESERVED_9_8(x)  (((x) << 8) & GENMASK(9, 8))
#define DDR_PHY_DX6GCR3_DX6GCR3_RESERVED_9_8_M   GENMASK(9, 8)
#define DDR_PHY_DX6GCR3_DX6GCR3_RESERVED_9_8_X(x) (((x) & GENMASK(9, 8)) >> 8)

#define DDR_PHY_DX6GCR3_DX6GCR3_DMPDRMODE(x)     (((x) << 10) & GENMASK(11, 10))
#define DDR_PHY_DX6GCR3_DX6GCR3_DMPDRMODE_M      GENMASK(11, 10)
#define DDR_PHY_DX6GCR3_DX6GCR3_DMPDRMODE_X(x)   (((x) & GENMASK(11, 10)) >> 10)

#define DDR_PHY_DX6GCR3_DX6GCR3_DMTEMODE(x)      (((x) << 12) & GENMASK(13, 12))
#define DDR_PHY_DX6GCR3_DX6GCR3_DMTEMODE_M       GENMASK(13, 12)
#define DDR_PHY_DX6GCR3_DX6GCR3_DMTEMODE_X(x)    (((x) & GENMASK(13, 12)) >> 12)

#define DDR_PHY_DX6GCR3_DX6GCR3_DMOEMODE(x)      (((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX6GCR3_DX6GCR3_DMOEMODE_M       GENMASK(15, 14)
#define DDR_PHY_DX6GCR3_DX6GCR3_DMOEMODE_X(x)    (((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX6GCR3_DX6GCR3_RESERVED_17_16(x)\
	(((x) << 16) & GENMASK(17, 16))
#define DDR_PHY_DX6GCR3_DX6GCR3_RESERVED_17_16_M GENMASK(17, 16)
#define DDR_PHY_DX6GCR3_DX6GCR3_RESERVED_17_16_X(x)\
	(((x) & GENMASK(17, 16)) >> 16)

#define DDR_PHY_DX6GCR3_DX6GCR3_OEBVT(x)         (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_DX6GCR3_DX6GCR3_OEBVT_M          GENMASK(18, 18)
#define DDR_PHY_DX6GCR3_DX6GCR3_OEBVT_X(x)       (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_DX6GCR3_DX6GCR3_PDRBVT(x)        (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_DX6GCR3_DX6GCR3_PDRBVT_M         GENMASK(19, 19)
#define DDR_PHY_DX6GCR3_DX6GCR3_PDRBVT_X(x)      (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_DX6GCR3_DX6GCR3_TEBVT(x)         (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX6GCR3_DX6GCR3_TEBVT_M          GENMASK(20, 20)
#define DDR_PHY_DX6GCR3_DX6GCR3_TEBVT_X(x)       (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX6GCR3_DX6GCR3_WDSBVT(x)        (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX6GCR3_DX6GCR3_WDSBVT_M         GENMASK(21, 21)
#define DDR_PHY_DX6GCR3_DX6GCR3_WDSBVT_X(x)      (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX6GCR3_DX6GCR3_RDSBVT(x)        (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX6GCR3_DX6GCR3_RDSBVT_M         GENMASK(22, 22)
#define DDR_PHY_DX6GCR3_DX6GCR3_RDSBVT_X(x)      (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX6GCR3_DX6GCR3_RGSLVT(x)        (((x) << 23) & GENMASK(23, 23))
#define DDR_PHY_DX6GCR3_DX6GCR3_RGSLVT_M         GENMASK(23, 23)
#define DDR_PHY_DX6GCR3_DX6GCR3_RGSLVT_X(x)      (((x) & GENMASK(23, 23)) >> 23)

#define DDR_PHY_DX6GCR3_DX6GCR3_WLLVT(x)         (((x) << 24) & GENMASK(24, 24))
#define DDR_PHY_DX6GCR3_DX6GCR3_WLLVT_M          GENMASK(24, 24)
#define DDR_PHY_DX6GCR3_DX6GCR3_WLLVT_X(x)       (((x) & GENMASK(24, 24)) >> 24)

#define DDR_PHY_DX6GCR3_DX6GCR3_WDLVT(x)         (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_DX6GCR3_DX6GCR3_WDLVT_M          GENMASK(25, 25)
#define DDR_PHY_DX6GCR3_DX6GCR3_WDLVT_X(x)       (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_DX6GCR3_DX6GCR3_RDLVT(x)         (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_DX6GCR3_DX6GCR3_RDLVT_M          GENMASK(26, 26)
#define DDR_PHY_DX6GCR3_DX6GCR3_RDLVT_X(x)       (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_DX6GCR3_DX6GCR3_RGLVT(x)         (((x) << 27) & GENMASK(27, 27))
#define DDR_PHY_DX6GCR3_DX6GCR3_RGLVT_M          GENMASK(27, 27)
#define DDR_PHY_DX6GCR3_DX6GCR3_RGLVT_X(x)       (((x) & GENMASK(27, 27)) >> 27)

#define DDR_PHY_DX6GCR3_DX6GCR3_WDBVT(x)         (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_DX6GCR3_DX6GCR3_WDBVT_M          GENMASK(28, 28)
#define DDR_PHY_DX6GCR3_DX6GCR3_WDBVT_X(x)       (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_DX6GCR3_DX6GCR3_RDBVT(x)         (((x) << 29) & GENMASK(29, 29))
#define DDR_PHY_DX6GCR3_DX6GCR3_RDBVT_M          GENMASK(29, 29)
#define DDR_PHY_DX6GCR3_DX6GCR3_RDBVT_X(x)       (((x) & GENMASK(29, 29)) >> 29)

#define DDR_PHY_DX6GCR3_DX6GCR3_WDMBVT(x)        (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX6GCR3_DX6GCR3_WDMBVT_M         GENMASK(30, 30)
#define DDR_PHY_DX6GCR3_DX6GCR3_WDMBVT_X(x)      (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX6GCR3_DX6GCR3_RDMBVT(x)        (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX6GCR3_DX6GCR3_RDMBVT_M         GENMASK(31, 31)
#define DDR_PHY_DX6GCR3_DX6GCR3_RDMBVT_X(x)      (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6GCR4 */
#define DDR_PHY_DX6GCR4(t)        (t + 0xd10)

#define DDR_PHY_DX6GCR4_DX6GCR4_DXREFIMON(x)     ((x) & GENMASK(1, 0))
#define DDR_PHY_DX6GCR4_DX6GCR4_DXREFIMON_M      GENMASK(1, 0)
#define DDR_PHY_DX6GCR4_DX6GCR4_DXREFIMON_X(x)   ((x) & GENMASK(1, 0))

#define DDR_PHY_DX6GCR4_DX6GCR4_DXREFIEN(x)      (((x) << 2) & GENMASK(5, 2))
#define DDR_PHY_DX6GCR4_DX6GCR4_DXREFIEN_M       GENMASK(5, 2)
#define DDR_PHY_DX6GCR4_DX6GCR4_DXREFIEN_X(x)    (((x) & GENMASK(5, 2)) >> 2)

#define DDR_PHY_DX6GCR4_DX6GCR4_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX6GCR4_DX6GCR4_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX6GCR4_DX6GCR4_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX6GCR4_DX6GCR4_DXREFSSEL(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX6GCR4_DX6GCR4_DXREFSSEL_M      GENMASK(13, 8)
#define DDR_PHY_DX6GCR4_DX6GCR4_DXREFSSEL_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX6GCR4_DX6GCR4_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX6GCR4_DX6GCR4_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX6GCR4_DX6GCR4_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX6GCR4_DX6GCR4_DXREFESEL(x)     (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX6GCR4_DX6GCR4_DXREFESEL_M      GENMASK(21, 16)
#define DDR_PHY_DX6GCR4_DX6GCR4_DXREFESEL_X(x)   (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX6GCR4_DX6GCR4_RESERVED_24_22(x)\
	(((x) << 22) & GENMASK(24, 22))
#define DDR_PHY_DX6GCR4_DX6GCR4_RESERVED_24_22_M GENMASK(24, 22)
#define DDR_PHY_DX6GCR4_DX6GCR4_RESERVED_24_22_X(x)\
	(((x) & GENMASK(24, 22)) >> 22)

#define DDR_PHY_DX6GCR4_DX6GCR4_DXREFSEN(x)      (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_DX6GCR4_DX6GCR4_DXREFSEN_M       GENMASK(25, 25)
#define DDR_PHY_DX6GCR4_DX6GCR4_DXREFSEN_X(x)    (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_DX6GCR4_DX6GCR4_DXREFEEN(x)      (((x) << 26) & GENMASK(27, 26))
#define DDR_PHY_DX6GCR4_DX6GCR4_DXREFEEN_M       GENMASK(27, 26)
#define DDR_PHY_DX6GCR4_DX6GCR4_DXREFEEN_X(x)    (((x) & GENMASK(27, 26)) >> 26)

#define DDR_PHY_DX6GCR4_DX6GCR4_DXREFPEN(x)      (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_DX6GCR4_DX6GCR4_DXREFPEN_M       GENMASK(28, 28)
#define DDR_PHY_DX6GCR4_DX6GCR4_DXREFPEN_X(x)    (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_DX6GCR4_DX6GCR4_DXREFIOM(x)      (((x) << 29) & GENMASK(31, 29))
#define DDR_PHY_DX6GCR4_DX6GCR4_DXREFIOM_M       GENMASK(31, 29)
#define DDR_PHY_DX6GCR4_DX6GCR4_DXREFIOM_X(x)    (((x) & GENMASK(31, 29)) >> 29)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6GCR5 */
#define DDR_PHY_DX6GCR5(t)        (t + 0xd14)

#define DDR_PHY_DX6GCR5_DX6GCR5_DXREFISELR0(x)   ((x) & GENMASK(5, 0))
#define DDR_PHY_DX6GCR5_DX6GCR5_DXREFISELR0_M    GENMASK(5, 0)
#define DDR_PHY_DX6GCR5_DX6GCR5_DXREFISELR0_X(x) ((x) & GENMASK(5, 0))

#define DDR_PHY_DX6GCR5_DX6GCR5_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX6GCR5_DX6GCR5_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX6GCR5_DX6GCR5_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX6GCR5_DX6GCR5_DXREFISELR1(x)   (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX6GCR5_DX6GCR5_DXREFISELR1_M    GENMASK(13, 8)
#define DDR_PHY_DX6GCR5_DX6GCR5_DXREFISELR1_X(x) (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX6GCR5_DX6GCR5_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX6GCR5_DX6GCR5_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX6GCR5_DX6GCR5_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX6GCR5_DX6GCR5_DXREFISELR2(x)   (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX6GCR5_DX6GCR5_DXREFISELR2_M    GENMASK(21, 16)
#define DDR_PHY_DX6GCR5_DX6GCR5_DXREFISELR2_X(x) (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX6GCR5_DX6GCR5_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX6GCR5_DX6GCR5_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX6GCR5_DX6GCR5_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX6GCR5_DX6GCR5_DXREFISELR3(x)   (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX6GCR5_DX6GCR5_DXREFISELR3_M    GENMASK(29, 24)
#define DDR_PHY_DX6GCR5_DX6GCR5_DXREFISELR3_X(x) (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX6GCR5_DX6GCR5_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX6GCR5_DX6GCR5_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX6GCR5_DX6GCR5_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6GCR6 */
#define DDR_PHY_DX6GCR6(t)        (t + 0xd18)

#define DDR_PHY_DX6GCR6_DX6GCR6_DXDQVREFR0(x)    ((x) & GENMASK(5, 0))
#define DDR_PHY_DX6GCR6_DX6GCR6_DXDQVREFR0_M     GENMASK(5, 0)
#define DDR_PHY_DX6GCR6_DX6GCR6_DXDQVREFR0_X(x)  ((x) & GENMASK(5, 0))

#define DDR_PHY_DX6GCR6_DX6GCR6_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX6GCR6_DX6GCR6_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX6GCR6_DX6GCR6_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX6GCR6_DX6GCR6_DXDQVREFR1(x)    (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX6GCR6_DX6GCR6_DXDQVREFR1_M     GENMASK(13, 8)
#define DDR_PHY_DX6GCR6_DX6GCR6_DXDQVREFR1_X(x)  (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX6GCR6_DX6GCR6_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX6GCR6_DX6GCR6_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX6GCR6_DX6GCR6_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX6GCR6_DX6GCR6_DXDQVREFR2(x)    (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX6GCR6_DX6GCR6_DXDQVREFR2_M     GENMASK(21, 16)
#define DDR_PHY_DX6GCR6_DX6GCR6_DXDQVREFR2_X(x)  (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX6GCR6_DX6GCR6_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX6GCR6_DX6GCR6_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX6GCR6_DX6GCR6_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX6GCR6_DX6GCR6_DXDQVREFR3(x)    (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX6GCR6_DX6GCR6_DXDQVREFR3_M     GENMASK(29, 24)
#define DDR_PHY_DX6GCR6_DX6GCR6_DXDQVREFR3_X(x)  (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX6GCR6_DX6GCR6_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX6GCR6_DX6GCR6_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX6GCR6_DX6GCR6_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6GCR7 */
#define DDR_PHY_DX6GCR7(t)        (t + 0xd1c)

#define DDR_PHY_DX6GCR7_DX6GCR7_RESERVED_1_0(x)  ((x) & GENMASK(1, 0))
#define DDR_PHY_DX6GCR7_DX6GCR7_RESERVED_1_0_M   GENMASK(1, 0)
#define DDR_PHY_DX6GCR7_DX6GCR7_RESERVED_1_0_X(x) ((x) & GENMASK(1, 0))

#define DDR_PHY_DX6GCR7_DX6GCR7_X4DSPDRMODE(x)   (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DX6GCR7_DX6GCR7_X4DSPDRMODE_M    GENMASK(3, 2)
#define DDR_PHY_DX6GCR7_DX6GCR7_X4DSPDRMODE_X(x) (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DX6GCR7_DX6GCR7_X4DSTEMODE(x)    (((x) << 4) & GENMASK(5, 4))
#define DDR_PHY_DX6GCR7_DX6GCR7_X4DSTEMODE_M     GENMASK(5, 4)
#define DDR_PHY_DX6GCR7_DX6GCR7_X4DSTEMODE_X(x)  (((x) & GENMASK(5, 4)) >> 4)

#define DDR_PHY_DX6GCR7_DX6GCR7_X4DSOEMODE(x)    (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX6GCR7_DX6GCR7_X4DSOEMODE_M     GENMASK(7, 6)
#define DDR_PHY_DX6GCR7_DX6GCR7_X4DSOEMODE_X(x)  (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX6GCR7_DX6GCR7_RESERVED_9_8(x)  (((x) << 8) & GENMASK(9, 8))
#define DDR_PHY_DX6GCR7_DX6GCR7_RESERVED_9_8_M   GENMASK(9, 8)
#define DDR_PHY_DX6GCR7_DX6GCR7_RESERVED_9_8_X(x) (((x) & GENMASK(9, 8)) >> 8)

#define DDR_PHY_DX6GCR7_DX6GCR7_X4DXPDRMODE(x)   (((x) << 10) & GENMASK(11, 10))
#define DDR_PHY_DX6GCR7_DX6GCR7_X4DXPDRMODE_M    GENMASK(11, 10)
#define DDR_PHY_DX6GCR7_DX6GCR7_X4DXPDRMODE_X(x) (((x) & GENMASK(11, 10)) >> 10)

#define DDR_PHY_DX6GCR7_DX6GCR7_X4DXTEMODE(x)    (((x) << 12) & GENMASK(13, 12))
#define DDR_PHY_DX6GCR7_DX6GCR7_X4DXTEMODE_M     GENMASK(13, 12)
#define DDR_PHY_DX6GCR7_DX6GCR7_X4DXTEMODE_X(x)  (((x) & GENMASK(13, 12)) >> 12)

#define DDR_PHY_DX6GCR7_DX6GCR7_X4DXOEMODE(x)    (((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX6GCR7_DX6GCR7_X4DXOEMODE_M     GENMASK(15, 14)
#define DDR_PHY_DX6GCR7_DX6GCR7_X4DXOEMODE_X(x)  (((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX6GCR7_DX6GCR7_X4DQSGOE(x)      (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX6GCR7_DX6GCR7_X4DQSGOE_M       GENMASK(16, 16)
#define DDR_PHY_DX6GCR7_DX6GCR7_X4DQSGOE_X(x)    (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX6GCR7_DX6GCR7_X4DQSGODT(x)     (((x) << 17) & GENMASK(17, 17))
#define DDR_PHY_DX6GCR7_DX6GCR7_X4DQSGODT_M      GENMASK(17, 17)
#define DDR_PHY_DX6GCR7_DX6GCR7_X4DQSGODT_X(x)   (((x) & GENMASK(17, 17)) >> 17)

#define DDR_PHY_DX6GCR7_DX6GCR7_RESERVED_18(x)   (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_DX6GCR7_DX6GCR7_RESERVED_18_M    GENMASK(18, 18)
#define DDR_PHY_DX6GCR7_DX6GCR7_RESERVED_18_X(x) (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_DX6GCR7_DX6GCR7_X4DQSGPDR(x)     (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_DX6GCR7_DX6GCR7_X4DQSGPDR_M      GENMASK(19, 19)
#define DDR_PHY_DX6GCR7_DX6GCR7_X4DQSGPDR_X(x)   (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_DX6GCR7_DX6GCR7_RESERVED_20(x)   (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX6GCR7_DX6GCR7_RESERVED_20_M    GENMASK(20, 20)
#define DDR_PHY_DX6GCR7_DX6GCR7_RESERVED_20_X(x) (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX6GCR7_DX6GCR7_X4DQSSEPDR(x)    (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX6GCR7_DX6GCR7_X4DQSSEPDR_M     GENMASK(21, 21)
#define DDR_PHY_DX6GCR7_DX6GCR7_X4DQSSEPDR_X(x)  (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX6GCR7_DX6GCR7_X4DQSNSEPDR(x)   (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX6GCR7_DX6GCR7_X4DQSNSEPDR_M    GENMASK(22, 22)
#define DDR_PHY_DX6GCR7_DX6GCR7_X4DQSNSEPDR_X(x) (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX6GCR7_DX6GCR7_X4RTTOH(x)       (((x) << 23) & GENMASK(24, 23))
#define DDR_PHY_DX6GCR7_DX6GCR7_X4RTTOH_M        GENMASK(24, 23)
#define DDR_PHY_DX6GCR7_DX6GCR7_X4RTTOH_X(x)     (((x) & GENMASK(24, 23)) >> 23)

#define DDR_PHY_DX6GCR7_DX6GCR7_X4RTTOAL(x)      (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_DX6GCR7_DX6GCR7_X4RTTOAL_M       GENMASK(25, 25)
#define DDR_PHY_DX6GCR7_DX6GCR7_X4RTTOAL_X(x)    (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_DX6GCR7_DX6GCR7_X4RDDLY(x)       (((x) << 26) & GENMASK(29, 26))
#define DDR_PHY_DX6GCR7_DX6GCR7_X4RDDLY_M        GENMASK(29, 26)
#define DDR_PHY_DX6GCR7_DX6GCR7_X4RDDLY_X(x)     (((x) & GENMASK(29, 26)) >> 26)

#define DDR_PHY_DX6GCR7_DX6GCR7_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX6GCR7_DX6GCR7_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX6GCR7_DX6GCR7_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6GCR8 */
#define DDR_PHY_DX6GCR8(t)        (t + 0xd20)

#define DDR_PHY_DX6GCR8_DX6GCR8_X4DXREFISELR0(x) ((x) & GENMASK(5, 0))
#define DDR_PHY_DX6GCR8_DX6GCR8_X4DXREFISELR0_M  GENMASK(5, 0)
#define DDR_PHY_DX6GCR8_DX6GCR8_X4DXREFISELR0_X(x) ((x) & GENMASK(5, 0))

#define DDR_PHY_DX6GCR8_DX6GCR8_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX6GCR8_DX6GCR8_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX6GCR8_DX6GCR8_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX6GCR8_DX6GCR8_X4DXREFISELR1(x) (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX6GCR8_DX6GCR8_X4DXREFISELR1_M  GENMASK(13, 8)
#define DDR_PHY_DX6GCR8_DX6GCR8_X4DXREFISELR1_X(x) (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX6GCR8_DX6GCR8_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX6GCR8_DX6GCR8_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX6GCR8_DX6GCR8_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX6GCR8_DX6GCR8_X4DXREFISELR2(x) (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX6GCR8_DX6GCR8_X4DXREFISELR2_M  GENMASK(21, 16)
#define DDR_PHY_DX6GCR8_DX6GCR8_X4DXREFISELR2_X(x)\
	(((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX6GCR8_DX6GCR8_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX6GCR8_DX6GCR8_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX6GCR8_DX6GCR8_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX6GCR8_DX6GCR8_X4DXREFISELR3(x) (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX6GCR8_DX6GCR8_X4DXREFISELR3_M  GENMASK(29, 24)
#define DDR_PHY_DX6GCR8_DX6GCR8_X4DXREFISELR3_X(x)\
	(((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX6GCR8_DX6GCR8_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX6GCR8_DX6GCR8_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX6GCR8_DX6GCR8_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6GCR9 */
#define DDR_PHY_DX6GCR9(t)        (t + 0xd24)

#define DDR_PHY_DX6GCR9_DX6GCR9_X4DXDQVREFR0(x)  ((x) & GENMASK(5, 0))
#define DDR_PHY_DX6GCR9_DX6GCR9_X4DXDQVREFR0_M   GENMASK(5, 0)
#define DDR_PHY_DX6GCR9_DX6GCR9_X4DXDQVREFR0_X(x) ((x) & GENMASK(5, 0))

#define DDR_PHY_DX6GCR9_DX6GCR9_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX6GCR9_DX6GCR9_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX6GCR9_DX6GCR9_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX6GCR9_DX6GCR9_X4DXDQVREFR1(x)  (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX6GCR9_DX6GCR9_X4DXDQVREFR1_M   GENMASK(13, 8)
#define DDR_PHY_DX6GCR9_DX6GCR9_X4DXDQVREFR1_X(x) (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX6GCR9_DX6GCR9_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX6GCR9_DX6GCR9_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX6GCR9_DX6GCR9_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX6GCR9_DX6GCR9_X4DXDQVREFR2(x)  (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX6GCR9_DX6GCR9_X4DXDQVREFR2_M   GENMASK(21, 16)
#define DDR_PHY_DX6GCR9_DX6GCR9_X4DXDQVREFR2_X(x)\
	(((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX6GCR9_DX6GCR9_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX6GCR9_DX6GCR9_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX6GCR9_DX6GCR9_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX6GCR9_DX6GCR9_X4DXDQVREFR3(x)  (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX6GCR9_DX6GCR9_X4DXDQVREFR3_M   GENMASK(29, 24)
#define DDR_PHY_DX6GCR9_DX6GCR9_X4DXDQVREFR3_X(x)\
	(((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX6GCR9_DX6GCR9_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX6GCR9_DX6GCR9_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX6GCR9_DX6GCR9_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6BDLR0 */
#define DDR_PHY_DX6BDLR0(t)       (t + 0xd40)

#define DDR_PHY_DX6BDLR0_DX6BDLR0_DQ0WBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX6BDLR0_DX6BDLR0_DQ0WBD_M       GENMASK(5, 0)
#define DDR_PHY_DX6BDLR0_DX6BDLR0_DQ0WBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX6BDLR0_DX6BDLR0_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX6BDLR0_DX6BDLR0_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX6BDLR0_DX6BDLR0_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX6BDLR0_DX6BDLR0_DQ1WBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX6BDLR0_DX6BDLR0_DQ1WBD_M       GENMASK(13, 8)
#define DDR_PHY_DX6BDLR0_DX6BDLR0_DQ1WBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX6BDLR0_DX6BDLR0_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX6BDLR0_DX6BDLR0_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX6BDLR0_DX6BDLR0_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX6BDLR0_DX6BDLR0_DQ2WBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX6BDLR0_DX6BDLR0_DQ2WBD_M       GENMASK(21, 16)
#define DDR_PHY_DX6BDLR0_DX6BDLR0_DQ2WBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX6BDLR0_DX6BDLR0_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX6BDLR0_DX6BDLR0_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX6BDLR0_DX6BDLR0_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX6BDLR0_DX6BDLR0_DQ3WBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX6BDLR0_DX6BDLR0_DQ3WBD_M       GENMASK(29, 24)
#define DDR_PHY_DX6BDLR0_DX6BDLR0_DQ3WBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX6BDLR0_DX6BDLR0_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX6BDLR0_DX6BDLR0_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX6BDLR0_DX6BDLR0_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6BDLR1 */
#define DDR_PHY_DX6BDLR1(t)       (t + 0xd44)

#define DDR_PHY_DX6BDLR1_DX6BDLR1_DQ4WBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX6BDLR1_DX6BDLR1_DQ4WBD_M       GENMASK(5, 0)
#define DDR_PHY_DX6BDLR1_DX6BDLR1_DQ4WBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX6BDLR1_DX6BDLR1_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX6BDLR1_DX6BDLR1_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX6BDLR1_DX6BDLR1_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX6BDLR1_DX6BDLR1_DQ5WBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX6BDLR1_DX6BDLR1_DQ5WBD_M       GENMASK(13, 8)
#define DDR_PHY_DX6BDLR1_DX6BDLR1_DQ5WBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX6BDLR1_DX6BDLR1_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX6BDLR1_DX6BDLR1_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX6BDLR1_DX6BDLR1_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX6BDLR1_DX6BDLR1_DQ6WBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX6BDLR1_DX6BDLR1_DQ6WBD_M       GENMASK(21, 16)
#define DDR_PHY_DX6BDLR1_DX6BDLR1_DQ6WBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX6BDLR1_DX6BDLR1_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX6BDLR1_DX6BDLR1_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX6BDLR1_DX6BDLR1_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX6BDLR1_DX6BDLR1_DQ7WBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX6BDLR1_DX6BDLR1_DQ7WBD_M       GENMASK(29, 24)
#define DDR_PHY_DX6BDLR1_DX6BDLR1_DQ7WBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX6BDLR1_DX6BDLR1_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX6BDLR1_DX6BDLR1_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX6BDLR1_DX6BDLR1_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6BDLR2 */
#define DDR_PHY_DX6BDLR2(t)       (t + 0xd48)

#define DDR_PHY_DX6BDLR2_DX6BDLR2_DMWBD(x)       ((x) & GENMASK(5, 0))
#define DDR_PHY_DX6BDLR2_DX6BDLR2_DMWBD_M        GENMASK(5, 0)
#define DDR_PHY_DX6BDLR2_DX6BDLR2_DMWBD_X(x)     ((x) & GENMASK(5, 0))

#define DDR_PHY_DX6BDLR2_DX6BDLR2_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX6BDLR2_DX6BDLR2_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX6BDLR2_DX6BDLR2_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX6BDLR2_DX6BDLR2_DSWBD(x)       (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX6BDLR2_DX6BDLR2_DSWBD_M        GENMASK(13, 8)
#define DDR_PHY_DX6BDLR2_DX6BDLR2_DSWBD_X(x)     (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX6BDLR2_DX6BDLR2_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX6BDLR2_DX6BDLR2_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX6BDLR2_DX6BDLR2_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX6BDLR2_DX6BDLR2_DSOEBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX6BDLR2_DX6BDLR2_DSOEBD_M       GENMASK(21, 16)
#define DDR_PHY_DX6BDLR2_DX6BDLR2_DSOEBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX6BDLR2_DX6BDLR2_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX6BDLR2_DX6BDLR2_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX6BDLR2_DX6BDLR2_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6BDLR3 */
#define DDR_PHY_DX6BDLR3(t)       (t + 0xd50)

#define DDR_PHY_DX6BDLR3_DX6BDLR3_DQ0RBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX6BDLR3_DX6BDLR3_DQ0RBD_M       GENMASK(5, 0)
#define DDR_PHY_DX6BDLR3_DX6BDLR3_DQ0RBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX6BDLR3_DX6BDLR3_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX6BDLR3_DX6BDLR3_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX6BDLR3_DX6BDLR3_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX6BDLR3_DX6BDLR3_DQ1RBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX6BDLR3_DX6BDLR3_DQ1RBD_M       GENMASK(13, 8)
#define DDR_PHY_DX6BDLR3_DX6BDLR3_DQ1RBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX6BDLR3_DX6BDLR3_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX6BDLR3_DX6BDLR3_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX6BDLR3_DX6BDLR3_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX6BDLR3_DX6BDLR3_DQ2RBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX6BDLR3_DX6BDLR3_DQ2RBD_M       GENMASK(21, 16)
#define DDR_PHY_DX6BDLR3_DX6BDLR3_DQ2RBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX6BDLR3_DX6BDLR3_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX6BDLR3_DX6BDLR3_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX6BDLR3_DX6BDLR3_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX6BDLR3_DX6BDLR3_DQ3RBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX6BDLR3_DX6BDLR3_DQ3RBD_M       GENMASK(29, 24)
#define DDR_PHY_DX6BDLR3_DX6BDLR3_DQ3RBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX6BDLR3_DX6BDLR3_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX6BDLR3_DX6BDLR3_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX6BDLR3_DX6BDLR3_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6BDLR4 */
#define DDR_PHY_DX6BDLR4(t)       (t + 0xd54)

#define DDR_PHY_DX6BDLR4_DX6BDLR4_DQ4RBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX6BDLR4_DX6BDLR4_DQ4RBD_M       GENMASK(5, 0)
#define DDR_PHY_DX6BDLR4_DX6BDLR4_DQ4RBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX6BDLR4_DX6BDLR4_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX6BDLR4_DX6BDLR4_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX6BDLR4_DX6BDLR4_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX6BDLR4_DX6BDLR4_DQ5RBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX6BDLR4_DX6BDLR4_DQ5RBD_M       GENMASK(13, 8)
#define DDR_PHY_DX6BDLR4_DX6BDLR4_DQ5RBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX6BDLR4_DX6BDLR4_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX6BDLR4_DX6BDLR4_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX6BDLR4_DX6BDLR4_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX6BDLR4_DX6BDLR4_DQ6RBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX6BDLR4_DX6BDLR4_DQ6RBD_M       GENMASK(21, 16)
#define DDR_PHY_DX6BDLR4_DX6BDLR4_DQ6RBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX6BDLR4_DX6BDLR4_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX6BDLR4_DX6BDLR4_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX6BDLR4_DX6BDLR4_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX6BDLR4_DX6BDLR4_DQ7RBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX6BDLR4_DX6BDLR4_DQ7RBD_M       GENMASK(29, 24)
#define DDR_PHY_DX6BDLR4_DX6BDLR4_DQ7RBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX6BDLR4_DX6BDLR4_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX6BDLR4_DX6BDLR4_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX6BDLR4_DX6BDLR4_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6BDLR5 */
#define DDR_PHY_DX6BDLR5(t)       (t + 0xd58)

#define DDR_PHY_DX6BDLR5_DX6BDLR5_DMRBD(x)       ((x) & GENMASK(5, 0))
#define DDR_PHY_DX6BDLR5_DX6BDLR5_DMRBD_M        GENMASK(5, 0)
#define DDR_PHY_DX6BDLR5_DX6BDLR5_DMRBD_X(x)     ((x) & GENMASK(5, 0))

#define DDR_PHY_DX6BDLR5_DX6BDLR5_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX6BDLR5_DX6BDLR5_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX6BDLR5_DX6BDLR5_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX6BDLR5_DX6BDLR5_DSRBD(x)       (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX6BDLR5_DX6BDLR5_DSRBD_M        GENMASK(13, 8)
#define DDR_PHY_DX6BDLR5_DX6BDLR5_DSRBD_X(x)     (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX6BDLR5_DX6BDLR5_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX6BDLR5_DX6BDLR5_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX6BDLR5_DX6BDLR5_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX6BDLR5_DX6BDLR5_DSNRBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX6BDLR5_DX6BDLR5_DSNRBD_M       GENMASK(21, 16)
#define DDR_PHY_DX6BDLR5_DX6BDLR5_DSNRBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX6BDLR5_DX6BDLR5_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX6BDLR5_DX6BDLR5_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX6BDLR5_DX6BDLR5_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6BDLR6 */
#define DDR_PHY_DX6BDLR6(t)       (t + 0xd60)

#define DDR_PHY_DX6BDLR6_DX6BDLR6_RESERVED_7_0(x) ((x) & GENMASK(7, 0))
#define DDR_PHY_DX6BDLR6_DX6BDLR6_RESERVED_7_0_M GENMASK(7, 0)
#define DDR_PHY_DX6BDLR6_DX6BDLR6_RESERVED_7_0_X(x) ((x) & GENMASK(7, 0))

#define DDR_PHY_DX6BDLR6_DX6BDLR6_PDRBD(x)       (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX6BDLR6_DX6BDLR6_PDRBD_M        GENMASK(13, 8)
#define DDR_PHY_DX6BDLR6_DX6BDLR6_PDRBD_X(x)     (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX6BDLR6_DX6BDLR6_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX6BDLR6_DX6BDLR6_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX6BDLR6_DX6BDLR6_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX6BDLR6_DX6BDLR6_TERBD(x)       (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX6BDLR6_DX6BDLR6_TERBD_M        GENMASK(21, 16)
#define DDR_PHY_DX6BDLR6_DX6BDLR6_TERBD_X(x)     (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX6BDLR6_DX6BDLR6_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX6BDLR6_DX6BDLR6_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX6BDLR6_DX6BDLR6_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6BDLR7 */
#define DDR_PHY_DX6BDLR7(t)       (t + 0xd64)

#define DDR_PHY_DX6BDLR7_DX6BDLR7_X4DMWBD(x)     ((x) & GENMASK(5, 0))
#define DDR_PHY_DX6BDLR7_DX6BDLR7_X4DMWBD_M      GENMASK(5, 0)
#define DDR_PHY_DX6BDLR7_DX6BDLR7_X4DMWBD_X(x)   ((x) & GENMASK(5, 0))

#define DDR_PHY_DX6BDLR7_DX6BDLR7_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX6BDLR7_DX6BDLR7_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX6BDLR7_DX6BDLR7_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX6BDLR7_DX6BDLR7_X4DSWBD(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX6BDLR7_DX6BDLR7_X4DSWBD_M      GENMASK(13, 8)
#define DDR_PHY_DX6BDLR7_DX6BDLR7_X4DSWBD_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX6BDLR7_DX6BDLR7_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX6BDLR7_DX6BDLR7_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX6BDLR7_DX6BDLR7_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX6BDLR7_DX6BDLR7_X4DSOEBD(x)    (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX6BDLR7_DX6BDLR7_X4DSOEBD_M     GENMASK(21, 16)
#define DDR_PHY_DX6BDLR7_DX6BDLR7_X4DSOEBD_X(x)  (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX6BDLR7_DX6BDLR7_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX6BDLR7_DX6BDLR7_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX6BDLR7_DX6BDLR7_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6BDLR8 */
#define DDR_PHY_DX6BDLR8(t)       (t + 0xd68)

#define DDR_PHY_DX6BDLR8_DX6BDLR8_X4DMRBD(x)     ((x) & GENMASK(5, 0))
#define DDR_PHY_DX6BDLR8_DX6BDLR8_X4DMRBD_M      GENMASK(5, 0)
#define DDR_PHY_DX6BDLR8_DX6BDLR8_X4DMRBD_X(x)   ((x) & GENMASK(5, 0))

#define DDR_PHY_DX6BDLR8_DX6BDLR8_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX6BDLR8_DX6BDLR8_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX6BDLR8_DX6BDLR8_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX6BDLR8_DX6BDLR8_X4DSRBD(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX6BDLR8_DX6BDLR8_X4DSRBD_M      GENMASK(13, 8)
#define DDR_PHY_DX6BDLR8_DX6BDLR8_X4DSRBD_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX6BDLR8_DX6BDLR8_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX6BDLR8_DX6BDLR8_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX6BDLR8_DX6BDLR8_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX6BDLR8_DX6BDLR8_X4DSNRBD(x)    (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX6BDLR8_DX6BDLR8_X4DSNRBD_M     GENMASK(21, 16)
#define DDR_PHY_DX6BDLR8_DX6BDLR8_X4DSNRBD_X(x)  (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX6BDLR8_DX6BDLR8_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX6BDLR8_DX6BDLR8_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX6BDLR8_DX6BDLR8_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6BDLR9 */
#define DDR_PHY_DX6BDLR9(t)       (t + 0xd6c)

#define DDR_PHY_DX6BDLR9_DX6BDLR9_RESERVED_7_0(x) ((x) & GENMASK(7, 0))
#define DDR_PHY_DX6BDLR9_DX6BDLR9_RESERVED_7_0_M GENMASK(7, 0)
#define DDR_PHY_DX6BDLR9_DX6BDLR9_RESERVED_7_0_X(x) ((x) & GENMASK(7, 0))

#define DDR_PHY_DX6BDLR9_DX6BDLR9_X4PDRBD(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX6BDLR9_DX6BDLR9_X4PDRBD_M      GENMASK(13, 8)
#define DDR_PHY_DX6BDLR9_DX6BDLR9_X4PDRBD_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX6BDLR9_DX6BDLR9_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX6BDLR9_DX6BDLR9_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX6BDLR9_DX6BDLR9_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX6BDLR9_DX6BDLR9_X4TERBD(x)     (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX6BDLR9_DX6BDLR9_X4TERBD_M      GENMASK(21, 16)
#define DDR_PHY_DX6BDLR9_DX6BDLR9_X4TERBD_X(x)   (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX6BDLR9_DX6BDLR9_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX6BDLR9_DX6BDLR9_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX6BDLR9_DX6BDLR9_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6LCDLR0 */
#define DDR_PHY_DX6LCDLR0(t)      (t + 0xd80)

#define DDR_PHY_DX6LCDLR0_DX6LCDLR0_WLD(x)       ((x) & GENMASK(8, 0))
#define DDR_PHY_DX6LCDLR0_DX6LCDLR0_WLD_M        GENMASK(8, 0)
#define DDR_PHY_DX6LCDLR0_DX6LCDLR0_WLD_X(x)     ((x) & GENMASK(8, 0))

#define DDR_PHY_DX6LCDLR0_DX6LCDLR0_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX6LCDLR0_DX6LCDLR0_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX6LCDLR0_DX6LCDLR0_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX6LCDLR0_DX6LCDLR0_X4WLD(x)     (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX6LCDLR0_DX6LCDLR0_X4WLD_M      GENMASK(24, 16)
#define DDR_PHY_DX6LCDLR0_DX6LCDLR0_X4WLD_X(x)   (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX6LCDLR0_DX6LCDLR0_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX6LCDLR0_DX6LCDLR0_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX6LCDLR0_DX6LCDLR0_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6LCDLR1 */
#define DDR_PHY_DX6LCDLR1(t)      (t + 0xd84)

#define DDR_PHY_DX6LCDLR1_DX6LCDLR1_WDQD(x)      ((x) & GENMASK(8, 0))
#define DDR_PHY_DX6LCDLR1_DX6LCDLR1_WDQD_M       GENMASK(8, 0)
#define DDR_PHY_DX6LCDLR1_DX6LCDLR1_WDQD_X(x)    ((x) & GENMASK(8, 0))

#define DDR_PHY_DX6LCDLR1_DX6LCDLR1_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX6LCDLR1_DX6LCDLR1_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX6LCDLR1_DX6LCDLR1_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX6LCDLR1_DX6LCDLR1_X4WDQD(x)    (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX6LCDLR1_DX6LCDLR1_X4WDQD_M     GENMASK(24, 16)
#define DDR_PHY_DX6LCDLR1_DX6LCDLR1_X4WDQD_X(x)  (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX6LCDLR1_DX6LCDLR1_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX6LCDLR1_DX6LCDLR1_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX6LCDLR1_DX6LCDLR1_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6LCDLR2 */
#define DDR_PHY_DX6LCDLR2(t)      (t + 0xd88)

#define DDR_PHY_DX6LCDLR2_DX6LCDLR2_DQSGD(x)     ((x) & GENMASK(8, 0))
#define DDR_PHY_DX6LCDLR2_DX6LCDLR2_DQSGD_M      GENMASK(8, 0)
#define DDR_PHY_DX6LCDLR2_DX6LCDLR2_DQSGD_X(x)   ((x) & GENMASK(8, 0))

#define DDR_PHY_DX6LCDLR2_DX6LCDLR2_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX6LCDLR2_DX6LCDLR2_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX6LCDLR2_DX6LCDLR2_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX6LCDLR2_DX6LCDLR2_X4DQSGD(x)   (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX6LCDLR2_DX6LCDLR2_X4DQSGD_M    GENMASK(24, 16)
#define DDR_PHY_DX6LCDLR2_DX6LCDLR2_X4DQSGD_X(x) (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX6LCDLR2_DX6LCDLR2_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX6LCDLR2_DX6LCDLR2_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX6LCDLR2_DX6LCDLR2_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6LCDLR3 */
#define DDR_PHY_DX6LCDLR3(t)      (t + 0xd8c)

#define DDR_PHY_DX6LCDLR3_DX6LCDLR3_RDQSD(x)     ((x) & GENMASK(8, 0))
#define DDR_PHY_DX6LCDLR3_DX6LCDLR3_RDQSD_M      GENMASK(8, 0)
#define DDR_PHY_DX6LCDLR3_DX6LCDLR3_RDQSD_X(x)   ((x) & GENMASK(8, 0))

#define DDR_PHY_DX6LCDLR3_DX6LCDLR3_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX6LCDLR3_DX6LCDLR3_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX6LCDLR3_DX6LCDLR3_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX6LCDLR3_DX6LCDLR3_X4RDQSD(x)   (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX6LCDLR3_DX6LCDLR3_X4RDQSD_M    GENMASK(24, 16)
#define DDR_PHY_DX6LCDLR3_DX6LCDLR3_X4RDQSD_X(x) (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX6LCDLR3_DX6LCDLR3_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX6LCDLR3_DX6LCDLR3_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX6LCDLR3_DX6LCDLR3_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6LCDLR4 */
#define DDR_PHY_DX6LCDLR4(t)      (t + 0xd90)

#define DDR_PHY_DX6LCDLR4_DX6LCDLR4_RDQSND(x)    ((x) & GENMASK(8, 0))
#define DDR_PHY_DX6LCDLR4_DX6LCDLR4_RDQSND_M     GENMASK(8, 0)
#define DDR_PHY_DX6LCDLR4_DX6LCDLR4_RDQSND_X(x)  ((x) & GENMASK(8, 0))

#define DDR_PHY_DX6LCDLR4_DX6LCDLR4_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX6LCDLR4_DX6LCDLR4_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX6LCDLR4_DX6LCDLR4_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX6LCDLR4_DX6LCDLR4_X4RDQSND(x)  (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX6LCDLR4_DX6LCDLR4_X4RDQSND_M   GENMASK(24, 16)
#define DDR_PHY_DX6LCDLR4_DX6LCDLR4_X4RDQSND_X(x)\
	(((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX6LCDLR4_DX6LCDLR4_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX6LCDLR4_DX6LCDLR4_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX6LCDLR4_DX6LCDLR4_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6LCDLR5 */
#define DDR_PHY_DX6LCDLR5(t)      (t + 0xd94)

#define DDR_PHY_DX6LCDLR5_DX6LCDLR5_DQSGSD(x)    ((x) & GENMASK(8, 0))
#define DDR_PHY_DX6LCDLR5_DX6LCDLR5_DQSGSD_M     GENMASK(8, 0)
#define DDR_PHY_DX6LCDLR5_DX6LCDLR5_DQSGSD_X(x)  ((x) & GENMASK(8, 0))

#define DDR_PHY_DX6LCDLR5_DX6LCDLR5_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX6LCDLR5_DX6LCDLR5_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX6LCDLR5_DX6LCDLR5_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX6LCDLR5_DX6LCDLR5_X4DQSGSD(x)  (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX6LCDLR5_DX6LCDLR5_X4DQSGSD_M   GENMASK(24, 16)
#define DDR_PHY_DX6LCDLR5_DX6LCDLR5_X4DQSGSD_X(x)\
	(((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX6LCDLR5_DX6LCDLR5_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX6LCDLR5_DX6LCDLR5_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX6LCDLR5_DX6LCDLR5_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6MDLR0 */
#define DDR_PHY_DX6MDLR0(t)       (t + 0xda0)

#define DDR_PHY_DX6MDLR0_DX6MDLR0_IPRD(x)        ((x) & GENMASK(8, 0))
#define DDR_PHY_DX6MDLR0_DX6MDLR0_IPRD_M         GENMASK(8, 0)
#define DDR_PHY_DX6MDLR0_DX6MDLR0_IPRD_X(x)      ((x) & GENMASK(8, 0))

#define DDR_PHY_DX6MDLR0_DX6MDLR0_RESERVED_15_9(x) (((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX6MDLR0_DX6MDLR0_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX6MDLR0_DX6MDLR0_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX6MDLR0_DX6MDLR0_TPRD(x)        (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX6MDLR0_DX6MDLR0_TPRD_M         GENMASK(24, 16)
#define DDR_PHY_DX6MDLR0_DX6MDLR0_TPRD_X(x)      (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX6MDLR0_DX6MDLR0_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX6MDLR0_DX6MDLR0_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX6MDLR0_DX6MDLR0_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6MDLR1 */
#define DDR_PHY_DX6MDLR1(t)       (t + 0xda4)

#define DDR_PHY_DX6MDLR1_DX6MDLR1_MDLD(x)        ((x) & GENMASK(8, 0))
#define DDR_PHY_DX6MDLR1_DX6MDLR1_MDLD_M         GENMASK(8, 0)
#define DDR_PHY_DX6MDLR1_DX6MDLR1_MDLD_X(x)      ((x) & GENMASK(8, 0))

#define DDR_PHY_DX6MDLR1_DX6MDLR1_RESERVED_31_9(x) (((x) << 9) & GENMASK(31, 9))
#define DDR_PHY_DX6MDLR1_DX6MDLR1_RESERVED_31_9_M GENMASK(31, 9)
#define DDR_PHY_DX6MDLR1_DX6MDLR1_RESERVED_31_9_X(x)\
	(((x) & GENMASK(31, 9)) >> 9)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6GTR0 */
#define DDR_PHY_DX6GTR0(t)        (t + 0xdc0)

#define DDR_PHY_DX6GTR0_DX6GTR0_DGSL(x)          ((x) & GENMASK(4, 0))
#define DDR_PHY_DX6GTR0_DX6GTR0_DGSL_M           GENMASK(4, 0)
#define DDR_PHY_DX6GTR0_DX6GTR0_DGSL_X(x)        ((x) & GENMASK(4, 0))

#define DDR_PHY_DX6GTR0_DX6GTR0_RESERVED_7_5(x)  (((x) << 5) & GENMASK(7, 5))
#define DDR_PHY_DX6GTR0_DX6GTR0_RESERVED_7_5_M   GENMASK(7, 5)
#define DDR_PHY_DX6GTR0_DX6GTR0_RESERVED_7_5_X(x) (((x) & GENMASK(7, 5)) >> 5)

#define DDR_PHY_DX6GTR0_DX6GTR0_X4DGSL(x)        (((x) << 8) & GENMASK(12, 8))
#define DDR_PHY_DX6GTR0_DX6GTR0_X4DGSL_M         GENMASK(12, 8)
#define DDR_PHY_DX6GTR0_DX6GTR0_X4DGSL_X(x)      (((x) & GENMASK(12, 8)) >> 8)

#define DDR_PHY_DX6GTR0_DX6GTR0_RESERVED_15_13(x)\
	(((x) << 13) & GENMASK(15, 13))
#define DDR_PHY_DX6GTR0_DX6GTR0_RESERVED_15_13_M GENMASK(15, 13)
#define DDR_PHY_DX6GTR0_DX6GTR0_RESERVED_15_13_X(x)\
	(((x) & GENMASK(15, 13)) >> 13)

#define DDR_PHY_DX6GTR0_DX6GTR0_WLSL(x)          (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DX6GTR0_DX6GTR0_WLSL_M           GENMASK(19, 16)
#define DDR_PHY_DX6GTR0_DX6GTR0_WLSL_X(x)        (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DX6GTR0_DX6GTR0_X4WLSL(x)        (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX6GTR0_DX6GTR0_X4WLSL_M         GENMASK(23, 20)
#define DDR_PHY_DX6GTR0_DX6GTR0_X4WLSL_X(x)      (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX6GTR0_DX6GTR0_RESERVED_31_24(x)\
	(((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_DX6GTR0_DX6GTR0_RESERVED_31_24_M GENMASK(31, 24)
#define DDR_PHY_DX6GTR0_DX6GTR0_RESERVED_31_24_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6RSR0 */
#define DDR_PHY_DX6RSR0(t)        (t + 0xdd0)

#define DDR_PHY_DX6RSR0_DX6RSR0_QSGERR(x)        ((x) & GENMASK(15, 0))
#define DDR_PHY_DX6RSR0_DX6RSR0_QSGERR_M         GENMASK(15, 0)
#define DDR_PHY_DX6RSR0_DX6RSR0_QSGERR_X(x)      ((x) & GENMASK(15, 0))

#define DDR_PHY_DX6RSR0_DX6RSR0_X4QSGERR(x)      (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX6RSR0_DX6RSR0_X4QSGERR_M       GENMASK(31, 16)
#define DDR_PHY_DX6RSR0_DX6RSR0_X4QSGERR_X(x)    (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6RSR1 */
#define DDR_PHY_DX6RSR1(t)        (t + 0xdd4)

#define DDR_PHY_DX6RSR1_DX6RSR1_RDLVLERR(x)      ((x) & GENMASK(15, 0))
#define DDR_PHY_DX6RSR1_DX6RSR1_RDLVLERR_M       GENMASK(15, 0)
#define DDR_PHY_DX6RSR1_DX6RSR1_RDLVLERR_X(x)    ((x) & GENMASK(15, 0))

#define DDR_PHY_DX6RSR1_DX6RSR1_X4RDLVLERR(x)    (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX6RSR1_DX6RSR1_X4RDLVLERR_M     GENMASK(31, 16)
#define DDR_PHY_DX6RSR1_DX6RSR1_X4RDLVLERR_X(x)  (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6RSR2 */
#define DDR_PHY_DX6RSR2(t)        (t + 0xdd8)

#define DDR_PHY_DX6RSR2_DX6RSR2_WLAWN(x)         ((x) & GENMASK(15, 0))
#define DDR_PHY_DX6RSR2_DX6RSR2_WLAWN_M          GENMASK(15, 0)
#define DDR_PHY_DX6RSR2_DX6RSR2_WLAWN_X(x)       ((x) & GENMASK(15, 0))

#define DDR_PHY_DX6RSR2_DX6RSR2_X4WLAWN(x)       (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX6RSR2_DX6RSR2_X4WLAWN_M        GENMASK(31, 16)
#define DDR_PHY_DX6RSR2_DX6RSR2_X4WLAWN_X(x)     (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6RSR3 */
#define DDR_PHY_DX6RSR3(t)        (t + 0xddc)

#define DDR_PHY_DX6RSR3_DX6RSR3_WLAERR(x)        ((x) & GENMASK(15, 0))
#define DDR_PHY_DX6RSR3_DX6RSR3_WLAERR_M         GENMASK(15, 0)
#define DDR_PHY_DX6RSR3_DX6RSR3_WLAERR_X(x)      ((x) & GENMASK(15, 0))

#define DDR_PHY_DX6RSR3_DX6RSR3_X4WLAERR(x)      (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX6RSR3_DX6RSR3_X4WLAERR_M       GENMASK(31, 16)
#define DDR_PHY_DX6RSR3_DX6RSR3_X4WLAERR_X(x)    (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6GSR0 */
#define DDR_PHY_DX6GSR0(t)        (t + 0xde0)

#define DDR_PHY_DX6GSR0_DX6GSR0_WDQCAL(x)        ((x) & GENMASK(0, 0))
#define DDR_PHY_DX6GSR0_DX6GSR0_WDQCAL_M         GENMASK(0, 0)
#define DDR_PHY_DX6GSR0_DX6GSR0_WDQCAL_X(x)      ((x) & GENMASK(0, 0))

#define DDR_PHY_DX6GSR0_DX6GSR0_RDQSCAL(x)       (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX6GSR0_DX6GSR0_RDQSCAL_M        GENMASK(1, 1)
#define DDR_PHY_DX6GSR0_DX6GSR0_RDQSCAL_X(x)     (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX6GSR0_DX6GSR0_RDQSNCAL(x)      (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX6GSR0_DX6GSR0_RDQSNCAL_M       GENMASK(2, 2)
#define DDR_PHY_DX6GSR0_DX6GSR0_RDQSNCAL_X(x)    (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX6GSR0_DX6GSR0_GDQSCAL(x)       (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX6GSR0_DX6GSR0_GDQSCAL_M        GENMASK(3, 3)
#define DDR_PHY_DX6GSR0_DX6GSR0_GDQSCAL_X(x)     (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX6GSR0_DX6GSR0_WLCAL(x)         (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX6GSR0_DX6GSR0_WLCAL_M          GENMASK(4, 4)
#define DDR_PHY_DX6GSR0_DX6GSR0_WLCAL_X(x)       (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX6GSR0_DX6GSR0_WLDONE(x)        (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX6GSR0_DX6GSR0_WLDONE_M         GENMASK(5, 5)
#define DDR_PHY_DX6GSR0_DX6GSR0_WLDONE_X(x)      (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX6GSR0_DX6GSR0_WLERR(x)         (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX6GSR0_DX6GSR0_WLERR_M          GENMASK(6, 6)
#define DDR_PHY_DX6GSR0_DX6GSR0_WLERR_X(x)       (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX6GSR0_DX6GSR0_WLPRD(x)         (((x) << 7) & GENMASK(15, 7))
#define DDR_PHY_DX6GSR0_DX6GSR0_WLPRD_M          GENMASK(15, 7)
#define DDR_PHY_DX6GSR0_DX6GSR0_WLPRD_X(x)       (((x) & GENMASK(15, 7)) >> 7)

#define DDR_PHY_DX6GSR0_DX6GSR0_DPLOCK(x)        (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX6GSR0_DX6GSR0_DPLOCK_M         GENMASK(16, 16)
#define DDR_PHY_DX6GSR0_DX6GSR0_DPLOCK_X(x)      (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX6GSR0_DX6GSR0_GDQSPRD(x)       (((x) << 17) & GENMASK(25, 17))
#define DDR_PHY_DX6GSR0_DX6GSR0_GDQSPRD_M        GENMASK(25, 17)
#define DDR_PHY_DX6GSR0_DX6GSR0_GDQSPRD_X(x)     (((x) & GENMASK(25, 17)) >> 17)

#define DDR_PHY_DX6GSR0_DX6GSR0_WLWN(x)          (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_DX6GSR0_DX6GSR0_WLWN_M           GENMASK(26, 26)
#define DDR_PHY_DX6GSR0_DX6GSR0_WLWN_X(x)        (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_DX6GSR0_DX6GSR0_RESERVED_29_27(x)\
	(((x) << 27) & GENMASK(29, 27))
#define DDR_PHY_DX6GSR0_DX6GSR0_RESERVED_29_27_M GENMASK(29, 27)
#define DDR_PHY_DX6GSR0_DX6GSR0_RESERVED_29_27_X(x)\
	(((x) & GENMASK(29, 27)) >> 27)

#define DDR_PHY_DX6GSR0_DX6GSR0_WLDQ(x)          (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX6GSR0_DX6GSR0_WLDQ_M           GENMASK(30, 30)
#define DDR_PHY_DX6GSR0_DX6GSR0_WLDQ_X(x)        (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX6GSR0_DX6GSR0_RESERVED_31(x)   (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX6GSR0_DX6GSR0_RESERVED_31_M    GENMASK(31, 31)
#define DDR_PHY_DX6GSR0_DX6GSR0_RESERVED_31_X(x) (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6GSR1 */
#define DDR_PHY_DX6GSR1(t)        (t + 0xde4)

#define DDR_PHY_DX6GSR1_DX6GSR1_DLTDONE(x)       ((x) & GENMASK(0, 0))
#define DDR_PHY_DX6GSR1_DX6GSR1_DLTDONE_M        GENMASK(0, 0)
#define DDR_PHY_DX6GSR1_DX6GSR1_DLTDONE_X(x)     ((x) & GENMASK(0, 0))

#define DDR_PHY_DX6GSR1_DX6GSR1_DLTCODE(x)       (((x) << 1) & GENMASK(24, 1))
#define DDR_PHY_DX6GSR1_DX6GSR1_DLTCODE_M        GENMASK(24, 1)
#define DDR_PHY_DX6GSR1_DX6GSR1_DLTCODE_X(x)     (((x) & GENMASK(24, 1)) >> 1)

#define DDR_PHY_DX6GSR1_DX6GSR1_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX6GSR1_DX6GSR1_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX6GSR1_DX6GSR1_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6GSR2 */
#define DDR_PHY_DX6GSR2(t)        (t + 0xde8)

#define DDR_PHY_DX6GSR2_DX6GSR2_RDERR(x)         ((x) & GENMASK(0, 0))
#define DDR_PHY_DX6GSR2_DX6GSR2_RDERR_M          GENMASK(0, 0)
#define DDR_PHY_DX6GSR2_DX6GSR2_RDERR_X(x)       ((x) & GENMASK(0, 0))

#define DDR_PHY_DX6GSR2_DX6GSR2_RDWN(x)          (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX6GSR2_DX6GSR2_RDWN_M           GENMASK(1, 1)
#define DDR_PHY_DX6GSR2_DX6GSR2_RDWN_X(x)        (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX6GSR2_DX6GSR2_WDERR(x)         (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX6GSR2_DX6GSR2_WDERR_M          GENMASK(2, 2)
#define DDR_PHY_DX6GSR2_DX6GSR2_WDERR_X(x)       (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX6GSR2_DX6GSR2_WDWN(x)          (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX6GSR2_DX6GSR2_WDWN_M           GENMASK(3, 3)
#define DDR_PHY_DX6GSR2_DX6GSR2_WDWN_X(x)        (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX6GSR2_DX6GSR2_REERR(x)         (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX6GSR2_DX6GSR2_REERR_M          GENMASK(4, 4)
#define DDR_PHY_DX6GSR2_DX6GSR2_REERR_X(x)       (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX6GSR2_DX6GSR2_REWN(x)          (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX6GSR2_DX6GSR2_REWN_M           GENMASK(5, 5)
#define DDR_PHY_DX6GSR2_DX6GSR2_REWN_X(x)        (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX6GSR2_DX6GSR2_WEERR(x)         (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX6GSR2_DX6GSR2_WEERR_M          GENMASK(6, 6)
#define DDR_PHY_DX6GSR2_DX6GSR2_WEERR_X(x)       (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX6GSR2_DX6GSR2_WEWN(x)          (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_DX6GSR2_DX6GSR2_WEWN_M           GENMASK(7, 7)
#define DDR_PHY_DX6GSR2_DX6GSR2_WEWN_X(x)        (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_DX6GSR2_DX6GSR2_ESTAT(x)         (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX6GSR2_DX6GSR2_ESTAT_M          GENMASK(11, 8)
#define DDR_PHY_DX6GSR2_DX6GSR2_ESTAT_X(x)       (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX6GSR2_DX6GSR2_DBDQ(x)          (((x) << 12) & GENMASK(19, 12))
#define DDR_PHY_DX6GSR2_DX6GSR2_DBDQ_M           GENMASK(19, 12)
#define DDR_PHY_DX6GSR2_DX6GSR2_DBDQ_X(x)        (((x) & GENMASK(19, 12)) >> 12)

#define DDR_PHY_DX6GSR2_DX6GSR2_SRDERR(x)        (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX6GSR2_DX6GSR2_SRDERR_M         GENMASK(20, 20)
#define DDR_PHY_DX6GSR2_DX6GSR2_SRDERR_X(x)      (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX6GSR2_DX6GSR2_RESERVED_21(x)   (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX6GSR2_DX6GSR2_RESERVED_21_M    GENMASK(21, 21)
#define DDR_PHY_DX6GSR2_DX6GSR2_RESERVED_21_X(x) (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX6GSR2_DX6GSR2_GSDQSCAL(x)      (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX6GSR2_DX6GSR2_GSDQSCAL_M       GENMASK(22, 22)
#define DDR_PHY_DX6GSR2_DX6GSR2_GSDQSCAL_X(x)    (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX6GSR2_DX6GSR2_GSDQSPRD(x)      (((x) << 23) & GENMASK(31, 23))
#define DDR_PHY_DX6GSR2_DX6GSR2_GSDQSPRD_M       GENMASK(31, 23)
#define DDR_PHY_DX6GSR2_DX6GSR2_GSDQSPRD_X(x)    (((x) & GENMASK(31, 23)) >> 23)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6GSR3 */
#define DDR_PHY_DX6GSR3(t)        (t + 0xdec)

#define DDR_PHY_DX6GSR3_DX6GSR3_SRDPC(x)         ((x) & GENMASK(1, 0))
#define DDR_PHY_DX6GSR3_DX6GSR3_SRDPC_M          GENMASK(1, 0)
#define DDR_PHY_DX6GSR3_DX6GSR3_SRDPC_X(x)       ((x) & GENMASK(1, 0))

#define DDR_PHY_DX6GSR3_DX6GSR3_RESERVED_7_2(x)  (((x) << 2) & GENMASK(7, 2))
#define DDR_PHY_DX6GSR3_DX6GSR3_RESERVED_7_2_M   GENMASK(7, 2)
#define DDR_PHY_DX6GSR3_DX6GSR3_RESERVED_7_2_X(x) (((x) & GENMASK(7, 2)) >> 2)

#define DDR_PHY_DX6GSR3_DX6GSR3_HVERR(x)         (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX6GSR3_DX6GSR3_HVERR_M          GENMASK(11, 8)
#define DDR_PHY_DX6GSR3_DX6GSR3_HVERR_X(x)       (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX6GSR3_DX6GSR3_HVWRN(x)         (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_DX6GSR3_DX6GSR3_HVWRN_M          GENMASK(15, 12)
#define DDR_PHY_DX6GSR3_DX6GSR3_HVWRN_X(x)       (((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_DX6GSR3_DX6GSR3_DVERR(x)         (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DX6GSR3_DX6GSR3_DVERR_M          GENMASK(19, 16)
#define DDR_PHY_DX6GSR3_DX6GSR3_DVERR_X(x)       (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DX6GSR3_DX6GSR3_DVWRN(x)         (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX6GSR3_DX6GSR3_DVWRN_M          GENMASK(23, 20)
#define DDR_PHY_DX6GSR3_DX6GSR3_DVWRN_X(x)       (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX6GSR3_DX6GSR3_ESTAT(x)         (((x) << 24) & GENMASK(26, 24))
#define DDR_PHY_DX6GSR3_DX6GSR3_ESTAT_M          GENMASK(26, 24)
#define DDR_PHY_DX6GSR3_DX6GSR3_ESTAT_X(x)       (((x) & GENMASK(26, 24)) >> 24)

#define DDR_PHY_DX6GSR3_DX6GSR3_RESERVED_31_27(x)\
	(((x) << 27) & GENMASK(31, 27))
#define DDR_PHY_DX6GSR3_DX6GSR3_RESERVED_31_27_M GENMASK(31, 27)
#define DDR_PHY_DX6GSR3_DX6GSR3_RESERVED_31_27_X(x)\
	(((x) & GENMASK(31, 27)) >> 27)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6GSR4 */
#define DDR_PHY_DX6GSR4(t)        (t + 0xdf0)

#define DDR_PHY_DX6GSR4_DX6GSR4_X4WDQCAL(x)      ((x) & GENMASK(0, 0))
#define DDR_PHY_DX6GSR4_DX6GSR4_X4WDQCAL_M       GENMASK(0, 0)
#define DDR_PHY_DX6GSR4_DX6GSR4_X4WDQCAL_X(x)    ((x) & GENMASK(0, 0))

#define DDR_PHY_DX6GSR4_DX6GSR4_X4RDQSCAL(x)     (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX6GSR4_DX6GSR4_X4RDQSCAL_M      GENMASK(1, 1)
#define DDR_PHY_DX6GSR4_DX6GSR4_X4RDQSCAL_X(x)   (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX6GSR4_DX6GSR4_X4RDQSNCAL(x)    (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX6GSR4_DX6GSR4_X4RDQSNCAL_M     GENMASK(2, 2)
#define DDR_PHY_DX6GSR4_DX6GSR4_X4RDQSNCAL_X(x)  (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX6GSR4_DX6GSR4_X4GDQSCAL(x)     (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX6GSR4_DX6GSR4_X4GDQSCAL_M      GENMASK(3, 3)
#define DDR_PHY_DX6GSR4_DX6GSR4_X4GDQSCAL_X(x)   (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX6GSR4_DX6GSR4_X4WLCAL(x)       (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX6GSR4_DX6GSR4_X4WLCAL_M        GENMASK(4, 4)
#define DDR_PHY_DX6GSR4_DX6GSR4_X4WLCAL_X(x)     (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX6GSR4_DX6GSR4_X4WLDONE(x)      (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX6GSR4_DX6GSR4_X4WLDONE_M       GENMASK(5, 5)
#define DDR_PHY_DX6GSR4_DX6GSR4_X4WLDONE_X(x)    (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX6GSR4_DX6GSR4_X4WLERR(x)       (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX6GSR4_DX6GSR4_X4WLERR_M        GENMASK(6, 6)
#define DDR_PHY_DX6GSR4_DX6GSR4_X4WLERR_X(x)     (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX6GSR4_DX6GSR4_X4WLPRD(x)       (((x) << 7) & GENMASK(15, 7))
#define DDR_PHY_DX6GSR4_DX6GSR4_X4WLPRD_M        GENMASK(15, 7)
#define DDR_PHY_DX6GSR4_DX6GSR4_X4WLPRD_X(x)     (((x) & GENMASK(15, 7)) >> 7)

#define DDR_PHY_DX6GSR4_DX6GSR4_X4DPLOCK(x)      (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX6GSR4_DX6GSR4_X4DPLOCK_M       GENMASK(16, 16)
#define DDR_PHY_DX6GSR4_DX6GSR4_X4DPLOCK_X(x)    (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX6GSR4_DX6GSR4_X4GDQSPRD(x)     (((x) << 17) & GENMASK(25, 17))
#define DDR_PHY_DX6GSR4_DX6GSR4_X4GDQSPRD_M      GENMASK(25, 17)
#define DDR_PHY_DX6GSR4_DX6GSR4_X4GDQSPRD_X(x)   (((x) & GENMASK(25, 17)) >> 17)

#define DDR_PHY_DX6GSR4_DX6GSR4_X4WLWN(x)        (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_DX6GSR4_DX6GSR4_X4WLWN_M         GENMASK(26, 26)
#define DDR_PHY_DX6GSR4_DX6GSR4_X4WLWN_X(x)      (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_DX6GSR4_DX6GSR4_RESERVED_29_27(x)\
	(((x) << 27) & GENMASK(29, 27))
#define DDR_PHY_DX6GSR4_DX6GSR4_RESERVED_29_27_M GENMASK(29, 27)
#define DDR_PHY_DX6GSR4_DX6GSR4_RESERVED_29_27_X(x)\
	(((x) & GENMASK(29, 27)) >> 27)

#define DDR_PHY_DX6GSR4_DX6GSR4_X4WLDQ(x)        (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX6GSR4_DX6GSR4_X4WLDQ_M         GENMASK(30, 30)
#define DDR_PHY_DX6GSR4_DX6GSR4_X4WLDQ_X(x)      (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX6GSR4_DX6GSR4_RESERVED_31(x)   (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX6GSR4_DX6GSR4_RESERVED_31_M    GENMASK(31, 31)
#define DDR_PHY_DX6GSR4_DX6GSR4_RESERVED_31_X(x) (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6GSR5 */
#define DDR_PHY_DX6GSR5(t)        (t + 0xdf4)

#define DDR_PHY_DX6GSR5_DX6GSR5_X4RDERR(x)       ((x) & GENMASK(0, 0))
#define DDR_PHY_DX6GSR5_DX6GSR5_X4RDERR_M        GENMASK(0, 0)
#define DDR_PHY_DX6GSR5_DX6GSR5_X4RDERR_X(x)     ((x) & GENMASK(0, 0))

#define DDR_PHY_DX6GSR5_DX6GSR5_X4RDWN(x)        (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX6GSR5_DX6GSR5_X4RDWN_M         GENMASK(1, 1)
#define DDR_PHY_DX6GSR5_DX6GSR5_X4RDWN_X(x)      (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX6GSR5_DX6GSR5_X4WDERR(x)       (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX6GSR5_DX6GSR5_X4WDERR_M        GENMASK(2, 2)
#define DDR_PHY_DX6GSR5_DX6GSR5_X4WDERR_X(x)     (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX6GSR5_DX6GSR5_X4WDWN(x)        (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX6GSR5_DX6GSR5_X4WDWN_M         GENMASK(3, 3)
#define DDR_PHY_DX6GSR5_DX6GSR5_X4WDWN_X(x)      (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX6GSR5_DX6GSR5_X4REERR(x)       (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX6GSR5_DX6GSR5_X4REERR_M        GENMASK(4, 4)
#define DDR_PHY_DX6GSR5_DX6GSR5_X4REERR_X(x)     (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX6GSR5_DX6GSR5_X4REWN(x)        (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX6GSR5_DX6GSR5_X4REWN_M         GENMASK(5, 5)
#define DDR_PHY_DX6GSR5_DX6GSR5_X4REWN_X(x)      (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX6GSR5_DX6GSR5_X4WEERR(x)       (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX6GSR5_DX6GSR5_X4WEERR_M        GENMASK(6, 6)
#define DDR_PHY_DX6GSR5_DX6GSR5_X4WEERR_X(x)     (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX6GSR5_DX6GSR5_X4WEWN(x)        (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_DX6GSR5_DX6GSR5_X4WEWN_M         GENMASK(7, 7)
#define DDR_PHY_DX6GSR5_DX6GSR5_X4WEWN_X(x)      (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_DX6GSR5_DX6GSR5_X4ESTAT(x)       (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX6GSR5_DX6GSR5_X4ESTAT_M        GENMASK(11, 8)
#define DDR_PHY_DX6GSR5_DX6GSR5_X4ESTAT_X(x)     (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX6GSR5_DX6GSR5_RESERVED_19_12(x)\
	(((x) << 12) & GENMASK(19, 12))
#define DDR_PHY_DX6GSR5_DX6GSR5_RESERVED_19_12_M GENMASK(19, 12)
#define DDR_PHY_DX6GSR5_DX6GSR5_RESERVED_19_12_X(x)\
	(((x) & GENMASK(19, 12)) >> 12)

#define DDR_PHY_DX6GSR5_DX6GSR5_X4SRDERR(x)      (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX6GSR5_DX6GSR5_X4SRDERR_M       GENMASK(20, 20)
#define DDR_PHY_DX6GSR5_DX6GSR5_X4SRDERR_X(x)    (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX6GSR5_DX6GSR5_RESERVED_21(x)   (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX6GSR5_DX6GSR5_RESERVED_21_M    GENMASK(21, 21)
#define DDR_PHY_DX6GSR5_DX6GSR5_RESERVED_21_X(x) (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX6GSR5_DX6GSR5_X4GSDQSCAL(x)    (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX6GSR5_DX6GSR5_X4GSDQSCAL_M     GENMASK(22, 22)
#define DDR_PHY_DX6GSR5_DX6GSR5_X4GSDQSCAL_X(x)  (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX6GSR5_DX6GSR5_X4GSDQSPRD(x)    (((x) << 23) & GENMASK(31, 23))
#define DDR_PHY_DX6GSR5_DX6GSR5_X4GSDQSPRD_M     GENMASK(31, 23)
#define DDR_PHY_DX6GSR5_DX6GSR5_X4GSDQSPRD_X(x)  (((x) & GENMASK(31, 23)) >> 23)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX6GSR6 */
#define DDR_PHY_DX6GSR6(t)        (t + 0xdf8)

#define DDR_PHY_DX6GSR6_DX6GSR6_RESERVED_1_0(x)  ((x) & GENMASK(1, 0))
#define DDR_PHY_DX6GSR6_DX6GSR6_RESERVED_1_0_M   GENMASK(1, 0)
#define DDR_PHY_DX6GSR6_DX6GSR6_RESERVED_1_0_X(x) ((x) & GENMASK(1, 0))

#define DDR_PHY_DX6GSR6_DX6GSR6_X4SRDPC(x)       (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DX6GSR6_DX6GSR6_X4SRDPC_M        GENMASK(3, 2)
#define DDR_PHY_DX6GSR6_DX6GSR6_X4SRDPC_X(x)     (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DX6GSR6_DX6GSR6_RESERVED_7_4(x)  (((x) << 4) & GENMASK(7, 4))
#define DDR_PHY_DX6GSR6_DX6GSR6_RESERVED_7_4_M   GENMASK(7, 4)
#define DDR_PHY_DX6GSR6_DX6GSR6_RESERVED_7_4_X(x) (((x) & GENMASK(7, 4)) >> 4)

#define DDR_PHY_DX6GSR6_DX6GSR6_X4HVERR(x)       (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX6GSR6_DX6GSR6_X4HVERR_M        GENMASK(11, 8)
#define DDR_PHY_DX6GSR6_DX6GSR6_X4HVERR_X(x)     (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX6GSR6_DX6GSR6_X4HVWRN(x)       (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_DX6GSR6_DX6GSR6_X4HVWRN_M        GENMASK(15, 12)
#define DDR_PHY_DX6GSR6_DX6GSR6_X4HVWRN_X(x)     (((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_DX6GSR6_DX6GSR6_X4DVERR(x)       (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DX6GSR6_DX6GSR6_X4DVERR_M        GENMASK(19, 16)
#define DDR_PHY_DX6GSR6_DX6GSR6_X4DVERR_X(x)     (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DX6GSR6_DX6GSR6_X4DVWRN(x)       (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX6GSR6_DX6GSR6_X4DVWRN_M        GENMASK(23, 20)
#define DDR_PHY_DX6GSR6_DX6GSR6_X4DVWRN_X(x)     (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX6GSR6_DX6GSR6_RESERVED_31_24(x)\
	(((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_DX6GSR6_DX6GSR6_RESERVED_31_24_M GENMASK(31, 24)
#define DDR_PHY_DX6GSR6_DX6GSR6_RESERVED_31_24_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7GCR0 */
#define DDR_PHY_DX7GCR0(t)        (t + 0xe00)

#define DDR_PHY_DX7GCR0_DX7GCR0_DXEN(x)          ((x) & GENMASK(0, 0))
#define DDR_PHY_DX7GCR0_DX7GCR0_DXEN_M           GENMASK(0, 0)
#define DDR_PHY_DX7GCR0_DX7GCR0_DXEN_X(x)        ((x) & GENMASK(0, 0))

#define DDR_PHY_DX7GCR0_DX7GCR0_DXIOM(x)         (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX7GCR0_DX7GCR0_DXIOM_M          GENMASK(1, 1)
#define DDR_PHY_DX7GCR0_DX7GCR0_DXIOM_X(x)       (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX7GCR0_DX7GCR0_DQSGOE(x)        (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX7GCR0_DX7GCR0_DQSGOE_M         GENMASK(2, 2)
#define DDR_PHY_DX7GCR0_DX7GCR0_DQSGOE_X(x)      (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX7GCR0_DX7GCR0_DQSGODT(x)       (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX7GCR0_DX7GCR0_DQSGODT_M        GENMASK(3, 3)
#define DDR_PHY_DX7GCR0_DX7GCR0_DQSGODT_X(x)     (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX7GCR0_DX7GCR0_RESERVED_4(x)    (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX7GCR0_DX7GCR0_RESERVED_4_M     GENMASK(4, 4)
#define DDR_PHY_DX7GCR0_DX7GCR0_RESERVED_4_X(x)  (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX7GCR0_DX7GCR0_DQSGPDR(x)       (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX7GCR0_DX7GCR0_DQSGPDR_M        GENMASK(5, 5)
#define DDR_PHY_DX7GCR0_DX7GCR0_DQSGPDR_X(x)     (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX7GCR0_DX7GCR0_RESERVED_6(x)    (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX7GCR0_DX7GCR0_RESERVED_6_M     GENMASK(6, 6)
#define DDR_PHY_DX7GCR0_DX7GCR0_RESERVED_6_X(x)  (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX7GCR0_DX7GCR0_PDRAL(x)         (((x) << 7) & GENMASK(8, 7))
#define DDR_PHY_DX7GCR0_DX7GCR0_PDRAL_M          GENMASK(8, 7)
#define DDR_PHY_DX7GCR0_DX7GCR0_PDRAL_X(x)       (((x) & GENMASK(8, 7)) >> 7)

#define DDR_PHY_DX7GCR0_DX7GCR0_RTTOH(x)         (((x) << 9) & GENMASK(10, 9))
#define DDR_PHY_DX7GCR0_DX7GCR0_RTTOH_M          GENMASK(10, 9)
#define DDR_PHY_DX7GCR0_DX7GCR0_RTTOH_X(x)       (((x) & GENMASK(10, 9)) >> 9)

#define DDR_PHY_DX7GCR0_DX7GCR0_RTTOAL(x)        (((x) << 11) & GENMASK(11, 11))
#define DDR_PHY_DX7GCR0_DX7GCR0_RTTOAL_M         GENMASK(11, 11)
#define DDR_PHY_DX7GCR0_DX7GCR0_RTTOAL_X(x)      (((x) & GENMASK(11, 11)) >> 11)

#define DDR_PHY_DX7GCR0_DX7GCR0_DQSSEPDR(x)      (((x) << 12) & GENMASK(12, 12))
#define DDR_PHY_DX7GCR0_DX7GCR0_DQSSEPDR_M       GENMASK(12, 12)
#define DDR_PHY_DX7GCR0_DX7GCR0_DQSSEPDR_X(x)    (((x) & GENMASK(12, 12)) >> 12)

#define DDR_PHY_DX7GCR0_DX7GCR0_DQSNSEPDR(x)     (((x) << 13) & GENMASK(13, 13))
#define DDR_PHY_DX7GCR0_DX7GCR0_DQSNSEPDR_M      GENMASK(13, 13)
#define DDR_PHY_DX7GCR0_DX7GCR0_DQSNSEPDR_X(x)   (((x) & GENMASK(13, 13)) >> 13)

#define DDR_PHY_DX7GCR0_DX7GCR0_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX7GCR0_DX7GCR0_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX7GCR0_DX7GCR0_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX7GCR0_DX7GCR0_PLLRST(x)        (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX7GCR0_DX7GCR0_PLLRST_M         GENMASK(16, 16)
#define DDR_PHY_DX7GCR0_DX7GCR0_PLLRST_X(x)      (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX7GCR0_DX7GCR0_PLLPD(x)         (((x) << 17) & GENMASK(17, 17))
#define DDR_PHY_DX7GCR0_DX7GCR0_PLLPD_M          GENMASK(17, 17)
#define DDR_PHY_DX7GCR0_DX7GCR0_PLLPD_X(x)       (((x) & GENMASK(17, 17)) >> 17)

#define DDR_PHY_DX7GCR0_DX7GCR0_GSHIFT(x)        (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_DX7GCR0_DX7GCR0_GSHIFT_M         GENMASK(18, 18)
#define DDR_PHY_DX7GCR0_DX7GCR0_GSHIFT_X(x)      (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_DX7GCR0_DX7GCR0_PLLBYP(x)        (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_DX7GCR0_DX7GCR0_PLLBYP_M         GENMASK(19, 19)
#define DDR_PHY_DX7GCR0_DX7GCR0_PLLBYP_X(x)      (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_DX7GCR0_DX7GCR0_RDDLY(x)         (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX7GCR0_DX7GCR0_RDDLY_M          GENMASK(23, 20)
#define DDR_PHY_DX7GCR0_DX7GCR0_RDDLY_X(x)       (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX7GCR0_DX7GCR0_RESERVED_29_24(x)\
	(((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX7GCR0_DX7GCR0_RESERVED_29_24_M GENMASK(29, 24)
#define DDR_PHY_DX7GCR0_DX7GCR0_RESERVED_29_24_X(x)\
	(((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX7GCR0_DX7GCR0_MDLEN(x)         (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX7GCR0_DX7GCR0_MDLEN_M          GENMASK(30, 30)
#define DDR_PHY_DX7GCR0_DX7GCR0_MDLEN_X(x)       (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX7GCR0_DX7GCR0_CALBYP(x)        (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX7GCR0_DX7GCR0_CALBYP_M         GENMASK(31, 31)
#define DDR_PHY_DX7GCR0_DX7GCR0_CALBYP_X(x)      (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7GCR1 */
#define DDR_PHY_DX7GCR1(t)        (t + 0xe04)

#define DDR_PHY_DX7GCR1_DX7GCR1_RESERVED_15_0(x) ((x) & GENMASK(15, 0))
#define DDR_PHY_DX7GCR1_DX7GCR1_RESERVED_15_0_M  GENMASK(15, 0)
#define DDR_PHY_DX7GCR1_DX7GCR1_RESERVED_15_0_X(x) ((x) & GENMASK(15, 0))

#define DDR_PHY_DX7GCR1_DX7GCR1_DXPDRMODE(x)     (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX7GCR1_DX7GCR1_DXPDRMODE_M      GENMASK(31, 16)
#define DDR_PHY_DX7GCR1_DX7GCR1_DXPDRMODE_X(x)   (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7GCR2 */
#define DDR_PHY_DX7GCR2(t)        (t + 0xe08)

#define DDR_PHY_DX7GCR2_DX7GCR2_DXTEMODE(x)      ((x) & GENMASK(15, 0))
#define DDR_PHY_DX7GCR2_DX7GCR2_DXTEMODE_M       GENMASK(15, 0)
#define DDR_PHY_DX7GCR2_DX7GCR2_DXTEMODE_X(x)    ((x) & GENMASK(15, 0))

#define DDR_PHY_DX7GCR2_DX7GCR2_DXOEMODE(x)      (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX7GCR2_DX7GCR2_DXOEMODE_M       GENMASK(31, 16)
#define DDR_PHY_DX7GCR2_DX7GCR2_DXOEMODE_X(x)    (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7GCR3 */
#define DDR_PHY_DX7GCR3(t)        (t + 0xe0c)

#define DDR_PHY_DX7GCR3_DX7GCR3_RESERVED_1_0(x)  ((x) & GENMASK(1, 0))
#define DDR_PHY_DX7GCR3_DX7GCR3_RESERVED_1_0_M   GENMASK(1, 0)
#define DDR_PHY_DX7GCR3_DX7GCR3_RESERVED_1_0_X(x) ((x) & GENMASK(1, 0))

#define DDR_PHY_DX7GCR3_DX7GCR3_DSPDRMODE(x)     (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DX7GCR3_DX7GCR3_DSPDRMODE_M      GENMASK(3, 2)
#define DDR_PHY_DX7GCR3_DX7GCR3_DSPDRMODE_X(x)   (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DX7GCR3_DX7GCR3_DSTEMODE(x)      (((x) << 4) & GENMASK(5, 4))
#define DDR_PHY_DX7GCR3_DX7GCR3_DSTEMODE_M       GENMASK(5, 4)
#define DDR_PHY_DX7GCR3_DX7GCR3_DSTEMODE_X(x)    (((x) & GENMASK(5, 4)) >> 4)

#define DDR_PHY_DX7GCR3_DX7GCR3_DSOEMODE(x)      (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX7GCR3_DX7GCR3_DSOEMODE_M       GENMASK(7, 6)
#define DDR_PHY_DX7GCR3_DX7GCR3_DSOEMODE_X(x)    (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX7GCR3_DX7GCR3_RESERVED_9_8(x)  (((x) << 8) & GENMASK(9, 8))
#define DDR_PHY_DX7GCR3_DX7GCR3_RESERVED_9_8_M   GENMASK(9, 8)
#define DDR_PHY_DX7GCR3_DX7GCR3_RESERVED_9_8_X(x) (((x) & GENMASK(9, 8)) >> 8)

#define DDR_PHY_DX7GCR3_DX7GCR3_DMPDRMODE(x)     (((x) << 10) & GENMASK(11, 10))
#define DDR_PHY_DX7GCR3_DX7GCR3_DMPDRMODE_M      GENMASK(11, 10)
#define DDR_PHY_DX7GCR3_DX7GCR3_DMPDRMODE_X(x)   (((x) & GENMASK(11, 10)) >> 10)

#define DDR_PHY_DX7GCR3_DX7GCR3_DMTEMODE(x)      (((x) << 12) & GENMASK(13, 12))
#define DDR_PHY_DX7GCR3_DX7GCR3_DMTEMODE_M       GENMASK(13, 12)
#define DDR_PHY_DX7GCR3_DX7GCR3_DMTEMODE_X(x)    (((x) & GENMASK(13, 12)) >> 12)

#define DDR_PHY_DX7GCR3_DX7GCR3_DMOEMODE(x)      (((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX7GCR3_DX7GCR3_DMOEMODE_M       GENMASK(15, 14)
#define DDR_PHY_DX7GCR3_DX7GCR3_DMOEMODE_X(x)    (((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX7GCR3_DX7GCR3_RESERVED_17_16(x)\
	(((x) << 16) & GENMASK(17, 16))
#define DDR_PHY_DX7GCR3_DX7GCR3_RESERVED_17_16_M GENMASK(17, 16)
#define DDR_PHY_DX7GCR3_DX7GCR3_RESERVED_17_16_X(x)\
	(((x) & GENMASK(17, 16)) >> 16)

#define DDR_PHY_DX7GCR3_DX7GCR3_OEBVT(x)         (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_DX7GCR3_DX7GCR3_OEBVT_M          GENMASK(18, 18)
#define DDR_PHY_DX7GCR3_DX7GCR3_OEBVT_X(x)       (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_DX7GCR3_DX7GCR3_PDRBVT(x)        (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_DX7GCR3_DX7GCR3_PDRBVT_M         GENMASK(19, 19)
#define DDR_PHY_DX7GCR3_DX7GCR3_PDRBVT_X(x)      (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_DX7GCR3_DX7GCR3_TEBVT(x)         (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX7GCR3_DX7GCR3_TEBVT_M          GENMASK(20, 20)
#define DDR_PHY_DX7GCR3_DX7GCR3_TEBVT_X(x)       (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX7GCR3_DX7GCR3_WDSBVT(x)        (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX7GCR3_DX7GCR3_WDSBVT_M         GENMASK(21, 21)
#define DDR_PHY_DX7GCR3_DX7GCR3_WDSBVT_X(x)      (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX7GCR3_DX7GCR3_RDSBVT(x)        (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX7GCR3_DX7GCR3_RDSBVT_M         GENMASK(22, 22)
#define DDR_PHY_DX7GCR3_DX7GCR3_RDSBVT_X(x)      (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX7GCR3_DX7GCR3_RGSLVT(x)        (((x) << 23) & GENMASK(23, 23))
#define DDR_PHY_DX7GCR3_DX7GCR3_RGSLVT_M         GENMASK(23, 23)
#define DDR_PHY_DX7GCR3_DX7GCR3_RGSLVT_X(x)      (((x) & GENMASK(23, 23)) >> 23)

#define DDR_PHY_DX7GCR3_DX7GCR3_WLLVT(x)         (((x) << 24) & GENMASK(24, 24))
#define DDR_PHY_DX7GCR3_DX7GCR3_WLLVT_M          GENMASK(24, 24)
#define DDR_PHY_DX7GCR3_DX7GCR3_WLLVT_X(x)       (((x) & GENMASK(24, 24)) >> 24)

#define DDR_PHY_DX7GCR3_DX7GCR3_WDLVT(x)         (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_DX7GCR3_DX7GCR3_WDLVT_M          GENMASK(25, 25)
#define DDR_PHY_DX7GCR3_DX7GCR3_WDLVT_X(x)       (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_DX7GCR3_DX7GCR3_RDLVT(x)         (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_DX7GCR3_DX7GCR3_RDLVT_M          GENMASK(26, 26)
#define DDR_PHY_DX7GCR3_DX7GCR3_RDLVT_X(x)       (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_DX7GCR3_DX7GCR3_RGLVT(x)         (((x) << 27) & GENMASK(27, 27))
#define DDR_PHY_DX7GCR3_DX7GCR3_RGLVT_M          GENMASK(27, 27)
#define DDR_PHY_DX7GCR3_DX7GCR3_RGLVT_X(x)       (((x) & GENMASK(27, 27)) >> 27)

#define DDR_PHY_DX7GCR3_DX7GCR3_WDBVT(x)         (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_DX7GCR3_DX7GCR3_WDBVT_M          GENMASK(28, 28)
#define DDR_PHY_DX7GCR3_DX7GCR3_WDBVT_X(x)       (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_DX7GCR3_DX7GCR3_RDBVT(x)         (((x) << 29) & GENMASK(29, 29))
#define DDR_PHY_DX7GCR3_DX7GCR3_RDBVT_M          GENMASK(29, 29)
#define DDR_PHY_DX7GCR3_DX7GCR3_RDBVT_X(x)       (((x) & GENMASK(29, 29)) >> 29)

#define DDR_PHY_DX7GCR3_DX7GCR3_WDMBVT(x)        (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX7GCR3_DX7GCR3_WDMBVT_M         GENMASK(30, 30)
#define DDR_PHY_DX7GCR3_DX7GCR3_WDMBVT_X(x)      (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX7GCR3_DX7GCR3_RDMBVT(x)        (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX7GCR3_DX7GCR3_RDMBVT_M         GENMASK(31, 31)
#define DDR_PHY_DX7GCR3_DX7GCR3_RDMBVT_X(x)      (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7GCR4 */
#define DDR_PHY_DX7GCR4(t)        (t + 0xe10)

#define DDR_PHY_DX7GCR4_DX7GCR4_DXREFIMON(x)     ((x) & GENMASK(1, 0))
#define DDR_PHY_DX7GCR4_DX7GCR4_DXREFIMON_M      GENMASK(1, 0)
#define DDR_PHY_DX7GCR4_DX7GCR4_DXREFIMON_X(x)   ((x) & GENMASK(1, 0))

#define DDR_PHY_DX7GCR4_DX7GCR4_DXREFIEN(x)      (((x) << 2) & GENMASK(5, 2))
#define DDR_PHY_DX7GCR4_DX7GCR4_DXREFIEN_M       GENMASK(5, 2)
#define DDR_PHY_DX7GCR4_DX7GCR4_DXREFIEN_X(x)    (((x) & GENMASK(5, 2)) >> 2)

#define DDR_PHY_DX7GCR4_DX7GCR4_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX7GCR4_DX7GCR4_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX7GCR4_DX7GCR4_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX7GCR4_DX7GCR4_DXREFSSEL(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX7GCR4_DX7GCR4_DXREFSSEL_M      GENMASK(13, 8)
#define DDR_PHY_DX7GCR4_DX7GCR4_DXREFSSEL_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX7GCR4_DX7GCR4_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX7GCR4_DX7GCR4_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX7GCR4_DX7GCR4_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX7GCR4_DX7GCR4_DXREFESEL(x)     (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX7GCR4_DX7GCR4_DXREFESEL_M      GENMASK(21, 16)
#define DDR_PHY_DX7GCR4_DX7GCR4_DXREFESEL_X(x)   (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX7GCR4_DX7GCR4_RESERVED_24_22(x)\
	(((x) << 22) & GENMASK(24, 22))
#define DDR_PHY_DX7GCR4_DX7GCR4_RESERVED_24_22_M GENMASK(24, 22)
#define DDR_PHY_DX7GCR4_DX7GCR4_RESERVED_24_22_X(x)\
	(((x) & GENMASK(24, 22)) >> 22)

#define DDR_PHY_DX7GCR4_DX7GCR4_DXREFSEN(x)      (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_DX7GCR4_DX7GCR4_DXREFSEN_M       GENMASK(25, 25)
#define DDR_PHY_DX7GCR4_DX7GCR4_DXREFSEN_X(x)    (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_DX7GCR4_DX7GCR4_DXREFEEN(x)      (((x) << 26) & GENMASK(27, 26))
#define DDR_PHY_DX7GCR4_DX7GCR4_DXREFEEN_M       GENMASK(27, 26)
#define DDR_PHY_DX7GCR4_DX7GCR4_DXREFEEN_X(x)    (((x) & GENMASK(27, 26)) >> 26)

#define DDR_PHY_DX7GCR4_DX7GCR4_DXREFPEN(x)      (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_DX7GCR4_DX7GCR4_DXREFPEN_M       GENMASK(28, 28)
#define DDR_PHY_DX7GCR4_DX7GCR4_DXREFPEN_X(x)    (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_DX7GCR4_DX7GCR4_DXREFIOM(x)      (((x) << 29) & GENMASK(31, 29))
#define DDR_PHY_DX7GCR4_DX7GCR4_DXREFIOM_M       GENMASK(31, 29)
#define DDR_PHY_DX7GCR4_DX7GCR4_DXREFIOM_X(x)    (((x) & GENMASK(31, 29)) >> 29)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7GCR5 */
#define DDR_PHY_DX7GCR5(t)        (t + 0xe14)

#define DDR_PHY_DX7GCR5_DX7GCR5_DXREFISELR0(x)   ((x) & GENMASK(5, 0))
#define DDR_PHY_DX7GCR5_DX7GCR5_DXREFISELR0_M    GENMASK(5, 0)
#define DDR_PHY_DX7GCR5_DX7GCR5_DXREFISELR0_X(x) ((x) & GENMASK(5, 0))

#define DDR_PHY_DX7GCR5_DX7GCR5_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX7GCR5_DX7GCR5_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX7GCR5_DX7GCR5_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX7GCR5_DX7GCR5_DXREFISELR1(x)   (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX7GCR5_DX7GCR5_DXREFISELR1_M    GENMASK(13, 8)
#define DDR_PHY_DX7GCR5_DX7GCR5_DXREFISELR1_X(x) (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX7GCR5_DX7GCR5_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX7GCR5_DX7GCR5_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX7GCR5_DX7GCR5_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX7GCR5_DX7GCR5_DXREFISELR2(x)   (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX7GCR5_DX7GCR5_DXREFISELR2_M    GENMASK(21, 16)
#define DDR_PHY_DX7GCR5_DX7GCR5_DXREFISELR2_X(x) (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX7GCR5_DX7GCR5_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX7GCR5_DX7GCR5_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX7GCR5_DX7GCR5_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX7GCR5_DX7GCR5_DXREFISELR3(x)   (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX7GCR5_DX7GCR5_DXREFISELR3_M    GENMASK(29, 24)
#define DDR_PHY_DX7GCR5_DX7GCR5_DXREFISELR3_X(x) (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX7GCR5_DX7GCR5_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX7GCR5_DX7GCR5_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX7GCR5_DX7GCR5_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7GCR6 */
#define DDR_PHY_DX7GCR6(t)        (t + 0xe18)

#define DDR_PHY_DX7GCR6_DX7GCR6_DXDQVREFR0(x)    ((x) & GENMASK(5, 0))
#define DDR_PHY_DX7GCR6_DX7GCR6_DXDQVREFR0_M     GENMASK(5, 0)
#define DDR_PHY_DX7GCR6_DX7GCR6_DXDQVREFR0_X(x)  ((x) & GENMASK(5, 0))

#define DDR_PHY_DX7GCR6_DX7GCR6_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX7GCR6_DX7GCR6_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX7GCR6_DX7GCR6_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX7GCR6_DX7GCR6_DXDQVREFR1(x)    (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX7GCR6_DX7GCR6_DXDQVREFR1_M     GENMASK(13, 8)
#define DDR_PHY_DX7GCR6_DX7GCR6_DXDQVREFR1_X(x)  (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX7GCR6_DX7GCR6_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX7GCR6_DX7GCR6_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX7GCR6_DX7GCR6_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX7GCR6_DX7GCR6_DXDQVREFR2(x)    (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX7GCR6_DX7GCR6_DXDQVREFR2_M     GENMASK(21, 16)
#define DDR_PHY_DX7GCR6_DX7GCR6_DXDQVREFR2_X(x)  (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX7GCR6_DX7GCR6_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX7GCR6_DX7GCR6_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX7GCR6_DX7GCR6_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX7GCR6_DX7GCR6_DXDQVREFR3(x)    (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX7GCR6_DX7GCR6_DXDQVREFR3_M     GENMASK(29, 24)
#define DDR_PHY_DX7GCR6_DX7GCR6_DXDQVREFR3_X(x)  (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX7GCR6_DX7GCR6_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX7GCR6_DX7GCR6_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX7GCR6_DX7GCR6_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7GCR7 */
#define DDR_PHY_DX7GCR7(t)        (t + 0xe1c)

#define DDR_PHY_DX7GCR7_DX7GCR7_RESERVED_1_0(x)  ((x) & GENMASK(1, 0))
#define DDR_PHY_DX7GCR7_DX7GCR7_RESERVED_1_0_M   GENMASK(1, 0)
#define DDR_PHY_DX7GCR7_DX7GCR7_RESERVED_1_0_X(x) ((x) & GENMASK(1, 0))

#define DDR_PHY_DX7GCR7_DX7GCR7_X4DSPDRMODE(x)   (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DX7GCR7_DX7GCR7_X4DSPDRMODE_M    GENMASK(3, 2)
#define DDR_PHY_DX7GCR7_DX7GCR7_X4DSPDRMODE_X(x) (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DX7GCR7_DX7GCR7_X4DSTEMODE(x)    (((x) << 4) & GENMASK(5, 4))
#define DDR_PHY_DX7GCR7_DX7GCR7_X4DSTEMODE_M     GENMASK(5, 4)
#define DDR_PHY_DX7GCR7_DX7GCR7_X4DSTEMODE_X(x)  (((x) & GENMASK(5, 4)) >> 4)

#define DDR_PHY_DX7GCR7_DX7GCR7_X4DSOEMODE(x)    (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX7GCR7_DX7GCR7_X4DSOEMODE_M     GENMASK(7, 6)
#define DDR_PHY_DX7GCR7_DX7GCR7_X4DSOEMODE_X(x)  (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX7GCR7_DX7GCR7_RESERVED_9_8(x)  (((x) << 8) & GENMASK(9, 8))
#define DDR_PHY_DX7GCR7_DX7GCR7_RESERVED_9_8_M   GENMASK(9, 8)
#define DDR_PHY_DX7GCR7_DX7GCR7_RESERVED_9_8_X(x) (((x) & GENMASK(9, 8)) >> 8)

#define DDR_PHY_DX7GCR7_DX7GCR7_X4DXPDRMODE(x)   (((x) << 10) & GENMASK(11, 10))
#define DDR_PHY_DX7GCR7_DX7GCR7_X4DXPDRMODE_M    GENMASK(11, 10)
#define DDR_PHY_DX7GCR7_DX7GCR7_X4DXPDRMODE_X(x) (((x) & GENMASK(11, 10)) >> 10)

#define DDR_PHY_DX7GCR7_DX7GCR7_X4DXTEMODE(x)    (((x) << 12) & GENMASK(13, 12))
#define DDR_PHY_DX7GCR7_DX7GCR7_X4DXTEMODE_M     GENMASK(13, 12)
#define DDR_PHY_DX7GCR7_DX7GCR7_X4DXTEMODE_X(x)  (((x) & GENMASK(13, 12)) >> 12)

#define DDR_PHY_DX7GCR7_DX7GCR7_X4DXOEMODE(x)    (((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX7GCR7_DX7GCR7_X4DXOEMODE_M     GENMASK(15, 14)
#define DDR_PHY_DX7GCR7_DX7GCR7_X4DXOEMODE_X(x)  (((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX7GCR7_DX7GCR7_X4DQSGOE(x)      (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX7GCR7_DX7GCR7_X4DQSGOE_M       GENMASK(16, 16)
#define DDR_PHY_DX7GCR7_DX7GCR7_X4DQSGOE_X(x)    (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX7GCR7_DX7GCR7_X4DQSGODT(x)     (((x) << 17) & GENMASK(17, 17))
#define DDR_PHY_DX7GCR7_DX7GCR7_X4DQSGODT_M      GENMASK(17, 17)
#define DDR_PHY_DX7GCR7_DX7GCR7_X4DQSGODT_X(x)   (((x) & GENMASK(17, 17)) >> 17)

#define DDR_PHY_DX7GCR7_DX7GCR7_RESERVED_18(x)   (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_DX7GCR7_DX7GCR7_RESERVED_18_M    GENMASK(18, 18)
#define DDR_PHY_DX7GCR7_DX7GCR7_RESERVED_18_X(x) (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_DX7GCR7_DX7GCR7_X4DQSGPDR(x)     (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_DX7GCR7_DX7GCR7_X4DQSGPDR_M      GENMASK(19, 19)
#define DDR_PHY_DX7GCR7_DX7GCR7_X4DQSGPDR_X(x)   (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_DX7GCR7_DX7GCR7_RESERVED_20(x)   (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX7GCR7_DX7GCR7_RESERVED_20_M    GENMASK(20, 20)
#define DDR_PHY_DX7GCR7_DX7GCR7_RESERVED_20_X(x) (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX7GCR7_DX7GCR7_X4DQSSEPDR(x)    (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX7GCR7_DX7GCR7_X4DQSSEPDR_M     GENMASK(21, 21)
#define DDR_PHY_DX7GCR7_DX7GCR7_X4DQSSEPDR_X(x)  (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX7GCR7_DX7GCR7_X4DQSNSEPDR(x)   (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX7GCR7_DX7GCR7_X4DQSNSEPDR_M    GENMASK(22, 22)
#define DDR_PHY_DX7GCR7_DX7GCR7_X4DQSNSEPDR_X(x) (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX7GCR7_DX7GCR7_X4RTTOH(x)       (((x) << 23) & GENMASK(24, 23))
#define DDR_PHY_DX7GCR7_DX7GCR7_X4RTTOH_M        GENMASK(24, 23)
#define DDR_PHY_DX7GCR7_DX7GCR7_X4RTTOH_X(x)     (((x) & GENMASK(24, 23)) >> 23)

#define DDR_PHY_DX7GCR7_DX7GCR7_X4RTTOAL(x)      (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_DX7GCR7_DX7GCR7_X4RTTOAL_M       GENMASK(25, 25)
#define DDR_PHY_DX7GCR7_DX7GCR7_X4RTTOAL_X(x)    (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_DX7GCR7_DX7GCR7_X4RDDLY(x)       (((x) << 26) & GENMASK(29, 26))
#define DDR_PHY_DX7GCR7_DX7GCR7_X4RDDLY_M        GENMASK(29, 26)
#define DDR_PHY_DX7GCR7_DX7GCR7_X4RDDLY_X(x)     (((x) & GENMASK(29, 26)) >> 26)

#define DDR_PHY_DX7GCR7_DX7GCR7_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX7GCR7_DX7GCR7_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX7GCR7_DX7GCR7_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7GCR8 */
#define DDR_PHY_DX7GCR8(t)        (t + 0xe20)

#define DDR_PHY_DX7GCR8_DX7GCR8_X4DXREFISELR0(x) ((x) & GENMASK(5, 0))
#define DDR_PHY_DX7GCR8_DX7GCR8_X4DXREFISELR0_M  GENMASK(5, 0)
#define DDR_PHY_DX7GCR8_DX7GCR8_X4DXREFISELR0_X(x) ((x) & GENMASK(5, 0))

#define DDR_PHY_DX7GCR8_DX7GCR8_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX7GCR8_DX7GCR8_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX7GCR8_DX7GCR8_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX7GCR8_DX7GCR8_X4DXREFISELR1(x) (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX7GCR8_DX7GCR8_X4DXREFISELR1_M  GENMASK(13, 8)
#define DDR_PHY_DX7GCR8_DX7GCR8_X4DXREFISELR1_X(x) (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX7GCR8_DX7GCR8_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX7GCR8_DX7GCR8_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX7GCR8_DX7GCR8_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX7GCR8_DX7GCR8_X4DXREFISELR2(x) (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX7GCR8_DX7GCR8_X4DXREFISELR2_M  GENMASK(21, 16)
#define DDR_PHY_DX7GCR8_DX7GCR8_X4DXREFISELR2_X(x)\
	(((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX7GCR8_DX7GCR8_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX7GCR8_DX7GCR8_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX7GCR8_DX7GCR8_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX7GCR8_DX7GCR8_X4DXREFISELR3(x) (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX7GCR8_DX7GCR8_X4DXREFISELR3_M  GENMASK(29, 24)
#define DDR_PHY_DX7GCR8_DX7GCR8_X4DXREFISELR3_X(x)\
	(((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX7GCR8_DX7GCR8_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX7GCR8_DX7GCR8_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX7GCR8_DX7GCR8_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7GCR9 */
#define DDR_PHY_DX7GCR9(t)        (t + 0xe24)

#define DDR_PHY_DX7GCR9_DX7GCR9_X4DXDQVREFR0(x)  ((x) & GENMASK(5, 0))
#define DDR_PHY_DX7GCR9_DX7GCR9_X4DXDQVREFR0_M   GENMASK(5, 0)
#define DDR_PHY_DX7GCR9_DX7GCR9_X4DXDQVREFR0_X(x) ((x) & GENMASK(5, 0))

#define DDR_PHY_DX7GCR9_DX7GCR9_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX7GCR9_DX7GCR9_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX7GCR9_DX7GCR9_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX7GCR9_DX7GCR9_X4DXDQVREFR1(x)  (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX7GCR9_DX7GCR9_X4DXDQVREFR1_M   GENMASK(13, 8)
#define DDR_PHY_DX7GCR9_DX7GCR9_X4DXDQVREFR1_X(x) (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX7GCR9_DX7GCR9_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX7GCR9_DX7GCR9_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX7GCR9_DX7GCR9_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX7GCR9_DX7GCR9_X4DXDQVREFR2(x)  (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX7GCR9_DX7GCR9_X4DXDQVREFR2_M   GENMASK(21, 16)
#define DDR_PHY_DX7GCR9_DX7GCR9_X4DXDQVREFR2_X(x)\
	(((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX7GCR9_DX7GCR9_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX7GCR9_DX7GCR9_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX7GCR9_DX7GCR9_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX7GCR9_DX7GCR9_X4DXDQVREFR3(x)  (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX7GCR9_DX7GCR9_X4DXDQVREFR3_M   GENMASK(29, 24)
#define DDR_PHY_DX7GCR9_DX7GCR9_X4DXDQVREFR3_X(x)\
	(((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX7GCR9_DX7GCR9_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX7GCR9_DX7GCR9_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX7GCR9_DX7GCR9_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7BDLR0 */
#define DDR_PHY_DX7BDLR0(t)       (t + 0xe40)

#define DDR_PHY_DX7BDLR0_DX7BDLR0_DQ0WBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX7BDLR0_DX7BDLR0_DQ0WBD_M       GENMASK(5, 0)
#define DDR_PHY_DX7BDLR0_DX7BDLR0_DQ0WBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX7BDLR0_DX7BDLR0_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX7BDLR0_DX7BDLR0_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX7BDLR0_DX7BDLR0_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX7BDLR0_DX7BDLR0_DQ1WBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX7BDLR0_DX7BDLR0_DQ1WBD_M       GENMASK(13, 8)
#define DDR_PHY_DX7BDLR0_DX7BDLR0_DQ1WBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX7BDLR0_DX7BDLR0_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX7BDLR0_DX7BDLR0_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX7BDLR0_DX7BDLR0_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX7BDLR0_DX7BDLR0_DQ2WBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX7BDLR0_DX7BDLR0_DQ2WBD_M       GENMASK(21, 16)
#define DDR_PHY_DX7BDLR0_DX7BDLR0_DQ2WBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX7BDLR0_DX7BDLR0_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX7BDLR0_DX7BDLR0_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX7BDLR0_DX7BDLR0_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX7BDLR0_DX7BDLR0_DQ3WBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX7BDLR0_DX7BDLR0_DQ3WBD_M       GENMASK(29, 24)
#define DDR_PHY_DX7BDLR0_DX7BDLR0_DQ3WBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX7BDLR0_DX7BDLR0_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX7BDLR0_DX7BDLR0_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX7BDLR0_DX7BDLR0_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7BDLR1 */
#define DDR_PHY_DX7BDLR1(t)       (t + 0xe44)

#define DDR_PHY_DX7BDLR1_DX7BDLR1_DQ4WBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX7BDLR1_DX7BDLR1_DQ4WBD_M       GENMASK(5, 0)
#define DDR_PHY_DX7BDLR1_DX7BDLR1_DQ4WBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX7BDLR1_DX7BDLR1_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX7BDLR1_DX7BDLR1_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX7BDLR1_DX7BDLR1_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX7BDLR1_DX7BDLR1_DQ5WBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX7BDLR1_DX7BDLR1_DQ5WBD_M       GENMASK(13, 8)
#define DDR_PHY_DX7BDLR1_DX7BDLR1_DQ5WBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX7BDLR1_DX7BDLR1_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX7BDLR1_DX7BDLR1_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX7BDLR1_DX7BDLR1_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX7BDLR1_DX7BDLR1_DQ6WBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX7BDLR1_DX7BDLR1_DQ6WBD_M       GENMASK(21, 16)
#define DDR_PHY_DX7BDLR1_DX7BDLR1_DQ6WBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX7BDLR1_DX7BDLR1_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX7BDLR1_DX7BDLR1_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX7BDLR1_DX7BDLR1_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX7BDLR1_DX7BDLR1_DQ7WBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX7BDLR1_DX7BDLR1_DQ7WBD_M       GENMASK(29, 24)
#define DDR_PHY_DX7BDLR1_DX7BDLR1_DQ7WBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX7BDLR1_DX7BDLR1_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX7BDLR1_DX7BDLR1_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX7BDLR1_DX7BDLR1_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7BDLR2 */
#define DDR_PHY_DX7BDLR2(t)       (t + 0xe48)

#define DDR_PHY_DX7BDLR2_DX7BDLR2_DMWBD(x)       ((x) & GENMASK(5, 0))
#define DDR_PHY_DX7BDLR2_DX7BDLR2_DMWBD_M        GENMASK(5, 0)
#define DDR_PHY_DX7BDLR2_DX7BDLR2_DMWBD_X(x)     ((x) & GENMASK(5, 0))

#define DDR_PHY_DX7BDLR2_DX7BDLR2_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX7BDLR2_DX7BDLR2_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX7BDLR2_DX7BDLR2_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX7BDLR2_DX7BDLR2_DSWBD(x)       (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX7BDLR2_DX7BDLR2_DSWBD_M        GENMASK(13, 8)
#define DDR_PHY_DX7BDLR2_DX7BDLR2_DSWBD_X(x)     (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX7BDLR2_DX7BDLR2_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX7BDLR2_DX7BDLR2_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX7BDLR2_DX7BDLR2_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX7BDLR2_DX7BDLR2_DSOEBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX7BDLR2_DX7BDLR2_DSOEBD_M       GENMASK(21, 16)
#define DDR_PHY_DX7BDLR2_DX7BDLR2_DSOEBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX7BDLR2_DX7BDLR2_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX7BDLR2_DX7BDLR2_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX7BDLR2_DX7BDLR2_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7BDLR3 */
#define DDR_PHY_DX7BDLR3(t)       (t + 0xe50)

#define DDR_PHY_DX7BDLR3_DX7BDLR3_DQ0RBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX7BDLR3_DX7BDLR3_DQ0RBD_M       GENMASK(5, 0)
#define DDR_PHY_DX7BDLR3_DX7BDLR3_DQ0RBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX7BDLR3_DX7BDLR3_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX7BDLR3_DX7BDLR3_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX7BDLR3_DX7BDLR3_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX7BDLR3_DX7BDLR3_DQ1RBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX7BDLR3_DX7BDLR3_DQ1RBD_M       GENMASK(13, 8)
#define DDR_PHY_DX7BDLR3_DX7BDLR3_DQ1RBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX7BDLR3_DX7BDLR3_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX7BDLR3_DX7BDLR3_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX7BDLR3_DX7BDLR3_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX7BDLR3_DX7BDLR3_DQ2RBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX7BDLR3_DX7BDLR3_DQ2RBD_M       GENMASK(21, 16)
#define DDR_PHY_DX7BDLR3_DX7BDLR3_DQ2RBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX7BDLR3_DX7BDLR3_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX7BDLR3_DX7BDLR3_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX7BDLR3_DX7BDLR3_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX7BDLR3_DX7BDLR3_DQ3RBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX7BDLR3_DX7BDLR3_DQ3RBD_M       GENMASK(29, 24)
#define DDR_PHY_DX7BDLR3_DX7BDLR3_DQ3RBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX7BDLR3_DX7BDLR3_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX7BDLR3_DX7BDLR3_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX7BDLR3_DX7BDLR3_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7BDLR4 */
#define DDR_PHY_DX7BDLR4(t)       (t + 0xe54)

#define DDR_PHY_DX7BDLR4_DX7BDLR4_DQ4RBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX7BDLR4_DX7BDLR4_DQ4RBD_M       GENMASK(5, 0)
#define DDR_PHY_DX7BDLR4_DX7BDLR4_DQ4RBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX7BDLR4_DX7BDLR4_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX7BDLR4_DX7BDLR4_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX7BDLR4_DX7BDLR4_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX7BDLR4_DX7BDLR4_DQ5RBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX7BDLR4_DX7BDLR4_DQ5RBD_M       GENMASK(13, 8)
#define DDR_PHY_DX7BDLR4_DX7BDLR4_DQ5RBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX7BDLR4_DX7BDLR4_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX7BDLR4_DX7BDLR4_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX7BDLR4_DX7BDLR4_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX7BDLR4_DX7BDLR4_DQ6RBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX7BDLR4_DX7BDLR4_DQ6RBD_M       GENMASK(21, 16)
#define DDR_PHY_DX7BDLR4_DX7BDLR4_DQ6RBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX7BDLR4_DX7BDLR4_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX7BDLR4_DX7BDLR4_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX7BDLR4_DX7BDLR4_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX7BDLR4_DX7BDLR4_DQ7RBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX7BDLR4_DX7BDLR4_DQ7RBD_M       GENMASK(29, 24)
#define DDR_PHY_DX7BDLR4_DX7BDLR4_DQ7RBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX7BDLR4_DX7BDLR4_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX7BDLR4_DX7BDLR4_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX7BDLR4_DX7BDLR4_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7BDLR5 */
#define DDR_PHY_DX7BDLR5(t)       (t + 0xe58)

#define DDR_PHY_DX7BDLR5_DX7BDLR5_DMRBD(x)       ((x) & GENMASK(5, 0))
#define DDR_PHY_DX7BDLR5_DX7BDLR5_DMRBD_M        GENMASK(5, 0)
#define DDR_PHY_DX7BDLR5_DX7BDLR5_DMRBD_X(x)     ((x) & GENMASK(5, 0))

#define DDR_PHY_DX7BDLR5_DX7BDLR5_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX7BDLR5_DX7BDLR5_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX7BDLR5_DX7BDLR5_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX7BDLR5_DX7BDLR5_DSRBD(x)       (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX7BDLR5_DX7BDLR5_DSRBD_M        GENMASK(13, 8)
#define DDR_PHY_DX7BDLR5_DX7BDLR5_DSRBD_X(x)     (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX7BDLR5_DX7BDLR5_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX7BDLR5_DX7BDLR5_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX7BDLR5_DX7BDLR5_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX7BDLR5_DX7BDLR5_DSNRBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX7BDLR5_DX7BDLR5_DSNRBD_M       GENMASK(21, 16)
#define DDR_PHY_DX7BDLR5_DX7BDLR5_DSNRBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX7BDLR5_DX7BDLR5_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX7BDLR5_DX7BDLR5_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX7BDLR5_DX7BDLR5_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7BDLR6 */
#define DDR_PHY_DX7BDLR6(t)       (t + 0xe60)

#define DDR_PHY_DX7BDLR6_DX7BDLR6_RESERVED_7_0(x) ((x) & GENMASK(7, 0))
#define DDR_PHY_DX7BDLR6_DX7BDLR6_RESERVED_7_0_M GENMASK(7, 0)
#define DDR_PHY_DX7BDLR6_DX7BDLR6_RESERVED_7_0_X(x) ((x) & GENMASK(7, 0))

#define DDR_PHY_DX7BDLR6_DX7BDLR6_PDRBD(x)       (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX7BDLR6_DX7BDLR6_PDRBD_M        GENMASK(13, 8)
#define DDR_PHY_DX7BDLR6_DX7BDLR6_PDRBD_X(x)     (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX7BDLR6_DX7BDLR6_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX7BDLR6_DX7BDLR6_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX7BDLR6_DX7BDLR6_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX7BDLR6_DX7BDLR6_TERBD(x)       (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX7BDLR6_DX7BDLR6_TERBD_M        GENMASK(21, 16)
#define DDR_PHY_DX7BDLR6_DX7BDLR6_TERBD_X(x)     (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX7BDLR6_DX7BDLR6_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX7BDLR6_DX7BDLR6_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX7BDLR6_DX7BDLR6_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7BDLR7 */
#define DDR_PHY_DX7BDLR7(t)       (t + 0xe64)

#define DDR_PHY_DX7BDLR7_DX7BDLR7_X4DMWBD(x)     ((x) & GENMASK(5, 0))
#define DDR_PHY_DX7BDLR7_DX7BDLR7_X4DMWBD_M      GENMASK(5, 0)
#define DDR_PHY_DX7BDLR7_DX7BDLR7_X4DMWBD_X(x)   ((x) & GENMASK(5, 0))

#define DDR_PHY_DX7BDLR7_DX7BDLR7_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX7BDLR7_DX7BDLR7_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX7BDLR7_DX7BDLR7_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX7BDLR7_DX7BDLR7_X4DSWBD(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX7BDLR7_DX7BDLR7_X4DSWBD_M      GENMASK(13, 8)
#define DDR_PHY_DX7BDLR7_DX7BDLR7_X4DSWBD_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX7BDLR7_DX7BDLR7_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX7BDLR7_DX7BDLR7_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX7BDLR7_DX7BDLR7_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX7BDLR7_DX7BDLR7_X4DSOEBD(x)    (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX7BDLR7_DX7BDLR7_X4DSOEBD_M     GENMASK(21, 16)
#define DDR_PHY_DX7BDLR7_DX7BDLR7_X4DSOEBD_X(x)  (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX7BDLR7_DX7BDLR7_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX7BDLR7_DX7BDLR7_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX7BDLR7_DX7BDLR7_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7BDLR8 */
#define DDR_PHY_DX7BDLR8(t)       (t + 0xe68)

#define DDR_PHY_DX7BDLR8_DX7BDLR8_X4DMRBD(x)     ((x) & GENMASK(5, 0))
#define DDR_PHY_DX7BDLR8_DX7BDLR8_X4DMRBD_M      GENMASK(5, 0)
#define DDR_PHY_DX7BDLR8_DX7BDLR8_X4DMRBD_X(x)   ((x) & GENMASK(5, 0))

#define DDR_PHY_DX7BDLR8_DX7BDLR8_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX7BDLR8_DX7BDLR8_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX7BDLR8_DX7BDLR8_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX7BDLR8_DX7BDLR8_X4DSRBD(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX7BDLR8_DX7BDLR8_X4DSRBD_M      GENMASK(13, 8)
#define DDR_PHY_DX7BDLR8_DX7BDLR8_X4DSRBD_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX7BDLR8_DX7BDLR8_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX7BDLR8_DX7BDLR8_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX7BDLR8_DX7BDLR8_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX7BDLR8_DX7BDLR8_X4DSNRBD(x)    (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX7BDLR8_DX7BDLR8_X4DSNRBD_M     GENMASK(21, 16)
#define DDR_PHY_DX7BDLR8_DX7BDLR8_X4DSNRBD_X(x)  (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX7BDLR8_DX7BDLR8_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX7BDLR8_DX7BDLR8_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX7BDLR8_DX7BDLR8_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7BDLR9 */
#define DDR_PHY_DX7BDLR9(t)       (t + 0xe6c)

#define DDR_PHY_DX7BDLR9_DX7BDLR9_RESERVED_7_0(x) ((x) & GENMASK(7, 0))
#define DDR_PHY_DX7BDLR9_DX7BDLR9_RESERVED_7_0_M GENMASK(7, 0)
#define DDR_PHY_DX7BDLR9_DX7BDLR9_RESERVED_7_0_X(x) ((x) & GENMASK(7, 0))

#define DDR_PHY_DX7BDLR9_DX7BDLR9_X4PDRBD(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX7BDLR9_DX7BDLR9_X4PDRBD_M      GENMASK(13, 8)
#define DDR_PHY_DX7BDLR9_DX7BDLR9_X4PDRBD_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX7BDLR9_DX7BDLR9_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX7BDLR9_DX7BDLR9_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX7BDLR9_DX7BDLR9_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX7BDLR9_DX7BDLR9_X4TERBD(x)     (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX7BDLR9_DX7BDLR9_X4TERBD_M      GENMASK(21, 16)
#define DDR_PHY_DX7BDLR9_DX7BDLR9_X4TERBD_X(x)   (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX7BDLR9_DX7BDLR9_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX7BDLR9_DX7BDLR9_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX7BDLR9_DX7BDLR9_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7LCDLR0 */
#define DDR_PHY_DX7LCDLR0(t)      (t + 0xe80)

#define DDR_PHY_DX7LCDLR0_DX7LCDLR0_WLD(x)       ((x) & GENMASK(8, 0))
#define DDR_PHY_DX7LCDLR0_DX7LCDLR0_WLD_M        GENMASK(8, 0)
#define DDR_PHY_DX7LCDLR0_DX7LCDLR0_WLD_X(x)     ((x) & GENMASK(8, 0))

#define DDR_PHY_DX7LCDLR0_DX7LCDLR0_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX7LCDLR0_DX7LCDLR0_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX7LCDLR0_DX7LCDLR0_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX7LCDLR0_DX7LCDLR0_X4WLD(x)     (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX7LCDLR0_DX7LCDLR0_X4WLD_M      GENMASK(24, 16)
#define DDR_PHY_DX7LCDLR0_DX7LCDLR0_X4WLD_X(x)   (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX7LCDLR0_DX7LCDLR0_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX7LCDLR0_DX7LCDLR0_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX7LCDLR0_DX7LCDLR0_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7LCDLR1 */
#define DDR_PHY_DX7LCDLR1(t)      (t + 0xe84)

#define DDR_PHY_DX7LCDLR1_DX7LCDLR1_WDQD(x)      ((x) & GENMASK(8, 0))
#define DDR_PHY_DX7LCDLR1_DX7LCDLR1_WDQD_M       GENMASK(8, 0)
#define DDR_PHY_DX7LCDLR1_DX7LCDLR1_WDQD_X(x)    ((x) & GENMASK(8, 0))

#define DDR_PHY_DX7LCDLR1_DX7LCDLR1_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX7LCDLR1_DX7LCDLR1_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX7LCDLR1_DX7LCDLR1_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX7LCDLR1_DX7LCDLR1_X4WDQD(x)    (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX7LCDLR1_DX7LCDLR1_X4WDQD_M     GENMASK(24, 16)
#define DDR_PHY_DX7LCDLR1_DX7LCDLR1_X4WDQD_X(x)  (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX7LCDLR1_DX7LCDLR1_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX7LCDLR1_DX7LCDLR1_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX7LCDLR1_DX7LCDLR1_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7LCDLR2 */
#define DDR_PHY_DX7LCDLR2(t)      (t + 0xe88)

#define DDR_PHY_DX7LCDLR2_DX7LCDLR2_DQSGD(x)     ((x) & GENMASK(8, 0))
#define DDR_PHY_DX7LCDLR2_DX7LCDLR2_DQSGD_M      GENMASK(8, 0)
#define DDR_PHY_DX7LCDLR2_DX7LCDLR2_DQSGD_X(x)   ((x) & GENMASK(8, 0))

#define DDR_PHY_DX7LCDLR2_DX7LCDLR2_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX7LCDLR2_DX7LCDLR2_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX7LCDLR2_DX7LCDLR2_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX7LCDLR2_DX7LCDLR2_X4DQSGD(x)   (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX7LCDLR2_DX7LCDLR2_X4DQSGD_M    GENMASK(24, 16)
#define DDR_PHY_DX7LCDLR2_DX7LCDLR2_X4DQSGD_X(x) (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX7LCDLR2_DX7LCDLR2_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX7LCDLR2_DX7LCDLR2_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX7LCDLR2_DX7LCDLR2_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7LCDLR3 */
#define DDR_PHY_DX7LCDLR3(t)      (t + 0xe8c)

#define DDR_PHY_DX7LCDLR3_DX7LCDLR3_RDQSD(x)     ((x) & GENMASK(8, 0))
#define DDR_PHY_DX7LCDLR3_DX7LCDLR3_RDQSD_M      GENMASK(8, 0)
#define DDR_PHY_DX7LCDLR3_DX7LCDLR3_RDQSD_X(x)   ((x) & GENMASK(8, 0))

#define DDR_PHY_DX7LCDLR3_DX7LCDLR3_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX7LCDLR3_DX7LCDLR3_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX7LCDLR3_DX7LCDLR3_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX7LCDLR3_DX7LCDLR3_X4RDQSD(x)   (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX7LCDLR3_DX7LCDLR3_X4RDQSD_M    GENMASK(24, 16)
#define DDR_PHY_DX7LCDLR3_DX7LCDLR3_X4RDQSD_X(x) (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX7LCDLR3_DX7LCDLR3_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX7LCDLR3_DX7LCDLR3_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX7LCDLR3_DX7LCDLR3_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7LCDLR4 */
#define DDR_PHY_DX7LCDLR4(t)      (t + 0xe90)

#define DDR_PHY_DX7LCDLR4_DX7LCDLR4_RDQSND(x)    ((x) & GENMASK(8, 0))
#define DDR_PHY_DX7LCDLR4_DX7LCDLR4_RDQSND_M     GENMASK(8, 0)
#define DDR_PHY_DX7LCDLR4_DX7LCDLR4_RDQSND_X(x)  ((x) & GENMASK(8, 0))

#define DDR_PHY_DX7LCDLR4_DX7LCDLR4_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX7LCDLR4_DX7LCDLR4_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX7LCDLR4_DX7LCDLR4_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX7LCDLR4_DX7LCDLR4_X4RDQSND(x)  (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX7LCDLR4_DX7LCDLR4_X4RDQSND_M   GENMASK(24, 16)
#define DDR_PHY_DX7LCDLR4_DX7LCDLR4_X4RDQSND_X(x)\
	(((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX7LCDLR4_DX7LCDLR4_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX7LCDLR4_DX7LCDLR4_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX7LCDLR4_DX7LCDLR4_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7LCDLR5 */
#define DDR_PHY_DX7LCDLR5(t)      (t + 0xe94)

#define DDR_PHY_DX7LCDLR5_DX7LCDLR5_DQSGSD(x)    ((x) & GENMASK(8, 0))
#define DDR_PHY_DX7LCDLR5_DX7LCDLR5_DQSGSD_M     GENMASK(8, 0)
#define DDR_PHY_DX7LCDLR5_DX7LCDLR5_DQSGSD_X(x)  ((x) & GENMASK(8, 0))

#define DDR_PHY_DX7LCDLR5_DX7LCDLR5_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX7LCDLR5_DX7LCDLR5_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX7LCDLR5_DX7LCDLR5_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX7LCDLR5_DX7LCDLR5_X4DQSGSD(x)  (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX7LCDLR5_DX7LCDLR5_X4DQSGSD_M   GENMASK(24, 16)
#define DDR_PHY_DX7LCDLR5_DX7LCDLR5_X4DQSGSD_X(x)\
	(((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX7LCDLR5_DX7LCDLR5_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX7LCDLR5_DX7LCDLR5_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX7LCDLR5_DX7LCDLR5_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7MDLR0 */
#define DDR_PHY_DX7MDLR0(t)       (t + 0xea0)

#define DDR_PHY_DX7MDLR0_DX7MDLR0_IPRD(x)        ((x) & GENMASK(8, 0))
#define DDR_PHY_DX7MDLR0_DX7MDLR0_IPRD_M         GENMASK(8, 0)
#define DDR_PHY_DX7MDLR0_DX7MDLR0_IPRD_X(x)      ((x) & GENMASK(8, 0))

#define DDR_PHY_DX7MDLR0_DX7MDLR0_RESERVED_15_9(x) (((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX7MDLR0_DX7MDLR0_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX7MDLR0_DX7MDLR0_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX7MDLR0_DX7MDLR0_TPRD(x)        (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX7MDLR0_DX7MDLR0_TPRD_M         GENMASK(24, 16)
#define DDR_PHY_DX7MDLR0_DX7MDLR0_TPRD_X(x)      (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX7MDLR0_DX7MDLR0_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX7MDLR0_DX7MDLR0_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX7MDLR0_DX7MDLR0_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7MDLR1 */
#define DDR_PHY_DX7MDLR1(t)       (t + 0xea4)

#define DDR_PHY_DX7MDLR1_DX7MDLR1_MDLD(x)        ((x) & GENMASK(8, 0))
#define DDR_PHY_DX7MDLR1_DX7MDLR1_MDLD_M         GENMASK(8, 0)
#define DDR_PHY_DX7MDLR1_DX7MDLR1_MDLD_X(x)      ((x) & GENMASK(8, 0))

#define DDR_PHY_DX7MDLR1_DX7MDLR1_RESERVED_31_9(x) (((x) << 9) & GENMASK(31, 9))
#define DDR_PHY_DX7MDLR1_DX7MDLR1_RESERVED_31_9_M GENMASK(31, 9)
#define DDR_PHY_DX7MDLR1_DX7MDLR1_RESERVED_31_9_X(x)\
	(((x) & GENMASK(31, 9)) >> 9)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7GTR0 */
#define DDR_PHY_DX7GTR0(t)        (t + 0xec0)

#define DDR_PHY_DX7GTR0_DX7GTR0_DGSL(x)          ((x) & GENMASK(4, 0))
#define DDR_PHY_DX7GTR0_DX7GTR0_DGSL_M           GENMASK(4, 0)
#define DDR_PHY_DX7GTR0_DX7GTR0_DGSL_X(x)        ((x) & GENMASK(4, 0))

#define DDR_PHY_DX7GTR0_DX7GTR0_RESERVED_7_5(x)  (((x) << 5) & GENMASK(7, 5))
#define DDR_PHY_DX7GTR0_DX7GTR0_RESERVED_7_5_M   GENMASK(7, 5)
#define DDR_PHY_DX7GTR0_DX7GTR0_RESERVED_7_5_X(x) (((x) & GENMASK(7, 5)) >> 5)

#define DDR_PHY_DX7GTR0_DX7GTR0_X4DGSL(x)        (((x) << 8) & GENMASK(12, 8))
#define DDR_PHY_DX7GTR0_DX7GTR0_X4DGSL_M         GENMASK(12, 8)
#define DDR_PHY_DX7GTR0_DX7GTR0_X4DGSL_X(x)      (((x) & GENMASK(12, 8)) >> 8)

#define DDR_PHY_DX7GTR0_DX7GTR0_RESERVED_15_13(x)\
	(((x) << 13) & GENMASK(15, 13))
#define DDR_PHY_DX7GTR0_DX7GTR0_RESERVED_15_13_M GENMASK(15, 13)
#define DDR_PHY_DX7GTR0_DX7GTR0_RESERVED_15_13_X(x)\
	(((x) & GENMASK(15, 13)) >> 13)

#define DDR_PHY_DX7GTR0_DX7GTR0_WLSL(x)          (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DX7GTR0_DX7GTR0_WLSL_M           GENMASK(19, 16)
#define DDR_PHY_DX7GTR0_DX7GTR0_WLSL_X(x)        (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DX7GTR0_DX7GTR0_X4WLSL(x)        (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX7GTR0_DX7GTR0_X4WLSL_M         GENMASK(23, 20)
#define DDR_PHY_DX7GTR0_DX7GTR0_X4WLSL_X(x)      (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX7GTR0_DX7GTR0_RESERVED_31_24(x)\
	(((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_DX7GTR0_DX7GTR0_RESERVED_31_24_M GENMASK(31, 24)
#define DDR_PHY_DX7GTR0_DX7GTR0_RESERVED_31_24_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7RSR0 */
#define DDR_PHY_DX7RSR0(t)        (t + 0xed0)

#define DDR_PHY_DX7RSR0_DX7RSR0_QSGERR(x)        ((x) & GENMASK(15, 0))
#define DDR_PHY_DX7RSR0_DX7RSR0_QSGERR_M         GENMASK(15, 0)
#define DDR_PHY_DX7RSR0_DX7RSR0_QSGERR_X(x)      ((x) & GENMASK(15, 0))

#define DDR_PHY_DX7RSR0_DX7RSR0_X4QSGERR(x)      (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX7RSR0_DX7RSR0_X4QSGERR_M       GENMASK(31, 16)
#define DDR_PHY_DX7RSR0_DX7RSR0_X4QSGERR_X(x)    (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7RSR1 */
#define DDR_PHY_DX7RSR1(t)        (t + 0xed4)

#define DDR_PHY_DX7RSR1_DX7RSR1_RDLVLERR(x)      ((x) & GENMASK(15, 0))
#define DDR_PHY_DX7RSR1_DX7RSR1_RDLVLERR_M       GENMASK(15, 0)
#define DDR_PHY_DX7RSR1_DX7RSR1_RDLVLERR_X(x)    ((x) & GENMASK(15, 0))

#define DDR_PHY_DX7RSR1_DX7RSR1_X4RDLVLERR(x)    (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX7RSR1_DX7RSR1_X4RDLVLERR_M     GENMASK(31, 16)
#define DDR_PHY_DX7RSR1_DX7RSR1_X4RDLVLERR_X(x)  (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7RSR2 */
#define DDR_PHY_DX7RSR2(t)        (t + 0xed8)

#define DDR_PHY_DX7RSR2_DX7RSR2_WLAWN(x)         ((x) & GENMASK(15, 0))
#define DDR_PHY_DX7RSR2_DX7RSR2_WLAWN_M          GENMASK(15, 0)
#define DDR_PHY_DX7RSR2_DX7RSR2_WLAWN_X(x)       ((x) & GENMASK(15, 0))

#define DDR_PHY_DX7RSR2_DX7RSR2_X4WLAWN(x)       (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX7RSR2_DX7RSR2_X4WLAWN_M        GENMASK(31, 16)
#define DDR_PHY_DX7RSR2_DX7RSR2_X4WLAWN_X(x)     (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7RSR3 */
#define DDR_PHY_DX7RSR3(t)        (t + 0xedc)

#define DDR_PHY_DX7RSR3_DX7RSR3_WLAERR(x)        ((x) & GENMASK(15, 0))
#define DDR_PHY_DX7RSR3_DX7RSR3_WLAERR_M         GENMASK(15, 0)
#define DDR_PHY_DX7RSR3_DX7RSR3_WLAERR_X(x)      ((x) & GENMASK(15, 0))

#define DDR_PHY_DX7RSR3_DX7RSR3_X4WLAERR(x)      (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX7RSR3_DX7RSR3_X4WLAERR_M       GENMASK(31, 16)
#define DDR_PHY_DX7RSR3_DX7RSR3_X4WLAERR_X(x)    (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7GSR0 */
#define DDR_PHY_DX7GSR0(t)        (t + 0xee0)

#define DDR_PHY_DX7GSR0_DX7GSR0_WDQCAL(x)        ((x) & GENMASK(0, 0))
#define DDR_PHY_DX7GSR0_DX7GSR0_WDQCAL_M         GENMASK(0, 0)
#define DDR_PHY_DX7GSR0_DX7GSR0_WDQCAL_X(x)      ((x) & GENMASK(0, 0))

#define DDR_PHY_DX7GSR0_DX7GSR0_RDQSCAL(x)       (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX7GSR0_DX7GSR0_RDQSCAL_M        GENMASK(1, 1)
#define DDR_PHY_DX7GSR0_DX7GSR0_RDQSCAL_X(x)     (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX7GSR0_DX7GSR0_RDQSNCAL(x)      (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX7GSR0_DX7GSR0_RDQSNCAL_M       GENMASK(2, 2)
#define DDR_PHY_DX7GSR0_DX7GSR0_RDQSNCAL_X(x)    (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX7GSR0_DX7GSR0_GDQSCAL(x)       (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX7GSR0_DX7GSR0_GDQSCAL_M        GENMASK(3, 3)
#define DDR_PHY_DX7GSR0_DX7GSR0_GDQSCAL_X(x)     (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX7GSR0_DX7GSR0_WLCAL(x)         (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX7GSR0_DX7GSR0_WLCAL_M          GENMASK(4, 4)
#define DDR_PHY_DX7GSR0_DX7GSR0_WLCAL_X(x)       (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX7GSR0_DX7GSR0_WLDONE(x)        (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX7GSR0_DX7GSR0_WLDONE_M         GENMASK(5, 5)
#define DDR_PHY_DX7GSR0_DX7GSR0_WLDONE_X(x)      (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX7GSR0_DX7GSR0_WLERR(x)         (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX7GSR0_DX7GSR0_WLERR_M          GENMASK(6, 6)
#define DDR_PHY_DX7GSR0_DX7GSR0_WLERR_X(x)       (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX7GSR0_DX7GSR0_WLPRD(x)         (((x) << 7) & GENMASK(15, 7))
#define DDR_PHY_DX7GSR0_DX7GSR0_WLPRD_M          GENMASK(15, 7)
#define DDR_PHY_DX7GSR0_DX7GSR0_WLPRD_X(x)       (((x) & GENMASK(15, 7)) >> 7)

#define DDR_PHY_DX7GSR0_DX7GSR0_DPLOCK(x)        (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX7GSR0_DX7GSR0_DPLOCK_M         GENMASK(16, 16)
#define DDR_PHY_DX7GSR0_DX7GSR0_DPLOCK_X(x)      (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX7GSR0_DX7GSR0_GDQSPRD(x)       (((x) << 17) & GENMASK(25, 17))
#define DDR_PHY_DX7GSR0_DX7GSR0_GDQSPRD_M        GENMASK(25, 17)
#define DDR_PHY_DX7GSR0_DX7GSR0_GDQSPRD_X(x)     (((x) & GENMASK(25, 17)) >> 17)

#define DDR_PHY_DX7GSR0_DX7GSR0_WLWN(x)          (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_DX7GSR0_DX7GSR0_WLWN_M           GENMASK(26, 26)
#define DDR_PHY_DX7GSR0_DX7GSR0_WLWN_X(x)        (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_DX7GSR0_DX7GSR0_RESERVED_29_27(x)\
	(((x) << 27) & GENMASK(29, 27))
#define DDR_PHY_DX7GSR0_DX7GSR0_RESERVED_29_27_M GENMASK(29, 27)
#define DDR_PHY_DX7GSR0_DX7GSR0_RESERVED_29_27_X(x)\
	(((x) & GENMASK(29, 27)) >> 27)

#define DDR_PHY_DX7GSR0_DX7GSR0_WLDQ(x)          (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX7GSR0_DX7GSR0_WLDQ_M           GENMASK(30, 30)
#define DDR_PHY_DX7GSR0_DX7GSR0_WLDQ_X(x)        (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX7GSR0_DX7GSR0_RESERVED_31(x)   (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX7GSR0_DX7GSR0_RESERVED_31_M    GENMASK(31, 31)
#define DDR_PHY_DX7GSR0_DX7GSR0_RESERVED_31_X(x) (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7GSR1 */
#define DDR_PHY_DX7GSR1(t)        (t + 0xee4)

#define DDR_PHY_DX7GSR1_DX7GSR1_DLTDONE(x)       ((x) & GENMASK(0, 0))
#define DDR_PHY_DX7GSR1_DX7GSR1_DLTDONE_M        GENMASK(0, 0)
#define DDR_PHY_DX7GSR1_DX7GSR1_DLTDONE_X(x)     ((x) & GENMASK(0, 0))

#define DDR_PHY_DX7GSR1_DX7GSR1_DLTCODE(x)       (((x) << 1) & GENMASK(24, 1))
#define DDR_PHY_DX7GSR1_DX7GSR1_DLTCODE_M        GENMASK(24, 1)
#define DDR_PHY_DX7GSR1_DX7GSR1_DLTCODE_X(x)     (((x) & GENMASK(24, 1)) >> 1)

#define DDR_PHY_DX7GSR1_DX7GSR1_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX7GSR1_DX7GSR1_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX7GSR1_DX7GSR1_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7GSR2 */
#define DDR_PHY_DX7GSR2(t)        (t + 0xee8)

#define DDR_PHY_DX7GSR2_DX7GSR2_RDERR(x)         ((x) & GENMASK(0, 0))
#define DDR_PHY_DX7GSR2_DX7GSR2_RDERR_M          GENMASK(0, 0)
#define DDR_PHY_DX7GSR2_DX7GSR2_RDERR_X(x)       ((x) & GENMASK(0, 0))

#define DDR_PHY_DX7GSR2_DX7GSR2_RDWN(x)          (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX7GSR2_DX7GSR2_RDWN_M           GENMASK(1, 1)
#define DDR_PHY_DX7GSR2_DX7GSR2_RDWN_X(x)        (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX7GSR2_DX7GSR2_WDERR(x)         (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX7GSR2_DX7GSR2_WDERR_M          GENMASK(2, 2)
#define DDR_PHY_DX7GSR2_DX7GSR2_WDERR_X(x)       (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX7GSR2_DX7GSR2_WDWN(x)          (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX7GSR2_DX7GSR2_WDWN_M           GENMASK(3, 3)
#define DDR_PHY_DX7GSR2_DX7GSR2_WDWN_X(x)        (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX7GSR2_DX7GSR2_REERR(x)         (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX7GSR2_DX7GSR2_REERR_M          GENMASK(4, 4)
#define DDR_PHY_DX7GSR2_DX7GSR2_REERR_X(x)       (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX7GSR2_DX7GSR2_REWN(x)          (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX7GSR2_DX7GSR2_REWN_M           GENMASK(5, 5)
#define DDR_PHY_DX7GSR2_DX7GSR2_REWN_X(x)        (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX7GSR2_DX7GSR2_WEERR(x)         (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX7GSR2_DX7GSR2_WEERR_M          GENMASK(6, 6)
#define DDR_PHY_DX7GSR2_DX7GSR2_WEERR_X(x)       (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX7GSR2_DX7GSR2_WEWN(x)          (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_DX7GSR2_DX7GSR2_WEWN_M           GENMASK(7, 7)
#define DDR_PHY_DX7GSR2_DX7GSR2_WEWN_X(x)        (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_DX7GSR2_DX7GSR2_ESTAT(x)         (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX7GSR2_DX7GSR2_ESTAT_M          GENMASK(11, 8)
#define DDR_PHY_DX7GSR2_DX7GSR2_ESTAT_X(x)       (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX7GSR2_DX7GSR2_DBDQ(x)          (((x) << 12) & GENMASK(19, 12))
#define DDR_PHY_DX7GSR2_DX7GSR2_DBDQ_M           GENMASK(19, 12)
#define DDR_PHY_DX7GSR2_DX7GSR2_DBDQ_X(x)        (((x) & GENMASK(19, 12)) >> 12)

#define DDR_PHY_DX7GSR2_DX7GSR2_SRDERR(x)        (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX7GSR2_DX7GSR2_SRDERR_M         GENMASK(20, 20)
#define DDR_PHY_DX7GSR2_DX7GSR2_SRDERR_X(x)      (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX7GSR2_DX7GSR2_RESERVED_21(x)   (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX7GSR2_DX7GSR2_RESERVED_21_M    GENMASK(21, 21)
#define DDR_PHY_DX7GSR2_DX7GSR2_RESERVED_21_X(x) (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX7GSR2_DX7GSR2_GSDQSCAL(x)      (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX7GSR2_DX7GSR2_GSDQSCAL_M       GENMASK(22, 22)
#define DDR_PHY_DX7GSR2_DX7GSR2_GSDQSCAL_X(x)    (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX7GSR2_DX7GSR2_GSDQSPRD(x)      (((x) << 23) & GENMASK(31, 23))
#define DDR_PHY_DX7GSR2_DX7GSR2_GSDQSPRD_M       GENMASK(31, 23)
#define DDR_PHY_DX7GSR2_DX7GSR2_GSDQSPRD_X(x)    (((x) & GENMASK(31, 23)) >> 23)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7GSR3 */
#define DDR_PHY_DX7GSR3(t)        (t + 0xeec)

#define DDR_PHY_DX7GSR3_DX7GSR3_SRDPC(x)         ((x) & GENMASK(1, 0))
#define DDR_PHY_DX7GSR3_DX7GSR3_SRDPC_M          GENMASK(1, 0)
#define DDR_PHY_DX7GSR3_DX7GSR3_SRDPC_X(x)       ((x) & GENMASK(1, 0))

#define DDR_PHY_DX7GSR3_DX7GSR3_RESERVED_7_2(x)  (((x) << 2) & GENMASK(7, 2))
#define DDR_PHY_DX7GSR3_DX7GSR3_RESERVED_7_2_M   GENMASK(7, 2)
#define DDR_PHY_DX7GSR3_DX7GSR3_RESERVED_7_2_X(x) (((x) & GENMASK(7, 2)) >> 2)

#define DDR_PHY_DX7GSR3_DX7GSR3_HVERR(x)         (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX7GSR3_DX7GSR3_HVERR_M          GENMASK(11, 8)
#define DDR_PHY_DX7GSR3_DX7GSR3_HVERR_X(x)       (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX7GSR3_DX7GSR3_HVWRN(x)         (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_DX7GSR3_DX7GSR3_HVWRN_M          GENMASK(15, 12)
#define DDR_PHY_DX7GSR3_DX7GSR3_HVWRN_X(x)       (((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_DX7GSR3_DX7GSR3_DVERR(x)         (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DX7GSR3_DX7GSR3_DVERR_M          GENMASK(19, 16)
#define DDR_PHY_DX7GSR3_DX7GSR3_DVERR_X(x)       (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DX7GSR3_DX7GSR3_DVWRN(x)         (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX7GSR3_DX7GSR3_DVWRN_M          GENMASK(23, 20)
#define DDR_PHY_DX7GSR3_DX7GSR3_DVWRN_X(x)       (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX7GSR3_DX7GSR3_ESTAT(x)         (((x) << 24) & GENMASK(26, 24))
#define DDR_PHY_DX7GSR3_DX7GSR3_ESTAT_M          GENMASK(26, 24)
#define DDR_PHY_DX7GSR3_DX7GSR3_ESTAT_X(x)       (((x) & GENMASK(26, 24)) >> 24)

#define DDR_PHY_DX7GSR3_DX7GSR3_RESERVED_31_27(x)\
	(((x) << 27) & GENMASK(31, 27))
#define DDR_PHY_DX7GSR3_DX7GSR3_RESERVED_31_27_M GENMASK(31, 27)
#define DDR_PHY_DX7GSR3_DX7GSR3_RESERVED_31_27_X(x)\
	(((x) & GENMASK(31, 27)) >> 27)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7GSR4 */
#define DDR_PHY_DX7GSR4(t)        (t + 0xef0)

#define DDR_PHY_DX7GSR4_DX7GSR4_X4WDQCAL(x)      ((x) & GENMASK(0, 0))
#define DDR_PHY_DX7GSR4_DX7GSR4_X4WDQCAL_M       GENMASK(0, 0)
#define DDR_PHY_DX7GSR4_DX7GSR4_X4WDQCAL_X(x)    ((x) & GENMASK(0, 0))

#define DDR_PHY_DX7GSR4_DX7GSR4_X4RDQSCAL(x)     (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX7GSR4_DX7GSR4_X4RDQSCAL_M      GENMASK(1, 1)
#define DDR_PHY_DX7GSR4_DX7GSR4_X4RDQSCAL_X(x)   (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX7GSR4_DX7GSR4_X4RDQSNCAL(x)    (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX7GSR4_DX7GSR4_X4RDQSNCAL_M     GENMASK(2, 2)
#define DDR_PHY_DX7GSR4_DX7GSR4_X4RDQSNCAL_X(x)  (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX7GSR4_DX7GSR4_X4GDQSCAL(x)     (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX7GSR4_DX7GSR4_X4GDQSCAL_M      GENMASK(3, 3)
#define DDR_PHY_DX7GSR4_DX7GSR4_X4GDQSCAL_X(x)   (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX7GSR4_DX7GSR4_X4WLCAL(x)       (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX7GSR4_DX7GSR4_X4WLCAL_M        GENMASK(4, 4)
#define DDR_PHY_DX7GSR4_DX7GSR4_X4WLCAL_X(x)     (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX7GSR4_DX7GSR4_X4WLDONE(x)      (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX7GSR4_DX7GSR4_X4WLDONE_M       GENMASK(5, 5)
#define DDR_PHY_DX7GSR4_DX7GSR4_X4WLDONE_X(x)    (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX7GSR4_DX7GSR4_X4WLERR(x)       (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX7GSR4_DX7GSR4_X4WLERR_M        GENMASK(6, 6)
#define DDR_PHY_DX7GSR4_DX7GSR4_X4WLERR_X(x)     (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX7GSR4_DX7GSR4_X4WLPRD(x)       (((x) << 7) & GENMASK(15, 7))
#define DDR_PHY_DX7GSR4_DX7GSR4_X4WLPRD_M        GENMASK(15, 7)
#define DDR_PHY_DX7GSR4_DX7GSR4_X4WLPRD_X(x)     (((x) & GENMASK(15, 7)) >> 7)

#define DDR_PHY_DX7GSR4_DX7GSR4_X4DPLOCK(x)      (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX7GSR4_DX7GSR4_X4DPLOCK_M       GENMASK(16, 16)
#define DDR_PHY_DX7GSR4_DX7GSR4_X4DPLOCK_X(x)    (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX7GSR4_DX7GSR4_X4GDQSPRD(x)     (((x) << 17) & GENMASK(25, 17))
#define DDR_PHY_DX7GSR4_DX7GSR4_X4GDQSPRD_M      GENMASK(25, 17)
#define DDR_PHY_DX7GSR4_DX7GSR4_X4GDQSPRD_X(x)   (((x) & GENMASK(25, 17)) >> 17)

#define DDR_PHY_DX7GSR4_DX7GSR4_X4WLWN(x)        (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_DX7GSR4_DX7GSR4_X4WLWN_M         GENMASK(26, 26)
#define DDR_PHY_DX7GSR4_DX7GSR4_X4WLWN_X(x)      (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_DX7GSR4_DX7GSR4_RESERVED_29_27(x)\
	(((x) << 27) & GENMASK(29, 27))
#define DDR_PHY_DX7GSR4_DX7GSR4_RESERVED_29_27_M GENMASK(29, 27)
#define DDR_PHY_DX7GSR4_DX7GSR4_RESERVED_29_27_X(x)\
	(((x) & GENMASK(29, 27)) >> 27)

#define DDR_PHY_DX7GSR4_DX7GSR4_X4WLDQ(x)        (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX7GSR4_DX7GSR4_X4WLDQ_M         GENMASK(30, 30)
#define DDR_PHY_DX7GSR4_DX7GSR4_X4WLDQ_X(x)      (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX7GSR4_DX7GSR4_RESERVED_31(x)   (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX7GSR4_DX7GSR4_RESERVED_31_M    GENMASK(31, 31)
#define DDR_PHY_DX7GSR4_DX7GSR4_RESERVED_31_X(x) (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7GSR5 */
#define DDR_PHY_DX7GSR5(t)        (t + 0xef4)

#define DDR_PHY_DX7GSR5_DX7GSR5_X4RDERR(x)       ((x) & GENMASK(0, 0))
#define DDR_PHY_DX7GSR5_DX7GSR5_X4RDERR_M        GENMASK(0, 0)
#define DDR_PHY_DX7GSR5_DX7GSR5_X4RDERR_X(x)     ((x) & GENMASK(0, 0))

#define DDR_PHY_DX7GSR5_DX7GSR5_X4RDWN(x)        (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX7GSR5_DX7GSR5_X4RDWN_M         GENMASK(1, 1)
#define DDR_PHY_DX7GSR5_DX7GSR5_X4RDWN_X(x)      (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX7GSR5_DX7GSR5_X4WDERR(x)       (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX7GSR5_DX7GSR5_X4WDERR_M        GENMASK(2, 2)
#define DDR_PHY_DX7GSR5_DX7GSR5_X4WDERR_X(x)     (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX7GSR5_DX7GSR5_X4WDWN(x)        (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX7GSR5_DX7GSR5_X4WDWN_M         GENMASK(3, 3)
#define DDR_PHY_DX7GSR5_DX7GSR5_X4WDWN_X(x)      (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX7GSR5_DX7GSR5_X4REERR(x)       (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX7GSR5_DX7GSR5_X4REERR_M        GENMASK(4, 4)
#define DDR_PHY_DX7GSR5_DX7GSR5_X4REERR_X(x)     (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX7GSR5_DX7GSR5_X4REWN(x)        (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX7GSR5_DX7GSR5_X4REWN_M         GENMASK(5, 5)
#define DDR_PHY_DX7GSR5_DX7GSR5_X4REWN_X(x)      (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX7GSR5_DX7GSR5_X4WEERR(x)       (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX7GSR5_DX7GSR5_X4WEERR_M        GENMASK(6, 6)
#define DDR_PHY_DX7GSR5_DX7GSR5_X4WEERR_X(x)     (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX7GSR5_DX7GSR5_X4WEWN(x)        (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_DX7GSR5_DX7GSR5_X4WEWN_M         GENMASK(7, 7)
#define DDR_PHY_DX7GSR5_DX7GSR5_X4WEWN_X(x)      (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_DX7GSR5_DX7GSR5_X4ESTAT(x)       (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX7GSR5_DX7GSR5_X4ESTAT_M        GENMASK(11, 8)
#define DDR_PHY_DX7GSR5_DX7GSR5_X4ESTAT_X(x)     (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX7GSR5_DX7GSR5_RESERVED_19_12(x)\
	(((x) << 12) & GENMASK(19, 12))
#define DDR_PHY_DX7GSR5_DX7GSR5_RESERVED_19_12_M GENMASK(19, 12)
#define DDR_PHY_DX7GSR5_DX7GSR5_RESERVED_19_12_X(x)\
	(((x) & GENMASK(19, 12)) >> 12)

#define DDR_PHY_DX7GSR5_DX7GSR5_X4SRDERR(x)      (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX7GSR5_DX7GSR5_X4SRDERR_M       GENMASK(20, 20)
#define DDR_PHY_DX7GSR5_DX7GSR5_X4SRDERR_X(x)    (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX7GSR5_DX7GSR5_RESERVED_21(x)   (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX7GSR5_DX7GSR5_RESERVED_21_M    GENMASK(21, 21)
#define DDR_PHY_DX7GSR5_DX7GSR5_RESERVED_21_X(x) (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX7GSR5_DX7GSR5_X4GSDQSCAL(x)    (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX7GSR5_DX7GSR5_X4GSDQSCAL_M     GENMASK(22, 22)
#define DDR_PHY_DX7GSR5_DX7GSR5_X4GSDQSCAL_X(x)  (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX7GSR5_DX7GSR5_X4GSDQSPRD(x)    (((x) << 23) & GENMASK(31, 23))
#define DDR_PHY_DX7GSR5_DX7GSR5_X4GSDQSPRD_M     GENMASK(31, 23)
#define DDR_PHY_DX7GSR5_DX7GSR5_X4GSDQSPRD_X(x)  (((x) & GENMASK(31, 23)) >> 23)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX7GSR6 */
#define DDR_PHY_DX7GSR6(t)        (t + 0xef8)

#define DDR_PHY_DX7GSR6_DX7GSR6_RESERVED_1_0(x)  ((x) & GENMASK(1, 0))
#define DDR_PHY_DX7GSR6_DX7GSR6_RESERVED_1_0_M   GENMASK(1, 0)
#define DDR_PHY_DX7GSR6_DX7GSR6_RESERVED_1_0_X(x) ((x) & GENMASK(1, 0))

#define DDR_PHY_DX7GSR6_DX7GSR6_X4SRDPC(x)       (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DX7GSR6_DX7GSR6_X4SRDPC_M        GENMASK(3, 2)
#define DDR_PHY_DX7GSR6_DX7GSR6_X4SRDPC_X(x)     (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DX7GSR6_DX7GSR6_RESERVED_7_4(x)  (((x) << 4) & GENMASK(7, 4))
#define DDR_PHY_DX7GSR6_DX7GSR6_RESERVED_7_4_M   GENMASK(7, 4)
#define DDR_PHY_DX7GSR6_DX7GSR6_RESERVED_7_4_X(x) (((x) & GENMASK(7, 4)) >> 4)

#define DDR_PHY_DX7GSR6_DX7GSR6_X4HVERR(x)       (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX7GSR6_DX7GSR6_X4HVERR_M        GENMASK(11, 8)
#define DDR_PHY_DX7GSR6_DX7GSR6_X4HVERR_X(x)     (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX7GSR6_DX7GSR6_X4HVWRN(x)       (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_DX7GSR6_DX7GSR6_X4HVWRN_M        GENMASK(15, 12)
#define DDR_PHY_DX7GSR6_DX7GSR6_X4HVWRN_X(x)     (((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_DX7GSR6_DX7GSR6_X4DVERR(x)       (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DX7GSR6_DX7GSR6_X4DVERR_M        GENMASK(19, 16)
#define DDR_PHY_DX7GSR6_DX7GSR6_X4DVERR_X(x)     (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DX7GSR6_DX7GSR6_X4DVWRN(x)       (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX7GSR6_DX7GSR6_X4DVWRN_M        GENMASK(23, 20)
#define DDR_PHY_DX7GSR6_DX7GSR6_X4DVWRN_X(x)     (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX7GSR6_DX7GSR6_RESERVED_31_24(x)\
	(((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_DX7GSR6_DX7GSR6_RESERVED_31_24_M GENMASK(31, 24)
#define DDR_PHY_DX7GSR6_DX7GSR6_RESERVED_31_24_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8GCR0 */
#define DDR_PHY_DX8GCR0(t)        (t + 0xf00)

#define DDR_PHY_DX8GCR0_DX8GCR0_DXEN(x)          ((x) & GENMASK(0, 0))
#define DDR_PHY_DX8GCR0_DX8GCR0_DXEN_M           GENMASK(0, 0)
#define DDR_PHY_DX8GCR0_DX8GCR0_DXEN_X(x)        ((x) & GENMASK(0, 0))

#define DDR_PHY_DX8GCR0_DX8GCR0_DXIOM(x)         (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX8GCR0_DX8GCR0_DXIOM_M          GENMASK(1, 1)
#define DDR_PHY_DX8GCR0_DX8GCR0_DXIOM_X(x)       (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX8GCR0_DX8GCR0_DQSGOE(x)        (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX8GCR0_DX8GCR0_DQSGOE_M         GENMASK(2, 2)
#define DDR_PHY_DX8GCR0_DX8GCR0_DQSGOE_X(x)      (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX8GCR0_DX8GCR0_DQSGODT(x)       (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX8GCR0_DX8GCR0_DQSGODT_M        GENMASK(3, 3)
#define DDR_PHY_DX8GCR0_DX8GCR0_DQSGODT_X(x)     (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX8GCR0_DX8GCR0_RESERVED_4(x)    (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX8GCR0_DX8GCR0_RESERVED_4_M     GENMASK(4, 4)
#define DDR_PHY_DX8GCR0_DX8GCR0_RESERVED_4_X(x)  (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX8GCR0_DX8GCR0_DQSGPDR(x)       (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX8GCR0_DX8GCR0_DQSGPDR_M        GENMASK(5, 5)
#define DDR_PHY_DX8GCR0_DX8GCR0_DQSGPDR_X(x)     (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX8GCR0_DX8GCR0_RESERVED_6(x)    (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX8GCR0_DX8GCR0_RESERVED_6_M     GENMASK(6, 6)
#define DDR_PHY_DX8GCR0_DX8GCR0_RESERVED_6_X(x)  (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX8GCR0_DX8GCR0_PDRAL(x)         (((x) << 7) & GENMASK(8, 7))
#define DDR_PHY_DX8GCR0_DX8GCR0_PDRAL_M          GENMASK(8, 7)
#define DDR_PHY_DX8GCR0_DX8GCR0_PDRAL_X(x)       (((x) & GENMASK(8, 7)) >> 7)

#define DDR_PHY_DX8GCR0_DX8GCR0_RTTOH(x)         (((x) << 9) & GENMASK(10, 9))
#define DDR_PHY_DX8GCR0_DX8GCR0_RTTOH_M          GENMASK(10, 9)
#define DDR_PHY_DX8GCR0_DX8GCR0_RTTOH_X(x)       (((x) & GENMASK(10, 9)) >> 9)

#define DDR_PHY_DX8GCR0_DX8GCR0_RTTOAL(x)        (((x) << 11) & GENMASK(11, 11))
#define DDR_PHY_DX8GCR0_DX8GCR0_RTTOAL_M         GENMASK(11, 11)
#define DDR_PHY_DX8GCR0_DX8GCR0_RTTOAL_X(x)      (((x) & GENMASK(11, 11)) >> 11)

#define DDR_PHY_DX8GCR0_DX8GCR0_DQSSEPDR(x)      (((x) << 12) & GENMASK(12, 12))
#define DDR_PHY_DX8GCR0_DX8GCR0_DQSSEPDR_M       GENMASK(12, 12)
#define DDR_PHY_DX8GCR0_DX8GCR0_DQSSEPDR_X(x)    (((x) & GENMASK(12, 12)) >> 12)

#define DDR_PHY_DX8GCR0_DX8GCR0_DQSNSEPDR(x)     (((x) << 13) & GENMASK(13, 13))
#define DDR_PHY_DX8GCR0_DX8GCR0_DQSNSEPDR_M      GENMASK(13, 13)
#define DDR_PHY_DX8GCR0_DX8GCR0_DQSNSEPDR_X(x)   (((x) & GENMASK(13, 13)) >> 13)

#define DDR_PHY_DX8GCR0_DX8GCR0_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX8GCR0_DX8GCR0_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX8GCR0_DX8GCR0_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX8GCR0_DX8GCR0_PLLRST(x)        (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX8GCR0_DX8GCR0_PLLRST_M         GENMASK(16, 16)
#define DDR_PHY_DX8GCR0_DX8GCR0_PLLRST_X(x)      (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX8GCR0_DX8GCR0_PLLPD(x)         (((x) << 17) & GENMASK(17, 17))
#define DDR_PHY_DX8GCR0_DX8GCR0_PLLPD_M          GENMASK(17, 17)
#define DDR_PHY_DX8GCR0_DX8GCR0_PLLPD_X(x)       (((x) & GENMASK(17, 17)) >> 17)

#define DDR_PHY_DX8GCR0_DX8GCR0_GSHIFT(x)        (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_DX8GCR0_DX8GCR0_GSHIFT_M         GENMASK(18, 18)
#define DDR_PHY_DX8GCR0_DX8GCR0_GSHIFT_X(x)      (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_DX8GCR0_DX8GCR0_PLLBYP(x)        (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_DX8GCR0_DX8GCR0_PLLBYP_M         GENMASK(19, 19)
#define DDR_PHY_DX8GCR0_DX8GCR0_PLLBYP_X(x)      (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_DX8GCR0_DX8GCR0_RDDLY(x)         (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX8GCR0_DX8GCR0_RDDLY_M          GENMASK(23, 20)
#define DDR_PHY_DX8GCR0_DX8GCR0_RDDLY_X(x)       (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX8GCR0_DX8GCR0_RESERVED_29_24(x)\
	(((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX8GCR0_DX8GCR0_RESERVED_29_24_M GENMASK(29, 24)
#define DDR_PHY_DX8GCR0_DX8GCR0_RESERVED_29_24_X(x)\
	(((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX8GCR0_DX8GCR0_MDLEN(x)         (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX8GCR0_DX8GCR0_MDLEN_M          GENMASK(30, 30)
#define DDR_PHY_DX8GCR0_DX8GCR0_MDLEN_X(x)       (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX8GCR0_DX8GCR0_CALBYP(x)        (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX8GCR0_DX8GCR0_CALBYP_M         GENMASK(31, 31)
#define DDR_PHY_DX8GCR0_DX8GCR0_CALBYP_X(x)      (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8GCR1 */
#define DDR_PHY_DX8GCR1(t)        (t + 0xf04)

#define DDR_PHY_DX8GCR1_DX8GCR1_RESERVED_15_0(x) ((x) & GENMASK(15, 0))
#define DDR_PHY_DX8GCR1_DX8GCR1_RESERVED_15_0_M  GENMASK(15, 0)
#define DDR_PHY_DX8GCR1_DX8GCR1_RESERVED_15_0_X(x) ((x) & GENMASK(15, 0))

#define DDR_PHY_DX8GCR1_DX8GCR1_DXPDRMODE(x)     (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX8GCR1_DX8GCR1_DXPDRMODE_M      GENMASK(31, 16)
#define DDR_PHY_DX8GCR1_DX8GCR1_DXPDRMODE_X(x)   (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8GCR2 */
#define DDR_PHY_DX8GCR2(t)        (t + 0xf08)

#define DDR_PHY_DX8GCR2_DX8GCR2_DXTEMODE(x)      ((x) & GENMASK(15, 0))
#define DDR_PHY_DX8GCR2_DX8GCR2_DXTEMODE_M       GENMASK(15, 0)
#define DDR_PHY_DX8GCR2_DX8GCR2_DXTEMODE_X(x)    ((x) & GENMASK(15, 0))

#define DDR_PHY_DX8GCR2_DX8GCR2_DXOEMODE(x)      (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX8GCR2_DX8GCR2_DXOEMODE_M       GENMASK(31, 16)
#define DDR_PHY_DX8GCR2_DX8GCR2_DXOEMODE_X(x)    (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8GCR3 */
#define DDR_PHY_DX8GCR3(t)        (t + 0xf0c)

#define DDR_PHY_DX8GCR3_DX8GCR3_RESERVED_1_0(x)  ((x) & GENMASK(1, 0))
#define DDR_PHY_DX8GCR3_DX8GCR3_RESERVED_1_0_M   GENMASK(1, 0)
#define DDR_PHY_DX8GCR3_DX8GCR3_RESERVED_1_0_X(x) ((x) & GENMASK(1, 0))

#define DDR_PHY_DX8GCR3_DX8GCR3_DSPDRMODE(x)     (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DX8GCR3_DX8GCR3_DSPDRMODE_M      GENMASK(3, 2)
#define DDR_PHY_DX8GCR3_DX8GCR3_DSPDRMODE_X(x)   (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DX8GCR3_DX8GCR3_DSTEMODE(x)      (((x) << 4) & GENMASK(5, 4))
#define DDR_PHY_DX8GCR3_DX8GCR3_DSTEMODE_M       GENMASK(5, 4)
#define DDR_PHY_DX8GCR3_DX8GCR3_DSTEMODE_X(x)    (((x) & GENMASK(5, 4)) >> 4)

#define DDR_PHY_DX8GCR3_DX8GCR3_DSOEMODE(x)      (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX8GCR3_DX8GCR3_DSOEMODE_M       GENMASK(7, 6)
#define DDR_PHY_DX8GCR3_DX8GCR3_DSOEMODE_X(x)    (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX8GCR3_DX8GCR3_RESERVED_9_8(x)  (((x) << 8) & GENMASK(9, 8))
#define DDR_PHY_DX8GCR3_DX8GCR3_RESERVED_9_8_M   GENMASK(9, 8)
#define DDR_PHY_DX8GCR3_DX8GCR3_RESERVED_9_8_X(x) (((x) & GENMASK(9, 8)) >> 8)

#define DDR_PHY_DX8GCR3_DX8GCR3_DMPDRMODE(x)     (((x) << 10) & GENMASK(11, 10))
#define DDR_PHY_DX8GCR3_DX8GCR3_DMPDRMODE_M      GENMASK(11, 10)
#define DDR_PHY_DX8GCR3_DX8GCR3_DMPDRMODE_X(x)   (((x) & GENMASK(11, 10)) >> 10)

#define DDR_PHY_DX8GCR3_DX8GCR3_DMTEMODE(x)      (((x) << 12) & GENMASK(13, 12))
#define DDR_PHY_DX8GCR3_DX8GCR3_DMTEMODE_M       GENMASK(13, 12)
#define DDR_PHY_DX8GCR3_DX8GCR3_DMTEMODE_X(x)    (((x) & GENMASK(13, 12)) >> 12)

#define DDR_PHY_DX8GCR3_DX8GCR3_DMOEMODE(x)      (((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX8GCR3_DX8GCR3_DMOEMODE_M       GENMASK(15, 14)
#define DDR_PHY_DX8GCR3_DX8GCR3_DMOEMODE_X(x)    (((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX8GCR3_DX8GCR3_RESERVED_17_16(x)\
	(((x) << 16) & GENMASK(17, 16))
#define DDR_PHY_DX8GCR3_DX8GCR3_RESERVED_17_16_M GENMASK(17, 16)
#define DDR_PHY_DX8GCR3_DX8GCR3_RESERVED_17_16_X(x)\
	(((x) & GENMASK(17, 16)) >> 16)

#define DDR_PHY_DX8GCR3_DX8GCR3_OEBVT(x)         (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_DX8GCR3_DX8GCR3_OEBVT_M          GENMASK(18, 18)
#define DDR_PHY_DX8GCR3_DX8GCR3_OEBVT_X(x)       (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_DX8GCR3_DX8GCR3_PDRBVT(x)        (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_DX8GCR3_DX8GCR3_PDRBVT_M         GENMASK(19, 19)
#define DDR_PHY_DX8GCR3_DX8GCR3_PDRBVT_X(x)      (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_DX8GCR3_DX8GCR3_TEBVT(x)         (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX8GCR3_DX8GCR3_TEBVT_M          GENMASK(20, 20)
#define DDR_PHY_DX8GCR3_DX8GCR3_TEBVT_X(x)       (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX8GCR3_DX8GCR3_WDSBVT(x)        (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX8GCR3_DX8GCR3_WDSBVT_M         GENMASK(21, 21)
#define DDR_PHY_DX8GCR3_DX8GCR3_WDSBVT_X(x)      (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX8GCR3_DX8GCR3_RDSBVT(x)        (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX8GCR3_DX8GCR3_RDSBVT_M         GENMASK(22, 22)
#define DDR_PHY_DX8GCR3_DX8GCR3_RDSBVT_X(x)      (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX8GCR3_DX8GCR3_RGSLVT(x)        (((x) << 23) & GENMASK(23, 23))
#define DDR_PHY_DX8GCR3_DX8GCR3_RGSLVT_M         GENMASK(23, 23)
#define DDR_PHY_DX8GCR3_DX8GCR3_RGSLVT_X(x)      (((x) & GENMASK(23, 23)) >> 23)

#define DDR_PHY_DX8GCR3_DX8GCR3_WLLVT(x)         (((x) << 24) & GENMASK(24, 24))
#define DDR_PHY_DX8GCR3_DX8GCR3_WLLVT_M          GENMASK(24, 24)
#define DDR_PHY_DX8GCR3_DX8GCR3_WLLVT_X(x)       (((x) & GENMASK(24, 24)) >> 24)

#define DDR_PHY_DX8GCR3_DX8GCR3_WDLVT(x)         (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_DX8GCR3_DX8GCR3_WDLVT_M          GENMASK(25, 25)
#define DDR_PHY_DX8GCR3_DX8GCR3_WDLVT_X(x)       (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_DX8GCR3_DX8GCR3_RDLVT(x)         (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_DX8GCR3_DX8GCR3_RDLVT_M          GENMASK(26, 26)
#define DDR_PHY_DX8GCR3_DX8GCR3_RDLVT_X(x)       (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_DX8GCR3_DX8GCR3_RGLVT(x)         (((x) << 27) & GENMASK(27, 27))
#define DDR_PHY_DX8GCR3_DX8GCR3_RGLVT_M          GENMASK(27, 27)
#define DDR_PHY_DX8GCR3_DX8GCR3_RGLVT_X(x)       (((x) & GENMASK(27, 27)) >> 27)

#define DDR_PHY_DX8GCR3_DX8GCR3_WDBVT(x)         (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_DX8GCR3_DX8GCR3_WDBVT_M          GENMASK(28, 28)
#define DDR_PHY_DX8GCR3_DX8GCR3_WDBVT_X(x)       (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_DX8GCR3_DX8GCR3_RDBVT(x)         (((x) << 29) & GENMASK(29, 29))
#define DDR_PHY_DX8GCR3_DX8GCR3_RDBVT_M          GENMASK(29, 29)
#define DDR_PHY_DX8GCR3_DX8GCR3_RDBVT_X(x)       (((x) & GENMASK(29, 29)) >> 29)

#define DDR_PHY_DX8GCR3_DX8GCR3_WDMBVT(x)        (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX8GCR3_DX8GCR3_WDMBVT_M         GENMASK(30, 30)
#define DDR_PHY_DX8GCR3_DX8GCR3_WDMBVT_X(x)      (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX8GCR3_DX8GCR3_RDMBVT(x)        (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX8GCR3_DX8GCR3_RDMBVT_M         GENMASK(31, 31)
#define DDR_PHY_DX8GCR3_DX8GCR3_RDMBVT_X(x)      (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8GCR4 */
#define DDR_PHY_DX8GCR4(t)        (t + 0xf10)

#define DDR_PHY_DX8GCR4_DX8GCR4_DXREFIMON(x)     ((x) & GENMASK(1, 0))
#define DDR_PHY_DX8GCR4_DX8GCR4_DXREFIMON_M      GENMASK(1, 0)
#define DDR_PHY_DX8GCR4_DX8GCR4_DXREFIMON_X(x)   ((x) & GENMASK(1, 0))

#define DDR_PHY_DX8GCR4_DX8GCR4_DXREFIEN(x)      (((x) << 2) & GENMASK(5, 2))
#define DDR_PHY_DX8GCR4_DX8GCR4_DXREFIEN_M       GENMASK(5, 2)
#define DDR_PHY_DX8GCR4_DX8GCR4_DXREFIEN_X(x)    (((x) & GENMASK(5, 2)) >> 2)

#define DDR_PHY_DX8GCR4_DX8GCR4_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX8GCR4_DX8GCR4_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX8GCR4_DX8GCR4_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX8GCR4_DX8GCR4_DXREFSSEL(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX8GCR4_DX8GCR4_DXREFSSEL_M      GENMASK(13, 8)
#define DDR_PHY_DX8GCR4_DX8GCR4_DXREFSSEL_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX8GCR4_DX8GCR4_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX8GCR4_DX8GCR4_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX8GCR4_DX8GCR4_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX8GCR4_DX8GCR4_DXREFESEL(x)     (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX8GCR4_DX8GCR4_DXREFESEL_M      GENMASK(21, 16)
#define DDR_PHY_DX8GCR4_DX8GCR4_DXREFESEL_X(x)   (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX8GCR4_DX8GCR4_RESERVED_24_22(x)\
	(((x) << 22) & GENMASK(24, 22))
#define DDR_PHY_DX8GCR4_DX8GCR4_RESERVED_24_22_M GENMASK(24, 22)
#define DDR_PHY_DX8GCR4_DX8GCR4_RESERVED_24_22_X(x)\
	(((x) & GENMASK(24, 22)) >> 22)

#define DDR_PHY_DX8GCR4_DX8GCR4_DXREFSEN(x)      (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_DX8GCR4_DX8GCR4_DXREFSEN_M       GENMASK(25, 25)
#define DDR_PHY_DX8GCR4_DX8GCR4_DXREFSEN_X(x)    (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_DX8GCR4_DX8GCR4_DXREFEEN(x)      (((x) << 26) & GENMASK(27, 26))
#define DDR_PHY_DX8GCR4_DX8GCR4_DXREFEEN_M       GENMASK(27, 26)
#define DDR_PHY_DX8GCR4_DX8GCR4_DXREFEEN_X(x)    (((x) & GENMASK(27, 26)) >> 26)

#define DDR_PHY_DX8GCR4_DX8GCR4_DXREFPEN(x)      (((x) << 28) & GENMASK(28, 28))
#define DDR_PHY_DX8GCR4_DX8GCR4_DXREFPEN_M       GENMASK(28, 28)
#define DDR_PHY_DX8GCR4_DX8GCR4_DXREFPEN_X(x)    (((x) & GENMASK(28, 28)) >> 28)

#define DDR_PHY_DX8GCR4_DX8GCR4_DXREFIOM(x)      (((x) << 29) & GENMASK(31, 29))
#define DDR_PHY_DX8GCR4_DX8GCR4_DXREFIOM_M       GENMASK(31, 29)
#define DDR_PHY_DX8GCR4_DX8GCR4_DXREFIOM_X(x)    (((x) & GENMASK(31, 29)) >> 29)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8GCR5 */
#define DDR_PHY_DX8GCR5(t)        (t + 0xf14)

#define DDR_PHY_DX8GCR5_DX8GCR5_DXREFISELR0(x)   ((x) & GENMASK(5, 0))
#define DDR_PHY_DX8GCR5_DX8GCR5_DXREFISELR0_M    GENMASK(5, 0)
#define DDR_PHY_DX8GCR5_DX8GCR5_DXREFISELR0_X(x) ((x) & GENMASK(5, 0))

#define DDR_PHY_DX8GCR5_DX8GCR5_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX8GCR5_DX8GCR5_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX8GCR5_DX8GCR5_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX8GCR5_DX8GCR5_DXREFISELR1(x)   (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX8GCR5_DX8GCR5_DXREFISELR1_M    GENMASK(13, 8)
#define DDR_PHY_DX8GCR5_DX8GCR5_DXREFISELR1_X(x) (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX8GCR5_DX8GCR5_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX8GCR5_DX8GCR5_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX8GCR5_DX8GCR5_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX8GCR5_DX8GCR5_DXREFISELR2(x)   (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX8GCR5_DX8GCR5_DXREFISELR2_M    GENMASK(21, 16)
#define DDR_PHY_DX8GCR5_DX8GCR5_DXREFISELR2_X(x) (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX8GCR5_DX8GCR5_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX8GCR5_DX8GCR5_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX8GCR5_DX8GCR5_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX8GCR5_DX8GCR5_DXREFISELR3(x)   (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX8GCR5_DX8GCR5_DXREFISELR3_M    GENMASK(29, 24)
#define DDR_PHY_DX8GCR5_DX8GCR5_DXREFISELR3_X(x) (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX8GCR5_DX8GCR5_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX8GCR5_DX8GCR5_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX8GCR5_DX8GCR5_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8GCR6 */
#define DDR_PHY_DX8GCR6(t)        (t + 0xf18)

#define DDR_PHY_DX8GCR6_DX8GCR6_DXDQVREFR0(x)    ((x) & GENMASK(5, 0))
#define DDR_PHY_DX8GCR6_DX8GCR6_DXDQVREFR0_M     GENMASK(5, 0)
#define DDR_PHY_DX8GCR6_DX8GCR6_DXDQVREFR0_X(x)  ((x) & GENMASK(5, 0))

#define DDR_PHY_DX8GCR6_DX8GCR6_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX8GCR6_DX8GCR6_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX8GCR6_DX8GCR6_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX8GCR6_DX8GCR6_DXDQVREFR1(x)    (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX8GCR6_DX8GCR6_DXDQVREFR1_M     GENMASK(13, 8)
#define DDR_PHY_DX8GCR6_DX8GCR6_DXDQVREFR1_X(x)  (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX8GCR6_DX8GCR6_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX8GCR6_DX8GCR6_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX8GCR6_DX8GCR6_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX8GCR6_DX8GCR6_DXDQVREFR2(x)    (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX8GCR6_DX8GCR6_DXDQVREFR2_M     GENMASK(21, 16)
#define DDR_PHY_DX8GCR6_DX8GCR6_DXDQVREFR2_X(x)  (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX8GCR6_DX8GCR6_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX8GCR6_DX8GCR6_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX8GCR6_DX8GCR6_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX8GCR6_DX8GCR6_DXDQVREFR3(x)    (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX8GCR6_DX8GCR6_DXDQVREFR3_M     GENMASK(29, 24)
#define DDR_PHY_DX8GCR6_DX8GCR6_DXDQVREFR3_X(x)  (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX8GCR6_DX8GCR6_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX8GCR6_DX8GCR6_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX8GCR6_DX8GCR6_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8GCR7 */
#define DDR_PHY_DX8GCR7(t)        (t + 0xf1c)

#define DDR_PHY_DX8GCR7_DX8GCR7_RESERVED_1_0(x)  ((x) & GENMASK(1, 0))
#define DDR_PHY_DX8GCR7_DX8GCR7_RESERVED_1_0_M   GENMASK(1, 0)
#define DDR_PHY_DX8GCR7_DX8GCR7_RESERVED_1_0_X(x) ((x) & GENMASK(1, 0))

#define DDR_PHY_DX8GCR7_DX8GCR7_X4DSPDRMODE(x)   (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DX8GCR7_DX8GCR7_X4DSPDRMODE_M    GENMASK(3, 2)
#define DDR_PHY_DX8GCR7_DX8GCR7_X4DSPDRMODE_X(x) (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DX8GCR7_DX8GCR7_X4DSTEMODE(x)    (((x) << 4) & GENMASK(5, 4))
#define DDR_PHY_DX8GCR7_DX8GCR7_X4DSTEMODE_M     GENMASK(5, 4)
#define DDR_PHY_DX8GCR7_DX8GCR7_X4DSTEMODE_X(x)  (((x) & GENMASK(5, 4)) >> 4)

#define DDR_PHY_DX8GCR7_DX8GCR7_X4DSOEMODE(x)    (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX8GCR7_DX8GCR7_X4DSOEMODE_M     GENMASK(7, 6)
#define DDR_PHY_DX8GCR7_DX8GCR7_X4DSOEMODE_X(x)  (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX8GCR7_DX8GCR7_RESERVED_9_8(x)  (((x) << 8) & GENMASK(9, 8))
#define DDR_PHY_DX8GCR7_DX8GCR7_RESERVED_9_8_M   GENMASK(9, 8)
#define DDR_PHY_DX8GCR7_DX8GCR7_RESERVED_9_8_X(x) (((x) & GENMASK(9, 8)) >> 8)

#define DDR_PHY_DX8GCR7_DX8GCR7_X4DXPDRMODE(x)   (((x) << 10) & GENMASK(11, 10))
#define DDR_PHY_DX8GCR7_DX8GCR7_X4DXPDRMODE_M    GENMASK(11, 10)
#define DDR_PHY_DX8GCR7_DX8GCR7_X4DXPDRMODE_X(x) (((x) & GENMASK(11, 10)) >> 10)

#define DDR_PHY_DX8GCR7_DX8GCR7_X4DXTEMODE(x)    (((x) << 12) & GENMASK(13, 12))
#define DDR_PHY_DX8GCR7_DX8GCR7_X4DXTEMODE_M     GENMASK(13, 12)
#define DDR_PHY_DX8GCR7_DX8GCR7_X4DXTEMODE_X(x)  (((x) & GENMASK(13, 12)) >> 12)

#define DDR_PHY_DX8GCR7_DX8GCR7_X4DXOEMODE(x)    (((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX8GCR7_DX8GCR7_X4DXOEMODE_M     GENMASK(15, 14)
#define DDR_PHY_DX8GCR7_DX8GCR7_X4DXOEMODE_X(x)  (((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX8GCR7_DX8GCR7_X4DQSGOE(x)      (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX8GCR7_DX8GCR7_X4DQSGOE_M       GENMASK(16, 16)
#define DDR_PHY_DX8GCR7_DX8GCR7_X4DQSGOE_X(x)    (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX8GCR7_DX8GCR7_X4DQSGODT(x)     (((x) << 17) & GENMASK(17, 17))
#define DDR_PHY_DX8GCR7_DX8GCR7_X4DQSGODT_M      GENMASK(17, 17)
#define DDR_PHY_DX8GCR7_DX8GCR7_X4DQSGODT_X(x)   (((x) & GENMASK(17, 17)) >> 17)

#define DDR_PHY_DX8GCR7_DX8GCR7_RESERVED_18(x)   (((x) << 18) & GENMASK(18, 18))
#define DDR_PHY_DX8GCR7_DX8GCR7_RESERVED_18_M    GENMASK(18, 18)
#define DDR_PHY_DX8GCR7_DX8GCR7_RESERVED_18_X(x) (((x) & GENMASK(18, 18)) >> 18)

#define DDR_PHY_DX8GCR7_DX8GCR7_X4DQSGPDR(x)     (((x) << 19) & GENMASK(19, 19))
#define DDR_PHY_DX8GCR7_DX8GCR7_X4DQSGPDR_M      GENMASK(19, 19)
#define DDR_PHY_DX8GCR7_DX8GCR7_X4DQSGPDR_X(x)   (((x) & GENMASK(19, 19)) >> 19)

#define DDR_PHY_DX8GCR7_DX8GCR7_RESERVED_20(x)   (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX8GCR7_DX8GCR7_RESERVED_20_M    GENMASK(20, 20)
#define DDR_PHY_DX8GCR7_DX8GCR7_RESERVED_20_X(x) (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX8GCR7_DX8GCR7_X4DQSSEPDR(x)    (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX8GCR7_DX8GCR7_X4DQSSEPDR_M     GENMASK(21, 21)
#define DDR_PHY_DX8GCR7_DX8GCR7_X4DQSSEPDR_X(x)  (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX8GCR7_DX8GCR7_X4DQSNSEPDR(x)   (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX8GCR7_DX8GCR7_X4DQSNSEPDR_M    GENMASK(22, 22)
#define DDR_PHY_DX8GCR7_DX8GCR7_X4DQSNSEPDR_X(x) (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX8GCR7_DX8GCR7_X4RTTOH(x)       (((x) << 23) & GENMASK(24, 23))
#define DDR_PHY_DX8GCR7_DX8GCR7_X4RTTOH_M        GENMASK(24, 23)
#define DDR_PHY_DX8GCR7_DX8GCR7_X4RTTOH_X(x)     (((x) & GENMASK(24, 23)) >> 23)

#define DDR_PHY_DX8GCR7_DX8GCR7_X4RTTOAL(x)      (((x) << 25) & GENMASK(25, 25))
#define DDR_PHY_DX8GCR7_DX8GCR7_X4RTTOAL_M       GENMASK(25, 25)
#define DDR_PHY_DX8GCR7_DX8GCR7_X4RTTOAL_X(x)    (((x) & GENMASK(25, 25)) >> 25)

#define DDR_PHY_DX8GCR7_DX8GCR7_X4RDDLY(x)       (((x) << 26) & GENMASK(29, 26))
#define DDR_PHY_DX8GCR7_DX8GCR7_X4RDDLY_M        GENMASK(29, 26)
#define DDR_PHY_DX8GCR7_DX8GCR7_X4RDDLY_X(x)     (((x) & GENMASK(29, 26)) >> 26)

#define DDR_PHY_DX8GCR7_DX8GCR7_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX8GCR7_DX8GCR7_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX8GCR7_DX8GCR7_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8GCR8 */
#define DDR_PHY_DX8GCR8(t)        (t + 0xf20)

#define DDR_PHY_DX8GCR8_DX8GCR8_X4DXREFISELR0(x) ((x) & GENMASK(5, 0))
#define DDR_PHY_DX8GCR8_DX8GCR8_X4DXREFISELR0_M  GENMASK(5, 0)
#define DDR_PHY_DX8GCR8_DX8GCR8_X4DXREFISELR0_X(x) ((x) & GENMASK(5, 0))

#define DDR_PHY_DX8GCR8_DX8GCR8_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX8GCR8_DX8GCR8_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX8GCR8_DX8GCR8_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX8GCR8_DX8GCR8_X4DXREFISELR1(x) (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX8GCR8_DX8GCR8_X4DXREFISELR1_M  GENMASK(13, 8)
#define DDR_PHY_DX8GCR8_DX8GCR8_X4DXREFISELR1_X(x) (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX8GCR8_DX8GCR8_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX8GCR8_DX8GCR8_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX8GCR8_DX8GCR8_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX8GCR8_DX8GCR8_X4DXREFISELR2(x) (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX8GCR8_DX8GCR8_X4DXREFISELR2_M  GENMASK(21, 16)
#define DDR_PHY_DX8GCR8_DX8GCR8_X4DXREFISELR2_X(x)\
	(((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX8GCR8_DX8GCR8_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX8GCR8_DX8GCR8_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX8GCR8_DX8GCR8_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX8GCR8_DX8GCR8_X4DXREFISELR3(x) (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX8GCR8_DX8GCR8_X4DXREFISELR3_M  GENMASK(29, 24)
#define DDR_PHY_DX8GCR8_DX8GCR8_X4DXREFISELR3_X(x)\
	(((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX8GCR8_DX8GCR8_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX8GCR8_DX8GCR8_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX8GCR8_DX8GCR8_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8GCR9 */
#define DDR_PHY_DX8GCR9(t)        (t + 0xf24)

#define DDR_PHY_DX8GCR9_DX8GCR9_X4DXDQVREFR0(x)  ((x) & GENMASK(5, 0))
#define DDR_PHY_DX8GCR9_DX8GCR9_X4DXDQVREFR0_M   GENMASK(5, 0)
#define DDR_PHY_DX8GCR9_DX8GCR9_X4DXDQVREFR0_X(x) ((x) & GENMASK(5, 0))

#define DDR_PHY_DX8GCR9_DX8GCR9_RESERVED_7_6(x)  (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX8GCR9_DX8GCR9_RESERVED_7_6_M   GENMASK(7, 6)
#define DDR_PHY_DX8GCR9_DX8GCR9_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX8GCR9_DX8GCR9_X4DXDQVREFR1(x)  (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX8GCR9_DX8GCR9_X4DXDQVREFR1_M   GENMASK(13, 8)
#define DDR_PHY_DX8GCR9_DX8GCR9_X4DXDQVREFR1_X(x) (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX8GCR9_DX8GCR9_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX8GCR9_DX8GCR9_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX8GCR9_DX8GCR9_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX8GCR9_DX8GCR9_X4DXDQVREFR2(x)  (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX8GCR9_DX8GCR9_X4DXDQVREFR2_M   GENMASK(21, 16)
#define DDR_PHY_DX8GCR9_DX8GCR9_X4DXDQVREFR2_X(x)\
	(((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX8GCR9_DX8GCR9_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX8GCR9_DX8GCR9_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX8GCR9_DX8GCR9_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX8GCR9_DX8GCR9_X4DXDQVREFR3(x)  (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX8GCR9_DX8GCR9_X4DXDQVREFR3_M   GENMASK(29, 24)
#define DDR_PHY_DX8GCR9_DX8GCR9_X4DXDQVREFR3_X(x)\
	(((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX8GCR9_DX8GCR9_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX8GCR9_DX8GCR9_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX8GCR9_DX8GCR9_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8BDLR0 */
#define DDR_PHY_DX8BDLR0(t)       (t + 0xf40)

#define DDR_PHY_DX8BDLR0_DX8BDLR0_DQ0WBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX8BDLR0_DX8BDLR0_DQ0WBD_M       GENMASK(5, 0)
#define DDR_PHY_DX8BDLR0_DX8BDLR0_DQ0WBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX8BDLR0_DX8BDLR0_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX8BDLR0_DX8BDLR0_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX8BDLR0_DX8BDLR0_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX8BDLR0_DX8BDLR0_DQ1WBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX8BDLR0_DX8BDLR0_DQ1WBD_M       GENMASK(13, 8)
#define DDR_PHY_DX8BDLR0_DX8BDLR0_DQ1WBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX8BDLR0_DX8BDLR0_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX8BDLR0_DX8BDLR0_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX8BDLR0_DX8BDLR0_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX8BDLR0_DX8BDLR0_DQ2WBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX8BDLR0_DX8BDLR0_DQ2WBD_M       GENMASK(21, 16)
#define DDR_PHY_DX8BDLR0_DX8BDLR0_DQ2WBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX8BDLR0_DX8BDLR0_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX8BDLR0_DX8BDLR0_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX8BDLR0_DX8BDLR0_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX8BDLR0_DX8BDLR0_DQ3WBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX8BDLR0_DX8BDLR0_DQ3WBD_M       GENMASK(29, 24)
#define DDR_PHY_DX8BDLR0_DX8BDLR0_DQ3WBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX8BDLR0_DX8BDLR0_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX8BDLR0_DX8BDLR0_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX8BDLR0_DX8BDLR0_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8BDLR1 */
#define DDR_PHY_DX8BDLR1(t)       (t + 0xf44)

#define DDR_PHY_DX8BDLR1_DX8BDLR1_DQ4WBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX8BDLR1_DX8BDLR1_DQ4WBD_M       GENMASK(5, 0)
#define DDR_PHY_DX8BDLR1_DX8BDLR1_DQ4WBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX8BDLR1_DX8BDLR1_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX8BDLR1_DX8BDLR1_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX8BDLR1_DX8BDLR1_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX8BDLR1_DX8BDLR1_DQ5WBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX8BDLR1_DX8BDLR1_DQ5WBD_M       GENMASK(13, 8)
#define DDR_PHY_DX8BDLR1_DX8BDLR1_DQ5WBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX8BDLR1_DX8BDLR1_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX8BDLR1_DX8BDLR1_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX8BDLR1_DX8BDLR1_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX8BDLR1_DX8BDLR1_DQ6WBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX8BDLR1_DX8BDLR1_DQ6WBD_M       GENMASK(21, 16)
#define DDR_PHY_DX8BDLR1_DX8BDLR1_DQ6WBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX8BDLR1_DX8BDLR1_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX8BDLR1_DX8BDLR1_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX8BDLR1_DX8BDLR1_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX8BDLR1_DX8BDLR1_DQ7WBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX8BDLR1_DX8BDLR1_DQ7WBD_M       GENMASK(29, 24)
#define DDR_PHY_DX8BDLR1_DX8BDLR1_DQ7WBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX8BDLR1_DX8BDLR1_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX8BDLR1_DX8BDLR1_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX8BDLR1_DX8BDLR1_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8BDLR2 */
#define DDR_PHY_DX8BDLR2(t)       (t + 0xf48)

#define DDR_PHY_DX8BDLR2_DX8BDLR2_DMWBD(x)       ((x) & GENMASK(5, 0))
#define DDR_PHY_DX8BDLR2_DX8BDLR2_DMWBD_M        GENMASK(5, 0)
#define DDR_PHY_DX8BDLR2_DX8BDLR2_DMWBD_X(x)     ((x) & GENMASK(5, 0))

#define DDR_PHY_DX8BDLR2_DX8BDLR2_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX8BDLR2_DX8BDLR2_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX8BDLR2_DX8BDLR2_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX8BDLR2_DX8BDLR2_DSWBD(x)       (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX8BDLR2_DX8BDLR2_DSWBD_M        GENMASK(13, 8)
#define DDR_PHY_DX8BDLR2_DX8BDLR2_DSWBD_X(x)     (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX8BDLR2_DX8BDLR2_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX8BDLR2_DX8BDLR2_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX8BDLR2_DX8BDLR2_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX8BDLR2_DX8BDLR2_DSOEBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX8BDLR2_DX8BDLR2_DSOEBD_M       GENMASK(21, 16)
#define DDR_PHY_DX8BDLR2_DX8BDLR2_DSOEBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX8BDLR2_DX8BDLR2_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX8BDLR2_DX8BDLR2_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX8BDLR2_DX8BDLR2_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8BDLR3 */
#define DDR_PHY_DX8BDLR3(t)       (t + 0xf50)

#define DDR_PHY_DX8BDLR3_DX8BDLR3_DQ0RBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX8BDLR3_DX8BDLR3_DQ0RBD_M       GENMASK(5, 0)
#define DDR_PHY_DX8BDLR3_DX8BDLR3_DQ0RBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX8BDLR3_DX8BDLR3_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX8BDLR3_DX8BDLR3_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX8BDLR3_DX8BDLR3_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX8BDLR3_DX8BDLR3_DQ1RBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX8BDLR3_DX8BDLR3_DQ1RBD_M       GENMASK(13, 8)
#define DDR_PHY_DX8BDLR3_DX8BDLR3_DQ1RBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX8BDLR3_DX8BDLR3_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX8BDLR3_DX8BDLR3_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX8BDLR3_DX8BDLR3_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX8BDLR3_DX8BDLR3_DQ2RBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX8BDLR3_DX8BDLR3_DQ2RBD_M       GENMASK(21, 16)
#define DDR_PHY_DX8BDLR3_DX8BDLR3_DQ2RBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX8BDLR3_DX8BDLR3_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX8BDLR3_DX8BDLR3_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX8BDLR3_DX8BDLR3_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX8BDLR3_DX8BDLR3_DQ3RBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX8BDLR3_DX8BDLR3_DQ3RBD_M       GENMASK(29, 24)
#define DDR_PHY_DX8BDLR3_DX8BDLR3_DQ3RBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX8BDLR3_DX8BDLR3_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX8BDLR3_DX8BDLR3_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX8BDLR3_DX8BDLR3_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8BDLR4 */
#define DDR_PHY_DX8BDLR4(t)       (t + 0xf54)

#define DDR_PHY_DX8BDLR4_DX8BDLR4_DQ4RBD(x)      ((x) & GENMASK(5, 0))
#define DDR_PHY_DX8BDLR4_DX8BDLR4_DQ4RBD_M       GENMASK(5, 0)
#define DDR_PHY_DX8BDLR4_DX8BDLR4_DQ4RBD_X(x)    ((x) & GENMASK(5, 0))

#define DDR_PHY_DX8BDLR4_DX8BDLR4_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX8BDLR4_DX8BDLR4_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX8BDLR4_DX8BDLR4_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX8BDLR4_DX8BDLR4_DQ5RBD(x)      (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX8BDLR4_DX8BDLR4_DQ5RBD_M       GENMASK(13, 8)
#define DDR_PHY_DX8BDLR4_DX8BDLR4_DQ5RBD_X(x)    (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX8BDLR4_DX8BDLR4_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX8BDLR4_DX8BDLR4_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX8BDLR4_DX8BDLR4_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX8BDLR4_DX8BDLR4_DQ6RBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX8BDLR4_DX8BDLR4_DQ6RBD_M       GENMASK(21, 16)
#define DDR_PHY_DX8BDLR4_DX8BDLR4_DQ6RBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX8BDLR4_DX8BDLR4_RESERVED_23_22(x)\
	(((x) << 22) & GENMASK(23, 22))
#define DDR_PHY_DX8BDLR4_DX8BDLR4_RESERVED_23_22_M GENMASK(23, 22)
#define DDR_PHY_DX8BDLR4_DX8BDLR4_RESERVED_23_22_X(x)\
	(((x) & GENMASK(23, 22)) >> 22)

#define DDR_PHY_DX8BDLR4_DX8BDLR4_DQ7RBD(x)      (((x) << 24) & GENMASK(29, 24))
#define DDR_PHY_DX8BDLR4_DX8BDLR4_DQ7RBD_M       GENMASK(29, 24)
#define DDR_PHY_DX8BDLR4_DX8BDLR4_DQ7RBD_X(x)    (((x) & GENMASK(29, 24)) >> 24)

#define DDR_PHY_DX8BDLR4_DX8BDLR4_RESERVED_31_30(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_PHY_DX8BDLR4_DX8BDLR4_RESERVED_31_30_M GENMASK(31, 30)
#define DDR_PHY_DX8BDLR4_DX8BDLR4_RESERVED_31_30_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8BDLR5 */
#define DDR_PHY_DX8BDLR5(t)       (t + 0xf58)

#define DDR_PHY_DX8BDLR5_DX8BDLR5_DMRBD(x)       ((x) & GENMASK(5, 0))
#define DDR_PHY_DX8BDLR5_DX8BDLR5_DMRBD_M        GENMASK(5, 0)
#define DDR_PHY_DX8BDLR5_DX8BDLR5_DMRBD_X(x)     ((x) & GENMASK(5, 0))

#define DDR_PHY_DX8BDLR5_DX8BDLR5_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX8BDLR5_DX8BDLR5_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX8BDLR5_DX8BDLR5_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX8BDLR5_DX8BDLR5_DSRBD(x)       (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX8BDLR5_DX8BDLR5_DSRBD_M        GENMASK(13, 8)
#define DDR_PHY_DX8BDLR5_DX8BDLR5_DSRBD_X(x)     (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX8BDLR5_DX8BDLR5_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX8BDLR5_DX8BDLR5_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX8BDLR5_DX8BDLR5_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX8BDLR5_DX8BDLR5_DSNRBD(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX8BDLR5_DX8BDLR5_DSNRBD_M       GENMASK(21, 16)
#define DDR_PHY_DX8BDLR5_DX8BDLR5_DSNRBD_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX8BDLR5_DX8BDLR5_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX8BDLR5_DX8BDLR5_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX8BDLR5_DX8BDLR5_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8BDLR6 */
#define DDR_PHY_DX8BDLR6(t)       (t + 0xf60)

#define DDR_PHY_DX8BDLR6_DX8BDLR6_RESERVED_7_0(x) ((x) & GENMASK(7, 0))
#define DDR_PHY_DX8BDLR6_DX8BDLR6_RESERVED_7_0_M GENMASK(7, 0)
#define DDR_PHY_DX8BDLR6_DX8BDLR6_RESERVED_7_0_X(x) ((x) & GENMASK(7, 0))

#define DDR_PHY_DX8BDLR6_DX8BDLR6_PDRBD(x)       (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX8BDLR6_DX8BDLR6_PDRBD_M        GENMASK(13, 8)
#define DDR_PHY_DX8BDLR6_DX8BDLR6_PDRBD_X(x)     (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX8BDLR6_DX8BDLR6_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX8BDLR6_DX8BDLR6_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX8BDLR6_DX8BDLR6_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX8BDLR6_DX8BDLR6_TERBD(x)       (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX8BDLR6_DX8BDLR6_TERBD_M        GENMASK(21, 16)
#define DDR_PHY_DX8BDLR6_DX8BDLR6_TERBD_X(x)     (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX8BDLR6_DX8BDLR6_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX8BDLR6_DX8BDLR6_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX8BDLR6_DX8BDLR6_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8BDLR7 */
#define DDR_PHY_DX8BDLR7(t)       (t + 0xf64)

#define DDR_PHY_DX8BDLR7_DX8BDLR7_X4DMWBD(x)     ((x) & GENMASK(5, 0))
#define DDR_PHY_DX8BDLR7_DX8BDLR7_X4DMWBD_M      GENMASK(5, 0)
#define DDR_PHY_DX8BDLR7_DX8BDLR7_X4DMWBD_X(x)   ((x) & GENMASK(5, 0))

#define DDR_PHY_DX8BDLR7_DX8BDLR7_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX8BDLR7_DX8BDLR7_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX8BDLR7_DX8BDLR7_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX8BDLR7_DX8BDLR7_X4DSWBD(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX8BDLR7_DX8BDLR7_X4DSWBD_M      GENMASK(13, 8)
#define DDR_PHY_DX8BDLR7_DX8BDLR7_X4DSWBD_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX8BDLR7_DX8BDLR7_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX8BDLR7_DX8BDLR7_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX8BDLR7_DX8BDLR7_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX8BDLR7_DX8BDLR7_X4DSOEBD(x)    (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX8BDLR7_DX8BDLR7_X4DSOEBD_M     GENMASK(21, 16)
#define DDR_PHY_DX8BDLR7_DX8BDLR7_X4DSOEBD_X(x)  (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX8BDLR7_DX8BDLR7_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX8BDLR7_DX8BDLR7_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX8BDLR7_DX8BDLR7_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8BDLR8 */
#define DDR_PHY_DX8BDLR8(t)       (t + 0xf68)

#define DDR_PHY_DX8BDLR8_DX8BDLR8_X4DMRBD(x)     ((x) & GENMASK(5, 0))
#define DDR_PHY_DX8BDLR8_DX8BDLR8_X4DMRBD_M      GENMASK(5, 0)
#define DDR_PHY_DX8BDLR8_DX8BDLR8_X4DMRBD_X(x)   ((x) & GENMASK(5, 0))

#define DDR_PHY_DX8BDLR8_DX8BDLR8_RESERVED_7_6(x) (((x) << 6) & GENMASK(7, 6))
#define DDR_PHY_DX8BDLR8_DX8BDLR8_RESERVED_7_6_M GENMASK(7, 6)
#define DDR_PHY_DX8BDLR8_DX8BDLR8_RESERVED_7_6_X(x) (((x) & GENMASK(7, 6)) >> 6)

#define DDR_PHY_DX8BDLR8_DX8BDLR8_X4DSRBD(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX8BDLR8_DX8BDLR8_X4DSRBD_M      GENMASK(13, 8)
#define DDR_PHY_DX8BDLR8_DX8BDLR8_X4DSRBD_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX8BDLR8_DX8BDLR8_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX8BDLR8_DX8BDLR8_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX8BDLR8_DX8BDLR8_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX8BDLR8_DX8BDLR8_X4DSNRBD(x)    (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX8BDLR8_DX8BDLR8_X4DSNRBD_M     GENMASK(21, 16)
#define DDR_PHY_DX8BDLR8_DX8BDLR8_X4DSNRBD_X(x)  (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX8BDLR8_DX8BDLR8_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX8BDLR8_DX8BDLR8_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX8BDLR8_DX8BDLR8_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8BDLR9 */
#define DDR_PHY_DX8BDLR9(t)       (t + 0xf6c)

#define DDR_PHY_DX8BDLR9_DX8BDLR9_RESERVED_7_0(x) ((x) & GENMASK(7, 0))
#define DDR_PHY_DX8BDLR9_DX8BDLR9_RESERVED_7_0_M GENMASK(7, 0)
#define DDR_PHY_DX8BDLR9_DX8BDLR9_RESERVED_7_0_X(x) ((x) & GENMASK(7, 0))

#define DDR_PHY_DX8BDLR9_DX8BDLR9_X4PDRBD(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_PHY_DX8BDLR9_DX8BDLR9_X4PDRBD_M      GENMASK(13, 8)
#define DDR_PHY_DX8BDLR9_DX8BDLR9_X4PDRBD_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_PHY_DX8BDLR9_DX8BDLR9_RESERVED_15_14(x)\
	(((x) << 14) & GENMASK(15, 14))
#define DDR_PHY_DX8BDLR9_DX8BDLR9_RESERVED_15_14_M GENMASK(15, 14)
#define DDR_PHY_DX8BDLR9_DX8BDLR9_RESERVED_15_14_X(x)\
	(((x) & GENMASK(15, 14)) >> 14)

#define DDR_PHY_DX8BDLR9_DX8BDLR9_X4TERBD(x)     (((x) << 16) & GENMASK(21, 16))
#define DDR_PHY_DX8BDLR9_DX8BDLR9_X4TERBD_M      GENMASK(21, 16)
#define DDR_PHY_DX8BDLR9_DX8BDLR9_X4TERBD_X(x)   (((x) & GENMASK(21, 16)) >> 16)

#define DDR_PHY_DX8BDLR9_DX8BDLR9_RESERVED_31_22(x)\
	(((x) << 22) & GENMASK(31, 22))
#define DDR_PHY_DX8BDLR9_DX8BDLR9_RESERVED_31_22_M GENMASK(31, 22)
#define DDR_PHY_DX8BDLR9_DX8BDLR9_RESERVED_31_22_X(x)\
	(((x) & GENMASK(31, 22)) >> 22)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8LCDLR0 */
#define DDR_PHY_DX8LCDLR0(t)      (t + 0xf80)

#define DDR_PHY_DX8LCDLR0_DX8LCDLR0_WLD(x)       ((x) & GENMASK(8, 0))
#define DDR_PHY_DX8LCDLR0_DX8LCDLR0_WLD_M        GENMASK(8, 0)
#define DDR_PHY_DX8LCDLR0_DX8LCDLR0_WLD_X(x)     ((x) & GENMASK(8, 0))

#define DDR_PHY_DX8LCDLR0_DX8LCDLR0_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX8LCDLR0_DX8LCDLR0_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX8LCDLR0_DX8LCDLR0_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX8LCDLR0_DX8LCDLR0_X4WLD(x)     (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX8LCDLR0_DX8LCDLR0_X4WLD_M      GENMASK(24, 16)
#define DDR_PHY_DX8LCDLR0_DX8LCDLR0_X4WLD_X(x)   (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX8LCDLR0_DX8LCDLR0_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX8LCDLR0_DX8LCDLR0_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX8LCDLR0_DX8LCDLR0_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8LCDLR1 */
#define DDR_PHY_DX8LCDLR1(t)      (t + 0xf84)

#define DDR_PHY_DX8LCDLR1_DX8LCDLR1_WDQD(x)      ((x) & GENMASK(8, 0))
#define DDR_PHY_DX8LCDLR1_DX8LCDLR1_WDQD_M       GENMASK(8, 0)
#define DDR_PHY_DX8LCDLR1_DX8LCDLR1_WDQD_X(x)    ((x) & GENMASK(8, 0))

#define DDR_PHY_DX8LCDLR1_DX8LCDLR1_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX8LCDLR1_DX8LCDLR1_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX8LCDLR1_DX8LCDLR1_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX8LCDLR1_DX8LCDLR1_X4WDQD(x)    (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX8LCDLR1_DX8LCDLR1_X4WDQD_M     GENMASK(24, 16)
#define DDR_PHY_DX8LCDLR1_DX8LCDLR1_X4WDQD_X(x)  (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX8LCDLR1_DX8LCDLR1_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX8LCDLR1_DX8LCDLR1_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX8LCDLR1_DX8LCDLR1_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8LCDLR2 */
#define DDR_PHY_DX8LCDLR2(t)      (t + 0xf88)

#define DDR_PHY_DX8LCDLR2_DX8LCDLR2_DQSGD(x)     ((x) & GENMASK(8, 0))
#define DDR_PHY_DX8LCDLR2_DX8LCDLR2_DQSGD_M      GENMASK(8, 0)
#define DDR_PHY_DX8LCDLR2_DX8LCDLR2_DQSGD_X(x)   ((x) & GENMASK(8, 0))

#define DDR_PHY_DX8LCDLR2_DX8LCDLR2_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX8LCDLR2_DX8LCDLR2_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX8LCDLR2_DX8LCDLR2_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX8LCDLR2_DX8LCDLR2_X4DQSGD(x)   (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX8LCDLR2_DX8LCDLR2_X4DQSGD_M    GENMASK(24, 16)
#define DDR_PHY_DX8LCDLR2_DX8LCDLR2_X4DQSGD_X(x) (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX8LCDLR2_DX8LCDLR2_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX8LCDLR2_DX8LCDLR2_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX8LCDLR2_DX8LCDLR2_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8LCDLR3 */
#define DDR_PHY_DX8LCDLR3(t)      (t + 0xf8c)

#define DDR_PHY_DX8LCDLR3_DX8LCDLR3_RDQSD(x)     ((x) & GENMASK(8, 0))
#define DDR_PHY_DX8LCDLR3_DX8LCDLR3_RDQSD_M      GENMASK(8, 0)
#define DDR_PHY_DX8LCDLR3_DX8LCDLR3_RDQSD_X(x)   ((x) & GENMASK(8, 0))

#define DDR_PHY_DX8LCDLR3_DX8LCDLR3_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX8LCDLR3_DX8LCDLR3_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX8LCDLR3_DX8LCDLR3_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX8LCDLR3_DX8LCDLR3_X4RDQSD(x)   (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX8LCDLR3_DX8LCDLR3_X4RDQSD_M    GENMASK(24, 16)
#define DDR_PHY_DX8LCDLR3_DX8LCDLR3_X4RDQSD_X(x) (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX8LCDLR3_DX8LCDLR3_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX8LCDLR3_DX8LCDLR3_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX8LCDLR3_DX8LCDLR3_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8LCDLR4 */
#define DDR_PHY_DX8LCDLR4(t)      (t + 0xf90)

#define DDR_PHY_DX8LCDLR4_DX8LCDLR4_RDQSND(x)    ((x) & GENMASK(8, 0))
#define DDR_PHY_DX8LCDLR4_DX8LCDLR4_RDQSND_M     GENMASK(8, 0)
#define DDR_PHY_DX8LCDLR4_DX8LCDLR4_RDQSND_X(x)  ((x) & GENMASK(8, 0))

#define DDR_PHY_DX8LCDLR4_DX8LCDLR4_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX8LCDLR4_DX8LCDLR4_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX8LCDLR4_DX8LCDLR4_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX8LCDLR4_DX8LCDLR4_X4RDQSND(x)  (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX8LCDLR4_DX8LCDLR4_X4RDQSND_M   GENMASK(24, 16)
#define DDR_PHY_DX8LCDLR4_DX8LCDLR4_X4RDQSND_X(x)\
	(((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX8LCDLR4_DX8LCDLR4_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX8LCDLR4_DX8LCDLR4_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX8LCDLR4_DX8LCDLR4_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8LCDLR5 */
#define DDR_PHY_DX8LCDLR5(t)      (t + 0xf94)

#define DDR_PHY_DX8LCDLR5_DX8LCDLR5_DQSGSD(x)    ((x) & GENMASK(8, 0))
#define DDR_PHY_DX8LCDLR5_DX8LCDLR5_DQSGSD_M     GENMASK(8, 0)
#define DDR_PHY_DX8LCDLR5_DX8LCDLR5_DQSGSD_X(x)  ((x) & GENMASK(8, 0))

#define DDR_PHY_DX8LCDLR5_DX8LCDLR5_RESERVED_15_9(x)\
	(((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX8LCDLR5_DX8LCDLR5_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX8LCDLR5_DX8LCDLR5_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX8LCDLR5_DX8LCDLR5_X4DQSGSD(x)  (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX8LCDLR5_DX8LCDLR5_X4DQSGSD_M   GENMASK(24, 16)
#define DDR_PHY_DX8LCDLR5_DX8LCDLR5_X4DQSGSD_X(x)\
	(((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX8LCDLR5_DX8LCDLR5_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX8LCDLR5_DX8LCDLR5_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX8LCDLR5_DX8LCDLR5_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8MDLR0 */
#define DDR_PHY_DX8MDLR0(t)       (t + 0xfa0)

#define DDR_PHY_DX8MDLR0_DX8MDLR0_IPRD(x)        ((x) & GENMASK(8, 0))
#define DDR_PHY_DX8MDLR0_DX8MDLR0_IPRD_M         GENMASK(8, 0)
#define DDR_PHY_DX8MDLR0_DX8MDLR0_IPRD_X(x)      ((x) & GENMASK(8, 0))

#define DDR_PHY_DX8MDLR0_DX8MDLR0_RESERVED_15_9(x) (((x) << 9) & GENMASK(15, 9))
#define DDR_PHY_DX8MDLR0_DX8MDLR0_RESERVED_15_9_M GENMASK(15, 9)
#define DDR_PHY_DX8MDLR0_DX8MDLR0_RESERVED_15_9_X(x)\
	(((x) & GENMASK(15, 9)) >> 9)

#define DDR_PHY_DX8MDLR0_DX8MDLR0_TPRD(x)        (((x) << 16) & GENMASK(24, 16))
#define DDR_PHY_DX8MDLR0_DX8MDLR0_TPRD_M         GENMASK(24, 16)
#define DDR_PHY_DX8MDLR0_DX8MDLR0_TPRD_X(x)      (((x) & GENMASK(24, 16)) >> 16)

#define DDR_PHY_DX8MDLR0_DX8MDLR0_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX8MDLR0_DX8MDLR0_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX8MDLR0_DX8MDLR0_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8MDLR1 */
#define DDR_PHY_DX8MDLR1(t)       (t + 0xfa4)

#define DDR_PHY_DX8MDLR1_DX8MDLR1_MDLD(x)        ((x) & GENMASK(8, 0))
#define DDR_PHY_DX8MDLR1_DX8MDLR1_MDLD_M         GENMASK(8, 0)
#define DDR_PHY_DX8MDLR1_DX8MDLR1_MDLD_X(x)      ((x) & GENMASK(8, 0))

#define DDR_PHY_DX8MDLR1_DX8MDLR1_RESERVED_31_9(x) (((x) << 9) & GENMASK(31, 9))
#define DDR_PHY_DX8MDLR1_DX8MDLR1_RESERVED_31_9_M GENMASK(31, 9)
#define DDR_PHY_DX8MDLR1_DX8MDLR1_RESERVED_31_9_X(x)\
	(((x) & GENMASK(31, 9)) >> 9)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8GTR0 */
#define DDR_PHY_DX8GTR0(t)        (t + 0xfc0)

#define DDR_PHY_DX8GTR0_DX8GTR0_DGSL(x)          ((x) & GENMASK(4, 0))
#define DDR_PHY_DX8GTR0_DX8GTR0_DGSL_M           GENMASK(4, 0)
#define DDR_PHY_DX8GTR0_DX8GTR0_DGSL_X(x)        ((x) & GENMASK(4, 0))

#define DDR_PHY_DX8GTR0_DX8GTR0_RESERVED_7_5(x)  (((x) << 5) & GENMASK(7, 5))
#define DDR_PHY_DX8GTR0_DX8GTR0_RESERVED_7_5_M   GENMASK(7, 5)
#define DDR_PHY_DX8GTR0_DX8GTR0_RESERVED_7_5_X(x) (((x) & GENMASK(7, 5)) >> 5)

#define DDR_PHY_DX8GTR0_DX8GTR0_X4DGSL(x)        (((x) << 8) & GENMASK(12, 8))
#define DDR_PHY_DX8GTR0_DX8GTR0_X4DGSL_M         GENMASK(12, 8)
#define DDR_PHY_DX8GTR0_DX8GTR0_X4DGSL_X(x)      (((x) & GENMASK(12, 8)) >> 8)

#define DDR_PHY_DX8GTR0_DX8GTR0_RESERVED_15_13(x)\
	(((x) << 13) & GENMASK(15, 13))
#define DDR_PHY_DX8GTR0_DX8GTR0_RESERVED_15_13_M GENMASK(15, 13)
#define DDR_PHY_DX8GTR0_DX8GTR0_RESERVED_15_13_X(x)\
	(((x) & GENMASK(15, 13)) >> 13)

#define DDR_PHY_DX8GTR0_DX8GTR0_WLSL(x)          (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DX8GTR0_DX8GTR0_WLSL_M           GENMASK(19, 16)
#define DDR_PHY_DX8GTR0_DX8GTR0_WLSL_X(x)        (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DX8GTR0_DX8GTR0_X4WLSL(x)        (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX8GTR0_DX8GTR0_X4WLSL_M         GENMASK(23, 20)
#define DDR_PHY_DX8GTR0_DX8GTR0_X4WLSL_X(x)      (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX8GTR0_DX8GTR0_RESERVED_31_24(x)\
	(((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_DX8GTR0_DX8GTR0_RESERVED_31_24_M GENMASK(31, 24)
#define DDR_PHY_DX8GTR0_DX8GTR0_RESERVED_31_24_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8RSR0 */
#define DDR_PHY_DX8RSR0(t)        (t + 0xfd0)

#define DDR_PHY_DX8RSR0_DX8RSR0_QSGERR(x)        ((x) & GENMASK(15, 0))
#define DDR_PHY_DX8RSR0_DX8RSR0_QSGERR_M         GENMASK(15, 0)
#define DDR_PHY_DX8RSR0_DX8RSR0_QSGERR_X(x)      ((x) & GENMASK(15, 0))

#define DDR_PHY_DX8RSR0_DX8RSR0_X4QSGERR(x)      (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX8RSR0_DX8RSR0_X4QSGERR_M       GENMASK(31, 16)
#define DDR_PHY_DX8RSR0_DX8RSR0_X4QSGERR_X(x)    (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8RSR1 */
#define DDR_PHY_DX8RSR1(t)        (t + 0xfd4)

#define DDR_PHY_DX8RSR1_DX8RSR1_RDLVLERR(x)      ((x) & GENMASK(15, 0))
#define DDR_PHY_DX8RSR1_DX8RSR1_RDLVLERR_M       GENMASK(15, 0)
#define DDR_PHY_DX8RSR1_DX8RSR1_RDLVLERR_X(x)    ((x) & GENMASK(15, 0))

#define DDR_PHY_DX8RSR1_DX8RSR1_X4RDLVLERR(x)    (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX8RSR1_DX8RSR1_X4RDLVLERR_M     GENMASK(31, 16)
#define DDR_PHY_DX8RSR1_DX8RSR1_X4RDLVLERR_X(x)  (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8RSR2 */
#define DDR_PHY_DX8RSR2(t)        (t + 0xfd8)

#define DDR_PHY_DX8RSR2_DX8RSR2_WLAWN(x)         ((x) & GENMASK(15, 0))
#define DDR_PHY_DX8RSR2_DX8RSR2_WLAWN_M          GENMASK(15, 0)
#define DDR_PHY_DX8RSR2_DX8RSR2_WLAWN_X(x)       ((x) & GENMASK(15, 0))

#define DDR_PHY_DX8RSR2_DX8RSR2_X4WLAWN(x)       (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX8RSR2_DX8RSR2_X4WLAWN_M        GENMASK(31, 16)
#define DDR_PHY_DX8RSR2_DX8RSR2_X4WLAWN_X(x)     (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8RSR3 */
#define DDR_PHY_DX8RSR3(t)        (t + 0xfdc)

#define DDR_PHY_DX8RSR3_DX8RSR3_WLAERR(x)        ((x) & GENMASK(15, 0))
#define DDR_PHY_DX8RSR3_DX8RSR3_WLAERR_M         GENMASK(15, 0)
#define DDR_PHY_DX8RSR3_DX8RSR3_WLAERR_X(x)      ((x) & GENMASK(15, 0))

#define DDR_PHY_DX8RSR3_DX8RSR3_X4WLAERR(x)      (((x) << 16) & GENMASK(31, 16))
#define DDR_PHY_DX8RSR3_DX8RSR3_X4WLAERR_M       GENMASK(31, 16)
#define DDR_PHY_DX8RSR3_DX8RSR3_X4WLAERR_X(x)    (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8GSR0 */
#define DDR_PHY_DX8GSR0(t)        (t + 0xfe0)

#define DDR_PHY_DX8GSR0_DX8GSR0_WDQCAL(x)        ((x) & GENMASK(0, 0))
#define DDR_PHY_DX8GSR0_DX8GSR0_WDQCAL_M         GENMASK(0, 0)
#define DDR_PHY_DX8GSR0_DX8GSR0_WDQCAL_X(x)      ((x) & GENMASK(0, 0))

#define DDR_PHY_DX8GSR0_DX8GSR0_RDQSCAL(x)       (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX8GSR0_DX8GSR0_RDQSCAL_M        GENMASK(1, 1)
#define DDR_PHY_DX8GSR0_DX8GSR0_RDQSCAL_X(x)     (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX8GSR0_DX8GSR0_RDQSNCAL(x)      (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX8GSR0_DX8GSR0_RDQSNCAL_M       GENMASK(2, 2)
#define DDR_PHY_DX8GSR0_DX8GSR0_RDQSNCAL_X(x)    (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX8GSR0_DX8GSR0_GDQSCAL(x)       (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX8GSR0_DX8GSR0_GDQSCAL_M        GENMASK(3, 3)
#define DDR_PHY_DX8GSR0_DX8GSR0_GDQSCAL_X(x)     (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX8GSR0_DX8GSR0_WLCAL(x)         (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX8GSR0_DX8GSR0_WLCAL_M          GENMASK(4, 4)
#define DDR_PHY_DX8GSR0_DX8GSR0_WLCAL_X(x)       (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX8GSR0_DX8GSR0_WLDONE(x)        (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX8GSR0_DX8GSR0_WLDONE_M         GENMASK(5, 5)
#define DDR_PHY_DX8GSR0_DX8GSR0_WLDONE_X(x)      (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX8GSR0_DX8GSR0_WLERR(x)         (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX8GSR0_DX8GSR0_WLERR_M          GENMASK(6, 6)
#define DDR_PHY_DX8GSR0_DX8GSR0_WLERR_X(x)       (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX8GSR0_DX8GSR0_WLPRD(x)         (((x) << 7) & GENMASK(15, 7))
#define DDR_PHY_DX8GSR0_DX8GSR0_WLPRD_M          GENMASK(15, 7)
#define DDR_PHY_DX8GSR0_DX8GSR0_WLPRD_X(x)       (((x) & GENMASK(15, 7)) >> 7)

#define DDR_PHY_DX8GSR0_DX8GSR0_DPLOCK(x)        (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX8GSR0_DX8GSR0_DPLOCK_M         GENMASK(16, 16)
#define DDR_PHY_DX8GSR0_DX8GSR0_DPLOCK_X(x)      (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX8GSR0_DX8GSR0_GDQSPRD(x)       (((x) << 17) & GENMASK(25, 17))
#define DDR_PHY_DX8GSR0_DX8GSR0_GDQSPRD_M        GENMASK(25, 17)
#define DDR_PHY_DX8GSR0_DX8GSR0_GDQSPRD_X(x)     (((x) & GENMASK(25, 17)) >> 17)

#define DDR_PHY_DX8GSR0_DX8GSR0_WLWN(x)          (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_DX8GSR0_DX8GSR0_WLWN_M           GENMASK(26, 26)
#define DDR_PHY_DX8GSR0_DX8GSR0_WLWN_X(x)        (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_DX8GSR0_DX8GSR0_RESERVED_29_27(x)\
	(((x) << 27) & GENMASK(29, 27))
#define DDR_PHY_DX8GSR0_DX8GSR0_RESERVED_29_27_M GENMASK(29, 27)
#define DDR_PHY_DX8GSR0_DX8GSR0_RESERVED_29_27_X(x)\
	(((x) & GENMASK(29, 27)) >> 27)

#define DDR_PHY_DX8GSR0_DX8GSR0_WLDQ(x)          (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX8GSR0_DX8GSR0_WLDQ_M           GENMASK(30, 30)
#define DDR_PHY_DX8GSR0_DX8GSR0_WLDQ_X(x)        (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX8GSR0_DX8GSR0_RESERVED_31(x)   (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX8GSR0_DX8GSR0_RESERVED_31_M    GENMASK(31, 31)
#define DDR_PHY_DX8GSR0_DX8GSR0_RESERVED_31_X(x) (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8GSR1 */
#define DDR_PHY_DX8GSR1(t)        (t + 0xfe4)

#define DDR_PHY_DX8GSR1_DX8GSR1_DLTDONE(x)       ((x) & GENMASK(0, 0))
#define DDR_PHY_DX8GSR1_DX8GSR1_DLTDONE_M        GENMASK(0, 0)
#define DDR_PHY_DX8GSR1_DX8GSR1_DLTDONE_X(x)     ((x) & GENMASK(0, 0))

#define DDR_PHY_DX8GSR1_DX8GSR1_DLTCODE(x)       (((x) << 1) & GENMASK(24, 1))
#define DDR_PHY_DX8GSR1_DX8GSR1_DLTCODE_M        GENMASK(24, 1)
#define DDR_PHY_DX8GSR1_DX8GSR1_DLTCODE_X(x)     (((x) & GENMASK(24, 1)) >> 1)

#define DDR_PHY_DX8GSR1_DX8GSR1_RESERVED_31_25(x)\
	(((x) << 25) & GENMASK(31, 25))
#define DDR_PHY_DX8GSR1_DX8GSR1_RESERVED_31_25_M GENMASK(31, 25)
#define DDR_PHY_DX8GSR1_DX8GSR1_RESERVED_31_25_X(x)\
	(((x) & GENMASK(31, 25)) >> 25)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8GSR2 */
#define DDR_PHY_DX8GSR2(t)        (t + 0xfe8)

#define DDR_PHY_DX8GSR2_DX8GSR2_RDERR(x)         ((x) & GENMASK(0, 0))
#define DDR_PHY_DX8GSR2_DX8GSR2_RDERR_M          GENMASK(0, 0)
#define DDR_PHY_DX8GSR2_DX8GSR2_RDERR_X(x)       ((x) & GENMASK(0, 0))

#define DDR_PHY_DX8GSR2_DX8GSR2_RDWN(x)          (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX8GSR2_DX8GSR2_RDWN_M           GENMASK(1, 1)
#define DDR_PHY_DX8GSR2_DX8GSR2_RDWN_X(x)        (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX8GSR2_DX8GSR2_WDERR(x)         (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX8GSR2_DX8GSR2_WDERR_M          GENMASK(2, 2)
#define DDR_PHY_DX8GSR2_DX8GSR2_WDERR_X(x)       (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX8GSR2_DX8GSR2_WDWN(x)          (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX8GSR2_DX8GSR2_WDWN_M           GENMASK(3, 3)
#define DDR_PHY_DX8GSR2_DX8GSR2_WDWN_X(x)        (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX8GSR2_DX8GSR2_REERR(x)         (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX8GSR2_DX8GSR2_REERR_M          GENMASK(4, 4)
#define DDR_PHY_DX8GSR2_DX8GSR2_REERR_X(x)       (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX8GSR2_DX8GSR2_REWN(x)          (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX8GSR2_DX8GSR2_REWN_M           GENMASK(5, 5)
#define DDR_PHY_DX8GSR2_DX8GSR2_REWN_X(x)        (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX8GSR2_DX8GSR2_WEERR(x)         (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX8GSR2_DX8GSR2_WEERR_M          GENMASK(6, 6)
#define DDR_PHY_DX8GSR2_DX8GSR2_WEERR_X(x)       (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX8GSR2_DX8GSR2_WEWN(x)          (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_DX8GSR2_DX8GSR2_WEWN_M           GENMASK(7, 7)
#define DDR_PHY_DX8GSR2_DX8GSR2_WEWN_X(x)        (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_DX8GSR2_DX8GSR2_ESTAT(x)         (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX8GSR2_DX8GSR2_ESTAT_M          GENMASK(11, 8)
#define DDR_PHY_DX8GSR2_DX8GSR2_ESTAT_X(x)       (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX8GSR2_DX8GSR2_DBDQ(x)          (((x) << 12) & GENMASK(19, 12))
#define DDR_PHY_DX8GSR2_DX8GSR2_DBDQ_M           GENMASK(19, 12)
#define DDR_PHY_DX8GSR2_DX8GSR2_DBDQ_X(x)        (((x) & GENMASK(19, 12)) >> 12)

#define DDR_PHY_DX8GSR2_DX8GSR2_SRDERR(x)        (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX8GSR2_DX8GSR2_SRDERR_M         GENMASK(20, 20)
#define DDR_PHY_DX8GSR2_DX8GSR2_SRDERR_X(x)      (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX8GSR2_DX8GSR2_RESERVED_21(x)   (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX8GSR2_DX8GSR2_RESERVED_21_M    GENMASK(21, 21)
#define DDR_PHY_DX8GSR2_DX8GSR2_RESERVED_21_X(x) (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX8GSR2_DX8GSR2_GSDQSCAL(x)      (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX8GSR2_DX8GSR2_GSDQSCAL_M       GENMASK(22, 22)
#define DDR_PHY_DX8GSR2_DX8GSR2_GSDQSCAL_X(x)    (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX8GSR2_DX8GSR2_GSDQSPRD(x)      (((x) << 23) & GENMASK(31, 23))
#define DDR_PHY_DX8GSR2_DX8GSR2_GSDQSPRD_M       GENMASK(31, 23)
#define DDR_PHY_DX8GSR2_DX8GSR2_GSDQSPRD_X(x)    (((x) & GENMASK(31, 23)) >> 23)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8GSR3 */
#define DDR_PHY_DX8GSR3(t)        (t + 0xfec)

#define DDR_PHY_DX8GSR3_DX8GSR3_SRDPC(x)         ((x) & GENMASK(1, 0))
#define DDR_PHY_DX8GSR3_DX8GSR3_SRDPC_M          GENMASK(1, 0)
#define DDR_PHY_DX8GSR3_DX8GSR3_SRDPC_X(x)       ((x) & GENMASK(1, 0))

#define DDR_PHY_DX8GSR3_DX8GSR3_RESERVED_7_2(x)  (((x) << 2) & GENMASK(7, 2))
#define DDR_PHY_DX8GSR3_DX8GSR3_RESERVED_7_2_M   GENMASK(7, 2)
#define DDR_PHY_DX8GSR3_DX8GSR3_RESERVED_7_2_X(x) (((x) & GENMASK(7, 2)) >> 2)

#define DDR_PHY_DX8GSR3_DX8GSR3_HVERR(x)         (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX8GSR3_DX8GSR3_HVERR_M          GENMASK(11, 8)
#define DDR_PHY_DX8GSR3_DX8GSR3_HVERR_X(x)       (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX8GSR3_DX8GSR3_HVWRN(x)         (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_DX8GSR3_DX8GSR3_HVWRN_M          GENMASK(15, 12)
#define DDR_PHY_DX8GSR3_DX8GSR3_HVWRN_X(x)       (((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_DX8GSR3_DX8GSR3_DVERR(x)         (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DX8GSR3_DX8GSR3_DVERR_M          GENMASK(19, 16)
#define DDR_PHY_DX8GSR3_DX8GSR3_DVERR_X(x)       (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DX8GSR3_DX8GSR3_DVWRN(x)         (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX8GSR3_DX8GSR3_DVWRN_M          GENMASK(23, 20)
#define DDR_PHY_DX8GSR3_DX8GSR3_DVWRN_X(x)       (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX8GSR3_DX8GSR3_ESTAT(x)         (((x) << 24) & GENMASK(26, 24))
#define DDR_PHY_DX8GSR3_DX8GSR3_ESTAT_M          GENMASK(26, 24)
#define DDR_PHY_DX8GSR3_DX8GSR3_ESTAT_X(x)       (((x) & GENMASK(26, 24)) >> 24)

#define DDR_PHY_DX8GSR3_DX8GSR3_RESERVED_31_27(x)\
	(((x) << 27) & GENMASK(31, 27))
#define DDR_PHY_DX8GSR3_DX8GSR3_RESERVED_31_27_M GENMASK(31, 27)
#define DDR_PHY_DX8GSR3_DX8GSR3_RESERVED_31_27_X(x)\
	(((x) & GENMASK(31, 27)) >> 27)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8GSR4 */
#define DDR_PHY_DX8GSR4(t)        (t + 0xff0)

#define DDR_PHY_DX8GSR4_DX8GSR4_X4WDQCAL(x)      ((x) & GENMASK(0, 0))
#define DDR_PHY_DX8GSR4_DX8GSR4_X4WDQCAL_M       GENMASK(0, 0)
#define DDR_PHY_DX8GSR4_DX8GSR4_X4WDQCAL_X(x)    ((x) & GENMASK(0, 0))

#define DDR_PHY_DX8GSR4_DX8GSR4_X4RDQSCAL(x)     (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX8GSR4_DX8GSR4_X4RDQSCAL_M      GENMASK(1, 1)
#define DDR_PHY_DX8GSR4_DX8GSR4_X4RDQSCAL_X(x)   (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX8GSR4_DX8GSR4_X4RDQSNCAL(x)    (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX8GSR4_DX8GSR4_X4RDQSNCAL_M     GENMASK(2, 2)
#define DDR_PHY_DX8GSR4_DX8GSR4_X4RDQSNCAL_X(x)  (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX8GSR4_DX8GSR4_X4GDQSCAL(x)     (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX8GSR4_DX8GSR4_X4GDQSCAL_M      GENMASK(3, 3)
#define DDR_PHY_DX8GSR4_DX8GSR4_X4GDQSCAL_X(x)   (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX8GSR4_DX8GSR4_X4WLCAL(x)       (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX8GSR4_DX8GSR4_X4WLCAL_M        GENMASK(4, 4)
#define DDR_PHY_DX8GSR4_DX8GSR4_X4WLCAL_X(x)     (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX8GSR4_DX8GSR4_X4WLDONE(x)      (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX8GSR4_DX8GSR4_X4WLDONE_M       GENMASK(5, 5)
#define DDR_PHY_DX8GSR4_DX8GSR4_X4WLDONE_X(x)    (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX8GSR4_DX8GSR4_X4WLERR(x)       (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX8GSR4_DX8GSR4_X4WLERR_M        GENMASK(6, 6)
#define DDR_PHY_DX8GSR4_DX8GSR4_X4WLERR_X(x)     (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX8GSR4_DX8GSR4_X4WLPRD(x)       (((x) << 7) & GENMASK(15, 7))
#define DDR_PHY_DX8GSR4_DX8GSR4_X4WLPRD_M        GENMASK(15, 7)
#define DDR_PHY_DX8GSR4_DX8GSR4_X4WLPRD_X(x)     (((x) & GENMASK(15, 7)) >> 7)

#define DDR_PHY_DX8GSR4_DX8GSR4_X4DPLOCK(x)      (((x) << 16) & GENMASK(16, 16))
#define DDR_PHY_DX8GSR4_DX8GSR4_X4DPLOCK_M       GENMASK(16, 16)
#define DDR_PHY_DX8GSR4_DX8GSR4_X4DPLOCK_X(x)    (((x) & GENMASK(16, 16)) >> 16)

#define DDR_PHY_DX8GSR4_DX8GSR4_X4GDQSPRD(x)     (((x) << 17) & GENMASK(25, 17))
#define DDR_PHY_DX8GSR4_DX8GSR4_X4GDQSPRD_M      GENMASK(25, 17)
#define DDR_PHY_DX8GSR4_DX8GSR4_X4GDQSPRD_X(x)   (((x) & GENMASK(25, 17)) >> 17)

#define DDR_PHY_DX8GSR4_DX8GSR4_X4WLWN(x)        (((x) << 26) & GENMASK(26, 26))
#define DDR_PHY_DX8GSR4_DX8GSR4_X4WLWN_M         GENMASK(26, 26)
#define DDR_PHY_DX8GSR4_DX8GSR4_X4WLWN_X(x)      (((x) & GENMASK(26, 26)) >> 26)

#define DDR_PHY_DX8GSR4_DX8GSR4_RESERVED_29_27(x)\
	(((x) << 27) & GENMASK(29, 27))
#define DDR_PHY_DX8GSR4_DX8GSR4_RESERVED_29_27_M GENMASK(29, 27)
#define DDR_PHY_DX8GSR4_DX8GSR4_RESERVED_29_27_X(x)\
	(((x) & GENMASK(29, 27)) >> 27)

#define DDR_PHY_DX8GSR4_DX8GSR4_X4WLDQ(x)        (((x) << 30) & GENMASK(30, 30))
#define DDR_PHY_DX8GSR4_DX8GSR4_X4WLDQ_M         GENMASK(30, 30)
#define DDR_PHY_DX8GSR4_DX8GSR4_X4WLDQ_X(x)      (((x) & GENMASK(30, 30)) >> 30)

#define DDR_PHY_DX8GSR4_DX8GSR4_RESERVED_31(x)   (((x) << 31) & GENMASK(31, 31))
#define DDR_PHY_DX8GSR4_DX8GSR4_RESERVED_31_M    GENMASK(31, 31)
#define DDR_PHY_DX8GSR4_DX8GSR4_RESERVED_31_X(x) (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8GSR5 */
#define DDR_PHY_DX8GSR5(t)        (t + 0xff4)

#define DDR_PHY_DX8GSR5_DX8GSR5_X4RDERR(x)       ((x) & GENMASK(0, 0))
#define DDR_PHY_DX8GSR5_DX8GSR5_X4RDERR_M        GENMASK(0, 0)
#define DDR_PHY_DX8GSR5_DX8GSR5_X4RDERR_X(x)     ((x) & GENMASK(0, 0))

#define DDR_PHY_DX8GSR5_DX8GSR5_X4RDWN(x)        (((x) << 1) & GENMASK(1, 1))
#define DDR_PHY_DX8GSR5_DX8GSR5_X4RDWN_M         GENMASK(1, 1)
#define DDR_PHY_DX8GSR5_DX8GSR5_X4RDWN_X(x)      (((x) & GENMASK(1, 1)) >> 1)

#define DDR_PHY_DX8GSR5_DX8GSR5_X4WDERR(x)       (((x) << 2) & GENMASK(2, 2))
#define DDR_PHY_DX8GSR5_DX8GSR5_X4WDERR_M        GENMASK(2, 2)
#define DDR_PHY_DX8GSR5_DX8GSR5_X4WDERR_X(x)     (((x) & GENMASK(2, 2)) >> 2)

#define DDR_PHY_DX8GSR5_DX8GSR5_X4WDWN(x)        (((x) << 3) & GENMASK(3, 3))
#define DDR_PHY_DX8GSR5_DX8GSR5_X4WDWN_M         GENMASK(3, 3)
#define DDR_PHY_DX8GSR5_DX8GSR5_X4WDWN_X(x)      (((x) & GENMASK(3, 3)) >> 3)

#define DDR_PHY_DX8GSR5_DX8GSR5_X4REERR(x)       (((x) << 4) & GENMASK(4, 4))
#define DDR_PHY_DX8GSR5_DX8GSR5_X4REERR_M        GENMASK(4, 4)
#define DDR_PHY_DX8GSR5_DX8GSR5_X4REERR_X(x)     (((x) & GENMASK(4, 4)) >> 4)

#define DDR_PHY_DX8GSR5_DX8GSR5_X4REWN(x)        (((x) << 5) & GENMASK(5, 5))
#define DDR_PHY_DX8GSR5_DX8GSR5_X4REWN_M         GENMASK(5, 5)
#define DDR_PHY_DX8GSR5_DX8GSR5_X4REWN_X(x)      (((x) & GENMASK(5, 5)) >> 5)

#define DDR_PHY_DX8GSR5_DX8GSR5_X4WEERR(x)       (((x) << 6) & GENMASK(6, 6))
#define DDR_PHY_DX8GSR5_DX8GSR5_X4WEERR_M        GENMASK(6, 6)
#define DDR_PHY_DX8GSR5_DX8GSR5_X4WEERR_X(x)     (((x) & GENMASK(6, 6)) >> 6)

#define DDR_PHY_DX8GSR5_DX8GSR5_X4WEWN(x)        (((x) << 7) & GENMASK(7, 7))
#define DDR_PHY_DX8GSR5_DX8GSR5_X4WEWN_M         GENMASK(7, 7)
#define DDR_PHY_DX8GSR5_DX8GSR5_X4WEWN_X(x)      (((x) & GENMASK(7, 7)) >> 7)

#define DDR_PHY_DX8GSR5_DX8GSR5_X4ESTAT(x)       (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX8GSR5_DX8GSR5_X4ESTAT_M        GENMASK(11, 8)
#define DDR_PHY_DX8GSR5_DX8GSR5_X4ESTAT_X(x)     (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX8GSR5_DX8GSR5_RESERVED_19_12(x)\
	(((x) << 12) & GENMASK(19, 12))
#define DDR_PHY_DX8GSR5_DX8GSR5_RESERVED_19_12_M GENMASK(19, 12)
#define DDR_PHY_DX8GSR5_DX8GSR5_RESERVED_19_12_X(x)\
	(((x) & GENMASK(19, 12)) >> 12)

#define DDR_PHY_DX8GSR5_DX8GSR5_X4SRDERR(x)      (((x) << 20) & GENMASK(20, 20))
#define DDR_PHY_DX8GSR5_DX8GSR5_X4SRDERR_M       GENMASK(20, 20)
#define DDR_PHY_DX8GSR5_DX8GSR5_X4SRDERR_X(x)    (((x) & GENMASK(20, 20)) >> 20)

#define DDR_PHY_DX8GSR5_DX8GSR5_RESERVED_21(x)   (((x) << 21) & GENMASK(21, 21))
#define DDR_PHY_DX8GSR5_DX8GSR5_RESERVED_21_M    GENMASK(21, 21)
#define DDR_PHY_DX8GSR5_DX8GSR5_RESERVED_21_X(x) (((x) & GENMASK(21, 21)) >> 21)

#define DDR_PHY_DX8GSR5_DX8GSR5_X4GSDQSCAL(x)    (((x) << 22) & GENMASK(22, 22))
#define DDR_PHY_DX8GSR5_DX8GSR5_X4GSDQSCAL_M     GENMASK(22, 22)
#define DDR_PHY_DX8GSR5_DX8GSR5_X4GSDQSCAL_X(x)  (((x) & GENMASK(22, 22)) >> 22)

#define DDR_PHY_DX8GSR5_DX8GSR5_X4GSDQSPRD(x)    (((x) << 23) & GENMASK(31, 23))
#define DDR_PHY_DX8GSR5_DX8GSR5_X4GSDQSPRD_M     GENMASK(31, 23)
#define DDR_PHY_DX8GSR5_DX8GSR5_X4GSDQSPRD_X(x)  (((x) & GENMASK(31, 23)) >> 23)

/*      DDR_PHY:DWC_DDRPHY_PUB:DX8GSR6 */
#define DDR_PHY_DX8GSR6(t)        (t + 0xff8)

#define DDR_PHY_DX8GSR6_DX8GSR6_RESERVED_1_0(x)  ((x) & GENMASK(1, 0))
#define DDR_PHY_DX8GSR6_DX8GSR6_RESERVED_1_0_M   GENMASK(1, 0)
#define DDR_PHY_DX8GSR6_DX8GSR6_RESERVED_1_0_X(x) ((x) & GENMASK(1, 0))

#define DDR_PHY_DX8GSR6_DX8GSR6_X4SRDPC(x)       (((x) << 2) & GENMASK(3, 2))
#define DDR_PHY_DX8GSR6_DX8GSR6_X4SRDPC_M        GENMASK(3, 2)
#define DDR_PHY_DX8GSR6_DX8GSR6_X4SRDPC_X(x)     (((x) & GENMASK(3, 2)) >> 2)

#define DDR_PHY_DX8GSR6_DX8GSR6_RESERVED_7_4(x)  (((x) << 4) & GENMASK(7, 4))
#define DDR_PHY_DX8GSR6_DX8GSR6_RESERVED_7_4_M   GENMASK(7, 4)
#define DDR_PHY_DX8GSR6_DX8GSR6_RESERVED_7_4_X(x) (((x) & GENMASK(7, 4)) >> 4)

#define DDR_PHY_DX8GSR6_DX8GSR6_X4HVERR(x)       (((x) << 8) & GENMASK(11, 8))
#define DDR_PHY_DX8GSR6_DX8GSR6_X4HVERR_M        GENMASK(11, 8)
#define DDR_PHY_DX8GSR6_DX8GSR6_X4HVERR_X(x)     (((x) & GENMASK(11, 8)) >> 8)

#define DDR_PHY_DX8GSR6_DX8GSR6_X4HVWRN(x)       (((x) << 12) & GENMASK(15, 12))
#define DDR_PHY_DX8GSR6_DX8GSR6_X4HVWRN_M        GENMASK(15, 12)
#define DDR_PHY_DX8GSR6_DX8GSR6_X4HVWRN_X(x)     (((x) & GENMASK(15, 12)) >> 12)

#define DDR_PHY_DX8GSR6_DX8GSR6_X4DVERR(x)       (((x) << 16) & GENMASK(19, 16))
#define DDR_PHY_DX8GSR6_DX8GSR6_X4DVERR_M        GENMASK(19, 16)
#define DDR_PHY_DX8GSR6_DX8GSR6_X4DVERR_X(x)     (((x) & GENMASK(19, 16)) >> 16)

#define DDR_PHY_DX8GSR6_DX8GSR6_X4DVWRN(x)       (((x) << 20) & GENMASK(23, 20))
#define DDR_PHY_DX8GSR6_DX8GSR6_X4DVWRN_M        GENMASK(23, 20)
#define DDR_PHY_DX8GSR6_DX8GSR6_X4DVWRN_X(x)     (((x) & GENMASK(23, 20)) >> 20)

#define DDR_PHY_DX8GSR6_DX8GSR6_RESERVED_31_24(x)\
	(((x) << 24) & GENMASK(31, 24))
#define DDR_PHY_DX8GSR6_DX8GSR6_RESERVED_31_24_M GENMASK(31, 24)
#define DDR_PHY_DX8GSR6_DX8GSR6_RESERVED_31_24_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:MSTR */
#define DDR_UMCTL2_MSTR(t)        (t + 0x00)

#define DDR_UMCTL2_MSTR_DDR3ENA(x)               ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_MSTR_DDR3ENA_M                GENMASK(0, 0)
#define DDR_UMCTL2_MSTR_DDR3ENA_X(x)             ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_MSTR_DDR4(x)                  (((x) << 4) & GENMASK(4, 4))
#define DDR_UMCTL2_MSTR_DDR4_M                   GENMASK(4, 4)
#define DDR_UMCTL2_MSTR_DDR4_X(x)                (((x) & GENMASK(4, 4)) >> 4)

#define DDR_UMCTL2_MSTR_BURSTCHOP(x)             (((x) << 9) & GENMASK(9, 9))
#define DDR_UMCTL2_MSTR_BURSTCHOP_M              GENMASK(9, 9)
#define DDR_UMCTL2_MSTR_BURSTCHOP_X(x)           (((x) & GENMASK(9, 9)) >> 9)

#define DDR_UMCTL2_MSTR_EN_2T_TIMING_MODE(x)     (((x) << 10) & GENMASK(10, 10))
#define DDR_UMCTL2_MSTR_EN_2T_TIMING_MODE_M      GENMASK(10, 10)
#define DDR_UMCTL2_MSTR_EN_2T_TIMING_MODE_X(x)   (((x) & GENMASK(10, 10)) >> 10)

#define DDR_UMCTL2_MSTR_GEARDOWN_MODE(x)         (((x) << 11) & GENMASK(11, 11))
#define DDR_UMCTL2_MSTR_GEARDOWN_MODE_M          GENMASK(11, 11)
#define DDR_UMCTL2_MSTR_GEARDOWN_MODE_X(x)       (((x) & GENMASK(11, 11)) >> 11)

#define DDR_UMCTL2_MSTR_DATA_BUS_WIDTH(x)        (((x) << 12) & GENMASK(13, 12))
#define DDR_UMCTL2_MSTR_DATA_BUS_WIDTH_M         GENMASK(13, 12)
#define DDR_UMCTL2_MSTR_DATA_BUS_WIDTH_X(x)      (((x) & GENMASK(13, 12)) >> 12)

#define DDR_UMCTL2_MSTR_DLL_OFF_MODE(x)          (((x) << 15) & GENMASK(15, 15))
#define DDR_UMCTL2_MSTR_DLL_OFF_MODE_M           GENMASK(15, 15)
#define DDR_UMCTL2_MSTR_DLL_OFF_MODE_X(x)        (((x) & GENMASK(15, 15)) >> 15)

#define DDR_UMCTL2_MSTR_BURST_RDWR(x)            (((x) << 16) & GENMASK(19, 16))
#define DDR_UMCTL2_MSTR_BURST_RDWR_M             GENMASK(19, 16)
#define DDR_UMCTL2_MSTR_BURST_RDWR_X(x)          (((x) & GENMASK(19, 16)) >> 16)

#define DDR_UMCTL2_MSTR_ACTIVE_RANKS(x)          (((x) << 24) & GENMASK(25, 24))
#define DDR_UMCTL2_MSTR_ACTIVE_RANKS_M           GENMASK(25, 24)
#define DDR_UMCTL2_MSTR_ACTIVE_RANKS_X(x)        (((x) & GENMASK(25, 24)) >> 24)

#define DDR_UMCTL2_MSTR_DEVICE_CONFIG(x)         (((x) << 30) & GENMASK(31, 30))
#define DDR_UMCTL2_MSTR_DEVICE_CONFIG_M          GENMASK(31, 30)
#define DDR_UMCTL2_MSTR_DEVICE_CONFIG_X(x)       (((x) & GENMASK(31, 30)) >> 30)

/*      DDR_UMCTL2:UMCTL2_REGS:STAT */
#define DDR_UMCTL2_STAT(t)        (t + 0x04)

#define DDR_UMCTL2_STAT_OPERATING_MODE(x)        ((x) & GENMASK(2, 0))
#define DDR_UMCTL2_STAT_OPERATING_MODE_M         GENMASK(2, 0)
#define DDR_UMCTL2_STAT_OPERATING_MODE_X(x)      ((x) & GENMASK(2, 0))

#define DDR_UMCTL2_STAT_SELFREF_TYPE(x)          (((x) << 4) & GENMASK(5, 4))
#define DDR_UMCTL2_STAT_SELFREF_TYPE_M           GENMASK(5, 4)
#define DDR_UMCTL2_STAT_SELFREF_TYPE_X(x)        (((x) & GENMASK(5, 4)) >> 4)

#define DDR_UMCTL2_STAT_SELFREF_CAM_NOT_EMPTY(x) (((x) << 12) & GENMASK(12, 12))
#define DDR_UMCTL2_STAT_SELFREF_CAM_NOT_EMPTY_M  GENMASK(12, 12)
#define DDR_UMCTL2_STAT_SELFREF_CAM_NOT_EMPTY_X(x)\
	(((x) & GENMASK(12, 12)) >> 12)

/*      DDR_UMCTL2:UMCTL2_REGS:MRCTRL0 */
#define DDR_UMCTL2_MRCTRL0(t)     (t + 0x10)

#define DDR_UMCTL2_MRCTRL0_MR_TYPE(x)            ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_MRCTRL0_MR_TYPE_M             GENMASK(0, 0)
#define DDR_UMCTL2_MRCTRL0_MR_TYPE_X(x)          ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_MRCTRL0_MPR_EN(x)             (((x) << 1) & GENMASK(1, 1))
#define DDR_UMCTL2_MRCTRL0_MPR_EN_M              GENMASK(1, 1)
#define DDR_UMCTL2_MRCTRL0_MPR_EN_X(x)           (((x) & GENMASK(1, 1)) >> 1)

#define DDR_UMCTL2_MRCTRL0_PDA_EN(x)             (((x) << 2) & GENMASK(2, 2))
#define DDR_UMCTL2_MRCTRL0_PDA_EN_M              GENMASK(2, 2)
#define DDR_UMCTL2_MRCTRL0_PDA_EN_X(x)           (((x) & GENMASK(2, 2)) >> 2)

#define DDR_UMCTL2_MRCTRL0_SW_INIT_INT(x)        (((x) << 3) & GENMASK(3, 3))
#define DDR_UMCTL2_MRCTRL0_SW_INIT_INT_M         GENMASK(3, 3)
#define DDR_UMCTL2_MRCTRL0_SW_INIT_INT_X(x)      (((x) & GENMASK(3, 3)) >> 3)

#define DDR_UMCTL2_MRCTRL0_MR_RANK(x)            (((x) << 4) & GENMASK(5, 4))
#define DDR_UMCTL2_MRCTRL0_MR_RANK_M             GENMASK(5, 4)
#define DDR_UMCTL2_MRCTRL0_MR_RANK_X(x)          (((x) & GENMASK(5, 4)) >> 4)

#define DDR_UMCTL2_MRCTRL0_MR_ADDR(x)            (((x) << 12) & GENMASK(15, 12))
#define DDR_UMCTL2_MRCTRL0_MR_ADDR_M             GENMASK(15, 12)
#define DDR_UMCTL2_MRCTRL0_MR_ADDR_X(x)          (((x) & GENMASK(15, 12)) >> 12)

#define DDR_UMCTL2_MRCTRL0_PBA_MODE(x)           (((x) << 30) & GENMASK(30, 30))
#define DDR_UMCTL2_MRCTRL0_PBA_MODE_M            GENMASK(30, 30)
#define DDR_UMCTL2_MRCTRL0_PBA_MODE_X(x)         (((x) & GENMASK(30, 30)) >> 30)

#define DDR_UMCTL2_MRCTRL0_MR_WR(x)              (((x) << 31) & GENMASK(31, 31))
#define DDR_UMCTL2_MRCTRL0_MR_WR_M               GENMASK(31, 31)
#define DDR_UMCTL2_MRCTRL0_MR_WR_X(x)            (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_UMCTL2:UMCTL2_REGS:MRCTRL1 */
#define DDR_UMCTL2_MRCTRL1(t)     (t + 0x14)

#define DDR_UMCTL2_MRCTRL1_MR_DATA(x)            ((x) & GENMASK(17, 0))
#define DDR_UMCTL2_MRCTRL1_MR_DATA_M             GENMASK(17, 0)
#define DDR_UMCTL2_MRCTRL1_MR_DATA_X(x)          ((x) & GENMASK(17, 0))

/*      DDR_UMCTL2:UMCTL2_REGS:MRSTAT */
#define DDR_UMCTL2_MRSTAT(t)      (t + 0x18)

#define DDR_UMCTL2_MRSTAT_MR_WR_BUSY(x)          ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_MRSTAT_MR_WR_BUSY_M           GENMASK(0, 0)
#define DDR_UMCTL2_MRSTAT_MR_WR_BUSY_X(x)        ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_MRSTAT_PDA_DONE(x)            (((x) << 8) & GENMASK(8, 8))
#define DDR_UMCTL2_MRSTAT_PDA_DONE_M             GENMASK(8, 8)
#define DDR_UMCTL2_MRSTAT_PDA_DONE_X(x)          (((x) & GENMASK(8, 8)) >> 8)

/*      DDR_UMCTL2:UMCTL2_REGS:MRCTRL2 */
#define DDR_UMCTL2_MRCTRL2(t)     (t + 0x1c)

/*      DDR_UMCTL2:UMCTL2_REGS:PWRCTL */
#define DDR_UMCTL2_PWRCTL(t)      (t + 0x30)

#define DDR_UMCTL2_PWRCTL_SELFREF_EN(x)          ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_PWRCTL_SELFREF_EN_M           GENMASK(0, 0)
#define DDR_UMCTL2_PWRCTL_SELFREF_EN_X(x)        ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_PWRCTL_POWERDOWN_EN(x)        (((x) << 1) & GENMASK(1, 1))
#define DDR_UMCTL2_PWRCTL_POWERDOWN_EN_M         GENMASK(1, 1)
#define DDR_UMCTL2_PWRCTL_POWERDOWN_EN_X(x)      (((x) & GENMASK(1, 1)) >> 1)

#define DDR_UMCTL2_PWRCTL_EN_DFI_DRAM_CLK_DISABLE(x)\
	(((x) << 3) & GENMASK(3, 3))
#define DDR_UMCTL2_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_M GENMASK(3, 3)
#define DDR_UMCTL2_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_X(x)\
	(((x) & GENMASK(3, 3)) >> 3)

#define DDR_UMCTL2_PWRCTL_MPSM_EN(x)             (((x) << 4) & GENMASK(4, 4))
#define DDR_UMCTL2_PWRCTL_MPSM_EN_M              GENMASK(4, 4)
#define DDR_UMCTL2_PWRCTL_MPSM_EN_X(x)           (((x) & GENMASK(4, 4)) >> 4)

#define DDR_UMCTL2_PWRCTL_SELFREF_SW(x)          (((x) << 5) & GENMASK(5, 5))
#define DDR_UMCTL2_PWRCTL_SELFREF_SW_M           GENMASK(5, 5)
#define DDR_UMCTL2_PWRCTL_SELFREF_SW_X(x)        (((x) & GENMASK(5, 5)) >> 5)

#define DDR_UMCTL2_PWRCTL_DIS_CAM_DRAIN_SELFREF(x) (((x) << 7) & GENMASK(7, 7))
#define DDR_UMCTL2_PWRCTL_DIS_CAM_DRAIN_SELFREF_M GENMASK(7, 7)
#define DDR_UMCTL2_PWRCTL_DIS_CAM_DRAIN_SELFREF_X(x)\
	(((x) & GENMASK(7, 7)) >> 7)

/*      DDR_UMCTL2:UMCTL2_REGS:PWRTMG */
#define DDR_UMCTL2_PWRTMG(t)      (t + 0x34)

#define DDR_UMCTL2_PWRTMG_POWERDOWN_TO_X32(x)    ((x) & GENMASK(4, 0))
#define DDR_UMCTL2_PWRTMG_POWERDOWN_TO_X32_M     GENMASK(4, 0)
#define DDR_UMCTL2_PWRTMG_POWERDOWN_TO_X32_X(x)  ((x) & GENMASK(4, 0))

#define DDR_UMCTL2_PWRTMG_SELFREF_TO_X32(x)      (((x) << 16) & GENMASK(23, 16))
#define DDR_UMCTL2_PWRTMG_SELFREF_TO_X32_M       GENMASK(23, 16)
#define DDR_UMCTL2_PWRTMG_SELFREF_TO_X32_X(x)    (((x) & GENMASK(23, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_REGS:HWLPCTL */
#define DDR_UMCTL2_HWLPCTL(t)     (t + 0x38)

#define DDR_UMCTL2_HWLPCTL_HW_LP_EN(x)           ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_HWLPCTL_HW_LP_EN_M            GENMASK(0, 0)
#define DDR_UMCTL2_HWLPCTL_HW_LP_EN_X(x)         ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_HWLPCTL_HW_LP_EXIT_IDLE_EN(x) (((x) << 1) & GENMASK(1, 1))
#define DDR_UMCTL2_HWLPCTL_HW_LP_EXIT_IDLE_EN_M  GENMASK(1, 1)
#define DDR_UMCTL2_HWLPCTL_HW_LP_EXIT_IDLE_EN_X(x) (((x) & GENMASK(1, 1)) >> 1)

#define DDR_UMCTL2_HWLPCTL_HW_LP_IDLE_X32(x)     (((x) << 16) & GENMASK(27, 16))
#define DDR_UMCTL2_HWLPCTL_HW_LP_IDLE_X32_M      GENMASK(27, 16)
#define DDR_UMCTL2_HWLPCTL_HW_LP_IDLE_X32_X(x)   (((x) & GENMASK(27, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_REGS:RFSHCTL0 */
#define DDR_UMCTL2_RFSHCTL0(t)    (t + 0x50)

#define DDR_UMCTL2_RFSHCTL0_REFRESH_BURST(x)     (((x) << 4) & GENMASK(9, 4))
#define DDR_UMCTL2_RFSHCTL0_REFRESH_BURST_M      GENMASK(9, 4)
#define DDR_UMCTL2_RFSHCTL0_REFRESH_BURST_X(x)   (((x) & GENMASK(9, 4)) >> 4)

#define DDR_UMCTL2_RFSHCTL0_REFRESH_TO_X1_X32(x) (((x) << 12) & GENMASK(16, 12))
#define DDR_UMCTL2_RFSHCTL0_REFRESH_TO_X1_X32_M  GENMASK(16, 12)
#define DDR_UMCTL2_RFSHCTL0_REFRESH_TO_X1_X32_X(x)\
	(((x) & GENMASK(16, 12)) >> 12)

#define DDR_UMCTL2_RFSHCTL0_REFRESH_MARGIN(x)    (((x) << 20) & GENMASK(23, 20))
#define DDR_UMCTL2_RFSHCTL0_REFRESH_MARGIN_M     GENMASK(23, 20)
#define DDR_UMCTL2_RFSHCTL0_REFRESH_MARGIN_X(x)  (((x) & GENMASK(23, 20)) >> 20)

/*      DDR_UMCTL2:UMCTL2_REGS:RFSHCTL1 */
#define DDR_UMCTL2_RFSHCTL1(t)    (t + 0x54)

#define DDR_UMCTL2_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32(x)\
	((x) & GENMASK(11, 0))
#define DDR_UMCTL2_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_M GENMASK(11, 0)
#define DDR_UMCTL2_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_X(x)\
	((x) & GENMASK(11, 0))

#define DDR_UMCTL2_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32(x)\
	(((x) << 16) & GENMASK(27, 16))
#define DDR_UMCTL2_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_M GENMASK(27, 16)
#define DDR_UMCTL2_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_X(x)\
	(((x) & GENMASK(27, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_REGS:RFSHCTL3 */
#define DDR_UMCTL2_RFSHCTL3(t)    (t + 0x60)

#define DDR_UMCTL2_RFSHCTL3_DIS_AUTO_REFRESH(x)  ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_RFSHCTL3_DIS_AUTO_REFRESH_M   GENMASK(0, 0)
#define DDR_UMCTL2_RFSHCTL3_DIS_AUTO_REFRESH_X(x) ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_RFSHCTL3_REFRESH_UPDATE_LEVEL(x) (((x) << 1) & GENMASK(1, 1))
#define DDR_UMCTL2_RFSHCTL3_REFRESH_UPDATE_LEVEL_M GENMASK(1, 1)
#define DDR_UMCTL2_RFSHCTL3_REFRESH_UPDATE_LEVEL_X(x)\
	(((x) & GENMASK(1, 1)) >> 1)

#define DDR_UMCTL2_RFSHCTL3_REFRESH_MODE(x)      (((x) << 4) & GENMASK(6, 4))
#define DDR_UMCTL2_RFSHCTL3_REFRESH_MODE_M       GENMASK(6, 4)
#define DDR_UMCTL2_RFSHCTL3_REFRESH_MODE_X(x)    (((x) & GENMASK(6, 4)) >> 4)

/*      DDR_UMCTL2:UMCTL2_REGS:RFSHTMG */
#define DDR_UMCTL2_RFSHTMG(t)     (t + 0x64)

#define DDR_UMCTL2_RFSHTMG_T_RFC_MIN(x)          ((x) & GENMASK(9, 0))
#define DDR_UMCTL2_RFSHTMG_T_RFC_MIN_M           GENMASK(9, 0)
#define DDR_UMCTL2_RFSHTMG_T_RFC_MIN_X(x)        ((x) & GENMASK(9, 0))

#define DDR_UMCTL2_RFSHTMG_T_RFC_NOM_X1_X32(x)   (((x) << 16) & GENMASK(27, 16))
#define DDR_UMCTL2_RFSHTMG_T_RFC_NOM_X1_X32_M    GENMASK(27, 16)
#define DDR_UMCTL2_RFSHTMG_T_RFC_NOM_X1_X32_X(x) (((x) & GENMASK(27, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_REGS:ECCCFG0 */
#define DDR_UMCTL2_ECCCFG0(t)     (t + 0x70)

#define DDR_UMCTL2_ECCCFG0_ECC_MODE(x)           ((x) & GENMASK(2, 0))
#define DDR_UMCTL2_ECCCFG0_ECC_MODE_M            GENMASK(2, 0)
#define DDR_UMCTL2_ECCCFG0_ECC_MODE_X(x)         ((x) & GENMASK(2, 0))

#define DDR_UMCTL2_ECCCFG0_DIS_SCRUB(x)          (((x) << 4) & GENMASK(4, 4))
#define DDR_UMCTL2_ECCCFG0_DIS_SCRUB_M           GENMASK(4, 4)
#define DDR_UMCTL2_ECCCFG0_DIS_SCRUB_X(x)        (((x) & GENMASK(4, 4)) >> 4)

#define DDR_UMCTL2_ECCCFG0_ECC_AP_EN(x)          (((x) << 6) & GENMASK(6, 6))
#define DDR_UMCTL2_ECCCFG0_ECC_AP_EN_M           GENMASK(6, 6)
#define DDR_UMCTL2_ECCCFG0_ECC_AP_EN_X(x)        (((x) & GENMASK(6, 6)) >> 6)

#define DDR_UMCTL2_ECCCFG0_ECC_REGION_REMAP_EN(x) (((x) << 7) & GENMASK(7, 7))
#define DDR_UMCTL2_ECCCFG0_ECC_REGION_REMAP_EN_M GENMASK(7, 7)
#define DDR_UMCTL2_ECCCFG0_ECC_REGION_REMAP_EN_X(x) (((x) & GENMASK(7, 7)) >> 7)

#define DDR_UMCTL2_ECCCFG0_ECC_REGION_MAP(x)     (((x) << 8) & GENMASK(14, 8))
#define DDR_UMCTL2_ECCCFG0_ECC_REGION_MAP_M      GENMASK(14, 8)
#define DDR_UMCTL2_ECCCFG0_ECC_REGION_MAP_X(x)   (((x) & GENMASK(14, 8)) >> 8)

#define DDR_UMCTL2_ECCCFG0_BLK_CHANNEL_IDLE_TIME_X32(x)\
	(((x) << 16) & GENMASK(21, 16))
#define DDR_UMCTL2_ECCCFG0_BLK_CHANNEL_IDLE_TIME_X32_M GENMASK(21, 16)
#define DDR_UMCTL2_ECCCFG0_BLK_CHANNEL_IDLE_TIME_X32_X(x)\
	(((x) & GENMASK(21, 16)) >> 16)

#define DDR_UMCTL2_ECCCFG0_ECC_AP_ERR_THRESHOLD(x)\
	(((x) << 24) & GENMASK(24, 24))
#define DDR_UMCTL2_ECCCFG0_ECC_AP_ERR_THRESHOLD_M GENMASK(24, 24)
#define DDR_UMCTL2_ECCCFG0_ECC_AP_ERR_THRESHOLD_X(x)\
	(((x) & GENMASK(24, 24)) >> 24)

#define DDR_UMCTL2_ECCCFG0_ECC_REGION_MAP_OTHER(x)\
	(((x) << 29) & GENMASK(29, 29))
#define DDR_UMCTL2_ECCCFG0_ECC_REGION_MAP_OTHER_M GENMASK(29, 29)
#define DDR_UMCTL2_ECCCFG0_ECC_REGION_MAP_OTHER_X(x)\
	(((x) & GENMASK(29, 29)) >> 29)

#define DDR_UMCTL2_ECCCFG0_ECC_REGION_MAP_GRANU(x)\
	(((x) << 30) & GENMASK(31, 30))
#define DDR_UMCTL2_ECCCFG0_ECC_REGION_MAP_GRANU_M GENMASK(31, 30)
#define DDR_UMCTL2_ECCCFG0_ECC_REGION_MAP_GRANU_X(x)\
	(((x) & GENMASK(31, 30)) >> 30)

/*      DDR_UMCTL2:UMCTL2_REGS:ECCCFG1 */
#define DDR_UMCTL2_ECCCFG1(t)     (t + 0x74)

#define DDR_UMCTL2_ECCCFG1_DATA_POISON_EN(x)     ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_ECCCFG1_DATA_POISON_EN_M      GENMASK(0, 0)
#define DDR_UMCTL2_ECCCFG1_DATA_POISON_EN_X(x)   ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_ECCCFG1_DATA_POISON_BIT(x)    (((x) << 1) & GENMASK(1, 1))
#define DDR_UMCTL2_ECCCFG1_DATA_POISON_BIT_M     GENMASK(1, 1)
#define DDR_UMCTL2_ECCCFG1_DATA_POISON_BIT_X(x)  (((x) & GENMASK(1, 1)) >> 1)

#define DDR_UMCTL2_ECCCFG1_ECC_REGION_PARITY_LOCK(x)\
	(((x) << 4) & GENMASK(4, 4))
#define DDR_UMCTL2_ECCCFG1_ECC_REGION_PARITY_LOCK_M GENMASK(4, 4)
#define DDR_UMCTL2_ECCCFG1_ECC_REGION_PARITY_LOCK_X(x)\
	(((x) & GENMASK(4, 4)) >> 4)

#define DDR_UMCTL2_ECCCFG1_ECC_REGION_WASTE_LOCK(x) (((x) << 5) & GENMASK(5, 5))
#define DDR_UMCTL2_ECCCFG1_ECC_REGION_WASTE_LOCK_M GENMASK(5, 5)
#define DDR_UMCTL2_ECCCFG1_ECC_REGION_WASTE_LOCK_X(x)\
	(((x) & GENMASK(5, 5)) >> 5)

#define DDR_UMCTL2_ECCCFG1_BLK_CHANNEL_ACTIVE_TERM(x)\
	(((x) << 7) & GENMASK(7, 7))
#define DDR_UMCTL2_ECCCFG1_BLK_CHANNEL_ACTIVE_TERM_M GENMASK(7, 7)
#define DDR_UMCTL2_ECCCFG1_BLK_CHANNEL_ACTIVE_TERM_X(x)\
	(((x) & GENMASK(7, 7)) >> 7)

#define DDR_UMCTL2_ECCCFG1_ACTIVE_BLK_CHANNEL(x) (((x) << 8) & GENMASK(12, 8))
#define DDR_UMCTL2_ECCCFG1_ACTIVE_BLK_CHANNEL_M  GENMASK(12, 8)
#define DDR_UMCTL2_ECCCFG1_ACTIVE_BLK_CHANNEL_X(x) (((x) & GENMASK(12, 8)) >> 8)

/*      DDR_UMCTL2:UMCTL2_REGS:ECCSTAT */
#define DDR_UMCTL2_ECCSTAT(t)     (t + 0x78)

#define DDR_UMCTL2_ECCSTAT_ECC_CORRECTED_BIT_NUM(x) ((x) & GENMASK(6, 0))
#define DDR_UMCTL2_ECCSTAT_ECC_CORRECTED_BIT_NUM_M GENMASK(6, 0)
#define DDR_UMCTL2_ECCSTAT_ECC_CORRECTED_BIT_NUM_X(x) ((x) & GENMASK(6, 0))

#define DDR_UMCTL2_ECCSTAT_ECC_CORRECTED_ERR(x)  (((x) << 8) & GENMASK(8, 8))
#define DDR_UMCTL2_ECCSTAT_ECC_CORRECTED_ERR_M   GENMASK(8, 8)
#define DDR_UMCTL2_ECCSTAT_ECC_CORRECTED_ERR_X(x) (((x) & GENMASK(8, 8)) >> 8)

#define DDR_UMCTL2_ECCSTAT_ECC_UNCORRECTED_ERR(x)\
	(((x) << 16) & GENMASK(16, 16))
#define DDR_UMCTL2_ECCSTAT_ECC_UNCORRECTED_ERR_M GENMASK(16, 16)
#define DDR_UMCTL2_ECCSTAT_ECC_UNCORRECTED_ERR_X(x)\
	(((x) & GENMASK(16, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_REGS:ECCCTL */
#define DDR_UMCTL2_ECCCTL(t)      (t + 0x7c)

#define DDR_UMCTL2_ECCCTL_ECC_CORRECTED_ERR_CLR(x) ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_ECCCTL_ECC_CORRECTED_ERR_CLR_M GENMASK(0, 0)
#define DDR_UMCTL2_ECCCTL_ECC_CORRECTED_ERR_CLR_X(x) ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_ECCCTL_ECC_UNCORRECTED_ERR_CLR(x)\
	(((x) << 1) & GENMASK(1, 1))
#define DDR_UMCTL2_ECCCTL_ECC_UNCORRECTED_ERR_CLR_M GENMASK(1, 1)
#define DDR_UMCTL2_ECCCTL_ECC_UNCORRECTED_ERR_CLR_X(x)\
	(((x) & GENMASK(1, 1)) >> 1)

#define DDR_UMCTL2_ECCCTL_ECC_CORR_ERR_CNT_CLR(x) (((x) << 2) & GENMASK(2, 2))
#define DDR_UMCTL2_ECCCTL_ECC_CORR_ERR_CNT_CLR_M GENMASK(2, 2)
#define DDR_UMCTL2_ECCCTL_ECC_CORR_ERR_CNT_CLR_X(x) (((x) & GENMASK(2, 2)) >> 2)

#define DDR_UMCTL2_ECCCTL_ECC_UNCORR_ERR_CNT_CLR(x) (((x) << 3) & GENMASK(3, 3))
#define DDR_UMCTL2_ECCCTL_ECC_UNCORR_ERR_CNT_CLR_M GENMASK(3, 3)
#define DDR_UMCTL2_ECCCTL_ECC_UNCORR_ERR_CNT_CLR_X(x)\
	(((x) & GENMASK(3, 3)) >> 3)

#define DDR_UMCTL2_ECCCTL_ECC_AP_ERR_INTR_CLR(x) (((x) << 4) & GENMASK(4, 4))
#define DDR_UMCTL2_ECCCTL_ECC_AP_ERR_INTR_CLR_M  GENMASK(4, 4)
#define DDR_UMCTL2_ECCCTL_ECC_AP_ERR_INTR_CLR_X(x) (((x) & GENMASK(4, 4)) >> 4)

#define DDR_UMCTL2_ECCCTL_ECC_CORRECTED_ERR_INTR_EN(x)\
	(((x) << 8) & GENMASK(8, 8))
#define DDR_UMCTL2_ECCCTL_ECC_CORRECTED_ERR_INTR_EN_M GENMASK(8, 8)
#define DDR_UMCTL2_ECCCTL_ECC_CORRECTED_ERR_INTR_EN_X(x)\
	(((x) & GENMASK(8, 8)) >> 8)

#define DDR_UMCTL2_ECCCTL_ECC_UNCORRECTED_ERR_INTR_EN(x)\
	(((x) << 9) & GENMASK(9, 9))
#define DDR_UMCTL2_ECCCTL_ECC_UNCORRECTED_ERR_INTR_EN_M GENMASK(9, 9)
#define DDR_UMCTL2_ECCCTL_ECC_UNCORRECTED_ERR_INTR_EN_X(x)\
	(((x) & GENMASK(9, 9)) >> 9)

#define DDR_UMCTL2_ECCCTL_ECC_AP_ERR_INTR_EN(x)  (((x) << 10) & GENMASK(10, 10))
#define DDR_UMCTL2_ECCCTL_ECC_AP_ERR_INTR_EN_M   GENMASK(10, 10)
#define DDR_UMCTL2_ECCCTL_ECC_AP_ERR_INTR_EN_X(x)\
	(((x) & GENMASK(10, 10)) >> 10)

#define DDR_UMCTL2_ECCCTL_ECC_CORRECTED_ERR_INTR_FORCE(x)\
	(((x) << 16) & GENMASK(16, 16))
#define DDR_UMCTL2_ECCCTL_ECC_CORRECTED_ERR_INTR_FORCE_M GENMASK(16, 16)
#define DDR_UMCTL2_ECCCTL_ECC_CORRECTED_ERR_INTR_FORCE_X(x)\
	(((x) & GENMASK(16, 16)) >> 16)

#define DDR_UMCTL2_ECCCTL_ECC_UNCORRECTED_ERR_INTR_FORCE(x)\
	(((x) << 17) & GENMASK(17, 17))
#define DDR_UMCTL2_ECCCTL_ECC_UNCORRECTED_ERR_INTR_FORCE_M GENMASK(17, 17)
#define DDR_UMCTL2_ECCCTL_ECC_UNCORRECTED_ERR_INTR_FORCE_X(x)\
	(((x) & GENMASK(17, 17)) >> 17)

#define DDR_UMCTL2_ECCCTL_ECC_AP_ERR_INTR_FORCE(x)\
	(((x) << 18) & GENMASK(18, 18))
#define DDR_UMCTL2_ECCCTL_ECC_AP_ERR_INTR_FORCE_M GENMASK(18, 18)
#define DDR_UMCTL2_ECCCTL_ECC_AP_ERR_INTR_FORCE_X(x)\
	(((x) & GENMASK(18, 18)) >> 18)

/*      DDR_UMCTL2:UMCTL2_REGS:ECCERRCNT */
#define DDR_UMCTL2_ECCERRCNT(t)   (t + 0x80)

#define DDR_UMCTL2_ECCERRCNT_ECC_CORR_ERR_CNT(x) ((x) & GENMASK(15, 0))
#define DDR_UMCTL2_ECCERRCNT_ECC_CORR_ERR_CNT_M  GENMASK(15, 0)
#define DDR_UMCTL2_ECCERRCNT_ECC_CORR_ERR_CNT_X(x) ((x) & GENMASK(15, 0))

#define DDR_UMCTL2_ECCERRCNT_ECC_UNCORR_ERR_CNT(x)\
	(((x) << 16) & GENMASK(31, 16))
#define DDR_UMCTL2_ECCERRCNT_ECC_UNCORR_ERR_CNT_M GENMASK(31, 16)
#define DDR_UMCTL2_ECCERRCNT_ECC_UNCORR_ERR_CNT_X(x)\
	(((x) & GENMASK(31, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_REGS:ECCCADDR0 */
#define DDR_UMCTL2_ECCCADDR0(t)   (t + 0x84)

#define DDR_UMCTL2_ECCCADDR0_ECC_CORR_ROW(x)     ((x) & GENMASK(17, 0))
#define DDR_UMCTL2_ECCCADDR0_ECC_CORR_ROW_M      GENMASK(17, 0)
#define DDR_UMCTL2_ECCCADDR0_ECC_CORR_ROW_X(x)   ((x) & GENMASK(17, 0))

#define DDR_UMCTL2_ECCCADDR0_ECC_CORR_RANK(x)    (((x) << 24) & GENMASK(24, 24))
#define DDR_UMCTL2_ECCCADDR0_ECC_CORR_RANK_M     GENMASK(24, 24)
#define DDR_UMCTL2_ECCCADDR0_ECC_CORR_RANK_X(x)  (((x) & GENMASK(24, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:ECCCADDR1 */
#define DDR_UMCTL2_ECCCADDR1(t)   (t + 0x88)

#define DDR_UMCTL2_ECCCADDR1_ECC_CORR_COL(x)     ((x) & GENMASK(11, 0))
#define DDR_UMCTL2_ECCCADDR1_ECC_CORR_COL_M      GENMASK(11, 0)
#define DDR_UMCTL2_ECCCADDR1_ECC_CORR_COL_X(x)   ((x) & GENMASK(11, 0))

#define DDR_UMCTL2_ECCCADDR1_ECC_CORR_BANK(x)    (((x) << 16) & GENMASK(18, 16))
#define DDR_UMCTL2_ECCCADDR1_ECC_CORR_BANK_M     GENMASK(18, 16)
#define DDR_UMCTL2_ECCCADDR1_ECC_CORR_BANK_X(x)  (((x) & GENMASK(18, 16)) >> 16)

#define DDR_UMCTL2_ECCCADDR1_ECC_CORR_BG(x)      (((x) << 24) & GENMASK(25, 24))
#define DDR_UMCTL2_ECCCADDR1_ECC_CORR_BG_M       GENMASK(25, 24)
#define DDR_UMCTL2_ECCCADDR1_ECC_CORR_BG_X(x)    (((x) & GENMASK(25, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:ECCCSYN0 */
#define DDR_UMCTL2_ECCCSYN0(t)    (t + 0x8c)

/*      DDR_UMCTL2:UMCTL2_REGS:ECCCSYN1 */
#define DDR_UMCTL2_ECCCSYN1(t)    (t + 0x90)

/*      DDR_UMCTL2:UMCTL2_REGS:ECCCSYN2 */
#define DDR_UMCTL2_ECCCSYN2(t)    (t + 0x94)

#define DDR_UMCTL2_ECCCSYN2_ECC_CORR_SYNDROMES_71_64(x) ((x) & GENMASK(7, 0))
#define DDR_UMCTL2_ECCCSYN2_ECC_CORR_SYNDROMES_71_64_M GENMASK(7, 0)
#define DDR_UMCTL2_ECCCSYN2_ECC_CORR_SYNDROMES_71_64_X(x) ((x) & GENMASK(7, 0))

/*      DDR_UMCTL2:UMCTL2_REGS:ECCBITMASK0 */
#define DDR_UMCTL2_ECCBITMASK0(t) (t + 0x98)

/*      DDR_UMCTL2:UMCTL2_REGS:ECCBITMASK1 */
#define DDR_UMCTL2_ECCBITMASK1(t) (t + 0x9c)

/*      DDR_UMCTL2:UMCTL2_REGS:ECCBITMASK2 */
#define DDR_UMCTL2_ECCBITMASK2(t) (t + 0xa0)

#define DDR_UMCTL2_ECCBITMASK2_ECC_CORR_BIT_MASK_71_64(x) ((x) & GENMASK(7, 0))
#define DDR_UMCTL2_ECCBITMASK2_ECC_CORR_BIT_MASK_71_64_M GENMASK(7, 0)
#define DDR_UMCTL2_ECCBITMASK2_ECC_CORR_BIT_MASK_71_64_X(x)\
	((x) & GENMASK(7, 0))

/*      DDR_UMCTL2:UMCTL2_REGS:ECCUADDR0 */
#define DDR_UMCTL2_ECCUADDR0(t)   (t + 0xa4)

#define DDR_UMCTL2_ECCUADDR0_ECC_UNCORR_ROW(x)   ((x) & GENMASK(17, 0))
#define DDR_UMCTL2_ECCUADDR0_ECC_UNCORR_ROW_M    GENMASK(17, 0)
#define DDR_UMCTL2_ECCUADDR0_ECC_UNCORR_ROW_X(x) ((x) & GENMASK(17, 0))

#define DDR_UMCTL2_ECCUADDR0_ECC_UNCORR_RANK(x)  (((x) << 24) & GENMASK(24, 24))
#define DDR_UMCTL2_ECCUADDR0_ECC_UNCORR_RANK_M   GENMASK(24, 24)
#define DDR_UMCTL2_ECCUADDR0_ECC_UNCORR_RANK_X(x)\
	(((x) & GENMASK(24, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:ECCUADDR1 */
#define DDR_UMCTL2_ECCUADDR1(t)   (t + 0xa8)

#define DDR_UMCTL2_ECCUADDR1_ECC_UNCORR_COL(x)   ((x) & GENMASK(11, 0))
#define DDR_UMCTL2_ECCUADDR1_ECC_UNCORR_COL_M    GENMASK(11, 0)
#define DDR_UMCTL2_ECCUADDR1_ECC_UNCORR_COL_X(x) ((x) & GENMASK(11, 0))

#define DDR_UMCTL2_ECCUADDR1_ECC_UNCORR_BANK(x)  (((x) << 16) & GENMASK(18, 16))
#define DDR_UMCTL2_ECCUADDR1_ECC_UNCORR_BANK_M   GENMASK(18, 16)
#define DDR_UMCTL2_ECCUADDR1_ECC_UNCORR_BANK_X(x)\
	(((x) & GENMASK(18, 16)) >> 16)

#define DDR_UMCTL2_ECCUADDR1_ECC_UNCORR_BG(x)    (((x) << 24) & GENMASK(25, 24))
#define DDR_UMCTL2_ECCUADDR1_ECC_UNCORR_BG_M     GENMASK(25, 24)
#define DDR_UMCTL2_ECCUADDR1_ECC_UNCORR_BG_X(x)  (((x) & GENMASK(25, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:ECCUSYN0 */
#define DDR_UMCTL2_ECCUSYN0(t)    (t + 0xac)

/*      DDR_UMCTL2:UMCTL2_REGS:ECCUSYN1 */
#define DDR_UMCTL2_ECCUSYN1(t)    (t + 0xb0)

/*      DDR_UMCTL2:UMCTL2_REGS:ECCUSYN2 */
#define DDR_UMCTL2_ECCUSYN2(t)    (t + 0xb4)

#define DDR_UMCTL2_ECCUSYN2_ECC_UNCORR_SYNDROMES_71_64(x) ((x) & GENMASK(7, 0))
#define DDR_UMCTL2_ECCUSYN2_ECC_UNCORR_SYNDROMES_71_64_M GENMASK(7, 0)
#define DDR_UMCTL2_ECCUSYN2_ECC_UNCORR_SYNDROMES_71_64_X(x)\
	((x) & GENMASK(7, 0))

/*      DDR_UMCTL2:UMCTL2_REGS:ECCPOISONADDR0 */
#define DDR_UMCTL2_ECCPOISONADDR0(t) (t + 0xb8)

#define DDR_UMCTL2_ECCPOISONADDR0_ECC_POISON_COL(x) ((x) & GENMASK(11, 0))
#define DDR_UMCTL2_ECCPOISONADDR0_ECC_POISON_COL_M GENMASK(11, 0)
#define DDR_UMCTL2_ECCPOISONADDR0_ECC_POISON_COL_X(x) ((x) & GENMASK(11, 0))

#define DDR_UMCTL2_ECCPOISONADDR0_ECC_POISON_RANK(x)\
	(((x) << 24) & GENMASK(24, 24))
#define DDR_UMCTL2_ECCPOISONADDR0_ECC_POISON_RANK_M GENMASK(24, 24)
#define DDR_UMCTL2_ECCPOISONADDR0_ECC_POISON_RANK_X(x)\
	(((x) & GENMASK(24, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:ECCPOISONADDR1 */
#define DDR_UMCTL2_ECCPOISONADDR1(t) (t + 0xbc)

#define DDR_UMCTL2_ECCPOISONADDR1_ECC_POISON_ROW(x) ((x) & GENMASK(17, 0))
#define DDR_UMCTL2_ECCPOISONADDR1_ECC_POISON_ROW_M GENMASK(17, 0)
#define DDR_UMCTL2_ECCPOISONADDR1_ECC_POISON_ROW_X(x) ((x) & GENMASK(17, 0))

#define DDR_UMCTL2_ECCPOISONADDR1_ECC_POISON_BANK(x)\
	(((x) << 24) & GENMASK(26, 24))
#define DDR_UMCTL2_ECCPOISONADDR1_ECC_POISON_BANK_M GENMASK(26, 24)
#define DDR_UMCTL2_ECCPOISONADDR1_ECC_POISON_BANK_X(x)\
	(((x) & GENMASK(26, 24)) >> 24)

#define DDR_UMCTL2_ECCPOISONADDR1_ECC_POISON_BG(x)\
	(((x) << 28) & GENMASK(29, 28))
#define DDR_UMCTL2_ECCPOISONADDR1_ECC_POISON_BG_M GENMASK(29, 28)
#define DDR_UMCTL2_ECCPOISONADDR1_ECC_POISON_BG_X(x)\
	(((x) & GENMASK(29, 28)) >> 28)

/*      DDR_UMCTL2:UMCTL2_REGS:CRCPARCTL0 */
#define DDR_UMCTL2_CRCPARCTL0(t)  (t + 0xc0)

#define DDR_UMCTL2_CRCPARCTL0_DFI_ALERT_ERR_INT_EN(x) ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_M GENMASK(0, 0)
#define DDR_UMCTL2_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_X(x) ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR(x)\
	(((x) << 1) & GENMASK(1, 1))
#define DDR_UMCTL2_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_M GENMASK(1, 1)
#define DDR_UMCTL2_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_X(x)\
	(((x) & GENMASK(1, 1)) >> 1)

#define DDR_UMCTL2_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR(x)\
	(((x) << 2) & GENMASK(2, 2))
#define DDR_UMCTL2_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_M GENMASK(2, 2)
#define DDR_UMCTL2_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_X(x)\
	(((x) & GENMASK(2, 2)) >> 2)

/*      DDR_UMCTL2:UMCTL2_REGS:CRCPARCTL1 */
#define DDR_UMCTL2_CRCPARCTL1(t)  (t + 0xc4)

#define DDR_UMCTL2_CRCPARCTL1_PARITY_ENABLE(x)   ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_CRCPARCTL1_PARITY_ENABLE_M    GENMASK(0, 0)
#define DDR_UMCTL2_CRCPARCTL1_PARITY_ENABLE_X(x) ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_CRCPARCTL1_CRC_ENABLE(x)      (((x) << 4) & GENMASK(4, 4))
#define DDR_UMCTL2_CRCPARCTL1_CRC_ENABLE_M       GENMASK(4, 4)
#define DDR_UMCTL2_CRCPARCTL1_CRC_ENABLE_X(x)    (((x) & GENMASK(4, 4)) >> 4)

#define DDR_UMCTL2_CRCPARCTL1_CRC_INC_DM(x)      (((x) << 7) & GENMASK(7, 7))
#define DDR_UMCTL2_CRCPARCTL1_CRC_INC_DM_M       GENMASK(7, 7)
#define DDR_UMCTL2_CRCPARCTL1_CRC_INC_DM_X(x)    (((x) & GENMASK(7, 7)) >> 7)

#define DDR_UMCTL2_CRCPARCTL1_CAPARITY_DISABLE_BEFORE_SR(x)\
	(((x) << 12) & GENMASK(12, 12))
#define DDR_UMCTL2_CRCPARCTL1_CAPARITY_DISABLE_BEFORE_SR_M GENMASK(12, 12)
#define DDR_UMCTL2_CRCPARCTL1_CAPARITY_DISABLE_BEFORE_SR_X(x)\
	(((x) & GENMASK(12, 12)) >> 12)

/*      DDR_UMCTL2:UMCTL2_REGS:CRCPARSTAT */
#define DDR_UMCTL2_CRCPARSTAT(t)  (t + 0xcc)

#define DDR_UMCTL2_CRCPARSTAT_DFI_ALERT_ERR_CNT(x) ((x) & GENMASK(15, 0))
#define DDR_UMCTL2_CRCPARSTAT_DFI_ALERT_ERR_CNT_M GENMASK(15, 0)
#define DDR_UMCTL2_CRCPARSTAT_DFI_ALERT_ERR_CNT_X(x) ((x) & GENMASK(15, 0))

#define DDR_UMCTL2_CRCPARSTAT_DFI_ALERT_ERR_INT(x)\
	(((x) << 16) & GENMASK(16, 16))
#define DDR_UMCTL2_CRCPARSTAT_DFI_ALERT_ERR_INT_M GENMASK(16, 16)
#define DDR_UMCTL2_CRCPARSTAT_DFI_ALERT_ERR_INT_X(x)\
	(((x) & GENMASK(16, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_REGS:INIT0 */
#define DDR_UMCTL2_INIT0(t)       (t + 0xd0)

#define DDR_UMCTL2_INIT0_PRE_CKE_X1024(x)        ((x) & GENMASK(11, 0))
#define DDR_UMCTL2_INIT0_PRE_CKE_X1024_M         GENMASK(11, 0)
#define DDR_UMCTL2_INIT0_PRE_CKE_X1024_X(x)      ((x) & GENMASK(11, 0))

#define DDR_UMCTL2_INIT0_POST_CKE_X1024(x)       (((x) << 16) & GENMASK(25, 16))
#define DDR_UMCTL2_INIT0_POST_CKE_X1024_M        GENMASK(25, 16)
#define DDR_UMCTL2_INIT0_POST_CKE_X1024_X(x)     (((x) & GENMASK(25, 16)) >> 16)

#define DDR_UMCTL2_INIT0_SKIP_DRAM_INIT(x)       (((x) << 30) & GENMASK(31, 30))
#define DDR_UMCTL2_INIT0_SKIP_DRAM_INIT_M        GENMASK(31, 30)
#define DDR_UMCTL2_INIT0_SKIP_DRAM_INIT_X(x)     (((x) & GENMASK(31, 30)) >> 30)

/*      DDR_UMCTL2:UMCTL2_REGS:INIT1 */
#define DDR_UMCTL2_INIT1(t)       (t + 0xd4)

#define DDR_UMCTL2_INIT1_PRE_OCD_X32(x)          ((x) & GENMASK(3, 0))
#define DDR_UMCTL2_INIT1_PRE_OCD_X32_M           GENMASK(3, 0)
#define DDR_UMCTL2_INIT1_PRE_OCD_X32_X(x)        ((x) & GENMASK(3, 0))

#define DDR_UMCTL2_INIT1_DRAM_RSTN_X1024(x)      (((x) << 16) & GENMASK(24, 16))
#define DDR_UMCTL2_INIT1_DRAM_RSTN_X1024_M       GENMASK(24, 16)
#define DDR_UMCTL2_INIT1_DRAM_RSTN_X1024_X(x)    (((x) & GENMASK(24, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_REGS:INIT3 */
#define DDR_UMCTL2_INIT3(t)       (t + 0xdc)

#define DDR_UMCTL2_INIT3_EMR(x)                  ((x) & GENMASK(15, 0))
#define DDR_UMCTL2_INIT3_EMR_M                   GENMASK(15, 0)
#define DDR_UMCTL2_INIT3_EMR_X(x)                ((x) & GENMASK(15, 0))

#define DDR_UMCTL2_INIT3_MR(x)                   (((x) << 16) & GENMASK(31, 16))
#define DDR_UMCTL2_INIT3_MR_M                    GENMASK(31, 16)
#define DDR_UMCTL2_INIT3_MR_X(x)                 (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_REGS:INIT4 */
#define DDR_UMCTL2_INIT4(t)       (t + 0xe0)

#define DDR_UMCTL2_INIT4_EMR3(x)                 ((x) & GENMASK(15, 0))
#define DDR_UMCTL2_INIT4_EMR3_M                  GENMASK(15, 0)
#define DDR_UMCTL2_INIT4_EMR3_X(x)               ((x) & GENMASK(15, 0))

#define DDR_UMCTL2_INIT4_EMR2(x)                 (((x) << 16) & GENMASK(31, 16))
#define DDR_UMCTL2_INIT4_EMR2_M                  GENMASK(31, 16)
#define DDR_UMCTL2_INIT4_EMR2_X(x)               (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_REGS:INIT5 */
#define DDR_UMCTL2_INIT5(t)       (t + 0xe4)

#define DDR_UMCTL2_INIT5_DEV_ZQINIT_X32(x)       (((x) << 16) & GENMASK(23, 16))
#define DDR_UMCTL2_INIT5_DEV_ZQINIT_X32_M        GENMASK(23, 16)
#define DDR_UMCTL2_INIT5_DEV_ZQINIT_X32_X(x)     (((x) & GENMASK(23, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_REGS:INIT6 */
#define DDR_UMCTL2_INIT6(t)       (t + 0xe8)

#define DDR_UMCTL2_INIT6_MR5(x)                  ((x) & GENMASK(15, 0))
#define DDR_UMCTL2_INIT6_MR5_M                   GENMASK(15, 0)
#define DDR_UMCTL2_INIT6_MR5_X(x)                ((x) & GENMASK(15, 0))

#define DDR_UMCTL2_INIT6_MR4(x)                  (((x) << 16) & GENMASK(31, 16))
#define DDR_UMCTL2_INIT6_MR4_M                   GENMASK(31, 16)
#define DDR_UMCTL2_INIT6_MR4_X(x)                (((x) & GENMASK(31, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_REGS:INIT7 */
#define DDR_UMCTL2_INIT7(t)       (t + 0xec)

#define DDR_UMCTL2_INIT7_MR6(x)                  ((x) & GENMASK(15, 0))
#define DDR_UMCTL2_INIT7_MR6_M                   GENMASK(15, 0)
#define DDR_UMCTL2_INIT7_MR6_X(x)                ((x) & GENMASK(15, 0))

/*      DDR_UMCTL2:UMCTL2_REGS:DIMMCTL */
#define DDR_UMCTL2_DIMMCTL(t)     (t + 0xf0)

#define DDR_UMCTL2_DIMMCTL_DIMM_STAGGER_CS_EN(x) ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_DIMMCTL_DIMM_STAGGER_CS_EN_M  GENMASK(0, 0)
#define DDR_UMCTL2_DIMMCTL_DIMM_STAGGER_CS_EN_X(x) ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_DIMMCTL_DIMM_ADDR_MIRR_EN(x)  (((x) << 1) & GENMASK(1, 1))
#define DDR_UMCTL2_DIMMCTL_DIMM_ADDR_MIRR_EN_M   GENMASK(1, 1)
#define DDR_UMCTL2_DIMMCTL_DIMM_ADDR_MIRR_EN_X(x) (((x) & GENMASK(1, 1)) >> 1)

#define DDR_UMCTL2_DIMMCTL_DIMM_OUTPUT_INV_EN(x) (((x) << 2) & GENMASK(2, 2))
#define DDR_UMCTL2_DIMMCTL_DIMM_OUTPUT_INV_EN_M  GENMASK(2, 2)
#define DDR_UMCTL2_DIMMCTL_DIMM_OUTPUT_INV_EN_X(x) (((x) & GENMASK(2, 2)) >> 2)

#define DDR_UMCTL2_DIMMCTL_MRS_A17_EN(x)         (((x) << 3) & GENMASK(3, 3))
#define DDR_UMCTL2_DIMMCTL_MRS_A17_EN_M          GENMASK(3, 3)
#define DDR_UMCTL2_DIMMCTL_MRS_A17_EN_X(x)       (((x) & GENMASK(3, 3)) >> 3)

#define DDR_UMCTL2_DIMMCTL_MRS_BG1_EN(x)         (((x) << 4) & GENMASK(4, 4))
#define DDR_UMCTL2_DIMMCTL_MRS_BG1_EN_M          GENMASK(4, 4)
#define DDR_UMCTL2_DIMMCTL_MRS_BG1_EN_X(x)       (((x) & GENMASK(4, 4)) >> 4)

#define DDR_UMCTL2_DIMMCTL_DIMM_DIS_BG_MIRRORING(x) (((x) << 5) & GENMASK(5, 5))
#define DDR_UMCTL2_DIMMCTL_DIMM_DIS_BG_MIRRORING_M GENMASK(5, 5)
#define DDR_UMCTL2_DIMMCTL_DIMM_DIS_BG_MIRRORING_X(x)\
	(((x) & GENMASK(5, 5)) >> 5)

#define DDR_UMCTL2_DIMMCTL_LRDIMM_BCOM_CMD_PROT(x) (((x) << 6) & GENMASK(6, 6))
#define DDR_UMCTL2_DIMMCTL_LRDIMM_BCOM_CMD_PROT_M GENMASK(6, 6)
#define DDR_UMCTL2_DIMMCTL_LRDIMM_BCOM_CMD_PROT_X(x)\
	(((x) & GENMASK(6, 6)) >> 6)

#define DDR_UMCTL2_DIMMCTL_RCD_WEAK_DRIVE(x)     (((x) << 12) & GENMASK(12, 12))
#define DDR_UMCTL2_DIMMCTL_RCD_WEAK_DRIVE_M      GENMASK(12, 12)
#define DDR_UMCTL2_DIMMCTL_RCD_WEAK_DRIVE_X(x)   (((x) & GENMASK(12, 12)) >> 12)

#define DDR_UMCTL2_DIMMCTL_RCD_A_OUTPUT_DISABLED(x)\
	(((x) << 13) & GENMASK(13, 13))
#define DDR_UMCTL2_DIMMCTL_RCD_A_OUTPUT_DISABLED_M GENMASK(13, 13)
#define DDR_UMCTL2_DIMMCTL_RCD_A_OUTPUT_DISABLED_X(x)\
	(((x) & GENMASK(13, 13)) >> 13)

#define DDR_UMCTL2_DIMMCTL_RCD_B_OUTPUT_DISABLED(x)\
	(((x) << 14) & GENMASK(14, 14))
#define DDR_UMCTL2_DIMMCTL_RCD_B_OUTPUT_DISABLED_M GENMASK(14, 14)
#define DDR_UMCTL2_DIMMCTL_RCD_B_OUTPUT_DISABLED_X(x)\
	(((x) & GENMASK(14, 14)) >> 14)

/*      DDR_UMCTL2:UMCTL2_REGS:RANKCTL */
#define DDR_UMCTL2_RANKCTL(t)     (t + 0xf4)

#define DDR_UMCTL2_RANKCTL_MAX_RANK_RD(x)        ((x) & GENMASK(3, 0))
#define DDR_UMCTL2_RANKCTL_MAX_RANK_RD_M         GENMASK(3, 0)
#define DDR_UMCTL2_RANKCTL_MAX_RANK_RD_X(x)      ((x) & GENMASK(3, 0))

#define DDR_UMCTL2_RANKCTL_DIFF_RANK_RD_GAP(x)   (((x) << 4) & GENMASK(7, 4))
#define DDR_UMCTL2_RANKCTL_DIFF_RANK_RD_GAP_M    GENMASK(7, 4)
#define DDR_UMCTL2_RANKCTL_DIFF_RANK_RD_GAP_X(x) (((x) & GENMASK(7, 4)) >> 4)

#define DDR_UMCTL2_RANKCTL_DIFF_RANK_WR_GAP(x)   (((x) << 8) & GENMASK(11, 8))
#define DDR_UMCTL2_RANKCTL_DIFF_RANK_WR_GAP_M    GENMASK(11, 8)
#define DDR_UMCTL2_RANKCTL_DIFF_RANK_WR_GAP_X(x) (((x) & GENMASK(11, 8)) >> 8)

#define DDR_UMCTL2_RANKCTL_MAX_RANK_WR(x)        (((x) << 12) & GENMASK(15, 12))
#define DDR_UMCTL2_RANKCTL_MAX_RANK_WR_M         GENMASK(15, 12)
#define DDR_UMCTL2_RANKCTL_MAX_RANK_WR_X(x)      (((x) & GENMASK(15, 12)) >> 12)

#define DDR_UMCTL2_RANKCTL_DIFF_RANK_RD_GAP_MSB(x)\
	(((x) << 24) & GENMASK(24, 24))
#define DDR_UMCTL2_RANKCTL_DIFF_RANK_RD_GAP_MSB_M GENMASK(24, 24)
#define DDR_UMCTL2_RANKCTL_DIFF_RANK_RD_GAP_MSB_X(x)\
	(((x) & GENMASK(24, 24)) >> 24)

#define DDR_UMCTL2_RANKCTL_DIFF_RANK_WR_GAP_MSB(x)\
	(((x) << 26) & GENMASK(26, 26))
#define DDR_UMCTL2_RANKCTL_DIFF_RANK_WR_GAP_MSB_M GENMASK(26, 26)
#define DDR_UMCTL2_RANKCTL_DIFF_RANK_WR_GAP_MSB_X(x)\
	(((x) & GENMASK(26, 26)) >> 26)

/*      DDR_UMCTL2:UMCTL2_REGS:DRAMTMG0 */
#define DDR_UMCTL2_DRAMTMG0(t)    (t + 0x100)

#define DDR_UMCTL2_DRAMTMG0_T_RAS_MIN(x)         ((x) & GENMASK(5, 0))
#define DDR_UMCTL2_DRAMTMG0_T_RAS_MIN_M          GENMASK(5, 0)
#define DDR_UMCTL2_DRAMTMG0_T_RAS_MIN_X(x)       ((x) & GENMASK(5, 0))

#define DDR_UMCTL2_DRAMTMG0_T_RAS_MAX(x)         (((x) << 8) & GENMASK(14, 8))
#define DDR_UMCTL2_DRAMTMG0_T_RAS_MAX_M          GENMASK(14, 8)
#define DDR_UMCTL2_DRAMTMG0_T_RAS_MAX_X(x)       (((x) & GENMASK(14, 8)) >> 8)

#define DDR_UMCTL2_DRAMTMG0_T_FAW(x)             (((x) << 16) & GENMASK(21, 16))
#define DDR_UMCTL2_DRAMTMG0_T_FAW_M              GENMASK(21, 16)
#define DDR_UMCTL2_DRAMTMG0_T_FAW_X(x)           (((x) & GENMASK(21, 16)) >> 16)

#define DDR_UMCTL2_DRAMTMG0_WR2PRE(x)            (((x) << 24) & GENMASK(30, 24))
#define DDR_UMCTL2_DRAMTMG0_WR2PRE_M             GENMASK(30, 24)
#define DDR_UMCTL2_DRAMTMG0_WR2PRE_X(x)          (((x) & GENMASK(30, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:DRAMTMG1 */
#define DDR_UMCTL2_DRAMTMG1(t)    (t + 0x104)

#define DDR_UMCTL2_DRAMTMG1_T_RC(x)              ((x) & GENMASK(6, 0))
#define DDR_UMCTL2_DRAMTMG1_T_RC_M               GENMASK(6, 0)
#define DDR_UMCTL2_DRAMTMG1_T_RC_X(x)            ((x) & GENMASK(6, 0))

#define DDR_UMCTL2_DRAMTMG1_RD2PRE(x)            (((x) << 8) & GENMASK(13, 8))
#define DDR_UMCTL2_DRAMTMG1_RD2PRE_M             GENMASK(13, 8)
#define DDR_UMCTL2_DRAMTMG1_RD2PRE_X(x)          (((x) & GENMASK(13, 8)) >> 8)

#define DDR_UMCTL2_DRAMTMG1_T_XP(x)              (((x) << 16) & GENMASK(20, 16))
#define DDR_UMCTL2_DRAMTMG1_T_XP_M               GENMASK(20, 16)
#define DDR_UMCTL2_DRAMTMG1_T_XP_X(x)            (((x) & GENMASK(20, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_REGS:DRAMTMG2 */
#define DDR_UMCTL2_DRAMTMG2(t)    (t + 0x108)

#define DDR_UMCTL2_DRAMTMG2_WR2RD(x)             ((x) & GENMASK(5, 0))
#define DDR_UMCTL2_DRAMTMG2_WR2RD_M              GENMASK(5, 0)
#define DDR_UMCTL2_DRAMTMG2_WR2RD_X(x)           ((x) & GENMASK(5, 0))

#define DDR_UMCTL2_DRAMTMG2_RD2WR(x)             (((x) << 8) & GENMASK(13, 8))
#define DDR_UMCTL2_DRAMTMG2_RD2WR_M              GENMASK(13, 8)
#define DDR_UMCTL2_DRAMTMG2_RD2WR_X(x)           (((x) & GENMASK(13, 8)) >> 8)

#define DDR_UMCTL2_DRAMTMG2_READ_LATENCY(x)      (((x) << 16) & GENMASK(21, 16))
#define DDR_UMCTL2_DRAMTMG2_READ_LATENCY_M       GENMASK(21, 16)
#define DDR_UMCTL2_DRAMTMG2_READ_LATENCY_X(x)    (((x) & GENMASK(21, 16)) >> 16)

#define DDR_UMCTL2_DRAMTMG2_WRITE_LATENCY(x)     (((x) << 24) & GENMASK(29, 24))
#define DDR_UMCTL2_DRAMTMG2_WRITE_LATENCY_M      GENMASK(29, 24)
#define DDR_UMCTL2_DRAMTMG2_WRITE_LATENCY_X(x)   (((x) & GENMASK(29, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:DRAMTMG3 */
#define DDR_UMCTL2_DRAMTMG3(t)    (t + 0x10c)

#define DDR_UMCTL2_DRAMTMG3_T_MOD(x)             ((x) & GENMASK(9, 0))
#define DDR_UMCTL2_DRAMTMG3_T_MOD_M              GENMASK(9, 0)
#define DDR_UMCTL2_DRAMTMG3_T_MOD_X(x)           ((x) & GENMASK(9, 0))

#define DDR_UMCTL2_DRAMTMG3_T_MRD(x)             (((x) << 12) & GENMASK(17, 12))
#define DDR_UMCTL2_DRAMTMG3_T_MRD_M              GENMASK(17, 12)
#define DDR_UMCTL2_DRAMTMG3_T_MRD_X(x)           (((x) & GENMASK(17, 12)) >> 12)

/*      DDR_UMCTL2:UMCTL2_REGS:DRAMTMG4 */
#define DDR_UMCTL2_DRAMTMG4(t)    (t + 0x110)

#define DDR_UMCTL2_DRAMTMG4_T_RP(x)              ((x) & GENMASK(4, 0))
#define DDR_UMCTL2_DRAMTMG4_T_RP_M               GENMASK(4, 0)
#define DDR_UMCTL2_DRAMTMG4_T_RP_X(x)            ((x) & GENMASK(4, 0))

#define DDR_UMCTL2_DRAMTMG4_T_RRD(x)             (((x) << 8) & GENMASK(11, 8))
#define DDR_UMCTL2_DRAMTMG4_T_RRD_M              GENMASK(11, 8)
#define DDR_UMCTL2_DRAMTMG4_T_RRD_X(x)           (((x) & GENMASK(11, 8)) >> 8)

#define DDR_UMCTL2_DRAMTMG4_T_CCD(x)             (((x) << 16) & GENMASK(19, 16))
#define DDR_UMCTL2_DRAMTMG4_T_CCD_M              GENMASK(19, 16)
#define DDR_UMCTL2_DRAMTMG4_T_CCD_X(x)           (((x) & GENMASK(19, 16)) >> 16)

#define DDR_UMCTL2_DRAMTMG4_T_RCD(x)             (((x) << 24) & GENMASK(28, 24))
#define DDR_UMCTL2_DRAMTMG4_T_RCD_M              GENMASK(28, 24)
#define DDR_UMCTL2_DRAMTMG4_T_RCD_X(x)           (((x) & GENMASK(28, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:DRAMTMG5 */
#define DDR_UMCTL2_DRAMTMG5(t)    (t + 0x114)

#define DDR_UMCTL2_DRAMTMG5_T_CKE(x)             ((x) & GENMASK(4, 0))
#define DDR_UMCTL2_DRAMTMG5_T_CKE_M              GENMASK(4, 0)
#define DDR_UMCTL2_DRAMTMG5_T_CKE_X(x)           ((x) & GENMASK(4, 0))

#define DDR_UMCTL2_DRAMTMG5_T_CKESR(x)           (((x) << 8) & GENMASK(15, 8))
#define DDR_UMCTL2_DRAMTMG5_T_CKESR_M            GENMASK(15, 8)
#define DDR_UMCTL2_DRAMTMG5_T_CKESR_X(x)         (((x) & GENMASK(15, 8)) >> 8)

#define DDR_UMCTL2_DRAMTMG5_T_CKSRE(x)           (((x) << 16) & GENMASK(23, 16))
#define DDR_UMCTL2_DRAMTMG5_T_CKSRE_M            GENMASK(23, 16)
#define DDR_UMCTL2_DRAMTMG5_T_CKSRE_X(x)         (((x) & GENMASK(23, 16)) >> 16)

#define DDR_UMCTL2_DRAMTMG5_T_CKSRX(x)           (((x) << 24) & GENMASK(27, 24))
#define DDR_UMCTL2_DRAMTMG5_T_CKSRX_M            GENMASK(27, 24)
#define DDR_UMCTL2_DRAMTMG5_T_CKSRX_X(x)         (((x) & GENMASK(27, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:DRAMTMG8 */
#define DDR_UMCTL2_DRAMTMG8(t)    (t + 0x120)

#define DDR_UMCTL2_DRAMTMG8_T_XS_X32(x)          ((x) & GENMASK(6, 0))
#define DDR_UMCTL2_DRAMTMG8_T_XS_X32_M           GENMASK(6, 0)
#define DDR_UMCTL2_DRAMTMG8_T_XS_X32_X(x)        ((x) & GENMASK(6, 0))

#define DDR_UMCTL2_DRAMTMG8_T_XS_DLL_X32(x)      (((x) << 8) & GENMASK(14, 8))
#define DDR_UMCTL2_DRAMTMG8_T_XS_DLL_X32_M       GENMASK(14, 8)
#define DDR_UMCTL2_DRAMTMG8_T_XS_DLL_X32_X(x)    (((x) & GENMASK(14, 8)) >> 8)

#define DDR_UMCTL2_DRAMTMG8_T_XS_ABORT_X32(x)    (((x) << 16) & GENMASK(22, 16))
#define DDR_UMCTL2_DRAMTMG8_T_XS_ABORT_X32_M     GENMASK(22, 16)
#define DDR_UMCTL2_DRAMTMG8_T_XS_ABORT_X32_X(x)  (((x) & GENMASK(22, 16)) >> 16)

#define DDR_UMCTL2_DRAMTMG8_T_XS_FAST_X32(x)     (((x) << 24) & GENMASK(30, 24))
#define DDR_UMCTL2_DRAMTMG8_T_XS_FAST_X32_M      GENMASK(30, 24)
#define DDR_UMCTL2_DRAMTMG8_T_XS_FAST_X32_X(x)   (((x) & GENMASK(30, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:DRAMTMG9 */
#define DDR_UMCTL2_DRAMTMG9(t)    (t + 0x124)

#define DDR_UMCTL2_DRAMTMG9_WR2RD_S(x)           ((x) & GENMASK(5, 0))
#define DDR_UMCTL2_DRAMTMG9_WR2RD_S_M            GENMASK(5, 0)
#define DDR_UMCTL2_DRAMTMG9_WR2RD_S_X(x)         ((x) & GENMASK(5, 0))

#define DDR_UMCTL2_DRAMTMG9_T_RRD_S(x)           (((x) << 8) & GENMASK(11, 8))
#define DDR_UMCTL2_DRAMTMG9_T_RRD_S_M            GENMASK(11, 8)
#define DDR_UMCTL2_DRAMTMG9_T_RRD_S_X(x)         (((x) & GENMASK(11, 8)) >> 8)

#define DDR_UMCTL2_DRAMTMG9_T_CCD_S(x)           (((x) << 16) & GENMASK(18, 16))
#define DDR_UMCTL2_DRAMTMG9_T_CCD_S_M            GENMASK(18, 16)
#define DDR_UMCTL2_DRAMTMG9_T_CCD_S_X(x)         (((x) & GENMASK(18, 16)) >> 16)

#define DDR_UMCTL2_DRAMTMG9_DDR4_WR_PREAMBLE(x)  (((x) << 30) & GENMASK(30, 30))
#define DDR_UMCTL2_DRAMTMG9_DDR4_WR_PREAMBLE_M   GENMASK(30, 30)
#define DDR_UMCTL2_DRAMTMG9_DDR4_WR_PREAMBLE_X(x)\
	(((x) & GENMASK(30, 30)) >> 30)

/*      DDR_UMCTL2:UMCTL2_REGS:DRAMTMG10 */
#define DDR_UMCTL2_DRAMTMG10(t)   (t + 0x128)

#define DDR_UMCTL2_DRAMTMG10_T_GEAR_HOLD(x)      ((x) & GENMASK(1, 0))
#define DDR_UMCTL2_DRAMTMG10_T_GEAR_HOLD_M       GENMASK(1, 0)
#define DDR_UMCTL2_DRAMTMG10_T_GEAR_HOLD_X(x)    ((x) & GENMASK(1, 0))

#define DDR_UMCTL2_DRAMTMG10_T_GEAR_SETUP(x)     (((x) << 2) & GENMASK(3, 2))
#define DDR_UMCTL2_DRAMTMG10_T_GEAR_SETUP_M      GENMASK(3, 2)
#define DDR_UMCTL2_DRAMTMG10_T_GEAR_SETUP_X(x)   (((x) & GENMASK(3, 2)) >> 2)

#define DDR_UMCTL2_DRAMTMG10_T_CMD_GEAR(x)       (((x) << 8) & GENMASK(12, 8))
#define DDR_UMCTL2_DRAMTMG10_T_CMD_GEAR_M        GENMASK(12, 8)
#define DDR_UMCTL2_DRAMTMG10_T_CMD_GEAR_X(x)     (((x) & GENMASK(12, 8)) >> 8)

#define DDR_UMCTL2_DRAMTMG10_T_SYNC_GEAR(x)      (((x) << 16) & GENMASK(20, 16))
#define DDR_UMCTL2_DRAMTMG10_T_SYNC_GEAR_M       GENMASK(20, 16)
#define DDR_UMCTL2_DRAMTMG10_T_SYNC_GEAR_X(x)    (((x) & GENMASK(20, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_REGS:DRAMTMG11 */
#define DDR_UMCTL2_DRAMTMG11(t)   (t + 0x12c)

#define DDR_UMCTL2_DRAMTMG11_T_CKMPE(x)          ((x) & GENMASK(4, 0))
#define DDR_UMCTL2_DRAMTMG11_T_CKMPE_M           GENMASK(4, 0)
#define DDR_UMCTL2_DRAMTMG11_T_CKMPE_X(x)        ((x) & GENMASK(4, 0))

#define DDR_UMCTL2_DRAMTMG11_T_MPX_S(x)          (((x) << 8) & GENMASK(9, 8))
#define DDR_UMCTL2_DRAMTMG11_T_MPX_S_M           GENMASK(9, 8)
#define DDR_UMCTL2_DRAMTMG11_T_MPX_S_X(x)        (((x) & GENMASK(9, 8)) >> 8)

#define DDR_UMCTL2_DRAMTMG11_T_MPX_LH(x)         (((x) << 16) & GENMASK(20, 16))
#define DDR_UMCTL2_DRAMTMG11_T_MPX_LH_M          GENMASK(20, 16)
#define DDR_UMCTL2_DRAMTMG11_T_MPX_LH_X(x)       (((x) & GENMASK(20, 16)) >> 16)

#define DDR_UMCTL2_DRAMTMG11_POST_MPSM_GAP_X32(x)\
	(((x) << 24) & GENMASK(30, 24))
#define DDR_UMCTL2_DRAMTMG11_POST_MPSM_GAP_X32_M GENMASK(30, 24)
#define DDR_UMCTL2_DRAMTMG11_POST_MPSM_GAP_X32_X(x)\
	(((x) & GENMASK(30, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:DRAMTMG12 */
#define DDR_UMCTL2_DRAMTMG12(t)   (t + 0x130)

#define DDR_UMCTL2_DRAMTMG12_T_MRD_PDA(x)        ((x) & GENMASK(4, 0))
#define DDR_UMCTL2_DRAMTMG12_T_MRD_PDA_M         GENMASK(4, 0)
#define DDR_UMCTL2_DRAMTMG12_T_MRD_PDA_X(x)      ((x) & GENMASK(4, 0))

#define DDR_UMCTL2_DRAMTMG12_T_WR_MPR(x)         (((x) << 24) & GENMASK(29, 24))
#define DDR_UMCTL2_DRAMTMG12_T_WR_MPR_M          GENMASK(29, 24)
#define DDR_UMCTL2_DRAMTMG12_T_WR_MPR_X(x)       (((x) & GENMASK(29, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:DRAMTMG15 */
#define DDR_UMCTL2_DRAMTMG15(t)   (t + 0x13c)

#define DDR_UMCTL2_DRAMTMG15_T_STAB_X32(x)       ((x) & GENMASK(7, 0))
#define DDR_UMCTL2_DRAMTMG15_T_STAB_X32_M        GENMASK(7, 0)
#define DDR_UMCTL2_DRAMTMG15_T_STAB_X32_X(x)     ((x) & GENMASK(7, 0))

#define DDR_UMCTL2_DRAMTMG15_EN_DFI_LP_T_STAB(x) (((x) << 31) & GENMASK(31, 31))
#define DDR_UMCTL2_DRAMTMG15_EN_DFI_LP_T_STAB_M  GENMASK(31, 31)
#define DDR_UMCTL2_DRAMTMG15_EN_DFI_LP_T_STAB_X(x)\
	(((x) & GENMASK(31, 31)) >> 31)

/*      DDR_UMCTL2:UMCTL2_REGS:ZQCTL0 */
#define DDR_UMCTL2_ZQCTL0(t)      (t + 0x180)

#define DDR_UMCTL2_ZQCTL0_T_ZQ_SHORT_NOP(x)      ((x) & GENMASK(9, 0))
#define DDR_UMCTL2_ZQCTL0_T_ZQ_SHORT_NOP_M       GENMASK(9, 0)
#define DDR_UMCTL2_ZQCTL0_T_ZQ_SHORT_NOP_X(x)    ((x) & GENMASK(9, 0))

#define DDR_UMCTL2_ZQCTL0_T_ZQ_LONG_NOP(x)       (((x) << 16) & GENMASK(26, 16))
#define DDR_UMCTL2_ZQCTL0_T_ZQ_LONG_NOP_M        GENMASK(26, 16)
#define DDR_UMCTL2_ZQCTL0_T_ZQ_LONG_NOP_X(x)     (((x) & GENMASK(26, 16)) >> 16)

#define DDR_UMCTL2_ZQCTL0_DIS_MPSMX_ZQCL(x)      (((x) << 28) & GENMASK(28, 28))
#define DDR_UMCTL2_ZQCTL0_DIS_MPSMX_ZQCL_M       GENMASK(28, 28)
#define DDR_UMCTL2_ZQCTL0_DIS_MPSMX_ZQCL_X(x)    (((x) & GENMASK(28, 28)) >> 28)

#define DDR_UMCTL2_ZQCTL0_ZQ_RESISTOR_SHARED(x)  (((x) << 29) & GENMASK(29, 29))
#define DDR_UMCTL2_ZQCTL0_ZQ_RESISTOR_SHARED_M   GENMASK(29, 29)
#define DDR_UMCTL2_ZQCTL0_ZQ_RESISTOR_SHARED_X(x)\
	(((x) & GENMASK(29, 29)) >> 29)

#define DDR_UMCTL2_ZQCTL0_DIS_SRX_ZQCL(x)        (((x) << 30) & GENMASK(30, 30))
#define DDR_UMCTL2_ZQCTL0_DIS_SRX_ZQCL_M         GENMASK(30, 30)
#define DDR_UMCTL2_ZQCTL0_DIS_SRX_ZQCL_X(x)      (((x) & GENMASK(30, 30)) >> 30)

#define DDR_UMCTL2_ZQCTL0_DIS_AUTO_ZQ(x)         (((x) << 31) & GENMASK(31, 31))
#define DDR_UMCTL2_ZQCTL0_DIS_AUTO_ZQ_M          GENMASK(31, 31)
#define DDR_UMCTL2_ZQCTL0_DIS_AUTO_ZQ_X(x)       (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_UMCTL2:UMCTL2_REGS:ZQCTL1 */
#define DDR_UMCTL2_ZQCTL1(t)      (t + 0x184)

#define DDR_UMCTL2_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024(x) ((x) & GENMASK(19, 0))
#define DDR_UMCTL2_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_M GENMASK(19, 0)
#define DDR_UMCTL2_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_X(x) ((x) & GENMASK(19, 0))

/*      DDR_UMCTL2:UMCTL2_REGS:DFITMG0 */
#define DDR_UMCTL2_DFITMG0(t)     (t + 0x190)

#define DDR_UMCTL2_DFITMG0_DFI_TPHY_WRLAT(x)     ((x) & GENMASK(5, 0))
#define DDR_UMCTL2_DFITMG0_DFI_TPHY_WRLAT_M      GENMASK(5, 0)
#define DDR_UMCTL2_DFITMG0_DFI_TPHY_WRLAT_X(x)   ((x) & GENMASK(5, 0))

#define DDR_UMCTL2_DFITMG0_DFI_TPHY_WRDATA(x)    (((x) << 8) & GENMASK(13, 8))
#define DDR_UMCTL2_DFITMG0_DFI_TPHY_WRDATA_M     GENMASK(13, 8)
#define DDR_UMCTL2_DFITMG0_DFI_TPHY_WRDATA_X(x)  (((x) & GENMASK(13, 8)) >> 8)

#define DDR_UMCTL2_DFITMG0_DFI_WRDATA_USE_DFI_PHY_CLK(x)\
	(((x) << 15) & GENMASK(15, 15))
#define DDR_UMCTL2_DFITMG0_DFI_WRDATA_USE_DFI_PHY_CLK_M GENMASK(15, 15)
#define DDR_UMCTL2_DFITMG0_DFI_WRDATA_USE_DFI_PHY_CLK_X(x)\
	(((x) & GENMASK(15, 15)) >> 15)

#define DDR_UMCTL2_DFITMG0_DFI_T_RDDATA_EN(x)    (((x) << 16) & GENMASK(22, 16))
#define DDR_UMCTL2_DFITMG0_DFI_T_RDDATA_EN_M     GENMASK(22, 16)
#define DDR_UMCTL2_DFITMG0_DFI_T_RDDATA_EN_X(x)  (((x) & GENMASK(22, 16)) >> 16)

#define DDR_UMCTL2_DFITMG0_DFI_RDDATA_USE_DFI_PHY_CLK(x)\
	(((x) << 23) & GENMASK(23, 23))
#define DDR_UMCTL2_DFITMG0_DFI_RDDATA_USE_DFI_PHY_CLK_M GENMASK(23, 23)
#define DDR_UMCTL2_DFITMG0_DFI_RDDATA_USE_DFI_PHY_CLK_X(x)\
	(((x) & GENMASK(23, 23)) >> 23)

#define DDR_UMCTL2_DFITMG0_DFI_T_CTRL_DELAY(x)   (((x) << 24) & GENMASK(28, 24))
#define DDR_UMCTL2_DFITMG0_DFI_T_CTRL_DELAY_M    GENMASK(28, 24)
#define DDR_UMCTL2_DFITMG0_DFI_T_CTRL_DELAY_X(x) (((x) & GENMASK(28, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:DFITMG1 */
#define DDR_UMCTL2_DFITMG1(t)     (t + 0x194)

#define DDR_UMCTL2_DFITMG1_DFI_T_DRAM_CLK_ENABLE(x) ((x) & GENMASK(4, 0))
#define DDR_UMCTL2_DFITMG1_DFI_T_DRAM_CLK_ENABLE_M GENMASK(4, 0)
#define DDR_UMCTL2_DFITMG1_DFI_T_DRAM_CLK_ENABLE_X(x) ((x) & GENMASK(4, 0))

#define DDR_UMCTL2_DFITMG1_DFI_T_DRAM_CLK_DISABLE(x)\
	(((x) << 8) & GENMASK(12, 8))
#define DDR_UMCTL2_DFITMG1_DFI_T_DRAM_CLK_DISABLE_M GENMASK(12, 8)
#define DDR_UMCTL2_DFITMG1_DFI_T_DRAM_CLK_DISABLE_X(x)\
	(((x) & GENMASK(12, 8)) >> 8)

#define DDR_UMCTL2_DFITMG1_DFI_T_WRDATA_DELAY(x) (((x) << 16) & GENMASK(20, 16))
#define DDR_UMCTL2_DFITMG1_DFI_T_WRDATA_DELAY_M  GENMASK(20, 16)
#define DDR_UMCTL2_DFITMG1_DFI_T_WRDATA_DELAY_X(x)\
	(((x) & GENMASK(20, 16)) >> 16)

#define DDR_UMCTL2_DFITMG1_DFI_T_PARIN_LAT(x)    (((x) << 24) & GENMASK(25, 24))
#define DDR_UMCTL2_DFITMG1_DFI_T_PARIN_LAT_M     GENMASK(25, 24)
#define DDR_UMCTL2_DFITMG1_DFI_T_PARIN_LAT_X(x)  (((x) & GENMASK(25, 24)) >> 24)

#define DDR_UMCTL2_DFITMG1_DFI_T_CMD_LAT(x)      (((x) << 28) & GENMASK(31, 28))
#define DDR_UMCTL2_DFITMG1_DFI_T_CMD_LAT_M       GENMASK(31, 28)
#define DDR_UMCTL2_DFITMG1_DFI_T_CMD_LAT_X(x)    (((x) & GENMASK(31, 28)) >> 28)

/*      DDR_UMCTL2:UMCTL2_REGS:DFILPCFG0 */
#define DDR_UMCTL2_DFILPCFG0(t)   (t + 0x198)

#define DDR_UMCTL2_DFILPCFG0_DFI_LP_EN_PD(x)     ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_DFILPCFG0_DFI_LP_EN_PD_M      GENMASK(0, 0)
#define DDR_UMCTL2_DFILPCFG0_DFI_LP_EN_PD_X(x)   ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_DFILPCFG0_DFI_LP_WAKEUP_PD(x) (((x) << 4) & GENMASK(7, 4))
#define DDR_UMCTL2_DFILPCFG0_DFI_LP_WAKEUP_PD_M  GENMASK(7, 4)
#define DDR_UMCTL2_DFILPCFG0_DFI_LP_WAKEUP_PD_X(x) (((x) & GENMASK(7, 4)) >> 4)

#define DDR_UMCTL2_DFILPCFG0_DFI_LP_EN_SR(x)     (((x) << 8) & GENMASK(8, 8))
#define DDR_UMCTL2_DFILPCFG0_DFI_LP_EN_SR_M      GENMASK(8, 8)
#define DDR_UMCTL2_DFILPCFG0_DFI_LP_EN_SR_X(x)   (((x) & GENMASK(8, 8)) >> 8)

#define DDR_UMCTL2_DFILPCFG0_DFI_LP_WAKEUP_SR(x) (((x) << 12) & GENMASK(15, 12))
#define DDR_UMCTL2_DFILPCFG0_DFI_LP_WAKEUP_SR_M  GENMASK(15, 12)
#define DDR_UMCTL2_DFILPCFG0_DFI_LP_WAKEUP_SR_X(x)\
	(((x) & GENMASK(15, 12)) >> 12)

#define DDR_UMCTL2_DFILPCFG0_DFI_TLP_RESP(x)     (((x) << 24) & GENMASK(28, 24))
#define DDR_UMCTL2_DFILPCFG0_DFI_TLP_RESP_M      GENMASK(28, 24)
#define DDR_UMCTL2_DFILPCFG0_DFI_TLP_RESP_X(x)   (((x) & GENMASK(28, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:DFILPCFG1 */
#define DDR_UMCTL2_DFILPCFG1(t)   (t + 0x19c)

#define DDR_UMCTL2_DFILPCFG1_DFI_LP_EN_MPSM(x)   ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_DFILPCFG1_DFI_LP_EN_MPSM_M    GENMASK(0, 0)
#define DDR_UMCTL2_DFILPCFG1_DFI_LP_EN_MPSM_X(x) ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_DFILPCFG1_DFI_LP_WAKEUP_MPSM(x) (((x) << 4) & GENMASK(7, 4))
#define DDR_UMCTL2_DFILPCFG1_DFI_LP_WAKEUP_MPSM_M GENMASK(7, 4)
#define DDR_UMCTL2_DFILPCFG1_DFI_LP_WAKEUP_MPSM_X(x)\
	(((x) & GENMASK(7, 4)) >> 4)

/*      DDR_UMCTL2:UMCTL2_REGS:DFIUPD0 */
#define DDR_UMCTL2_DFIUPD0(t)     (t + 0x1a0)

#define DDR_UMCTL2_DFIUPD0_DFI_T_CTRLUP_MIN(x)   ((x) & GENMASK(9, 0))
#define DDR_UMCTL2_DFIUPD0_DFI_T_CTRLUP_MIN_M    GENMASK(9, 0)
#define DDR_UMCTL2_DFIUPD0_DFI_T_CTRLUP_MIN_X(x) ((x) & GENMASK(9, 0))

#define DDR_UMCTL2_DFIUPD0_DFI_T_CTRLUP_MAX(x)   (((x) << 16) & GENMASK(25, 16))
#define DDR_UMCTL2_DFIUPD0_DFI_T_CTRLUP_MAX_M    GENMASK(25, 16)
#define DDR_UMCTL2_DFIUPD0_DFI_T_CTRLUP_MAX_X(x) (((x) & GENMASK(25, 16)) >> 16)

#define DDR_UMCTL2_DFIUPD0_CTRLUPD_PRE_SRX(x)    (((x) << 29) & GENMASK(29, 29))
#define DDR_UMCTL2_DFIUPD0_CTRLUPD_PRE_SRX_M     GENMASK(29, 29)
#define DDR_UMCTL2_DFIUPD0_CTRLUPD_PRE_SRX_X(x)  (((x) & GENMASK(29, 29)) >> 29)

#define DDR_UMCTL2_DFIUPD0_DIS_AUTO_CTRLUPD_SRX(x)\
	(((x) << 30) & GENMASK(30, 30))
#define DDR_UMCTL2_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_M GENMASK(30, 30)
#define DDR_UMCTL2_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_X(x)\
	(((x) & GENMASK(30, 30)) >> 30)

#define DDR_UMCTL2_DFIUPD0_DIS_AUTO_CTRLUPD(x)   (((x) << 31) & GENMASK(31, 31))
#define DDR_UMCTL2_DFIUPD0_DIS_AUTO_CTRLUPD_M    GENMASK(31, 31)
#define DDR_UMCTL2_DFIUPD0_DIS_AUTO_CTRLUPD_X(x) (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_UMCTL2:UMCTL2_REGS:DFIUPD1 */
#define DDR_UMCTL2_DFIUPD1(t)     (t + 0x1a4)

#define DDR_UMCTL2_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024(x)\
	((x) & GENMASK(7, 0))
#define DDR_UMCTL2_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_M GENMASK(7, 0)
#define DDR_UMCTL2_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_X(x)\
	((x) & GENMASK(7, 0))

#define DDR_UMCTL2_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024(x)\
	(((x) << 16) & GENMASK(23, 16))
#define DDR_UMCTL2_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_M GENMASK(23, 16)
#define DDR_UMCTL2_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_X(x)\
	(((x) & GENMASK(23, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_REGS:DFIUPD2 */
#define DDR_UMCTL2_DFIUPD2(t)     (t + 0x1a8)

#define DDR_UMCTL2_DFIUPD2_DFI_PHYUPD_EN(x)      (((x) << 31) & GENMASK(31, 31))
#define DDR_UMCTL2_DFIUPD2_DFI_PHYUPD_EN_M       GENMASK(31, 31)
#define DDR_UMCTL2_DFIUPD2_DFI_PHYUPD_EN_X(x)    (((x) & GENMASK(31, 31)) >> 31)

/*      DDR_UMCTL2:UMCTL2_REGS:DFIMISC */
#define DDR_UMCTL2_DFIMISC(t)     (t + 0x1b0)

#define DDR_UMCTL2_DFIMISC_DFI_INIT_COMPLETE_EN(x) ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_DFIMISC_DFI_INIT_COMPLETE_EN_M GENMASK(0, 0)
#define DDR_UMCTL2_DFIMISC_DFI_INIT_COMPLETE_EN_X(x) ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_DFIMISC_PHY_DBI_MODE(x)       (((x) << 1) & GENMASK(1, 1))
#define DDR_UMCTL2_DFIMISC_PHY_DBI_MODE_M        GENMASK(1, 1)
#define DDR_UMCTL2_DFIMISC_PHY_DBI_MODE_X(x)     (((x) & GENMASK(1, 1)) >> 1)

#define DDR_UMCTL2_DFIMISC_CTL_IDLE_EN(x)        (((x) << 4) & GENMASK(4, 4))
#define DDR_UMCTL2_DFIMISC_CTL_IDLE_EN_M         GENMASK(4, 4)
#define DDR_UMCTL2_DFIMISC_CTL_IDLE_EN_X(x)      (((x) & GENMASK(4, 4)) >> 4)

#define DDR_UMCTL2_DFIMISC_DFI_INIT_START(x)     (((x) << 5) & GENMASK(5, 5))
#define DDR_UMCTL2_DFIMISC_DFI_INIT_START_M      GENMASK(5, 5)
#define DDR_UMCTL2_DFIMISC_DFI_INIT_START_X(x)   (((x) & GENMASK(5, 5)) >> 5)

#define DDR_UMCTL2_DFIMISC_DIS_DYN_ADR_TRI(x)    (((x) << 6) & GENMASK(6, 6))
#define DDR_UMCTL2_DFIMISC_DIS_DYN_ADR_TRI_M     GENMASK(6, 6)
#define DDR_UMCTL2_DFIMISC_DIS_DYN_ADR_TRI_X(x)  (((x) & GENMASK(6, 6)) >> 6)

#define DDR_UMCTL2_DFIMISC_DFI_FREQUENCY(x)      (((x) << 8) & GENMASK(12, 8))
#define DDR_UMCTL2_DFIMISC_DFI_FREQUENCY_M       GENMASK(12, 8)
#define DDR_UMCTL2_DFIMISC_DFI_FREQUENCY_X(x)    (((x) & GENMASK(12, 8)) >> 8)

/*      DDR_UMCTL2:UMCTL2_REGS:DFITMG3 */
#define DDR_UMCTL2_DFITMG3(t)     (t + 0x1b8)

#define DDR_UMCTL2_DFITMG3_DFI_T_GEARDOWN_DELAY(x) ((x) & GENMASK(4, 0))
#define DDR_UMCTL2_DFITMG3_DFI_T_GEARDOWN_DELAY_M GENMASK(4, 0)
#define DDR_UMCTL2_DFITMG3_DFI_T_GEARDOWN_DELAY_X(x) ((x) & GENMASK(4, 0))

/*      DDR_UMCTL2:UMCTL2_REGS:DFISTAT */
#define DDR_UMCTL2_DFISTAT(t)     (t + 0x1bc)

#define DDR_UMCTL2_DFISTAT_DFI_INIT_COMPLETE(x)  ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_DFISTAT_DFI_INIT_COMPLETE_M   GENMASK(0, 0)
#define DDR_UMCTL2_DFISTAT_DFI_INIT_COMPLETE_X(x) ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_DFISTAT_DFI_LP_ACK(x)         (((x) << 1) & GENMASK(1, 1))
#define DDR_UMCTL2_DFISTAT_DFI_LP_ACK_M          GENMASK(1, 1)
#define DDR_UMCTL2_DFISTAT_DFI_LP_ACK_X(x)       (((x) & GENMASK(1, 1)) >> 1)

/*      DDR_UMCTL2:UMCTL2_REGS:DBICTL */
#define DDR_UMCTL2_DBICTL(t)      (t + 0x1c0)

#define DDR_UMCTL2_DBICTL_DM_EN(x)               ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_DBICTL_DM_EN_M                GENMASK(0, 0)
#define DDR_UMCTL2_DBICTL_DM_EN_X(x)             ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_DBICTL_WR_DBI_EN(x)           (((x) << 1) & GENMASK(1, 1))
#define DDR_UMCTL2_DBICTL_WR_DBI_EN_M            GENMASK(1, 1)
#define DDR_UMCTL2_DBICTL_WR_DBI_EN_X(x)         (((x) & GENMASK(1, 1)) >> 1)

#define DDR_UMCTL2_DBICTL_RD_DBI_EN(x)           (((x) << 2) & GENMASK(2, 2))
#define DDR_UMCTL2_DBICTL_RD_DBI_EN_M            GENMASK(2, 2)
#define DDR_UMCTL2_DBICTL_RD_DBI_EN_X(x)         (((x) & GENMASK(2, 2)) >> 2)

/*      DDR_UMCTL2:UMCTL2_REGS:DFIPHYMSTR */
#define DDR_UMCTL2_DFIPHYMSTR(t)  (t + 0x1c4)

#define DDR_UMCTL2_DFIPHYMSTR_DFI_PHYMSTR_EN(x)  ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_DFIPHYMSTR_DFI_PHYMSTR_EN_M   GENMASK(0, 0)
#define DDR_UMCTL2_DFIPHYMSTR_DFI_PHYMSTR_EN_X(x) ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_DFIPHYMSTR_DFI_PHYMSTR_BLK_REF_X32(x)\
	(((x) << 24) & GENMASK(31, 24))
#define DDR_UMCTL2_DFIPHYMSTR_DFI_PHYMSTR_BLK_REF_X32_M GENMASK(31, 24)
#define DDR_UMCTL2_DFIPHYMSTR_DFI_PHYMSTR_BLK_REF_X32_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:ADDRMAP0 */
#define DDR_UMCTL2_ADDRMAP0(t)    (t + 0x200)

#define DDR_UMCTL2_ADDRMAP0_ADDRMAP_CS_BIT0(x)   ((x) & GENMASK(4, 0))
#define DDR_UMCTL2_ADDRMAP0_ADDRMAP_CS_BIT0_M    GENMASK(4, 0)
#define DDR_UMCTL2_ADDRMAP0_ADDRMAP_CS_BIT0_X(x) ((x) & GENMASK(4, 0))

/*      DDR_UMCTL2:UMCTL2_REGS:ADDRMAP1 */
#define DDR_UMCTL2_ADDRMAP1(t)    (t + 0x204)

#define DDR_UMCTL2_ADDRMAP1_ADDRMAP_BANK_B0(x)   ((x) & GENMASK(5, 0))
#define DDR_UMCTL2_ADDRMAP1_ADDRMAP_BANK_B0_M    GENMASK(5, 0)
#define DDR_UMCTL2_ADDRMAP1_ADDRMAP_BANK_B0_X(x) ((x) & GENMASK(5, 0))

#define DDR_UMCTL2_ADDRMAP1_ADDRMAP_BANK_B1(x)   (((x) << 8) & GENMASK(13, 8))
#define DDR_UMCTL2_ADDRMAP1_ADDRMAP_BANK_B1_M    GENMASK(13, 8)
#define DDR_UMCTL2_ADDRMAP1_ADDRMAP_BANK_B1_X(x) (((x) & GENMASK(13, 8)) >> 8)

#define DDR_UMCTL2_ADDRMAP1_ADDRMAP_BANK_B2(x)   (((x) << 16) & GENMASK(21, 16))
#define DDR_UMCTL2_ADDRMAP1_ADDRMAP_BANK_B2_M    GENMASK(21, 16)
#define DDR_UMCTL2_ADDRMAP1_ADDRMAP_BANK_B2_X(x) (((x) & GENMASK(21, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_REGS:ADDRMAP2 */
#define DDR_UMCTL2_ADDRMAP2(t)    (t + 0x208)

#define DDR_UMCTL2_ADDRMAP2_ADDRMAP_COL_B2(x)    ((x) & GENMASK(3, 0))
#define DDR_UMCTL2_ADDRMAP2_ADDRMAP_COL_B2_M     GENMASK(3, 0)
#define DDR_UMCTL2_ADDRMAP2_ADDRMAP_COL_B2_X(x)  ((x) & GENMASK(3, 0))

#define DDR_UMCTL2_ADDRMAP2_ADDRMAP_COL_B3(x)    (((x) << 8) & GENMASK(12, 8))
#define DDR_UMCTL2_ADDRMAP2_ADDRMAP_COL_B3_M     GENMASK(12, 8)
#define DDR_UMCTL2_ADDRMAP2_ADDRMAP_COL_B3_X(x)  (((x) & GENMASK(12, 8)) >> 8)

#define DDR_UMCTL2_ADDRMAP2_ADDRMAP_COL_B4(x)    (((x) << 16) & GENMASK(19, 16))
#define DDR_UMCTL2_ADDRMAP2_ADDRMAP_COL_B4_M     GENMASK(19, 16)
#define DDR_UMCTL2_ADDRMAP2_ADDRMAP_COL_B4_X(x)  (((x) & GENMASK(19, 16)) >> 16)

#define DDR_UMCTL2_ADDRMAP2_ADDRMAP_COL_B5(x)    (((x) << 24) & GENMASK(27, 24))
#define DDR_UMCTL2_ADDRMAP2_ADDRMAP_COL_B5_M     GENMASK(27, 24)
#define DDR_UMCTL2_ADDRMAP2_ADDRMAP_COL_B5_X(x)  (((x) & GENMASK(27, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:ADDRMAP3 */
#define DDR_UMCTL2_ADDRMAP3(t)    (t + 0x20c)

#define DDR_UMCTL2_ADDRMAP3_ADDRMAP_COL_B6(x)    ((x) & GENMASK(4, 0))
#define DDR_UMCTL2_ADDRMAP3_ADDRMAP_COL_B6_M     GENMASK(4, 0)
#define DDR_UMCTL2_ADDRMAP3_ADDRMAP_COL_B6_X(x)  ((x) & GENMASK(4, 0))

#define DDR_UMCTL2_ADDRMAP3_ADDRMAP_COL_B7(x)    (((x) << 8) & GENMASK(12, 8))
#define DDR_UMCTL2_ADDRMAP3_ADDRMAP_COL_B7_M     GENMASK(12, 8)
#define DDR_UMCTL2_ADDRMAP3_ADDRMAP_COL_B7_X(x)  (((x) & GENMASK(12, 8)) >> 8)

#define DDR_UMCTL2_ADDRMAP3_ADDRMAP_COL_B8(x)    (((x) << 16) & GENMASK(20, 16))
#define DDR_UMCTL2_ADDRMAP3_ADDRMAP_COL_B8_M     GENMASK(20, 16)
#define DDR_UMCTL2_ADDRMAP3_ADDRMAP_COL_B8_X(x)  (((x) & GENMASK(20, 16)) >> 16)

#define DDR_UMCTL2_ADDRMAP3_ADDRMAP_COL_B9(x)    (((x) << 24) & GENMASK(28, 24))
#define DDR_UMCTL2_ADDRMAP3_ADDRMAP_COL_B9_M     GENMASK(28, 24)
#define DDR_UMCTL2_ADDRMAP3_ADDRMAP_COL_B9_X(x)  (((x) & GENMASK(28, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:ADDRMAP4 */
#define DDR_UMCTL2_ADDRMAP4(t)    (t + 0x210)

#define DDR_UMCTL2_ADDRMAP4_ADDRMAP_COL_B10(x)   ((x) & GENMASK(4, 0))
#define DDR_UMCTL2_ADDRMAP4_ADDRMAP_COL_B10_M    GENMASK(4, 0)
#define DDR_UMCTL2_ADDRMAP4_ADDRMAP_COL_B10_X(x) ((x) & GENMASK(4, 0))

#define DDR_UMCTL2_ADDRMAP4_ADDRMAP_COL_B11(x)   (((x) << 8) & GENMASK(12, 8))
#define DDR_UMCTL2_ADDRMAP4_ADDRMAP_COL_B11_M    GENMASK(12, 8)
#define DDR_UMCTL2_ADDRMAP4_ADDRMAP_COL_B11_X(x) (((x) & GENMASK(12, 8)) >> 8)

/*      DDR_UMCTL2:UMCTL2_REGS:ADDRMAP5 */
#define DDR_UMCTL2_ADDRMAP5(t)    (t + 0x214)

#define DDR_UMCTL2_ADDRMAP5_ADDRMAP_ROW_B0(x)    ((x) & GENMASK(3, 0))
#define DDR_UMCTL2_ADDRMAP5_ADDRMAP_ROW_B0_M     GENMASK(3, 0)
#define DDR_UMCTL2_ADDRMAP5_ADDRMAP_ROW_B0_X(x)  ((x) & GENMASK(3, 0))

#define DDR_UMCTL2_ADDRMAP5_ADDRMAP_ROW_B1(x)    (((x) << 8) & GENMASK(11, 8))
#define DDR_UMCTL2_ADDRMAP5_ADDRMAP_ROW_B1_M     GENMASK(11, 8)
#define DDR_UMCTL2_ADDRMAP5_ADDRMAP_ROW_B1_X(x)  (((x) & GENMASK(11, 8)) >> 8)

#define DDR_UMCTL2_ADDRMAP5_ADDRMAP_ROW_B2_10(x) (((x) << 16) & GENMASK(19, 16))
#define DDR_UMCTL2_ADDRMAP5_ADDRMAP_ROW_B2_10_M  GENMASK(19, 16)
#define DDR_UMCTL2_ADDRMAP5_ADDRMAP_ROW_B2_10_X(x)\
	(((x) & GENMASK(19, 16)) >> 16)

#define DDR_UMCTL2_ADDRMAP5_ADDRMAP_ROW_B11(x)   (((x) << 24) & GENMASK(27, 24))
#define DDR_UMCTL2_ADDRMAP5_ADDRMAP_ROW_B11_M    GENMASK(27, 24)
#define DDR_UMCTL2_ADDRMAP5_ADDRMAP_ROW_B11_X(x) (((x) & GENMASK(27, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:ADDRMAP6 */
#define DDR_UMCTL2_ADDRMAP6(t)    (t + 0x218)

#define DDR_UMCTL2_ADDRMAP6_ADDRMAP_ROW_B12(x)   ((x) & GENMASK(3, 0))
#define DDR_UMCTL2_ADDRMAP6_ADDRMAP_ROW_B12_M    GENMASK(3, 0)
#define DDR_UMCTL2_ADDRMAP6_ADDRMAP_ROW_B12_X(x) ((x) & GENMASK(3, 0))

#define DDR_UMCTL2_ADDRMAP6_ADDRMAP_ROW_B13(x)   (((x) << 8) & GENMASK(11, 8))
#define DDR_UMCTL2_ADDRMAP6_ADDRMAP_ROW_B13_M    GENMASK(11, 8)
#define DDR_UMCTL2_ADDRMAP6_ADDRMAP_ROW_B13_X(x) (((x) & GENMASK(11, 8)) >> 8)

#define DDR_UMCTL2_ADDRMAP6_ADDRMAP_ROW_B14(x)   (((x) << 16) & GENMASK(19, 16))
#define DDR_UMCTL2_ADDRMAP6_ADDRMAP_ROW_B14_M    GENMASK(19, 16)
#define DDR_UMCTL2_ADDRMAP6_ADDRMAP_ROW_B14_X(x) (((x) & GENMASK(19, 16)) >> 16)

#define DDR_UMCTL2_ADDRMAP6_ADDRMAP_ROW_B15(x)   (((x) << 24) & GENMASK(27, 24))
#define DDR_UMCTL2_ADDRMAP6_ADDRMAP_ROW_B15_M    GENMASK(27, 24)
#define DDR_UMCTL2_ADDRMAP6_ADDRMAP_ROW_B15_X(x) (((x) & GENMASK(27, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:ADDRMAP7 */
#define DDR_UMCTL2_ADDRMAP7(t)    (t + 0x21c)

#define DDR_UMCTL2_ADDRMAP7_ADDRMAP_ROW_B16(x)   ((x) & GENMASK(3, 0))
#define DDR_UMCTL2_ADDRMAP7_ADDRMAP_ROW_B16_M    GENMASK(3, 0)
#define DDR_UMCTL2_ADDRMAP7_ADDRMAP_ROW_B16_X(x) ((x) & GENMASK(3, 0))

#define DDR_UMCTL2_ADDRMAP7_ADDRMAP_ROW_B17(x)   (((x) << 8) & GENMASK(11, 8))
#define DDR_UMCTL2_ADDRMAP7_ADDRMAP_ROW_B17_M    GENMASK(11, 8)
#define DDR_UMCTL2_ADDRMAP7_ADDRMAP_ROW_B17_X(x) (((x) & GENMASK(11, 8)) >> 8)

/*      DDR_UMCTL2:UMCTL2_REGS:ADDRMAP8 */
#define DDR_UMCTL2_ADDRMAP8(t)    (t + 0x220)

#define DDR_UMCTL2_ADDRMAP8_ADDRMAP_BG_B0(x)     ((x) & GENMASK(5, 0))
#define DDR_UMCTL2_ADDRMAP8_ADDRMAP_BG_B0_M      GENMASK(5, 0)
#define DDR_UMCTL2_ADDRMAP8_ADDRMAP_BG_B0_X(x)   ((x) & GENMASK(5, 0))

#define DDR_UMCTL2_ADDRMAP8_ADDRMAP_BG_B1(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_UMCTL2_ADDRMAP8_ADDRMAP_BG_B1_M      GENMASK(13, 8)
#define DDR_UMCTL2_ADDRMAP8_ADDRMAP_BG_B1_X(x)   (((x) & GENMASK(13, 8)) >> 8)

/*      DDR_UMCTL2:UMCTL2_REGS:ADDRMAP9 */
#define DDR_UMCTL2_ADDRMAP9(t)    (t + 0x224)

#define DDR_UMCTL2_ADDRMAP9_ADDRMAP_ROW_B2(x)    ((x) & GENMASK(3, 0))
#define DDR_UMCTL2_ADDRMAP9_ADDRMAP_ROW_B2_M     GENMASK(3, 0)
#define DDR_UMCTL2_ADDRMAP9_ADDRMAP_ROW_B2_X(x)  ((x) & GENMASK(3, 0))

#define DDR_UMCTL2_ADDRMAP9_ADDRMAP_ROW_B3(x)    (((x) << 8) & GENMASK(11, 8))
#define DDR_UMCTL2_ADDRMAP9_ADDRMAP_ROW_B3_M     GENMASK(11, 8)
#define DDR_UMCTL2_ADDRMAP9_ADDRMAP_ROW_B3_X(x)  (((x) & GENMASK(11, 8)) >> 8)

#define DDR_UMCTL2_ADDRMAP9_ADDRMAP_ROW_B4(x)    (((x) << 16) & GENMASK(19, 16))
#define DDR_UMCTL2_ADDRMAP9_ADDRMAP_ROW_B4_M     GENMASK(19, 16)
#define DDR_UMCTL2_ADDRMAP9_ADDRMAP_ROW_B4_X(x)  (((x) & GENMASK(19, 16)) >> 16)

#define DDR_UMCTL2_ADDRMAP9_ADDRMAP_ROW_B5(x)    (((x) << 24) & GENMASK(27, 24))
#define DDR_UMCTL2_ADDRMAP9_ADDRMAP_ROW_B5_M     GENMASK(27, 24)
#define DDR_UMCTL2_ADDRMAP9_ADDRMAP_ROW_B5_X(x)  (((x) & GENMASK(27, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:ADDRMAP10 */
#define DDR_UMCTL2_ADDRMAP10(t)   (t + 0x228)

#define DDR_UMCTL2_ADDRMAP10_ADDRMAP_ROW_B6(x)   ((x) & GENMASK(3, 0))
#define DDR_UMCTL2_ADDRMAP10_ADDRMAP_ROW_B6_M    GENMASK(3, 0)
#define DDR_UMCTL2_ADDRMAP10_ADDRMAP_ROW_B6_X(x) ((x) & GENMASK(3, 0))

#define DDR_UMCTL2_ADDRMAP10_ADDRMAP_ROW_B7(x)   (((x) << 8) & GENMASK(11, 8))
#define DDR_UMCTL2_ADDRMAP10_ADDRMAP_ROW_B7_M    GENMASK(11, 8)
#define DDR_UMCTL2_ADDRMAP10_ADDRMAP_ROW_B7_X(x) (((x) & GENMASK(11, 8)) >> 8)

#define DDR_UMCTL2_ADDRMAP10_ADDRMAP_ROW_B8(x)   (((x) << 16) & GENMASK(19, 16))
#define DDR_UMCTL2_ADDRMAP10_ADDRMAP_ROW_B8_M    GENMASK(19, 16)
#define DDR_UMCTL2_ADDRMAP10_ADDRMAP_ROW_B8_X(x) (((x) & GENMASK(19, 16)) >> 16)

#define DDR_UMCTL2_ADDRMAP10_ADDRMAP_ROW_B9(x)   (((x) << 24) & GENMASK(27, 24))
#define DDR_UMCTL2_ADDRMAP10_ADDRMAP_ROW_B9_M    GENMASK(27, 24)
#define DDR_UMCTL2_ADDRMAP10_ADDRMAP_ROW_B9_X(x) (((x) & GENMASK(27, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:ADDRMAP11 */
#define DDR_UMCTL2_ADDRMAP11(t)   (t + 0x22c)

#define DDR_UMCTL2_ADDRMAP11_ADDRMAP_ROW_B10(x)  ((x) & GENMASK(3, 0))
#define DDR_UMCTL2_ADDRMAP11_ADDRMAP_ROW_B10_M   GENMASK(3, 0)
#define DDR_UMCTL2_ADDRMAP11_ADDRMAP_ROW_B10_X(x) ((x) & GENMASK(3, 0))

/*      DDR_UMCTL2:UMCTL2_REGS:ODTCFG */
#define DDR_UMCTL2_ODTCFG(t)      (t + 0x240)

#define DDR_UMCTL2_ODTCFG_RD_ODT_DELAY(x)        (((x) << 2) & GENMASK(6, 2))
#define DDR_UMCTL2_ODTCFG_RD_ODT_DELAY_M         GENMASK(6, 2)
#define DDR_UMCTL2_ODTCFG_RD_ODT_DELAY_X(x)      (((x) & GENMASK(6, 2)) >> 2)

#define DDR_UMCTL2_ODTCFG_RD_ODT_HOLD(x)         (((x) << 8) & GENMASK(11, 8))
#define DDR_UMCTL2_ODTCFG_RD_ODT_HOLD_M          GENMASK(11, 8)
#define DDR_UMCTL2_ODTCFG_RD_ODT_HOLD_X(x)       (((x) & GENMASK(11, 8)) >> 8)

#define DDR_UMCTL2_ODTCFG_WR_ODT_DELAY(x)        (((x) << 16) & GENMASK(20, 16))
#define DDR_UMCTL2_ODTCFG_WR_ODT_DELAY_M         GENMASK(20, 16)
#define DDR_UMCTL2_ODTCFG_WR_ODT_DELAY_X(x)      (((x) & GENMASK(20, 16)) >> 16)

#define DDR_UMCTL2_ODTCFG_WR_ODT_HOLD(x)         (((x) << 24) & GENMASK(27, 24))
#define DDR_UMCTL2_ODTCFG_WR_ODT_HOLD_M          GENMASK(27, 24)
#define DDR_UMCTL2_ODTCFG_WR_ODT_HOLD_X(x)       (((x) & GENMASK(27, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:ODTMAP */
#define DDR_UMCTL2_ODTMAP(t)      (t + 0x244)

#define DDR_UMCTL2_ODTMAP_RANK0_WR_ODT(x)        ((x) & GENMASK(1, 0))
#define DDR_UMCTL2_ODTMAP_RANK0_WR_ODT_M         GENMASK(1, 0)
#define DDR_UMCTL2_ODTMAP_RANK0_WR_ODT_X(x)      ((x) & GENMASK(1, 0))

#define DDR_UMCTL2_ODTMAP_RANK0_RD_ODT(x)        (((x) << 4) & GENMASK(5, 4))
#define DDR_UMCTL2_ODTMAP_RANK0_RD_ODT_M         GENMASK(5, 4)
#define DDR_UMCTL2_ODTMAP_RANK0_RD_ODT_X(x)      (((x) & GENMASK(5, 4)) >> 4)

#define DDR_UMCTL2_ODTMAP_RANK1_WR_ODT(x)        (((x) << 8) & GENMASK(9, 8))
#define DDR_UMCTL2_ODTMAP_RANK1_WR_ODT_M         GENMASK(9, 8)
#define DDR_UMCTL2_ODTMAP_RANK1_WR_ODT_X(x)      (((x) & GENMASK(9, 8)) >> 8)

#define DDR_UMCTL2_ODTMAP_RANK1_RD_ODT(x)        (((x) << 12) & GENMASK(13, 12))
#define DDR_UMCTL2_ODTMAP_RANK1_RD_ODT_M         GENMASK(13, 12)
#define DDR_UMCTL2_ODTMAP_RANK1_RD_ODT_X(x)      (((x) & GENMASK(13, 12)) >> 12)

/*      DDR_UMCTL2:UMCTL2_REGS:SCHED */
#define DDR_UMCTL2_SCHED(t)       (t + 0x250)

#define DDR_UMCTL2_SCHED_DIS_OPT_WRECC_COLLISION_FLUSH(x) ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_SCHED_DIS_OPT_WRECC_COLLISION_FLUSH_M GENMASK(0, 0)
#define DDR_UMCTL2_SCHED_DIS_OPT_WRECC_COLLISION_FLUSH_X(x)\
	((x) & GENMASK(0, 0))

#define DDR_UMCTL2_SCHED_PREFER_WRITE(x)         (((x) << 1) & GENMASK(1, 1))
#define DDR_UMCTL2_SCHED_PREFER_WRITE_M          GENMASK(1, 1)
#define DDR_UMCTL2_SCHED_PREFER_WRITE_X(x)       (((x) & GENMASK(1, 1)) >> 1)

#define DDR_UMCTL2_SCHED_PAGECLOSE(x)            (((x) << 2) & GENMASK(2, 2))
#define DDR_UMCTL2_SCHED_PAGECLOSE_M             GENMASK(2, 2)
#define DDR_UMCTL2_SCHED_PAGECLOSE_X(x)          (((x) & GENMASK(2, 2)) >> 2)

#define DDR_UMCTL2_SCHED_AUTOPRE_RMW(x)          (((x) << 7) & GENMASK(7, 7))
#define DDR_UMCTL2_SCHED_AUTOPRE_RMW_M           GENMASK(7, 7)
#define DDR_UMCTL2_SCHED_AUTOPRE_RMW_X(x)        (((x) & GENMASK(7, 7)) >> 7)

#define DDR_UMCTL2_SCHED_LPR_NUM_ENTRIES(x)      (((x) << 8) & GENMASK(12, 8))
#define DDR_UMCTL2_SCHED_LPR_NUM_ENTRIES_M       GENMASK(12, 8)
#define DDR_UMCTL2_SCHED_LPR_NUM_ENTRIES_X(x)    (((x) & GENMASK(12, 8)) >> 8)

#define DDR_UMCTL2_SCHED_GO2CRITICAL_HYSTERESIS(x)\
	(((x) << 16) & GENMASK(23, 16))
#define DDR_UMCTL2_SCHED_GO2CRITICAL_HYSTERESIS_M GENMASK(23, 16)
#define DDR_UMCTL2_SCHED_GO2CRITICAL_HYSTERESIS_X(x)\
	(((x) & GENMASK(23, 16)) >> 16)

#define DDR_UMCTL2_SCHED_RDWR_IDLE_GAP(x)        (((x) << 24) & GENMASK(30, 24))
#define DDR_UMCTL2_SCHED_RDWR_IDLE_GAP_M         GENMASK(30, 24)
#define DDR_UMCTL2_SCHED_RDWR_IDLE_GAP_X(x)      (((x) & GENMASK(30, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:SCHED1 */
#define DDR_UMCTL2_SCHED1(t)      (t + 0x254)

#define DDR_UMCTL2_SCHED1_PAGECLOSE_TIMER(x)     ((x) & GENMASK(7, 0))
#define DDR_UMCTL2_SCHED1_PAGECLOSE_TIMER_M      GENMASK(7, 0)
#define DDR_UMCTL2_SCHED1_PAGECLOSE_TIMER_X(x)   ((x) & GENMASK(7, 0))

/*      DDR_UMCTL2:UMCTL2_REGS:PERFHPR1 */
#define DDR_UMCTL2_PERFHPR1(t)    (t + 0x25c)

#define DDR_UMCTL2_PERFHPR1_HPR_MAX_STARVE(x)    ((x) & GENMASK(15, 0))
#define DDR_UMCTL2_PERFHPR1_HPR_MAX_STARVE_M     GENMASK(15, 0)
#define DDR_UMCTL2_PERFHPR1_HPR_MAX_STARVE_X(x)  ((x) & GENMASK(15, 0))

#define DDR_UMCTL2_PERFHPR1_HPR_XACT_RUN_LENGTH(x)\
	(((x) << 24) & GENMASK(31, 24))
#define DDR_UMCTL2_PERFHPR1_HPR_XACT_RUN_LENGTH_M GENMASK(31, 24)
#define DDR_UMCTL2_PERFHPR1_HPR_XACT_RUN_LENGTH_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:PERFLPR1 */
#define DDR_UMCTL2_PERFLPR1(t)    (t + 0x264)

#define DDR_UMCTL2_PERFLPR1_LPR_MAX_STARVE(x)    ((x) & GENMASK(15, 0))
#define DDR_UMCTL2_PERFLPR1_LPR_MAX_STARVE_M     GENMASK(15, 0)
#define DDR_UMCTL2_PERFLPR1_LPR_MAX_STARVE_X(x)  ((x) & GENMASK(15, 0))

#define DDR_UMCTL2_PERFLPR1_LPR_XACT_RUN_LENGTH(x)\
	(((x) << 24) & GENMASK(31, 24))
#define DDR_UMCTL2_PERFLPR1_LPR_XACT_RUN_LENGTH_M GENMASK(31, 24)
#define DDR_UMCTL2_PERFLPR1_LPR_XACT_RUN_LENGTH_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:PERFWR1 */
#define DDR_UMCTL2_PERFWR1(t)     (t + 0x26c)

#define DDR_UMCTL2_PERFWR1_W_MAX_STARVE(x)       ((x) & GENMASK(15, 0))
#define DDR_UMCTL2_PERFWR1_W_MAX_STARVE_M        GENMASK(15, 0)
#define DDR_UMCTL2_PERFWR1_W_MAX_STARVE_X(x)     ((x) & GENMASK(15, 0))

#define DDR_UMCTL2_PERFWR1_W_XACT_RUN_LENGTH(x)  (((x) << 24) & GENMASK(31, 24))
#define DDR_UMCTL2_PERFWR1_W_XACT_RUN_LENGTH_M   GENMASK(31, 24)
#define DDR_UMCTL2_PERFWR1_W_XACT_RUN_LENGTH_X(x)\
	(((x) & GENMASK(31, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:DBG0 */
#define DDR_UMCTL2_DBG0(t)        (t + 0x300)

#define DDR_UMCTL2_DBG0_DIS_WC(x)                ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_DBG0_DIS_WC_M                 GENMASK(0, 0)
#define DDR_UMCTL2_DBG0_DIS_WC_X(x)              ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_DBG0_DIS_COLLISION_PAGE_OPT(x) (((x) << 4) & GENMASK(4, 4))
#define DDR_UMCTL2_DBG0_DIS_COLLISION_PAGE_OPT_M GENMASK(4, 4)
#define DDR_UMCTL2_DBG0_DIS_COLLISION_PAGE_OPT_X(x) (((x) & GENMASK(4, 4)) >> 4)

#define DDR_UMCTL2_DBG0_DIS_MAX_RANK_RD_OPT(x)   (((x) << 6) & GENMASK(6, 6))
#define DDR_UMCTL2_DBG0_DIS_MAX_RANK_RD_OPT_M    GENMASK(6, 6)
#define DDR_UMCTL2_DBG0_DIS_MAX_RANK_RD_OPT_X(x) (((x) & GENMASK(6, 6)) >> 6)

#define DDR_UMCTL2_DBG0_DIS_MAX_RANK_WR_OPT(x)   (((x) << 7) & GENMASK(7, 7))
#define DDR_UMCTL2_DBG0_DIS_MAX_RANK_WR_OPT_M    GENMASK(7, 7)
#define DDR_UMCTL2_DBG0_DIS_MAX_RANK_WR_OPT_X(x) (((x) & GENMASK(7, 7)) >> 7)

/*      DDR_UMCTL2:UMCTL2_REGS:DBG1 */
#define DDR_UMCTL2_DBG1(t)        (t + 0x304)

#define DDR_UMCTL2_DBG1_DIS_DQ(x)                ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_DBG1_DIS_DQ_M                 GENMASK(0, 0)
#define DDR_UMCTL2_DBG1_DIS_DQ_X(x)              ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_DBG1_DIS_HIF(x)               (((x) << 1) & GENMASK(1, 1))
#define DDR_UMCTL2_DBG1_DIS_HIF_M                GENMASK(1, 1)
#define DDR_UMCTL2_DBG1_DIS_HIF_X(x)             (((x) & GENMASK(1, 1)) >> 1)

/*      DDR_UMCTL2:UMCTL2_REGS:DBGCAM */
#define DDR_UMCTL2_DBGCAM(t)      (t + 0x308)

#define DDR_UMCTL2_DBGCAM_DBG_HPR_Q_DEPTH(x)     ((x) & GENMASK(5, 0))
#define DDR_UMCTL2_DBGCAM_DBG_HPR_Q_DEPTH_M      GENMASK(5, 0)
#define DDR_UMCTL2_DBGCAM_DBG_HPR_Q_DEPTH_X(x)   ((x) & GENMASK(5, 0))

#define DDR_UMCTL2_DBGCAM_DBG_LPR_Q_DEPTH(x)     (((x) << 8) & GENMASK(13, 8))
#define DDR_UMCTL2_DBGCAM_DBG_LPR_Q_DEPTH_M      GENMASK(13, 8)
#define DDR_UMCTL2_DBGCAM_DBG_LPR_Q_DEPTH_X(x)   (((x) & GENMASK(13, 8)) >> 8)

#define DDR_UMCTL2_DBGCAM_DBG_W_Q_DEPTH(x)       (((x) << 16) & GENMASK(21, 16))
#define DDR_UMCTL2_DBGCAM_DBG_W_Q_DEPTH_M        GENMASK(21, 16)
#define DDR_UMCTL2_DBGCAM_DBG_W_Q_DEPTH_X(x)     (((x) & GENMASK(21, 16)) >> 16)

#define DDR_UMCTL2_DBGCAM_DBG_STALL(x)           (((x) << 24) & GENMASK(24, 24))
#define DDR_UMCTL2_DBGCAM_DBG_STALL_M            GENMASK(24, 24)
#define DDR_UMCTL2_DBGCAM_DBG_STALL_X(x)         (((x) & GENMASK(24, 24)) >> 24)

#define DDR_UMCTL2_DBGCAM_DBG_RD_Q_EMPTY(x)      (((x) << 25) & GENMASK(25, 25))
#define DDR_UMCTL2_DBGCAM_DBG_RD_Q_EMPTY_M       GENMASK(25, 25)
#define DDR_UMCTL2_DBGCAM_DBG_RD_Q_EMPTY_X(x)    (((x) & GENMASK(25, 25)) >> 25)

#define DDR_UMCTL2_DBGCAM_DBG_WR_Q_EMPTY(x)      (((x) << 26) & GENMASK(26, 26))
#define DDR_UMCTL2_DBGCAM_DBG_WR_Q_EMPTY_M       GENMASK(26, 26)
#define DDR_UMCTL2_DBGCAM_DBG_WR_Q_EMPTY_X(x)    (((x) & GENMASK(26, 26)) >> 26)

#define DDR_UMCTL2_DBGCAM_RD_DATA_PIPELINE_EMPTY(x)\
	(((x) << 28) & GENMASK(28, 28))
#define DDR_UMCTL2_DBGCAM_RD_DATA_PIPELINE_EMPTY_M GENMASK(28, 28)
#define DDR_UMCTL2_DBGCAM_RD_DATA_PIPELINE_EMPTY_X(x)\
	(((x) & GENMASK(28, 28)) >> 28)

#define DDR_UMCTL2_DBGCAM_WR_DATA_PIPELINE_EMPTY(x)\
	(((x) << 29) & GENMASK(29, 29))
#define DDR_UMCTL2_DBGCAM_WR_DATA_PIPELINE_EMPTY_M GENMASK(29, 29)
#define DDR_UMCTL2_DBGCAM_WR_DATA_PIPELINE_EMPTY_X(x)\
	(((x) & GENMASK(29, 29)) >> 29)

/*      DDR_UMCTL2:UMCTL2_REGS:DBGCMD */
#define DDR_UMCTL2_DBGCMD(t)      (t + 0x30c)

#define DDR_UMCTL2_DBGCMD_RANK0_REFRESH(x)       ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_DBGCMD_RANK0_REFRESH_M        GENMASK(0, 0)
#define DDR_UMCTL2_DBGCMD_RANK0_REFRESH_X(x)     ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_DBGCMD_RANK1_REFRESH(x)       (((x) << 1) & GENMASK(1, 1))
#define DDR_UMCTL2_DBGCMD_RANK1_REFRESH_M        GENMASK(1, 1)
#define DDR_UMCTL2_DBGCMD_RANK1_REFRESH_X(x)     (((x) & GENMASK(1, 1)) >> 1)

#define DDR_UMCTL2_DBGCMD_ZQ_CALIB_SHORT(x)      (((x) << 4) & GENMASK(4, 4))
#define DDR_UMCTL2_DBGCMD_ZQ_CALIB_SHORT_M       GENMASK(4, 4)
#define DDR_UMCTL2_DBGCMD_ZQ_CALIB_SHORT_X(x)    (((x) & GENMASK(4, 4)) >> 4)

#define DDR_UMCTL2_DBGCMD_CTRLUPD(x)             (((x) << 5) & GENMASK(5, 5))
#define DDR_UMCTL2_DBGCMD_CTRLUPD_M              GENMASK(5, 5)
#define DDR_UMCTL2_DBGCMD_CTRLUPD_X(x)           (((x) & GENMASK(5, 5)) >> 5)

/*      DDR_UMCTL2:UMCTL2_REGS:DBGSTAT */
#define DDR_UMCTL2_DBGSTAT(t)     (t + 0x310)

#define DDR_UMCTL2_DBGSTAT_RANK0_REFRESH_BUSY(x) ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_DBGSTAT_RANK0_REFRESH_BUSY_M  GENMASK(0, 0)
#define DDR_UMCTL2_DBGSTAT_RANK0_REFRESH_BUSY_X(x) ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_DBGSTAT_RANK1_REFRESH_BUSY(x) (((x) << 1) & GENMASK(1, 1))
#define DDR_UMCTL2_DBGSTAT_RANK1_REFRESH_BUSY_M  GENMASK(1, 1)
#define DDR_UMCTL2_DBGSTAT_RANK1_REFRESH_BUSY_X(x) (((x) & GENMASK(1, 1)) >> 1)

#define DDR_UMCTL2_DBGSTAT_ZQ_CALIB_SHORT_BUSY(x) (((x) << 4) & GENMASK(4, 4))
#define DDR_UMCTL2_DBGSTAT_ZQ_CALIB_SHORT_BUSY_M GENMASK(4, 4)
#define DDR_UMCTL2_DBGSTAT_ZQ_CALIB_SHORT_BUSY_X(x) (((x) & GENMASK(4, 4)) >> 4)

#define DDR_UMCTL2_DBGSTAT_CTRLUPD_BUSY(x)       (((x) << 5) & GENMASK(5, 5))
#define DDR_UMCTL2_DBGSTAT_CTRLUPD_BUSY_M        GENMASK(5, 5)
#define DDR_UMCTL2_DBGSTAT_CTRLUPD_BUSY_X(x)     (((x) & GENMASK(5, 5)) >> 5)

/*      DDR_UMCTL2:UMCTL2_REGS:DBGCAM1 */
#define DDR_UMCTL2_DBGCAM1(t)     (t + 0x318)

#define DDR_UMCTL2_DBGCAM1_DBG_WRECC_Q_DEPTH(x)  ((x) & GENMASK(5, 0))
#define DDR_UMCTL2_DBGCAM1_DBG_WRECC_Q_DEPTH_M   GENMASK(5, 0)
#define DDR_UMCTL2_DBGCAM1_DBG_WRECC_Q_DEPTH_X(x) ((x) & GENMASK(5, 0))

/*      DDR_UMCTL2:UMCTL2_REGS:SWCTL */
#define DDR_UMCTL2_SWCTL(t)       (t + 0x320)

#define DDR_UMCTL2_SWCTL_SW_DONE(x)              ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_SWCTL_SW_DONE_M               GENMASK(0, 0)
#define DDR_UMCTL2_SWCTL_SW_DONE_X(x)            ((x) & GENMASK(0, 0))

/*      DDR_UMCTL2:UMCTL2_REGS:SWSTAT */
#define DDR_UMCTL2_SWSTAT(t)      (t + 0x324)

#define DDR_UMCTL2_SWSTAT_SW_DONE_ACK(x)         ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_SWSTAT_SW_DONE_ACK_M          GENMASK(0, 0)
#define DDR_UMCTL2_SWSTAT_SW_DONE_ACK_X(x)       ((x) & GENMASK(0, 0))

/*      DDR_UMCTL2:UMCTL2_REGS:SWCTLSTATIC */
#define DDR_UMCTL2_SWCTLSTATIC(t) (t + 0x328)

#define DDR_UMCTL2_SWCTLSTATIC_SW_STATIC_UNLOCK(x) ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_SWCTLSTATIC_SW_STATIC_UNLOCK_M GENMASK(0, 0)
#define DDR_UMCTL2_SWCTLSTATIC_SW_STATIC_UNLOCK_X(x) ((x) & GENMASK(0, 0))

/*      DDR_UMCTL2:UMCTL2_REGS:POISONCFG */
#define DDR_UMCTL2_POISONCFG(t)   (t + 0x36c)

#define DDR_UMCTL2_POISONCFG_WR_POISON_SLVERR_EN(x) ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_POISONCFG_WR_POISON_SLVERR_EN_M GENMASK(0, 0)
#define DDR_UMCTL2_POISONCFG_WR_POISON_SLVERR_EN_X(x) ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_POISONCFG_WR_POISON_INTR_EN(x) (((x) << 4) & GENMASK(4, 4))
#define DDR_UMCTL2_POISONCFG_WR_POISON_INTR_EN_M GENMASK(4, 4)
#define DDR_UMCTL2_POISONCFG_WR_POISON_INTR_EN_X(x) (((x) & GENMASK(4, 4)) >> 4)

#define DDR_UMCTL2_POISONCFG_WR_POISON_INTR_CLR(x) (((x) << 8) & GENMASK(8, 8))
#define DDR_UMCTL2_POISONCFG_WR_POISON_INTR_CLR_M GENMASK(8, 8)
#define DDR_UMCTL2_POISONCFG_WR_POISON_INTR_CLR_X(x)\
	(((x) & GENMASK(8, 8)) >> 8)

#define DDR_UMCTL2_POISONCFG_RD_POISON_SLVERR_EN(x)\
	(((x) << 16) & GENMASK(16, 16))
#define DDR_UMCTL2_POISONCFG_RD_POISON_SLVERR_EN_M GENMASK(16, 16)
#define DDR_UMCTL2_POISONCFG_RD_POISON_SLVERR_EN_X(x)\
	(((x) & GENMASK(16, 16)) >> 16)

#define DDR_UMCTL2_POISONCFG_RD_POISON_INTR_EN(x)\
	(((x) << 20) & GENMASK(20, 20))
#define DDR_UMCTL2_POISONCFG_RD_POISON_INTR_EN_M GENMASK(20, 20)
#define DDR_UMCTL2_POISONCFG_RD_POISON_INTR_EN_X(x)\
	(((x) & GENMASK(20, 20)) >> 20)

#define DDR_UMCTL2_POISONCFG_RD_POISON_INTR_CLR(x)\
	(((x) << 24) & GENMASK(24, 24))
#define DDR_UMCTL2_POISONCFG_RD_POISON_INTR_CLR_M GENMASK(24, 24)
#define DDR_UMCTL2_POISONCFG_RD_POISON_INTR_CLR_X(x)\
	(((x) & GENMASK(24, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_REGS:POISONSTAT */
#define DDR_UMCTL2_POISONSTAT(t)  (t + 0x370)

#define DDR_UMCTL2_POISONSTAT_WR_POISON_INTR_0(x) ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_POISONSTAT_WR_POISON_INTR_0_M GENMASK(0, 0)
#define DDR_UMCTL2_POISONSTAT_WR_POISON_INTR_0_X(x) ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_POISONSTAT_WR_POISON_INTR_1(x) (((x) << 1) & GENMASK(1, 1))
#define DDR_UMCTL2_POISONSTAT_WR_POISON_INTR_1_M GENMASK(1, 1)
#define DDR_UMCTL2_POISONSTAT_WR_POISON_INTR_1_X(x) (((x) & GENMASK(1, 1)) >> 1)

#define DDR_UMCTL2_POISONSTAT_WR_POISON_INTR_2(x) (((x) << 2) & GENMASK(2, 2))
#define DDR_UMCTL2_POISONSTAT_WR_POISON_INTR_2_M GENMASK(2, 2)
#define DDR_UMCTL2_POISONSTAT_WR_POISON_INTR_2_X(x) (((x) & GENMASK(2, 2)) >> 2)

#define DDR_UMCTL2_POISONSTAT_RD_POISON_INTR_0(x)\
	(((x) << 16) & GENMASK(16, 16))
#define DDR_UMCTL2_POISONSTAT_RD_POISON_INTR_0_M GENMASK(16, 16)
#define DDR_UMCTL2_POISONSTAT_RD_POISON_INTR_0_X(x)\
	(((x) & GENMASK(16, 16)) >> 16)

#define DDR_UMCTL2_POISONSTAT_RD_POISON_INTR_1(x)\
	(((x) << 17) & GENMASK(17, 17))
#define DDR_UMCTL2_POISONSTAT_RD_POISON_INTR_1_M GENMASK(17, 17)
#define DDR_UMCTL2_POISONSTAT_RD_POISON_INTR_1_X(x)\
	(((x) & GENMASK(17, 17)) >> 17)

#define DDR_UMCTL2_POISONSTAT_RD_POISON_INTR_2(x)\
	(((x) << 18) & GENMASK(18, 18))
#define DDR_UMCTL2_POISONSTAT_RD_POISON_INTR_2_M GENMASK(18, 18)
#define DDR_UMCTL2_POISONSTAT_RD_POISON_INTR_2_X(x)\
	(((x) & GENMASK(18, 18)) >> 18)

/*      DDR_UMCTL2:UMCTL2_REGS:ADVECCINDEX */
#define DDR_UMCTL2_ADVECCINDEX(t) (t + 0x374)

#define DDR_UMCTL2_ADVECCINDEX_ECC_SYNDROME_SEL(x) ((x) & GENMASK(2, 0))
#define DDR_UMCTL2_ADVECCINDEX_ECC_SYNDROME_SEL_M GENMASK(2, 0)
#define DDR_UMCTL2_ADVECCINDEX_ECC_SYNDROME_SEL_X(x) ((x) & GENMASK(2, 0))

#define DDR_UMCTL2_ADVECCINDEX_ECC_ERR_SYMBOL_SEL(x)\
	(((x) << 3) & GENMASK(4, 3))
#define DDR_UMCTL2_ADVECCINDEX_ECC_ERR_SYMBOL_SEL_M GENMASK(4, 3)
#define DDR_UMCTL2_ADVECCINDEX_ECC_ERR_SYMBOL_SEL_X(x)\
	(((x) & GENMASK(4, 3)) >> 3)

#define DDR_UMCTL2_ADVECCINDEX_ECC_POISON_BEATS_SEL(x)\
	(((x) << 5) & GENMASK(8, 5))
#define DDR_UMCTL2_ADVECCINDEX_ECC_POISON_BEATS_SEL_M GENMASK(8, 5)
#define DDR_UMCTL2_ADVECCINDEX_ECC_POISON_BEATS_SEL_X(x)\
	(((x) & GENMASK(8, 5)) >> 5)

/*      DDR_UMCTL2:UMCTL2_REGS:ECCPOISONPAT0 */
#define DDR_UMCTL2_ECCPOISONPAT0(t) (t + 0x37c)

/*      DDR_UMCTL2:UMCTL2_REGS:ECCPOISONPAT2 */
#define DDR_UMCTL2_ECCPOISONPAT2(t) (t + 0x384)

#define DDR_UMCTL2_ECCPOISONPAT2_ECC_POISON_DATA_71_64(x) ((x) & GENMASK(7, 0))
#define DDR_UMCTL2_ECCPOISONPAT2_ECC_POISON_DATA_71_64_M GENMASK(7, 0)
#define DDR_UMCTL2_ECCPOISONPAT2_ECC_POISON_DATA_71_64_X(x)\
	((x) & GENMASK(7, 0))

/*      DDR_UMCTL2:UMCTL2_REGS:ECCAPSTAT */
#define DDR_UMCTL2_ECCAPSTAT(t)   (t + 0x388)

#define DDR_UMCTL2_ECCAPSTAT_ECC_AP_ERR(x)       ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_ECCAPSTAT_ECC_AP_ERR_M        GENMASK(0, 0)
#define DDR_UMCTL2_ECCAPSTAT_ECC_AP_ERR_X(x)     ((x) & GENMASK(0, 0))

/*      DDR_UMCTL2:UMCTL2_MP:PSTAT */
#define DDR_UMCTL2_PSTAT(t)       (t + 0x3fc)

#define DDR_UMCTL2_PSTAT_RD_PORT_BUSY_0(x)       ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_PSTAT_RD_PORT_BUSY_0_M        GENMASK(0, 0)
#define DDR_UMCTL2_PSTAT_RD_PORT_BUSY_0_X(x)     ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_PSTAT_RD_PORT_BUSY_1(x)       (((x) << 1) & GENMASK(1, 1))
#define DDR_UMCTL2_PSTAT_RD_PORT_BUSY_1_M        GENMASK(1, 1)
#define DDR_UMCTL2_PSTAT_RD_PORT_BUSY_1_X(x)     (((x) & GENMASK(1, 1)) >> 1)

#define DDR_UMCTL2_PSTAT_RD_PORT_BUSY_2(x)       (((x) << 2) & GENMASK(2, 2))
#define DDR_UMCTL2_PSTAT_RD_PORT_BUSY_2_M        GENMASK(2, 2)
#define DDR_UMCTL2_PSTAT_RD_PORT_BUSY_2_X(x)     (((x) & GENMASK(2, 2)) >> 2)

#define DDR_UMCTL2_PSTAT_WR_PORT_BUSY_0(x)       (((x) << 16) & GENMASK(16, 16))
#define DDR_UMCTL2_PSTAT_WR_PORT_BUSY_0_M        GENMASK(16, 16)
#define DDR_UMCTL2_PSTAT_WR_PORT_BUSY_0_X(x)     (((x) & GENMASK(16, 16)) >> 16)

#define DDR_UMCTL2_PSTAT_WR_PORT_BUSY_1(x)       (((x) << 17) & GENMASK(17, 17))
#define DDR_UMCTL2_PSTAT_WR_PORT_BUSY_1_M        GENMASK(17, 17)
#define DDR_UMCTL2_PSTAT_WR_PORT_BUSY_1_X(x)     (((x) & GENMASK(17, 17)) >> 17)

#define DDR_UMCTL2_PSTAT_WR_PORT_BUSY_2(x)       (((x) << 18) & GENMASK(18, 18))
#define DDR_UMCTL2_PSTAT_WR_PORT_BUSY_2_M        GENMASK(18, 18)
#define DDR_UMCTL2_PSTAT_WR_PORT_BUSY_2_X(x)     (((x) & GENMASK(18, 18)) >> 18)

/*      DDR_UMCTL2:UMCTL2_MP:PCCFG */
#define DDR_UMCTL2_PCCFG(t)       (t + 0x400)

#define DDR_UMCTL2_PCCFG_GO2CRITICAL_EN(x)       ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_PCCFG_GO2CRITICAL_EN_M        GENMASK(0, 0)
#define DDR_UMCTL2_PCCFG_GO2CRITICAL_EN_X(x)     ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_PCCFG_PAGEMATCH_LIMIT(x)      (((x) << 4) & GENMASK(4, 4))
#define DDR_UMCTL2_PCCFG_PAGEMATCH_LIMIT_M       GENMASK(4, 4)
#define DDR_UMCTL2_PCCFG_PAGEMATCH_LIMIT_X(x)    (((x) & GENMASK(4, 4)) >> 4)

#define DDR_UMCTL2_PCCFG_BL_EXP_MODE(x)          (((x) << 8) & GENMASK(8, 8))
#define DDR_UMCTL2_PCCFG_BL_EXP_MODE_M           GENMASK(8, 8)
#define DDR_UMCTL2_PCCFG_BL_EXP_MODE_X(x)        (((x) & GENMASK(8, 8)) >> 8)

/*      DDR_UMCTL2:UMCTL2_MP:PCFGR_0 */
#define DDR_UMCTL2_PCFGR_0(t)     (t + 0x404)

#define DDR_UMCTL2_PCFGR_0_PCFGR_0_RD_PORT_PRIORITY(x) ((x) & GENMASK(9, 0))
#define DDR_UMCTL2_PCFGR_0_PCFGR_0_RD_PORT_PRIORITY_M GENMASK(9, 0)
#define DDR_UMCTL2_PCFGR_0_PCFGR_0_RD_PORT_PRIORITY_X(x) ((x) & GENMASK(9, 0))

#define DDR_UMCTL2_PCFGR_0_PCFGR_0_RD_PORT_AGING_EN(x)\
	(((x) << 12) & GENMASK(12, 12))
#define DDR_UMCTL2_PCFGR_0_PCFGR_0_RD_PORT_AGING_EN_M GENMASK(12, 12)
#define DDR_UMCTL2_PCFGR_0_PCFGR_0_RD_PORT_AGING_EN_X(x)\
	(((x) & GENMASK(12, 12)) >> 12)

#define DDR_UMCTL2_PCFGR_0_PCFGR_0_RD_PORT_URGENT_EN(x)\
	(((x) << 13) & GENMASK(13, 13))
#define DDR_UMCTL2_PCFGR_0_PCFGR_0_RD_PORT_URGENT_EN_M GENMASK(13, 13)
#define DDR_UMCTL2_PCFGR_0_PCFGR_0_RD_PORT_URGENT_EN_X(x)\
	(((x) & GENMASK(13, 13)) >> 13)

#define DDR_UMCTL2_PCFGR_0_PCFGR_0_RD_PORT_PAGEMATCH_EN(x)\
	(((x) << 14) & GENMASK(14, 14))
#define DDR_UMCTL2_PCFGR_0_PCFGR_0_RD_PORT_PAGEMATCH_EN_M GENMASK(14, 14)
#define DDR_UMCTL2_PCFGR_0_PCFGR_0_RD_PORT_PAGEMATCH_EN_X(x)\
	(((x) & GENMASK(14, 14)) >> 14)

/*      DDR_UMCTL2:UMCTL2_MP:PCFGW_0 */
#define DDR_UMCTL2_PCFGW_0(t)     (t + 0x408)

#define DDR_UMCTL2_PCFGW_0_PCFGW_0_WR_PORT_PRIORITY(x) ((x) & GENMASK(9, 0))
#define DDR_UMCTL2_PCFGW_0_PCFGW_0_WR_PORT_PRIORITY_M GENMASK(9, 0)
#define DDR_UMCTL2_PCFGW_0_PCFGW_0_WR_PORT_PRIORITY_X(x) ((x) & GENMASK(9, 0))

#define DDR_UMCTL2_PCFGW_0_PCFGW_0_WR_PORT_AGING_EN(x)\
	(((x) << 12) & GENMASK(12, 12))
#define DDR_UMCTL2_PCFGW_0_PCFGW_0_WR_PORT_AGING_EN_M GENMASK(12, 12)
#define DDR_UMCTL2_PCFGW_0_PCFGW_0_WR_PORT_AGING_EN_X(x)\
	(((x) & GENMASK(12, 12)) >> 12)

#define DDR_UMCTL2_PCFGW_0_PCFGW_0_WR_PORT_URGENT_EN(x)\
	(((x) << 13) & GENMASK(13, 13))
#define DDR_UMCTL2_PCFGW_0_PCFGW_0_WR_PORT_URGENT_EN_M GENMASK(13, 13)
#define DDR_UMCTL2_PCFGW_0_PCFGW_0_WR_PORT_URGENT_EN_X(x)\
	(((x) & GENMASK(13, 13)) >> 13)

#define DDR_UMCTL2_PCFGW_0_PCFGW_0_WR_PORT_PAGEMATCH_EN(x)\
	(((x) << 14) & GENMASK(14, 14))
#define DDR_UMCTL2_PCFGW_0_PCFGW_0_WR_PORT_PAGEMATCH_EN_M GENMASK(14, 14)
#define DDR_UMCTL2_PCFGW_0_PCFGW_0_WR_PORT_PAGEMATCH_EN_X(x)\
	(((x) & GENMASK(14, 14)) >> 14)

/*      DDR_UMCTL2:UMCTL2_MP:PCTRL_0 */
#define DDR_UMCTL2_PCTRL_0(t)     (t + 0x490)

#define DDR_UMCTL2_PCTRL_0_PCTRL_0_PORT_EN(x)    ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_PCTRL_0_PCTRL_0_PORT_EN_M     GENMASK(0, 0)
#define DDR_UMCTL2_PCTRL_0_PCTRL_0_PORT_EN_X(x)  ((x) & GENMASK(0, 0))

/*      DDR_UMCTL2:UMCTL2_MP:PCFGQOS0_0 */
#define DDR_UMCTL2_PCFGQOS0_0(t)  (t + 0x494)

#define DDR_UMCTL2_PCFGQOS0_0_PCFGQOS0_0_RQOS_MAP_LEVEL1(x)\
	((x) & GENMASK(3, 0))
#define DDR_UMCTL2_PCFGQOS0_0_PCFGQOS0_0_RQOS_MAP_LEVEL1_M GENMASK(3, 0)
#define DDR_UMCTL2_PCFGQOS0_0_PCFGQOS0_0_RQOS_MAP_LEVEL1_X(x)\
	((x) & GENMASK(3, 0))

#define DDR_UMCTL2_PCFGQOS0_0_PCFGQOS0_0_RQOS_MAP_REGION0(x)\
	(((x) << 16) & GENMASK(17, 16))
#define DDR_UMCTL2_PCFGQOS0_0_PCFGQOS0_0_RQOS_MAP_REGION0_M GENMASK(17, 16)
#define DDR_UMCTL2_PCFGQOS0_0_PCFGQOS0_0_RQOS_MAP_REGION0_X(x)\
	(((x) & GENMASK(17, 16)) >> 16)

#define DDR_UMCTL2_PCFGQOS0_0_PCFGQOS0_0_RQOS_MAP_REGION1(x)\
	(((x) << 20) & GENMASK(21, 20))
#define DDR_UMCTL2_PCFGQOS0_0_PCFGQOS0_0_RQOS_MAP_REGION1_M GENMASK(21, 20)
#define DDR_UMCTL2_PCFGQOS0_0_PCFGQOS0_0_RQOS_MAP_REGION1_X(x)\
	(((x) & GENMASK(21, 20)) >> 20)

/*      DDR_UMCTL2:UMCTL2_MP:PCFGQOS1_0 */
#define DDR_UMCTL2_PCFGQOS1_0(t)  (t + 0x498)

#define DDR_UMCTL2_PCFGQOS1_0_PCFGQOS1_0_RQOS_MAP_TIMEOUTB(x)\
	((x) & GENMASK(10, 0))
#define DDR_UMCTL2_PCFGQOS1_0_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_M GENMASK(10, 0)
#define DDR_UMCTL2_PCFGQOS1_0_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_X(x)\
	((x) & GENMASK(10, 0))

#define DDR_UMCTL2_PCFGQOS1_0_PCFGQOS1_0_RQOS_MAP_TIMEOUTR(x)\
	(((x) << 16) & GENMASK(26, 16))
#define DDR_UMCTL2_PCFGQOS1_0_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_M GENMASK(26, 16)
#define DDR_UMCTL2_PCFGQOS1_0_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_X(x)\
	(((x) & GENMASK(26, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_MP:PCFGWQOS0_0 */
#define DDR_UMCTL2_PCFGWQOS0_0(t) (t + 0x49c)

#define DDR_UMCTL2_PCFGWQOS0_0_PCFGWQOS0_0_WQOS_MAP_LEVEL1(x)\
	((x) & GENMASK(3, 0))
#define DDR_UMCTL2_PCFGWQOS0_0_PCFGWQOS0_0_WQOS_MAP_LEVEL1_M GENMASK(3, 0)
#define DDR_UMCTL2_PCFGWQOS0_0_PCFGWQOS0_0_WQOS_MAP_LEVEL1_X(x)\
	((x) & GENMASK(3, 0))

#define DDR_UMCTL2_PCFGWQOS0_0_PCFGWQOS0_0_WQOS_MAP_LEVEL2(x)\
	(((x) << 8) & GENMASK(11, 8))
#define DDR_UMCTL2_PCFGWQOS0_0_PCFGWQOS0_0_WQOS_MAP_LEVEL2_M GENMASK(11, 8)
#define DDR_UMCTL2_PCFGWQOS0_0_PCFGWQOS0_0_WQOS_MAP_LEVEL2_X(x)\
	(((x) & GENMASK(11, 8)) >> 8)

#define DDR_UMCTL2_PCFGWQOS0_0_PCFGWQOS0_0_WQOS_MAP_REGION0(x)\
	(((x) << 16) & GENMASK(17, 16))
#define DDR_UMCTL2_PCFGWQOS0_0_PCFGWQOS0_0_WQOS_MAP_REGION0_M GENMASK(17, 16)
#define DDR_UMCTL2_PCFGWQOS0_0_PCFGWQOS0_0_WQOS_MAP_REGION0_X(x)\
	(((x) & GENMASK(17, 16)) >> 16)

#define DDR_UMCTL2_PCFGWQOS0_0_PCFGWQOS0_0_WQOS_MAP_REGION1(x)\
	(((x) << 20) & GENMASK(21, 20))
#define DDR_UMCTL2_PCFGWQOS0_0_PCFGWQOS0_0_WQOS_MAP_REGION1_M GENMASK(21, 20)
#define DDR_UMCTL2_PCFGWQOS0_0_PCFGWQOS0_0_WQOS_MAP_REGION1_X(x)\
	(((x) & GENMASK(21, 20)) >> 20)

#define DDR_UMCTL2_PCFGWQOS0_0_PCFGWQOS0_0_WQOS_MAP_REGION2(x)\
	(((x) << 24) & GENMASK(25, 24))
#define DDR_UMCTL2_PCFGWQOS0_0_PCFGWQOS0_0_WQOS_MAP_REGION2_M GENMASK(25, 24)
#define DDR_UMCTL2_PCFGWQOS0_0_PCFGWQOS0_0_WQOS_MAP_REGION2_X(x)\
	(((x) & GENMASK(25, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_MP:PCFGWQOS1_0 */
#define DDR_UMCTL2_PCFGWQOS1_0(t) (t + 0x4a0)

#define DDR_UMCTL2_PCFGWQOS1_0_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1(x)\
	((x) & GENMASK(10, 0))
#define DDR_UMCTL2_PCFGWQOS1_0_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_M GENMASK(10, 0)
#define DDR_UMCTL2_PCFGWQOS1_0_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_X(x)\
	((x) & GENMASK(10, 0))

#define DDR_UMCTL2_PCFGWQOS1_0_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2(x)\
	(((x) << 16) & GENMASK(26, 16))
#define DDR_UMCTL2_PCFGWQOS1_0_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_M GENMASK(26, 16)
#define DDR_UMCTL2_PCFGWQOS1_0_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_X(x)\
	(((x) & GENMASK(26, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_MP:PCFGR_1 */
#define DDR_UMCTL2_PCFGR_1(t)     (t + 0x4b4)

#define DDR_UMCTL2_PCFGR_1_PCFGR_1_RD_PORT_PRIORITY(x) ((x) & GENMASK(9, 0))
#define DDR_UMCTL2_PCFGR_1_PCFGR_1_RD_PORT_PRIORITY_M GENMASK(9, 0)
#define DDR_UMCTL2_PCFGR_1_PCFGR_1_RD_PORT_PRIORITY_X(x) ((x) & GENMASK(9, 0))

#define DDR_UMCTL2_PCFGR_1_PCFGR_1_RD_PORT_AGING_EN(x)\
	(((x) << 12) & GENMASK(12, 12))
#define DDR_UMCTL2_PCFGR_1_PCFGR_1_RD_PORT_AGING_EN_M GENMASK(12, 12)
#define DDR_UMCTL2_PCFGR_1_PCFGR_1_RD_PORT_AGING_EN_X(x)\
	(((x) & GENMASK(12, 12)) >> 12)

#define DDR_UMCTL2_PCFGR_1_PCFGR_1_RD_PORT_URGENT_EN(x)\
	(((x) << 13) & GENMASK(13, 13))
#define DDR_UMCTL2_PCFGR_1_PCFGR_1_RD_PORT_URGENT_EN_M GENMASK(13, 13)
#define DDR_UMCTL2_PCFGR_1_PCFGR_1_RD_PORT_URGENT_EN_X(x)\
	(((x) & GENMASK(13, 13)) >> 13)

#define DDR_UMCTL2_PCFGR_1_PCFGR_1_RD_PORT_PAGEMATCH_EN(x)\
	(((x) << 14) & GENMASK(14, 14))
#define DDR_UMCTL2_PCFGR_1_PCFGR_1_RD_PORT_PAGEMATCH_EN_M GENMASK(14, 14)
#define DDR_UMCTL2_PCFGR_1_PCFGR_1_RD_PORT_PAGEMATCH_EN_X(x)\
	(((x) & GENMASK(14, 14)) >> 14)

/*      DDR_UMCTL2:UMCTL2_MP:PCFGW_1 */
#define DDR_UMCTL2_PCFGW_1(t)     (t + 0x4b8)

#define DDR_UMCTL2_PCFGW_1_PCFGW_1_WR_PORT_PRIORITY(x) ((x) & GENMASK(9, 0))
#define DDR_UMCTL2_PCFGW_1_PCFGW_1_WR_PORT_PRIORITY_M GENMASK(9, 0)
#define DDR_UMCTL2_PCFGW_1_PCFGW_1_WR_PORT_PRIORITY_X(x) ((x) & GENMASK(9, 0))

#define DDR_UMCTL2_PCFGW_1_PCFGW_1_WR_PORT_AGING_EN(x)\
	(((x) << 12) & GENMASK(12, 12))
#define DDR_UMCTL2_PCFGW_1_PCFGW_1_WR_PORT_AGING_EN_M GENMASK(12, 12)
#define DDR_UMCTL2_PCFGW_1_PCFGW_1_WR_PORT_AGING_EN_X(x)\
	(((x) & GENMASK(12, 12)) >> 12)

#define DDR_UMCTL2_PCFGW_1_PCFGW_1_WR_PORT_URGENT_EN(x)\
	(((x) << 13) & GENMASK(13, 13))
#define DDR_UMCTL2_PCFGW_1_PCFGW_1_WR_PORT_URGENT_EN_M GENMASK(13, 13)
#define DDR_UMCTL2_PCFGW_1_PCFGW_1_WR_PORT_URGENT_EN_X(x)\
	(((x) & GENMASK(13, 13)) >> 13)

#define DDR_UMCTL2_PCFGW_1_PCFGW_1_WR_PORT_PAGEMATCH_EN(x)\
	(((x) << 14) & GENMASK(14, 14))
#define DDR_UMCTL2_PCFGW_1_PCFGW_1_WR_PORT_PAGEMATCH_EN_M GENMASK(14, 14)
#define DDR_UMCTL2_PCFGW_1_PCFGW_1_WR_PORT_PAGEMATCH_EN_X(x)\
	(((x) & GENMASK(14, 14)) >> 14)

/*      DDR_UMCTL2:UMCTL2_MP:PCTRL_1 */
#define DDR_UMCTL2_PCTRL_1(t)     (t + 0x540)

#define DDR_UMCTL2_PCTRL_1_PCTRL_1_PORT_EN(x)    ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_PCTRL_1_PCTRL_1_PORT_EN_M     GENMASK(0, 0)
#define DDR_UMCTL2_PCTRL_1_PCTRL_1_PORT_EN_X(x)  ((x) & GENMASK(0, 0))

/*      DDR_UMCTL2:UMCTL2_MP:PCFGQOS0_1 */
#define DDR_UMCTL2_PCFGQOS0_1(t)  (t + 0x544)

#define DDR_UMCTL2_PCFGQOS0_1_PCFGQOS0_1_RQOS_MAP_LEVEL1(x)\
	((x) & GENMASK(3, 0))
#define DDR_UMCTL2_PCFGQOS0_1_PCFGQOS0_1_RQOS_MAP_LEVEL1_M GENMASK(3, 0)
#define DDR_UMCTL2_PCFGQOS0_1_PCFGQOS0_1_RQOS_MAP_LEVEL1_X(x)\
	((x) & GENMASK(3, 0))

#define DDR_UMCTL2_PCFGQOS0_1_PCFGQOS0_1_RQOS_MAP_REGION0(x)\
	(((x) << 16) & GENMASK(17, 16))
#define DDR_UMCTL2_PCFGQOS0_1_PCFGQOS0_1_RQOS_MAP_REGION0_M GENMASK(17, 16)
#define DDR_UMCTL2_PCFGQOS0_1_PCFGQOS0_1_RQOS_MAP_REGION0_X(x)\
	(((x) & GENMASK(17, 16)) >> 16)

#define DDR_UMCTL2_PCFGQOS0_1_PCFGQOS0_1_RQOS_MAP_REGION1(x)\
	(((x) << 20) & GENMASK(21, 20))
#define DDR_UMCTL2_PCFGQOS0_1_PCFGQOS0_1_RQOS_MAP_REGION1_M GENMASK(21, 20)
#define DDR_UMCTL2_PCFGQOS0_1_PCFGQOS0_1_RQOS_MAP_REGION1_X(x)\
	(((x) & GENMASK(21, 20)) >> 20)

/*      DDR_UMCTL2:UMCTL2_MP:PCFGQOS1_1 */
#define DDR_UMCTL2_PCFGQOS1_1(t)  (t + 0x548)

#define DDR_UMCTL2_PCFGQOS1_1_PCFGQOS1_1_RQOS_MAP_TIMEOUTB(x)\
	((x) & GENMASK(10, 0))
#define DDR_UMCTL2_PCFGQOS1_1_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_M GENMASK(10, 0)
#define DDR_UMCTL2_PCFGQOS1_1_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_X(x)\
	((x) & GENMASK(10, 0))

#define DDR_UMCTL2_PCFGQOS1_1_PCFGQOS1_1_RQOS_MAP_TIMEOUTR(x)\
	(((x) << 16) & GENMASK(26, 16))
#define DDR_UMCTL2_PCFGQOS1_1_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_M GENMASK(26, 16)
#define DDR_UMCTL2_PCFGQOS1_1_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_X(x)\
	(((x) & GENMASK(26, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_MP:PCFGWQOS0_1 */
#define DDR_UMCTL2_PCFGWQOS0_1(t) (t + 0x54c)

#define DDR_UMCTL2_PCFGWQOS0_1_PCFGWQOS0_1_WQOS_MAP_LEVEL1(x)\
	((x) & GENMASK(3, 0))
#define DDR_UMCTL2_PCFGWQOS0_1_PCFGWQOS0_1_WQOS_MAP_LEVEL1_M GENMASK(3, 0)
#define DDR_UMCTL2_PCFGWQOS0_1_PCFGWQOS0_1_WQOS_MAP_LEVEL1_X(x)\
	((x) & GENMASK(3, 0))

#define DDR_UMCTL2_PCFGWQOS0_1_PCFGWQOS0_1_WQOS_MAP_LEVEL2(x)\
	(((x) << 8) & GENMASK(11, 8))
#define DDR_UMCTL2_PCFGWQOS0_1_PCFGWQOS0_1_WQOS_MAP_LEVEL2_M GENMASK(11, 8)
#define DDR_UMCTL2_PCFGWQOS0_1_PCFGWQOS0_1_WQOS_MAP_LEVEL2_X(x)\
	(((x) & GENMASK(11, 8)) >> 8)

#define DDR_UMCTL2_PCFGWQOS0_1_PCFGWQOS0_1_WQOS_MAP_REGION0(x)\
	(((x) << 16) & GENMASK(17, 16))
#define DDR_UMCTL2_PCFGWQOS0_1_PCFGWQOS0_1_WQOS_MAP_REGION0_M GENMASK(17, 16)
#define DDR_UMCTL2_PCFGWQOS0_1_PCFGWQOS0_1_WQOS_MAP_REGION0_X(x)\
	(((x) & GENMASK(17, 16)) >> 16)

#define DDR_UMCTL2_PCFGWQOS0_1_PCFGWQOS0_1_WQOS_MAP_REGION1(x)\
	(((x) << 20) & GENMASK(21, 20))
#define DDR_UMCTL2_PCFGWQOS0_1_PCFGWQOS0_1_WQOS_MAP_REGION1_M GENMASK(21, 20)
#define DDR_UMCTL2_PCFGWQOS0_1_PCFGWQOS0_1_WQOS_MAP_REGION1_X(x)\
	(((x) & GENMASK(21, 20)) >> 20)

#define DDR_UMCTL2_PCFGWQOS0_1_PCFGWQOS0_1_WQOS_MAP_REGION2(x)\
	(((x) << 24) & GENMASK(25, 24))
#define DDR_UMCTL2_PCFGWQOS0_1_PCFGWQOS0_1_WQOS_MAP_REGION2_M GENMASK(25, 24)
#define DDR_UMCTL2_PCFGWQOS0_1_PCFGWQOS0_1_WQOS_MAP_REGION2_X(x)\
	(((x) & GENMASK(25, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_MP:PCFGWQOS1_1 */
#define DDR_UMCTL2_PCFGWQOS1_1(t) (t + 0x550)

#define DDR_UMCTL2_PCFGWQOS1_1_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1(x)\
	((x) & GENMASK(10, 0))
#define DDR_UMCTL2_PCFGWQOS1_1_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_M GENMASK(10, 0)
#define DDR_UMCTL2_PCFGWQOS1_1_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_X(x)\
	((x) & GENMASK(10, 0))

#define DDR_UMCTL2_PCFGWQOS1_1_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2(x)\
	(((x) << 16) & GENMASK(26, 16))
#define DDR_UMCTL2_PCFGWQOS1_1_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_M GENMASK(26, 16)
#define DDR_UMCTL2_PCFGWQOS1_1_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_X(x)\
	(((x) & GENMASK(26, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_MP:PCFGR_2 */
#define DDR_UMCTL2_PCFGR_2(t)     (t + 0x564)

#define DDR_UMCTL2_PCFGR_2_PCFGR_2_RD_PORT_PRIORITY(x) ((x) & GENMASK(9, 0))
#define DDR_UMCTL2_PCFGR_2_PCFGR_2_RD_PORT_PRIORITY_M GENMASK(9, 0)
#define DDR_UMCTL2_PCFGR_2_PCFGR_2_RD_PORT_PRIORITY_X(x) ((x) & GENMASK(9, 0))

#define DDR_UMCTL2_PCFGR_2_PCFGR_2_RD_PORT_AGING_EN(x)\
	(((x) << 12) & GENMASK(12, 12))
#define DDR_UMCTL2_PCFGR_2_PCFGR_2_RD_PORT_AGING_EN_M GENMASK(12, 12)
#define DDR_UMCTL2_PCFGR_2_PCFGR_2_RD_PORT_AGING_EN_X(x)\
	(((x) & GENMASK(12, 12)) >> 12)

#define DDR_UMCTL2_PCFGR_2_PCFGR_2_RD_PORT_URGENT_EN(x)\
	(((x) << 13) & GENMASK(13, 13))
#define DDR_UMCTL2_PCFGR_2_PCFGR_2_RD_PORT_URGENT_EN_M GENMASK(13, 13)
#define DDR_UMCTL2_PCFGR_2_PCFGR_2_RD_PORT_URGENT_EN_X(x)\
	(((x) & GENMASK(13, 13)) >> 13)

#define DDR_UMCTL2_PCFGR_2_PCFGR_2_RD_PORT_PAGEMATCH_EN(x)\
	(((x) << 14) & GENMASK(14, 14))
#define DDR_UMCTL2_PCFGR_2_PCFGR_2_RD_PORT_PAGEMATCH_EN_M GENMASK(14, 14)
#define DDR_UMCTL2_PCFGR_2_PCFGR_2_RD_PORT_PAGEMATCH_EN_X(x)\
	(((x) & GENMASK(14, 14)) >> 14)

/*      DDR_UMCTL2:UMCTL2_MP:PCFGW_2 */
#define DDR_UMCTL2_PCFGW_2(t)     (t + 0x568)

#define DDR_UMCTL2_PCFGW_2_PCFGW_2_WR_PORT_PRIORITY(x) ((x) & GENMASK(9, 0))
#define DDR_UMCTL2_PCFGW_2_PCFGW_2_WR_PORT_PRIORITY_M GENMASK(9, 0)
#define DDR_UMCTL2_PCFGW_2_PCFGW_2_WR_PORT_PRIORITY_X(x) ((x) & GENMASK(9, 0))

#define DDR_UMCTL2_PCFGW_2_PCFGW_2_WR_PORT_AGING_EN(x)\
	(((x) << 12) & GENMASK(12, 12))
#define DDR_UMCTL2_PCFGW_2_PCFGW_2_WR_PORT_AGING_EN_M GENMASK(12, 12)
#define DDR_UMCTL2_PCFGW_2_PCFGW_2_WR_PORT_AGING_EN_X(x)\
	(((x) & GENMASK(12, 12)) >> 12)

#define DDR_UMCTL2_PCFGW_2_PCFGW_2_WR_PORT_URGENT_EN(x)\
	(((x) << 13) & GENMASK(13, 13))
#define DDR_UMCTL2_PCFGW_2_PCFGW_2_WR_PORT_URGENT_EN_M GENMASK(13, 13)
#define DDR_UMCTL2_PCFGW_2_PCFGW_2_WR_PORT_URGENT_EN_X(x)\
	(((x) & GENMASK(13, 13)) >> 13)

#define DDR_UMCTL2_PCFGW_2_PCFGW_2_WR_PORT_PAGEMATCH_EN(x)\
	(((x) << 14) & GENMASK(14, 14))
#define DDR_UMCTL2_PCFGW_2_PCFGW_2_WR_PORT_PAGEMATCH_EN_M GENMASK(14, 14)
#define DDR_UMCTL2_PCFGW_2_PCFGW_2_WR_PORT_PAGEMATCH_EN_X(x)\
	(((x) & GENMASK(14, 14)) >> 14)

/*      DDR_UMCTL2:UMCTL2_MP:PCTRL_2 */
#define DDR_UMCTL2_PCTRL_2(t)     (t + 0x5f0)

#define DDR_UMCTL2_PCTRL_2_PCTRL_2_PORT_EN(x)    ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_PCTRL_2_PCTRL_2_PORT_EN_M     GENMASK(0, 0)
#define DDR_UMCTL2_PCTRL_2_PCTRL_2_PORT_EN_X(x)  ((x) & GENMASK(0, 0))

/*      DDR_UMCTL2:UMCTL2_MP:PCFGQOS0_2 */
#define DDR_UMCTL2_PCFGQOS0_2(t)  (t + 0x5f4)

#define DDR_UMCTL2_PCFGQOS0_2_PCFGQOS0_2_RQOS_MAP_LEVEL1(x)\
	((x) & GENMASK(3, 0))
#define DDR_UMCTL2_PCFGQOS0_2_PCFGQOS0_2_RQOS_MAP_LEVEL1_M GENMASK(3, 0)
#define DDR_UMCTL2_PCFGQOS0_2_PCFGQOS0_2_RQOS_MAP_LEVEL1_X(x)\
	((x) & GENMASK(3, 0))

#define DDR_UMCTL2_PCFGQOS0_2_PCFGQOS0_2_RQOS_MAP_REGION0(x)\
	(((x) << 16) & GENMASK(17, 16))
#define DDR_UMCTL2_PCFGQOS0_2_PCFGQOS0_2_RQOS_MAP_REGION0_M GENMASK(17, 16)
#define DDR_UMCTL2_PCFGQOS0_2_PCFGQOS0_2_RQOS_MAP_REGION0_X(x)\
	(((x) & GENMASK(17, 16)) >> 16)

#define DDR_UMCTL2_PCFGQOS0_2_PCFGQOS0_2_RQOS_MAP_REGION1(x)\
	(((x) << 20) & GENMASK(21, 20))
#define DDR_UMCTL2_PCFGQOS0_2_PCFGQOS0_2_RQOS_MAP_REGION1_M GENMASK(21, 20)
#define DDR_UMCTL2_PCFGQOS0_2_PCFGQOS0_2_RQOS_MAP_REGION1_X(x)\
	(((x) & GENMASK(21, 20)) >> 20)

/*      DDR_UMCTL2:UMCTL2_MP:PCFGQOS1_2 */
#define DDR_UMCTL2_PCFGQOS1_2(t)  (t + 0x5f8)

#define DDR_UMCTL2_PCFGQOS1_2_PCFGQOS1_2_RQOS_MAP_TIMEOUTB(x)\
	((x) & GENMASK(10, 0))
#define DDR_UMCTL2_PCFGQOS1_2_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_M GENMASK(10, 0)
#define DDR_UMCTL2_PCFGQOS1_2_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_X(x)\
	((x) & GENMASK(10, 0))

#define DDR_UMCTL2_PCFGQOS1_2_PCFGQOS1_2_RQOS_MAP_TIMEOUTR(x)\
	(((x) << 16) & GENMASK(26, 16))
#define DDR_UMCTL2_PCFGQOS1_2_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_M GENMASK(26, 16)
#define DDR_UMCTL2_PCFGQOS1_2_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_X(x)\
	(((x) & GENMASK(26, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_MP:PCFGWQOS0_2 */
#define DDR_UMCTL2_PCFGWQOS0_2(t) (t + 0x5fc)

#define DDR_UMCTL2_PCFGWQOS0_2_PCFGWQOS0_2_WQOS_MAP_LEVEL1(x)\
	((x) & GENMASK(3, 0))
#define DDR_UMCTL2_PCFGWQOS0_2_PCFGWQOS0_2_WQOS_MAP_LEVEL1_M GENMASK(3, 0)
#define DDR_UMCTL2_PCFGWQOS0_2_PCFGWQOS0_2_WQOS_MAP_LEVEL1_X(x)\
	((x) & GENMASK(3, 0))

#define DDR_UMCTL2_PCFGWQOS0_2_PCFGWQOS0_2_WQOS_MAP_LEVEL2(x)\
	(((x) << 8) & GENMASK(11, 8))
#define DDR_UMCTL2_PCFGWQOS0_2_PCFGWQOS0_2_WQOS_MAP_LEVEL2_M GENMASK(11, 8)
#define DDR_UMCTL2_PCFGWQOS0_2_PCFGWQOS0_2_WQOS_MAP_LEVEL2_X(x)\
	(((x) & GENMASK(11, 8)) >> 8)

#define DDR_UMCTL2_PCFGWQOS0_2_PCFGWQOS0_2_WQOS_MAP_REGION0(x)\
	(((x) << 16) & GENMASK(17, 16))
#define DDR_UMCTL2_PCFGWQOS0_2_PCFGWQOS0_2_WQOS_MAP_REGION0_M GENMASK(17, 16)
#define DDR_UMCTL2_PCFGWQOS0_2_PCFGWQOS0_2_WQOS_MAP_REGION0_X(x)\
	(((x) & GENMASK(17, 16)) >> 16)

#define DDR_UMCTL2_PCFGWQOS0_2_PCFGWQOS0_2_WQOS_MAP_REGION1(x)\
	(((x) << 20) & GENMASK(21, 20))
#define DDR_UMCTL2_PCFGWQOS0_2_PCFGWQOS0_2_WQOS_MAP_REGION1_M GENMASK(21, 20)
#define DDR_UMCTL2_PCFGWQOS0_2_PCFGWQOS0_2_WQOS_MAP_REGION1_X(x)\
	(((x) & GENMASK(21, 20)) >> 20)

#define DDR_UMCTL2_PCFGWQOS0_2_PCFGWQOS0_2_WQOS_MAP_REGION2(x)\
	(((x) << 24) & GENMASK(25, 24))
#define DDR_UMCTL2_PCFGWQOS0_2_PCFGWQOS0_2_WQOS_MAP_REGION2_M GENMASK(25, 24)
#define DDR_UMCTL2_PCFGWQOS0_2_PCFGWQOS0_2_WQOS_MAP_REGION2_X(x)\
	(((x) & GENMASK(25, 24)) >> 24)

/*      DDR_UMCTL2:UMCTL2_MP:PCFGWQOS1_2 */
#define DDR_UMCTL2_PCFGWQOS1_2(t) (t + 0x600)

#define DDR_UMCTL2_PCFGWQOS1_2_PCFGWQOS1_2_WQOS_MAP_TIMEOUT1(x)\
	((x) & GENMASK(10, 0))
#define DDR_UMCTL2_PCFGWQOS1_2_PCFGWQOS1_2_WQOS_MAP_TIMEOUT1_M GENMASK(10, 0)
#define DDR_UMCTL2_PCFGWQOS1_2_PCFGWQOS1_2_WQOS_MAP_TIMEOUT1_X(x)\
	((x) & GENMASK(10, 0))

#define DDR_UMCTL2_PCFGWQOS1_2_PCFGWQOS1_2_WQOS_MAP_TIMEOUT2(x)\
	(((x) << 16) & GENMASK(26, 16))
#define DDR_UMCTL2_PCFGWQOS1_2_PCFGWQOS1_2_WQOS_MAP_TIMEOUT2_M GENMASK(26, 16)
#define DDR_UMCTL2_PCFGWQOS1_2_PCFGWQOS1_2_WQOS_MAP_TIMEOUT2_X(x)\
	(((x) & GENMASK(26, 16)) >> 16)

/*      DDR_UMCTL2:UMCTL2_MP:SARBASE0 */
#define DDR_UMCTL2_SARBASE0(t)    (t + 0xf04)

#define DDR_UMCTL2_SARBASE0_BASE_ADDR(x)         ((x) & GENMASK(2, 0))
#define DDR_UMCTL2_SARBASE0_BASE_ADDR_M          GENMASK(2, 0)
#define DDR_UMCTL2_SARBASE0_BASE_ADDR_X(x)       ((x) & GENMASK(2, 0))

/*      DDR_UMCTL2:UMCTL2_MP:SARSIZE0 */
#define DDR_UMCTL2_SARSIZE0(t)    (t + 0xf08)

#define DDR_UMCTL2_SARSIZE0_NBLOCKS(x)           ((x) & GENMASK(7, 0))
#define DDR_UMCTL2_SARSIZE0_NBLOCKS_M            GENMASK(7, 0)
#define DDR_UMCTL2_SARSIZE0_NBLOCKS_X(x)         ((x) & GENMASK(7, 0))

/*      DDR_UMCTL2:UMCTL2_MP:SBRCTL */
#define DDR_UMCTL2_SBRCTL(t)      (t + 0xf24)

#define DDR_UMCTL2_SBRCTL_SCRUB_EN(x)            ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_SBRCTL_SCRUB_EN_M             GENMASK(0, 0)
#define DDR_UMCTL2_SBRCTL_SCRUB_EN_X(x)          ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_SBRCTL_SCRUB_DURING_LOWPOWER(x) (((x) << 1) & GENMASK(1, 1))
#define DDR_UMCTL2_SBRCTL_SCRUB_DURING_LOWPOWER_M GENMASK(1, 1)
#define DDR_UMCTL2_SBRCTL_SCRUB_DURING_LOWPOWER_X(x)\
	(((x) & GENMASK(1, 1)) >> 1)

#define DDR_UMCTL2_SBRCTL_SCRUB_MODE(x)          (((x) << 2) & GENMASK(2, 2))
#define DDR_UMCTL2_SBRCTL_SCRUB_MODE_M           GENMASK(2, 2)
#define DDR_UMCTL2_SBRCTL_SCRUB_MODE_X(x)        (((x) & GENMASK(2, 2)) >> 2)

#define DDR_UMCTL2_SBRCTL_SCRUB_BURST(x)         (((x) << 4) & GENMASK(6, 4))
#define DDR_UMCTL2_SBRCTL_SCRUB_BURST_M          GENMASK(6, 4)
#define DDR_UMCTL2_SBRCTL_SCRUB_BURST_X(x)       (((x) & GENMASK(6, 4)) >> 4)

#define DDR_UMCTL2_SBRCTL_SCRUB_INTERVAL(x)      (((x) << 8) & GENMASK(20, 8))
#define DDR_UMCTL2_SBRCTL_SCRUB_INTERVAL_M       GENMASK(20, 8)
#define DDR_UMCTL2_SBRCTL_SCRUB_INTERVAL_X(x)    (((x) & GENMASK(20, 8)) >> 8)

/*      DDR_UMCTL2:UMCTL2_MP:SBRSTAT */
#define DDR_UMCTL2_SBRSTAT(t)     (t + 0xf28)

#define DDR_UMCTL2_SBRSTAT_SCRUB_BUSY(x)         ((x) & GENMASK(0, 0))
#define DDR_UMCTL2_SBRSTAT_SCRUB_BUSY_M          GENMASK(0, 0)
#define DDR_UMCTL2_SBRSTAT_SCRUB_BUSY_X(x)       ((x) & GENMASK(0, 0))

#define DDR_UMCTL2_SBRSTAT_SCRUB_DONE(x)         (((x) << 1) & GENMASK(1, 1))
#define DDR_UMCTL2_SBRSTAT_SCRUB_DONE_M          GENMASK(1, 1)
#define DDR_UMCTL2_SBRSTAT_SCRUB_DONE_X(x)       (((x) & GENMASK(1, 1)) >> 1)

/*      DDR_UMCTL2:UMCTL2_MP:SBRWDATA0 */
#define DDR_UMCTL2_SBRWDATA0(t)   (t + 0xf2c)

/*      DDR_UMCTL2:UMCTL2_MP:SBRSTART0 */
#define DDR_UMCTL2_SBRSTART0(t)   (t + 0xf38)

/*      DDR_UMCTL2:UMCTL2_MP:SBRSTART1 */
#define DDR_UMCTL2_SBRSTART1(t)   (t + 0xf3c)

#define DDR_UMCTL2_SBRSTART1_SBR_ADDRESS_START_MASK_1(x) ((x) & GENMASK(3, 0))
#define DDR_UMCTL2_SBRSTART1_SBR_ADDRESS_START_MASK_1_M GENMASK(3, 0)
#define DDR_UMCTL2_SBRSTART1_SBR_ADDRESS_START_MASK_1_X(x) ((x) & GENMASK(3, 0))

/*      DDR_UMCTL2:UMCTL2_MP:SBRRANGE0 */
#define DDR_UMCTL2_SBRRANGE0(t)   (t + 0xf40)

/*      DDR_UMCTL2:UMCTL2_MP:SBRRANGE1 */
#define DDR_UMCTL2_SBRRANGE1(t)   (t + 0xf44)

#define DDR_UMCTL2_SBRRANGE1_SBR_ADDRESS_RANGE_MASK_1(x) ((x) & GENMASK(3, 0))
#define DDR_UMCTL2_SBRRANGE1_SBR_ADDRESS_RANGE_MASK_1_M GENMASK(3, 0)
#define DDR_UMCTL2_SBRRANGE1_SBR_ADDRESS_RANGE_MASK_1_X(x) ((x) & GENMASK(3, 0))

/*      DDR_UMCTL2:UMCTL2_MP:UMCTL2_VER_NUMBER */
#define DDR_UMCTL2_UMCTL2_VER_NUMBER(t) (t + 0xff0)

/*      DDR_UMCTL2:UMCTL2_MP:UMCTL2_VER_TYPE */
#define DDR_UMCTL2_UMCTL2_VER_TYPE(t) (t + 0xff4)


#endif /* _LAN969X_DDR_A0_H_ */
