// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*
 * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "microchip,lan969x";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	board: board {
		board-number = <100>; /* For DT-based board identification */
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;
		cpu0: cpu@0 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x0 0x0>;
			next-level-cache = <&L2_0>;
		};
		L2_0: l2-cache0 {
			compatible = "cache";
		};
	};

	memory: memory@60000000 {
		device_type = "memory";
		reg = <0x60000000 0x40000000>;  /* 1GB */
	};

	fabric_clk: fabric_clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <20000000>;
	};

	nic_clk: nic_clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <200000000>;	/* NIC clock = 200MHz */
	};

	dummy_clk: dummy_clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <30000000>;	/* CPU clock = 30MHz */
	};

	emmc_clk: emmc_clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
	};

	qspi_clk: qspi_clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

	axi {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

                ddr: ddr@e0080000 {
                        compatible = "microchip,ddr-umctl";
                        microchip,mem-speed = <2400>;
                };

		gic: interrupt-controller@e8c11000 {
			compatible = "arm,gic-400";
			#address-cells = <1>;
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0xe8c11000 0x1000>, /* Distributor GICD_ */
			      <0xe8c12000 0x2000>, /* CPU interface GICC_ */
			      <0xe8c14000 0x2000>, /* Virt interface control */
			      <0xe8c16000 0x2000>; /* Virt CPU interface */
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		};

		flx0: flexcom@e0040000 {
			compatible = "atmel,sama5d2-flexcom";
			reg = <0xe0040000 0x100>;
			clocks = <&fabric_clk>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xe0040000 0x800>;
			status = "disabled";
		};

		sdmmc0: sdhci-host@e0830000 {
			compatible = "microchip,lan966x-sdhci";
			reg = <0xe0830000 0x00000300>;
			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&emmc_clk>, <&emmc_clk>;
			clock-names = "hclock", "multclk";
			status = "disabled";
		};

		qspi0: spi@e0804000 {
			compatible = "microchip,lan966x-qspi";
			reg = <0xe0804000 0x00000100>, <0x20000000 0x08000000>;
			reg-names = "qspi_base", "qspi_mmap";
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			clocks =  <&qspi_clk>, <&qspi_clk>;
			clock-names = "pclk", "gclk";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		qspi2: spi@e0834000 {
			compatible = "microchip,lan966x-qspi";
			reg = <0xe0834000 0x00000100>, <0x30000000 0x04000000>;
			reg-names = "qspi_base", "qspi_mmap";
			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&dummy_clk>, <&dummy_clk>;
			clock-names = "pclk", "gclk";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
	};
};
