/* Copyright 2023 NXP
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 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution.
 * * Neither the name of the above-listed copyright holders nor the
 * names of any contributors may be used to endorse or promote products
 * derived from this software without specific prior written permission.
 *
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") as published by the Free Software
 * Foundation, either version 2 of that License or (at your option) any
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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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#ifndef __FSL_CORE_ARM_H
#define __FSL_CORE_ARM_H

//#include "arch/fsl_soc.h"

#define CORE_IS_LITTLE_ENDIAN
//#define CORE_IS_BIG_ENDIAN        0
#define CORE_CACHELINE_SIZE       64
//#define _STRING_ARCH_unaligned         1
//#define UINT_TO_PTR(_val)        ((void*)(uintptr_t)(_val))

#endif /* __FSL_CORE_ARM_H */

#define core_memory_barrier      arm_memory_barrier

static __inline__ void arm_memory_barrier(void)
{
	__asm__("dmb ish" : : : "memory");
} 


