The RCW directories names for the LS1046ARDB boards conform to the following
naming convention:

ab_cdefghij_k_l:

a = 'R' indicates RGMII1@DTSEC3 is supported
b = 'R' indicates RGMII2@DTSEC4 is supported
    'N' indicates not available/not used

c = What is available in SerDes1 Lane0
d = What is available in SerDes1 Lane1
e = What is available in SerDes1 Lane2
f = What is available in SerDes1 Lane3
g = What is available in SerDes2 Lane0
h = What is available in SerDes2 Lane1
i = What is available in SerDes2 Lane2
j = What is available in SerDes2 Lane3

For the Slots (c..j):
 'N' is NULL, not available/not used
 'P' is PCIe
 'X' is XAUI
 'S' is SGMII
 'Q' if QSGMII
 'F' is XFI
 'H' is SATA
 'A' is AURORA

Serdes1 protocol (k):
k = 'hex value of serdes1 protocol value'

Serdes2 protocol (l):
l = 'hex value of serdes2 protocol value'

BIN   Core/Platform/FMan/DDR
Bin1: 1600MHz/600MHz/700MHz/2100MT/s
Bin2: 1200MHz/400MHz/500MHz/1600MT/s

Serdes ptotocol:
================
RR_FFSSPPPH_1133_5559 means:
 - RGMII1@DTSEC3 on board
 - RGMII2@DTSEC4 on board
 - XFI9@TGEC1 on board
 - XFI10@TGEC2 on SFP cage
 - SGMII5@DTSEC5 on board
 - SGMII6@DTSEC6 on board
 - PCIe1 on Slot 1, mPCIe
 - PCIe2 on Slot 2
 - PCIe3 on Slot 3
 - SATA
 - SERDES1 Protocol is 0x1133
 - SERDES2 Protocol is 0x5559

RR_FFSSPPPN_1133_5506 means:
 - RGMII1@DTSEC3 on board
 - RGMII2@DTSEC4 on board
 - XFI9@TGEC1 on board
 - XFI10@TGEC2 on SFP cage
 - SGMII5@DTSEC5 on board
 - SGMII6@DTSEC6 on board
 - PCIe1 on Slot 1, mPCIe
 - PCIe2 on Slot 2
 - PCIe3 on Slot 3
 - SERDES1 Protocol is 0x1133
 - SERDES2 Protocol is 0x5506

Files naming convention
=============================
rcw_x.rcw
rcw_x_bootmode.rcw
rcw_x_specialsetting.rcw
x = Core frequency
bootmode = bootmode:qspiboot and so on.
specialsetting = special setting:
			sben:Secure boot
For example,
	rcw_1600_qspiboot.rcw means rcw for core frequency of 1600MHz with QSPI boot.

For more information please refer to the comments in rcw file.

Errata Workaround Implemented
=============================
A-008851:
	Invalid transmitter/receiver preset values are used in Gen3 equalization
	phases during link training for RC mode
	This errata is valid only for PCI gen3.
	Workaround:
		write 0x00000001 to MISC_CONTROL_1_OFF
		write 0x4747 to Lane Equalization Control register for each lane

A-010477:
	The PCI Express controller may not be able to establish the link at Gen3
	speed successfully with some Gen3-capable link partner. The link will be
	down-trained to either Gen1 or Gen2 speed.
	Workaround:
		Write 0x00800401 to GEN3 Control Register (GEN3_RELATED_OFF)
