# SPDX-License-Identifier: GPL-2.0-or-later

#
# Freescale i.MX6SoloX
#

if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
} else {
    set _CHIPNAME imx6sx
}

# 2x CoreSight Debug Access Port for Cortex-M4 and Cortex-A9
if { [info exists DAP_TAPID] } {
    set _DAP_TAPID $DAP_TAPID
} else {
    set _DAP_TAPID 0x4ba00477
}

jtag newtap $_CHIPNAME cpu_m4 -irlen 4 -ircapture 0x01 -irmask 0x0f \
        -expected-id $_DAP_TAPID
dap create $_CHIPNAME.dap_m4 -chain-position $_CHIPNAME.cpu_m4

jtag newtap $_CHIPNAME cpu_a9 -irlen 4 -ircapture 0x01 -irmask 0x0f \
        -expected-id $_DAP_TAPID
dap create $_CHIPNAME.dap_a9 -chain-position $_CHIPNAME.cpu_a9

# SDMA / no IDCODE
jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f

# System JTAG Controller
if { [info exists SJC_TAPID] } {
    set _SJC_TAPID $SJC_TAPID
} else {
    set _SJC_TAPID 0x0891c01d
}
jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
        -expected-id $_SJC_TAPID -ignore-version

# Cortex-A9 (boot core)
target create $_CHIPNAME.cpu_a9 cortex_a -dap $_CHIPNAME.dap_a9 \
        -coreid 0 -dbgbase 0x82150000

# Cortex-M4 (default off)
target create $_CHIPNAME.cpu_m4 cortex_m -dap $_CHIPNAME.dap_m4 \
        -ap-num 0 -defer-examine

# AHB mem-ap target
target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap_a9 -ap-num 0

# Default target is Cortex-A9
targets $_CHIPNAME.cpu_a9
