# SPDX-License-Identifier: GPL-2.0-or-later
# Cadence virtual debug interface
# RISCV Ibex core with Pulpissimo through JTAG

source [find interface/vdebug.cfg]

set _CHIPNAME ibex
set _HARTID 0x20
set _CPUTAPID 0x249511c3

# vdebug select transport
transport select jtag

# JTAG reset config, frequency and reset delay
reset_config trst_and_srst
adapter speed 12500
adapter srst delay 10

# BFM hierarchical path and input clk period
vdebug bfm_path tbench.u_vd_jtag_bfm 40ns

# DMA Memories to access backdoor (up to 4)
vdebug mem_path tbench.soc_domain_i.pulp_soc_i.gen_mem_l2_pri\[0\].sram_i.mem_array 0x1c000000 0x8000
vdebug mem_path tbench.soc_domain_i.pulp_soc_i.gen_mem_l2_pri\[1\].sram_i.mem_array 0x1c008000 0x8000
vdebug mem_path tbench.soc_domain_i.pulp_soc_i.gen_mem_l2\[0\].sram_i.mem_array 0x1c010000 0x80000

# need to explicitly define riscv tap, autoprobing does not work for icapture != 0x01
jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x05 -irmask 0x1f -expected-id $_CPUTAPID

jtag arp_init-reset

source [find target/vd_riscv.cfg]
