# SPDX-License-Identifier: GPL-2.0-or-later

# Setup register
#
# ncs_read_setup
# nrd_setup
# ncs_write_setup
# set nwe_setup
#
#
# Pulse register
#
# ncs_read_pulse
# nrd_pulse
# ncs_write_pulse
# nwe_pulse
#
#
# Cycle register
#
# read_cycle 0
# write_cycle 0
#
#
# Mode register
#
# mode
# tdf_cycles
proc sam9_smc_config { cs smc_config } {
	;# Setup Register for CS n
	set AT91_SMC_SETUP [expr {$::AT91_SMC + 0x00 + $cs * 0x10}]
	set val [expr {$smc_config(nwe_setup) << 0}]
	set val [expr {$val | $smc_config(ncs_write_setup) << 8}]
	set val [expr {$val | $smc_config(nrd_setup)) << 16}]
	set val [expr {$val | $smc_config(ncs_read_setup) << 24}]
	mww $AT91_SMC_SETUP $val

	;# Pulse Register for CS n
	set AT91_SMC_PULSE [expr {$::AT91_SMC + 0x04 + $cs * 0x10}]
	set val [expr {$smc_config(nwe_pulse) << 0}]
	set val [expr {$val | $smc_config(ncs_write_pulse) << 8}]
	set val [expr {$val | $smc_config(nrd_pulse) << 16}]
	set val [expr {$val | $smc_config(ncs_read_pulse) << 24}]
	mww $AT91_SMC_PULSE $val

	;# Cycle Register for CS n
	set AT91_SMC_CYCLE [expr {$::AT91_SMC + 0x08 + $cs * 0x10}]
	set val [expr {$smc_config(write_cycle) << 0}]
	set val [expr {$val | $smc_config(read_cycle) << 16}]
	mww $AT91_SMC_CYCLE $val

	;# Mode Register for CS n
	set AT91_SMC_MODE [expr {$::AT91_SMC + 0x0c + $cs * 0x10}]
	set val [expr {$smc_config(mode) << 0}]
	set val [expr {$val | $smc_config(tdf_cycles) << 16}]
	mww $AT91_SMC_MODE $val
}
