# SPDX-License-Identifier: GPL-2.0-or-later

# Product page:
# https://www.dptechnics.com/en/products/dpt-board-v1.html
#
# JTAG is a 5 pin array located close to main module in following order:
# 1. JTAG TCK
# 2. JTAG TDO
# 3. JTAG TDI
# 4. JTAG TMS
# 5. GND	The GND is located near letter G of word JTAG on board.
#
# Two RST pins are connected to:
# 1. GND
# 2. GPIO11	this pin is located near letter R of word RST.
#
# To enable EJTAG mode, GPIO11 (RST[1]) pin should be pulled up. For example
# with 10K resistor connected to V3.3 pin.
#
# This board is powered from micro USB connector. No real reset pin or button, for
# example RESET_L is available.

source [find target/atheros_ar9331.cfg]

$_TARGETNAME configure -event reset-init {
	ar9331_25mhz_pll_init
	sleep 1
	ar9331_ddr2_init
}

set ram_boot_address 0xa0000000
$_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000

flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
