# SPDX-License-Identifier: GPL-2.0-or-later

# script for ATMEL sam4l, a Cortex-M4 chip
#

source [find target/at91sam4XXX.cfg]

set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME at91sam4l 0x00000000 0 1 1 $_TARGETNAME

# SAM4L SMAP will hold the CPU in reset if TCK is low when RESET_N
# deasserts (see datasheet 42023E-SAM-07/2013 sec 8.11.3).
#
# smap_reset_deassert configures whether we want to run or halt out of reset,
# then instruct the SMAP to let us out of reset.
$_TARGETNAME configure -event reset-deassert-post "at91sam4l smap_reset_deassert"

# SRST (wired to RESET_N) resets debug circuitry
# srst_pulls_trst is not configured here to avoid an error raised in reset halt
reset_config srst_gates_jtag

# SAM4L starts from POR with SYSCLK set to 115kHz RCSYS, needs slow JTAG speed.
# Datasheet does not specify SYSCLK to JTAG/SWD clock ratio.
# Usually used SYSCLK/6 is hell slow, testing shows that debugging can work @ SYSCLK/2
# but your mileage may vary.
adapter speed 50

# System RC oscillator RCSYS starts in 3 cycles
adapter srst delay 0
