/*
 * Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved.
 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#if defined(CONFIG_CPU_BIG_ENDIAN)
#include "hppe_uniphy_reg_be.h"
#else
/**
 * @defgroup
 * @{
 */
#ifndef HPPE_UNIPHY_REG_H
#define HPPE_UNIPHY_REG_H

/*[register] UNIPHY_OFFSET_CALIB_4*/
#define UNIPHY_OFFSET_CALIB_4
#define UNIPHY_OFFSET_CALIB_4_ADDRESS 0x1e0
#define UNIPHY_OFFSET_CALIB_4_NUM     3
#define UNIPHY_OFFSET_CALIB_4_INC     0x1
#define UNIPHY_OFFSET_CALIB_4_TYPE    REG_TYPE_RW
#define UNIPHY_OFFSET_CALIB_4_DEFAULT 0x0
	/*[field] MMD1_REG_SMPL_CAL_READY*/
	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_SMPL_CAL_READY
	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_SMPL_CAL_READY_OFFSET  0
	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_SMPL_CAL_READY_LEN     1
	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_SMPL_CAL_READY_DEFAULT 0x0
	/*[field] MMD1_REG_CLR_SAMPLER_CALIB_TIMEOUT*/
	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CLR_SAMPLER_CALIB_TIMEOUT
	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CLR_SAMPLER_CALIB_TIMEOUT_OFFSET  1
	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CLR_SAMPLER_CALIB_TIMEOUT_LEN     1
	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CLR_SAMPLER_CALIB_TIMEOUT_DEFAULT 0x0
	/*[field] MMD1_REG_LOCKDET_LCKDT_REG*/
	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_LOCKDET_LCKDT_REG
	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_LOCKDET_LCKDT_REG_OFFSET  4
	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_LOCKDET_LCKDT_REG_LEN     1
	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_LOCKDET_LCKDT_REG_DEFAULT 0x0
	/*[field] MMD1_REG_PLL_LOCKED_REG*/
	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_PLL_LOCKED_REG
	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_PLL_LOCKED_REG_OFFSET  6
	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_PLL_LOCKED_REG_LEN     1
	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_PLL_LOCKED_REG_DEFAULT 0x0
	/*[field] MMD1_REG_CALIBRATION_DONE_REG*/
	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CALIBRATION_DONE_REG
	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CALIBRATION_DONE_REG_OFFSET  7
	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CALIBRATION_DONE_REG_LEN     1
	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CALIBRATION_DONE_REG_DEFAULT 0x0
	/*[field] MMD1_REG_CAL_DETECT_TIME*/
	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CAL_DETECT_TIME
	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CAL_DETECT_TIME_OFFSET  8
	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CAL_DETECT_TIME_LEN     5
	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CAL_DETECT_TIME_DEFAULT 0x0
	/*[field] MMD1_REG_CAL_REP_TIME*/
	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CAL_REP_TIME
	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CAL_REP_TIME_OFFSET  13
	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CAL_REP_TIME_LEN     3
	#define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CAL_REP_TIME_DEFAULT 0x0

struct uniphy_offset_calib_4 {
	a_uint32_t  mmd1_reg_smpl_cal_ready:1;
	a_uint32_t  mmd1_reg_clr_sampler_calib_timeout:1;
	a_uint32_t  _reserved0:2;
	a_uint32_t  mmd1_reg_lockdet_lckdt_reg:1;
	a_uint32_t  _reserved1:1;
	a_uint32_t  mmd1_reg_pll_locked_reg:1;
	a_uint32_t  mmd1_reg_calibration_done_reg:1;
	a_uint32_t  mmd1_reg_cal_detect_time:5;
	a_uint32_t  mmd1_reg_cal_rep_time:3;
	a_uint32_t  _reserved2:16;
};

union uniphy_offset_calib_4_u {
	a_uint32_t val;
	struct uniphy_offset_calib_4 bf;
};

/*[register] UNIPHY_MODE_CTRL*/
#define UNIPHY_MODE_CTRL
#define UNIPHY_MODE_CTRL_ADDRESS 0x46c
#define UNIPHY_MODE_CTRL_NUM     3
#define UNIPHY_MODE_CTRL_INC     0x1
#define UNIPHY_MODE_CTRL_TYPE    REG_TYPE_RW
#define UNIPHY_MODE_CTRL_DEFAULT 0x221
	/*[field] NEWADDEDFROMHERE_CH0_AUTONEG_MODE*/
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_AUTONEG_MODE
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_AUTONEG_MODE_OFFSET  0
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_AUTONEG_MODE_LEN     1
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_AUTONEG_MODE_DEFAULT 0x1
	/*[field] NEWADDEDFROMHERE_CH1_CH0_SGMII*/
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH1_CH0_SGMII
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH1_CH0_SGMII_OFFSET  1
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH1_CH0_SGMII_LEN     1
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH1_CH0_SGMII_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH4_CH1_0_SGMII*/
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH4_CH1_0_SGMII
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH4_CH1_0_SGMII_OFFSET  2
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH4_CH1_0_SGMII_LEN     1
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH4_CH1_0_SGMII_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_SGMII_EVEN_LOW*/
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SGMII_EVEN_LOW
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SGMII_EVEN_LOW_OFFSET  3
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SGMII_EVEN_LOW_LEN     1
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SGMII_EVEN_LOW_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH0_MODE_CTRL_25M*/
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_MODE_CTRL_25M
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_MODE_CTRL_25M_OFFSET  4
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_MODE_CTRL_25M_LEN     3
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_MODE_CTRL_25M_DEFAULT 0x2
	/*[field] NEWADDEDFROMHERE_CH0_QSGMII_SGMII*/
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_QSGMII_SGMII
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_QSGMII_SGMII_OFFSET  8
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_QSGMII_SGMII_LEN     1
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_QSGMII_SGMII_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH0_PSGMII_QSGMII*/
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_PSGMII_QSGMII
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_PSGMII_QSGMII_OFFSET  9
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_PSGMII_QSGMII_LEN     1
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_PSGMII_QSGMII_DEFAULT 0x1
	/*[field] NEWADDEDFROMHERE_SG_MODE*/
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SG_MODE
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SG_MODE_OFFSET  10
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SG_MODE_LEN     1
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SG_MODE_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_SGPLUS_MODE*/
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SGPLUS_MODE
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SGPLUS_MODE_OFFSET  11
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SGPLUS_MODE_LEN     1
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SGPLUS_MODE_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_XPCS_MODE*/
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_XPCS_MODE
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_XPCS_MODE_OFFSET  12
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_XPCS_MODE_LEN     1
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_XPCS_MODE_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_USXG_EN*/
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_USXG_EN
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_USXG_EN_OFFSET  13
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_USXG_EN_LEN     1
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_USXG_EN_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_SW_V17_V18*/
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SW_V17_V18
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SW_V17_V18_OFFSET  15
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SW_V17_V18_LEN     1
	#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SW_V17_V18_DEFAULT 0x0

struct uniphy_mode_ctrl {
	a_uint32_t  newaddedfromhere_ch0_autoneg_mode:1;
	a_uint32_t  newaddedfromhere_ch1_ch0_sgmii:1;
	a_uint32_t  newaddedfromhere_ch4_ch1_0_sgmii:1;
	a_uint32_t  newaddedfromhere_sgmii_even_low:1;
	a_uint32_t  newaddedfromhere_ch0_mode_ctrl_25m:3;
	a_uint32_t  _reserved0:1;
	a_uint32_t  newaddedfromhere_ch0_qsgmii_sgmii:1;
	a_uint32_t  newaddedfromhere_ch0_psgmii_qsgmii:1;
	a_uint32_t  newaddedfromhere_sg_mode:1;
	a_uint32_t  newaddedfromhere_sgplus_mode:1;
	a_uint32_t  newaddedfromhere_xpcs_mode:1;
	a_uint32_t  newaddedfromhere_usxg_en:1;
	a_uint32_t  _reserved1:1;
	a_uint32_t  newaddedfromhere_sw_v17_v18:1;
	a_uint32_t  _reserved2:16;
};

union uniphy_mode_ctrl_u {
	a_uint32_t val;
	struct uniphy_mode_ctrl bf;
};

/*[register] UNIPHY_CHANNEL0_INPUT_OUTPUT_4*/
#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4
#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_ADDRESS 0x480
#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NUM     3
#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_INC     0x1
#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_TYPE    REG_TYPE_RW
#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_DEFAULT 0x844
	/*[field] NEWADDEDFROMHERE_CH0_REM_PHY_LPBK*/
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_REM_PHY_LPBK
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_REM_PHY_LPBK_OFFSET  0
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_REM_PHY_LPBK_LEN     1
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_REM_PHY_LPBK_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH0_SPEED_25M*/
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_SPEED_25M
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_SPEED_25M_OFFSET  1
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_SPEED_25M_LEN     2
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_SPEED_25M_DEFAULT 0x2
	/*[field] NEWADDEDFROMHERE_CH0_FORCE_SPEED_25M*/
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_FORCE_SPEED_25M
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_FORCE_SPEED_25M_OFFSET  3
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_FORCE_SPEED_25M_LEN     1
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_FORCE_SPEED_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH0_MR_NP_LOADED_25M*/
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_NP_LOADED_25M
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_NP_LOADED_25M_OFFSET  4
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_NP_LOADED_25M_LEN     1
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_NP_LOADED_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH0_MR_REG4_CH_25M*/
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_REG4_CH_25M
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_REG4_CH_25M_OFFSET  5
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_REG4_CH_25M_LEN     1
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_REG4_CH_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH0_MR_AN_ENABLE_25M*/
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_AN_ENABLE_25M
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_AN_ENABLE_25M_OFFSET  6
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_AN_ENABLE_25M_LEN     1
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_AN_ENABLE_25M_DEFAULT 0x1
	/*[field] NEWADDEDFROMHERE_CH0_MR_RESTART_AN_25M*/
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_RESTART_AN_25M
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_RESTART_AN_25M_OFFSET  7
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_RESTART_AN_25M_LEN     1
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_RESTART_AN_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH0_MR_LOOPBACK_25M*/
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_LOOPBACK_25M
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_LOOPBACK_25M_OFFSET  8
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_LOOPBACK_25M_LEN     1
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_LOOPBACK_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH0_MR_MAIN_RESET_25M*/
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_MAIN_RESET_25M
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_MAIN_RESET_25M_OFFSET  9
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_MAIN_RESET_25M_LEN     1
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_MAIN_RESET_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH0_POWER_ON_25M*/
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_POWER_ON_25M
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_POWER_ON_25M_OFFSET  10
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_POWER_ON_25M_LEN     1
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_POWER_ON_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH0_ADP_SW_RSTN*/
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_ADP_SW_RSTN
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_ADP_SW_RSTN_OFFSET  11
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_ADP_SW_RSTN_LEN     1
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_ADP_SW_RSTN_DEFAULT 0x1

struct uniphy_channel0_input_output_4 {
	a_uint32_t  newaddedfromhere_ch0_rem_phy_lpbk:1;
	a_uint32_t  newaddedfromhere_ch0_speed_25m:2;
	a_uint32_t  newaddedfromhere_ch0_force_speed_25m:1;
	a_uint32_t  newaddedfromhere_ch0_mr_np_loaded_25m:1;
	a_uint32_t  newaddedfromhere_ch0_mr_reg4_ch_25m:1;
	a_uint32_t  newaddedfromhere_ch0_mr_an_enable_25m:1;
	a_uint32_t  newaddedfromhere_ch0_mr_restart_an_25m:1;
	a_uint32_t  newaddedfromhere_ch0_mr_loopback_25m:1;
	a_uint32_t  newaddedfromhere_ch0_mr_main_reset_25m:1;
	a_uint32_t  newaddedfromhere_ch0_power_on_25m:1;
	a_uint32_t  newaddedfromhere_ch0_adp_sw_rstn:1;
	a_uint32_t  _reserved0:20;
};

union uniphy_channel0_input_output_4_u {
	a_uint32_t val;
	struct uniphy_channel0_input_output_4 bf;
};

/*[register] UNIPHY_CHANNEL_0_INPUT_OUTPUT_6*/
#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6
#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_ADDRESS 0x488
#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_NUM     3
#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_INC     0x1
#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_TYPE    REG_TYPE_RW
#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_DEFAULT 0
	/*NEWADDEDFROMHERE_CH0_RECEIVE_PAUSE_EN_MAC*/
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_NEWADDEDFROMHERE_CH0_RECEIVE_PAUSE_EN
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_NEWADDEDFROMHERE_CH0_RECEIVE_PAUSE_EN_OFFSET     0
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_NEWADDEDFROMHERE_CH0_RECEIVE_PAUSE_EN_LEN        1
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_NEWADDEDFROMHERE_CH0_RECEIVE_PAUSE_EN_DEFAULT    0
	/*NEWADDEDFROMHERE_CH0_TRANSMIT_PAUSE_EN_MAC*/
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_NEWADDEDFROMHERE_CH0_TRANSMIT_PAUSE_EN
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_NEWADDEDFROMHERE_CH0_TRANSMIT_PAUSE_EN_OFFSET    1
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_NEWADDEDFROMHERE_CH0_TRANSMIT_PAUSE_EN_LEN       1
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_NEWADDEDFROMHERE_CH0_TRANSMIT_PAUSE_EN_DEFAULT   0
	/*NEWADDEDFROMHERE_CH0_ASYM_PAUSE_MAC*/
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_NEWADDEDFROMHERE_CH0_ASYM_PAUSE
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_NEWADDEDFROMHERE_CH0_ASYM_PAUSE_OFFSET           2
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_NEWADDEDFROMHERE_CH0_ASYM_PAUSE_LEN              1
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_NEWADDEDFROMHERE_CH0_ASYM_PAUSE_DEFAULT          0
	/*NEWADDEDFROMHERE_CH0_PAUSE_MAC*/
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_NEWADDEDFROMHERE_CH0_PAUSE
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_NEWADDEDFROMHERE_CH0_PAUSE_OFFSET                3
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_NEWADDEDFROMHERE_CH0_PAUSE_LEN                   1
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_NEWADDEDFROMHERE_CH0_PAUSE_DEFAULT               0
	/*NEWADDEDFROMHERE_CH0_SPEED_MODE_MAC*/
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_NEWADDEDFROMHERE_CH0_SPEED_MODE
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_NEWADDEDFROMHERE_CH0_SPEED_MODE_OFFSET           4
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_NEWADDEDFROMHERE_CH0_SPEED_MODE_LEN              2
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_NEWADDEDFROMHERE_CH0_SPEED_MODE_DEFAULT          0
	/*NEWADDEDFROMHERE_CH0_DUPLEX_MODE_MAC*/
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_NEWADDEDFROMHERE_CH0_DUPLEX_MODE
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_NEWADDEDFROMHERE_CH0_DUPLEX_MODE_OFFSET          6
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_NEWADDEDFROMHERE_CH0_DUPLEX_MODE_LEN             2
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_NEWADDEDFROMHERE_CH0_DUPLEX_MODE_DEFAULT         0
	/*NEWADDEDFROMHERE_CH0_LINK_MAC*/
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_NEWADDEDFROMHERE_CH0_LINK
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_NEWADDEDFROMHERE_CH0_LINK_OFFSET                 7
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_NEWADDEDFROMHERE_CH0_LINK_LEN                    2
	#define UNIPHY_CHANNEL0_INPUT_OUTPUT_6_NEWADDEDFROMHERE_CH0_LINK_DEFAULT                0

struct uniphy_channel0_input_output_6 {
	a_uint32_t  newaddedfromhere_ch0_receive_pause_en:1;
	a_uint32_t  newaddedfromhere_ch0_transmit_pause_en:1;
	a_uint32_t  newaddedfromhere_ch0_asym_pause:1;
	a_uint32_t  newaddedfromhere_ch0_pause:1;
	a_uint32_t  newaddedfromhere_ch0_speed_mode:2;
	a_uint32_t  newaddedfromhere_ch0_duplex_mode:1;
	a_uint32_t  newaddedfromhere_ch0_link:1;
	a_uint32_t  _reserved0:24;
};

union uniphy_channel0_input_output_6_u {
	a_uint32_t val;
	struct uniphy_channel0_input_output_6 bf;
};

/*[register] UNIPHY_CHANNEL1_INPUT_OUTPUT_4*/
#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4
#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_ADDRESS 0x498
#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NUM     3
#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_INC     0x1
#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_TYPE    REG_TYPE_RW
#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_DEFAULT 0x844
	/*[field] NEWADDEDFROMHERE_CH1_REM_PHY_LPBK*/
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_REM_PHY_LPBK
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_REM_PHY_LPBK_OFFSET  0
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_REM_PHY_LPBK_LEN     1
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_REM_PHY_LPBK_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH1_SPEED_25M*/
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_SPEED_25M
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_SPEED_25M_OFFSET  1
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_SPEED_25M_LEN     2
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_SPEED_25M_DEFAULT 0x2
	/*[field] NEWADDEDFROMHERE_CH1_FORCE_SPEED_25M*/
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_FORCE_SPEED_25M
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_FORCE_SPEED_25M_OFFSET  3
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_FORCE_SPEED_25M_LEN     1
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_FORCE_SPEED_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH1_MR_NP_LOADED_25M*/
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_NP_LOADED_25M
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_NP_LOADED_25M_OFFSET  4
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_NP_LOADED_25M_LEN     1
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_NP_LOADED_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH1_MR_REG4_CH_25M*/
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_REG4_CH_25M
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_REG4_CH_25M_OFFSET  5
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_REG4_CH_25M_LEN     1
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_REG4_CH_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH1_MR_AN_ENABLE_25M*/
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_AN_ENABLE_25M
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_AN_ENABLE_25M_OFFSET  6
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_AN_ENABLE_25M_LEN     1
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_AN_ENABLE_25M_DEFAULT 0x1
	/*[field] NEWADDEDFROMHERE_CH1_MR_RESTART_AN_25M*/
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_RESTART_AN_25M
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_RESTART_AN_25M_OFFSET  7
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_RESTART_AN_25M_LEN     1
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_RESTART_AN_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH1_MR_LOOPBACK_25M*/
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_LOOPBACK_25M
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_LOOPBACK_25M_OFFSET  8
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_LOOPBACK_25M_LEN     1
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_LOOPBACK_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH1_MR_MAIN_RESET_25M*/
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_MAIN_RESET_25M
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_MAIN_RESET_25M_OFFSET  9
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_MAIN_RESET_25M_LEN     1
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_MAIN_RESET_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH1_POWER_ON_25M*/
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_POWER_ON_25M
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_POWER_ON_25M_OFFSET  10
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_POWER_ON_25M_LEN     1
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_POWER_ON_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH1_ADP_SW_RSTN*/
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_ADP_SW_RSTN
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_ADP_SW_RSTN_OFFSET  11
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_ADP_SW_RSTN_LEN     1
	#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_ADP_SW_RSTN_DEFAULT 0x1

struct uniphy_channel1_input_output_4 {
	a_uint32_t  newaddedfromhere_ch1_rem_phy_lpbk:1;
	a_uint32_t  newaddedfromhere_ch1_speed_25m:2;
	a_uint32_t  newaddedfromhere_ch1_force_speed_25m:1;
	a_uint32_t  newaddedfromhere_ch1_mr_np_loaded_25m:1;
	a_uint32_t  newaddedfromhere_ch1_mr_reg4_ch_25m:1;
	a_uint32_t  newaddedfromhere_ch1_mr_an_enable_25m:1;
	a_uint32_t  newaddedfromhere_ch1_mr_restart_an_25m:1;
	a_uint32_t  newaddedfromhere_ch1_mr_loopback_25m:1;
	a_uint32_t  newaddedfromhere_ch1_mr_main_reset_25m:1;
	a_uint32_t  newaddedfromhere_ch1_power_on_25m:1;
	a_uint32_t  newaddedfromhere_ch1_adp_sw_rstn:1;
	a_uint32_t  _reserved0:20;
};

union uniphy_channel1_input_output_4_u {
	a_uint32_t val;
	struct uniphy_channel1_input_output_4 bf;
};

/*[register] UNIPHY_CHANNEL2_INPUT_OUTPUT_4*/
#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4
#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_ADDRESS 0x4b0
#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NUM     3
#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_INC     0x1
#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_TYPE    REG_TYPE_RW
#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_DEFAULT 0x844
	/*[field] NEWADDEDFROMHERE_CH2_REM_PHY_LPBK*/
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_REM_PHY_LPBK
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_REM_PHY_LPBK_OFFSET  0
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_REM_PHY_LPBK_LEN     1
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_REM_PHY_LPBK_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH2_SPEED_25M*/
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_SPEED_25M
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_SPEED_25M_OFFSET  1
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_SPEED_25M_LEN     2
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_SPEED_25M_DEFAULT 0x2
	/*[field] NEWADDEDFROMHERE_CH2_FORCE_SPEED_25M*/
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_FORCE_SPEED_25M
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_FORCE_SPEED_25M_OFFSET  3
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_FORCE_SPEED_25M_LEN     1
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_FORCE_SPEED_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH2_MR_NP_LOADED_25M*/
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_NP_LOADED_25M
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_NP_LOADED_25M_OFFSET  4
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_NP_LOADED_25M_LEN     1
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_NP_LOADED_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH2_MR_REG4_CH_25M*/
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_REG4_CH_25M
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_REG4_CH_25M_OFFSET  5
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_REG4_CH_25M_LEN     1
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_REG4_CH_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH2_MR_AN_ENABLE_25M*/
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_AN_ENABLE_25M
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_AN_ENABLE_25M_OFFSET  6
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_AN_ENABLE_25M_LEN     1
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_AN_ENABLE_25M_DEFAULT 0x1
	/*[field] NEWADDEDFROMHERE_CH2_MR_RESTART_AN_25M*/
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_RESTART_AN_25M
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_RESTART_AN_25M_OFFSET  7
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_RESTART_AN_25M_LEN     1
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_RESTART_AN_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH2_MR_LOOPBACK_25M*/
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_LOOPBACK_25M
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_LOOPBACK_25M_OFFSET  8
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_LOOPBACK_25M_LEN     1
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_LOOPBACK_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH2_MR_MAIN_RESET_25M*/
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_MAIN_RESET_25M
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_MAIN_RESET_25M_OFFSET  9
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_MAIN_RESET_25M_LEN     1
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_MAIN_RESET_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH2_POWER_ON_25M*/
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_POWER_ON_25M
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_POWER_ON_25M_OFFSET  10
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_POWER_ON_25M_LEN     1
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_POWER_ON_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH2_ADP_SW_RSTN*/
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_ADP_SW_RSTN
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_ADP_SW_RSTN_OFFSET  11
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_ADP_SW_RSTN_LEN     1
	#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_ADP_SW_RSTN_DEFAULT 0x1

struct uniphy_channel2_input_output_4 {
	a_uint32_t  newaddedfromhere_ch2_rem_phy_lpbk:1;
	a_uint32_t  newaddedfromhere_ch2_speed_25m:2;
	a_uint32_t  newaddedfromhere_ch2_force_speed_25m:1;
	a_uint32_t  newaddedfromhere_ch2_mr_np_loaded_25m:1;
	a_uint32_t  newaddedfromhere_ch2_mr_reg4_ch_25m:1;
	a_uint32_t  newaddedfromhere_ch2_mr_an_enable_25m:1;
	a_uint32_t  newaddedfromhere_ch2_mr_restart_an_25m:1;
	a_uint32_t  newaddedfromhere_ch2_mr_loopback_25m:1;
	a_uint32_t  newaddedfromhere_ch2_mr_main_reset_25m:1;
	a_uint32_t  newaddedfromhere_ch2_power_on_25m:1;
	a_uint32_t  newaddedfromhere_ch2_adp_sw_rstn:1;
	a_uint32_t  _reserved0:20;
};

union uniphy_channel2_input_output_4_u {
	a_uint32_t val;
	struct uniphy_channel2_input_output_4 bf;
};

/*[register] UNIPHY_CHANNEL3_INPUT_OUTPUT_4*/
#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4
#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_ADDRESS 0x4c8
#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NUM     3
#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_INC     0x1
#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_TYPE    REG_TYPE_RW
#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_DEFAULT 0x844
	/*[field] NEWADDEDFROMHERE_CH3_REM_PHY_LPBK*/
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_REM_PHY_LPBK
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_REM_PHY_LPBK_OFFSET  0
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_REM_PHY_LPBK_LEN     1
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_REM_PHY_LPBK_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH3_SPEED_25M*/
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_SPEED_25M
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_SPEED_25M_OFFSET  1
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_SPEED_25M_LEN     2
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_SPEED_25M_DEFAULT 0x2
	/*[field] NEWADDEDFROMHERE_CH3_FORCE_SPEED_25M*/
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_FORCE_SPEED_25M
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_FORCE_SPEED_25M_OFFSET  3
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_FORCE_SPEED_25M_LEN     1
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_FORCE_SPEED_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH3_MR_NP_LOADED_25M*/
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_NP_LOADED_25M
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_NP_LOADED_25M_OFFSET  4
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_NP_LOADED_25M_LEN     1
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_NP_LOADED_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH3_MR_REG4_CH_25M*/
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_REG4_CH_25M
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_REG4_CH_25M_OFFSET  5
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_REG4_CH_25M_LEN     1
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_REG4_CH_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH3_MR_AN_ENABLE_25M*/
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_AN_ENABLE_25M
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_AN_ENABLE_25M_OFFSET  6
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_AN_ENABLE_25M_LEN     1
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_AN_ENABLE_25M_DEFAULT 0x1
	/*[field] NEWADDEDFROMHERE_CH3_MR_RESTART_AN_25M*/
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_RESTART_AN_25M
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_RESTART_AN_25M_OFFSET  7
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_RESTART_AN_25M_LEN     1
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_RESTART_AN_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH3_MR_LOOPBACK_25M*/
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_LOOPBACK_25M
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_LOOPBACK_25M_OFFSET  8
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_LOOPBACK_25M_LEN     1
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_LOOPBACK_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH3_MR_MAIN_RESET_25M*/
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_MAIN_RESET_25M
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_MAIN_RESET_25M_OFFSET  9
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_MAIN_RESET_25M_LEN     1
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_MAIN_RESET_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH3_POWER_ON_25M*/
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_POWER_ON_25M
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_POWER_ON_25M_OFFSET  10
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_POWER_ON_25M_LEN     1
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_POWER_ON_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH3_ADP_SW_RSTN*/
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_ADP_SW_RSTN
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_ADP_SW_RSTN_OFFSET  11
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_ADP_SW_RSTN_LEN     1
	#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_ADP_SW_RSTN_DEFAULT 0x1

struct uniphy_channel3_input_output_4 {
	a_uint32_t  newaddedfromhere_ch3_rem_phy_lpbk:1;
	a_uint32_t  newaddedfromhere_ch3_speed_25m:2;
	a_uint32_t  newaddedfromhere_ch3_force_speed_25m:1;
	a_uint32_t  newaddedfromhere_ch3_mr_np_loaded_25m:1;
	a_uint32_t  newaddedfromhere_ch3_mr_reg4_ch_25m:1;
	a_uint32_t  newaddedfromhere_ch3_mr_an_enable_25m:1;
	a_uint32_t  newaddedfromhere_ch3_mr_restart_an_25m:1;
	a_uint32_t  newaddedfromhere_ch3_mr_loopback_25m:1;
	a_uint32_t  newaddedfromhere_ch3_mr_main_reset_25m:1;
	a_uint32_t  newaddedfromhere_ch3_power_on_25m:1;
	a_uint32_t  newaddedfromhere_ch3_adp_sw_rstn:1;
	a_uint32_t  _reserved0:20;
};

union uniphy_channel3_input_output_4_u {
	a_uint32_t val;
	struct uniphy_channel3_input_output_4 bf;
};

/*[register] UNIPHY_CHANNEL4_INPUT_OUTPUT_4*/
#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4
#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_ADDRESS 0x4e0
#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NUM     3
#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_INC     0x1
#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_TYPE    REG_TYPE_RW
#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_DEFAULT 0x844
	/*[field] NEWADDEDFROMHERE_CH4_REM_PHY_LPBK*/
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_REM_PHY_LPBK
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_REM_PHY_LPBK_OFFSET  0
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_REM_PHY_LPBK_LEN     1
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_REM_PHY_LPBK_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH4_SPEED_25M*/
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_SPEED_25M
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_SPEED_25M_OFFSET  1
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_SPEED_25M_LEN     2
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_SPEED_25M_DEFAULT 0x2
	/*[field] NEWADDEDFROMHERE_CH4_FORCE_SPEED_25M*/
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_FORCE_SPEED_25M
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_FORCE_SPEED_25M_OFFSET  3
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_FORCE_SPEED_25M_LEN     1
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_FORCE_SPEED_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH4_MR_NP_LOADED_25M*/
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_NP_LOADED_25M
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_NP_LOADED_25M_OFFSET  4
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_NP_LOADED_25M_LEN     1
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_NP_LOADED_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH4_MR_REG4_CH_25M*/
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_REG4_CH_25M
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_REG4_CH_25M_OFFSET  5
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_REG4_CH_25M_LEN     1
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_REG4_CH_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH4_MR_AN_ENABLE_25M*/
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_AN_ENABLE_25M
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_AN_ENABLE_25M_OFFSET  6
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_AN_ENABLE_25M_LEN     1
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_AN_ENABLE_25M_DEFAULT 0x1
	/*[field] NEWADDEDFROMHERE_CH4_MR_RESTART_AN_25M*/
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_RESTART_AN_25M
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_RESTART_AN_25M_OFFSET  7
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_RESTART_AN_25M_LEN     1
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_RESTART_AN_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH4_MR_LOOPBACK_25M*/
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_LOOPBACK_25M
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_LOOPBACK_25M_OFFSET  8
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_LOOPBACK_25M_LEN     1
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_LOOPBACK_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH4_MR_MAIN_RESET_25M*/
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_MAIN_RESET_25M
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_MAIN_RESET_25M_OFFSET  9
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_MAIN_RESET_25M_LEN     1
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_MAIN_RESET_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH4_POWER_ON_25M*/
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_POWER_ON_25M
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_POWER_ON_25M_OFFSET  10
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_POWER_ON_25M_LEN     1
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_POWER_ON_25M_DEFAULT 0x0
	/*[field] NEWADDEDFROMHERE_CH4_ADP_SW_RSTN*/
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_ADP_SW_RSTN
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_ADP_SW_RSTN_OFFSET  11
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_ADP_SW_RSTN_LEN     1
	#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_ADP_SW_RSTN_DEFAULT 0x1

struct uniphy_channel4_input_output_4 {
	a_uint32_t  newaddedfromhere_ch4_rem_phy_lpbk:1;
	a_uint32_t  newaddedfromhere_ch4_speed_25m:2;
	a_uint32_t  newaddedfromhere_ch4_force_speed_25m:1;
	a_uint32_t  newaddedfromhere_ch4_mr_np_loaded_25m:1;
	a_uint32_t  newaddedfromhere_ch4_mr_reg4_ch_25m:1;
	a_uint32_t  newaddedfromhere_ch4_mr_an_enable_25m:1;
	a_uint32_t  newaddedfromhere_ch4_mr_restart_an_25m:1;
	a_uint32_t  newaddedfromhere_ch4_mr_loopback_25m:1;
	a_uint32_t  newaddedfromhere_ch4_mr_main_reset_25m:1;
	a_uint32_t  newaddedfromhere_ch4_power_on_25m:1;
	a_uint32_t  newaddedfromhere_ch4_adp_sw_rstn:1;
	a_uint32_t  _reserved0:20;
};

union uniphy_channel4_input_output_4_u {
	a_uint32_t val;
	struct uniphy_channel4_input_output_4 bf;
};

/*[register] UNIPHY_INSTANCE_LINK_DETECT*/
#define UNIPHY_INSTANCE_LINK_DETECT
#define UNIPHY_INSTANCE_LINK_DETECT_ADDRESS 0x570
#define UNIPHY_INSTANCE_LINK_DETECT_NUM     3
#define UNIPHY_INSTANCE_LINK_DETECT_INC     0x1
#define UNIPHY_INSTANCE_LINK_DETECT_TYPE    REG_TYPE_RW
#define UNIPHY_INSTANCE_LINK_DETECT_DEFAULT 0x0

struct uniphy_instance_link_detect {
	a_uint32_t  _reserved0:6;
	a_uint32_t  detect_los_from_sfp:3;
	a_uint32_t  _reserved1:23;
};

union uniphy_instance_link_detect_u {
	a_uint32_t val;
	struct uniphy_instance_link_detect  bf;
};

/*[register] UNIPHY_1_QP_USXG_OPITON1 */
#define UNIPHY_1_QP_USXG_OPITON1
#define UNIPHY_1_QP_USXG_OPITON1_ADDRESS 0x584
#define UNIPHY_1_QP_USXG_OPITON1_NUM     3
#define UNIPHY_1_QP_USXG_OPITON1_INC     0x1
#define UNIPHY_1_QP_USXG_OPITON1_TYPE    REG_TYPE_RW
#define UNIPHY_1_QP_USXG_OPITON1_DEFAULT 0x0

struct qp_usxg_opiton1 {
	a_uint32_t  gmii_src_sel:1;
	a_uint32_t  _reserved0:3;
	a_uint32_t  xpcs_ch0_ipg_tune_enable:1;
	a_uint32_t  xpcs_ch1_ipg_tune_enable:1;
	a_uint32_t  xpcs_ch2_ipg_tune_enable:1;
	a_uint32_t  xpcs_ch3_ipg_tune_enable:1;
	a_uint32_t  xpcs_ch0_ipg_tune_rst:1;
	a_uint32_t  xpcs_ch1_ipg_tune_rst:1;
	a_uint32_t  xpcs_ch2_ipg_tune_rst:1;
	a_uint32_t  xpcs_ch3_ipg_tune_rst:1;
	a_uint32_t  _reserved1:20;
};

union qp_usxg_opiton1_u {
	a_uint32_t val;
	struct qp_usxg_opiton1  bf;
};


/*[register] SR_XS_PCS_KR_STS1*/
#define SR_XS_PCS_KR_STS1
#define SR_XS_PCS_KR_STS1_ADDRESS 0x30020
#define SR_XS_PCS_KR_STS1_NUM     3
#define SR_XS_PCS_KR_STS1_INC     0x1
#define SR_XS_PCS_KR_STS1_TYPE    REG_TYPE_RW
#define SR_XS_PCS_KR_STS1_DEFAULT 0x0
	/*[field] RPCS_BKLK*/
	#define SR_XS_PCS_KR_STS1_RPCS_BKLK
	#define SR_XS_PCS_KR_STS1_RPCS_BKLK_OFFSET  0
	#define SR_XS_PCS_KR_STS1_RPCS_BKLK_LEN     1
	#define SR_XS_PCS_KR_STS1_RPCS_BKLK_DEFAULT 0x0
	/*[field] PRCS_HIBER*/
	#define SR_XS_PCS_KR_STS1_PRCS_HIBER
	#define SR_XS_PCS_KR_STS1_PRCS_HIBER_OFFSET  1
	#define SR_XS_PCS_KR_STS1_PRCS_HIBER_LEN     1
	#define SR_XS_PCS_KR_STS1_PRCS_HIBER_DEFAULT 0x0
	/*[field] PRBS31ABL*/
	#define SR_XS_PCS_KR_STS1_PRBS31ABL
	#define SR_XS_PCS_KR_STS1_PRBS31ABL_OFFSET  2
	#define SR_XS_PCS_KR_STS1_PRBS31ABL_LEN     1
	#define SR_XS_PCS_KR_STS1_PRBS31ABL_DEFAULT 0x0
	/*[field] PRBS9ABL*/
	#define SR_XS_PCS_KR_STS1_PRBS9ABL
	#define SR_XS_PCS_KR_STS1_PRBS9ABL_OFFSET  3
	#define SR_XS_PCS_KR_STS1_PRBS9ABL_LEN     1
	#define SR_XS_PCS_KR_STS1_PRBS9ABL_DEFAULT 0x0
	/*[field] PLU*/
	#define SR_XS_PCS_KR_STS1_PLU
	#define SR_XS_PCS_KR_STS1_PLU_OFFSET  12
	#define SR_XS_PCS_KR_STS1_PLU_LEN     1
	#define SR_XS_PCS_KR_STS1_PLU_DEFAULT 0x0

struct sr_xs_pcs_kr_sts1 {
	a_uint32_t  rpcs_bklk:1;
	a_uint32_t  prcs_hiber:1;
	a_uint32_t  prbs31abl:1;
	a_uint32_t  prbs9abl:1;
	a_uint32_t  _reserved0:8;
	a_uint32_t  plu:1;
	a_uint32_t  _reserved1:19;
};

union sr_xs_pcs_kr_sts1_u {
	a_uint32_t val;
	struct sr_xs_pcs_kr_sts1 bf;
};

/*[register] VR_XS_PCS_DIG_CTRL1*/
#define VR_XS_PCS_DIG_CTRL1
#define VR_XS_PCS_DIG_CTRL1_ADDRESS 0x38000
#define VR_XS_PCS_DIG_CTRL1_NUM     3
#define VR_XS_PCS_DIG_CTRL1_INC     0x1
#define VR_XS_PCS_DIG_CTRL1_TYPE    REG_TYPE_RW
#define VR_XS_PCS_DIG_CTRL1_DEFAULT 0x0
	/*[field] DSKBYP*/
	#define VR_XS_PCS_DIG_CTRL1_DSKBYP
	#define VR_XS_PCS_DIG_CTRL1_DSKBYP_OFFSET  0
	#define VR_XS_PCS_DIG_CTRL1_DSKBYP_LEN     1
	#define VR_XS_PCS_DIG_CTRL1_DSKBYP_DEFAULT 0x0
	/*[field] BYP_PWRUP*/
	#define VR_XS_PCS_DIG_CTRL1_BYP_PWRUP
	#define VR_XS_PCS_DIG_CTRL1_BYP_PWRUP_OFFSET  1
	#define VR_XS_PCS_DIG_CTRL1_BYP_PWRUP_LEN     1
	#define VR_XS_PCS_DIG_CTRL1_BYP_PWRUP_DEFAULT 0x0
	/*[field] EN_2_5G_MODE*/
	#define VR_XS_PCS_DIG_CTRL1_EN_2_5G_MODE
	#define VR_XS_PCS_DIG_CTRL1_EN_2_5G_MODE_OFFSET  2
	#define VR_XS_PCS_DIG_CTRL1_EN_2_5G_MODE_LEN     1
	#define VR_XS_PCS_DIG_CTRL1_EN_2_5G_MODE_DEFAULT 0x0
	/*[field] CR_CJN*/
	#define VR_XS_PCS_DIG_CTRL1_CR_CJN
	#define VR_XS_PCS_DIG_CTRL1_CR_CJN_OFFSET  3
	#define VR_XS_PCS_DIG_CTRL1_CR_CJN_LEN     1
	#define VR_XS_PCS_DIG_CTRL1_CR_CJN_DEFAULT 0x0
	/*[field] DTXLANED_0*/
	#define VR_XS_PCS_DIG_CTRL1_DTXLANED_0
	#define VR_XS_PCS_DIG_CTRL1_DTXLANED_0_OFFSET  4
	#define VR_XS_PCS_DIG_CTRL1_DTXLANED_0_LEN     1
	#define VR_XS_PCS_DIG_CTRL1_DTXLANED_0_DEFAULT 0x0
	/*[field] DTXLANED_3_1*/
	#define VR_XS_PCS_DIG_CTRL1_DTXLANED_3_1
	#define VR_XS_PCS_DIG_CTRL1_DTXLANED_3_1_OFFSET  5
	#define VR_XS_PCS_DIG_CTRL1_DTXLANED_3_1_LEN     3
	#define VR_XS_PCS_DIG_CTRL1_DTXLANED_3_1_DEFAULT 0x0
	/*[field] INIT*/
	#define VR_XS_PCS_DIG_CTRL1_INIT
	#define VR_XS_PCS_DIG_CTRL1_INIT_OFFSET  8
	#define VR_XS_PCS_DIG_CTRL1_INIT_LEN     1
	#define VR_XS_PCS_DIG_CTRL1_INIT_DEFAULT 0x0
	/*[field] USXG_EN*/
	#define VR_XS_PCS_DIG_CTRL1_USXG_EN
	#define VR_XS_PCS_DIG_CTRL1_USXG_EN_OFFSET  9
	#define VR_XS_PCS_DIG_CTRL1_USXG_EN_LEN     1
	#define VR_XS_PCS_DIG_CTRL1_USXG_EN_DEFAULT 0x0
	/*[field] USRA_RST*/
	#define VR_XS_PCS_DIG_CTRL1_USRA_RST
	#define VR_XS_PCS_DIG_CTRL1_USRA_RST_OFFSET  10
	#define VR_XS_PCS_DIG_CTRL1_USRA_RST_LEN     1
	#define VR_XS_PCS_DIG_CTRL1_USRA_RST_DEFAULT 0x0
	/*[field] PWRSV*/
	#define VR_XS_PCS_DIG_CTRL1_PWRSV
	#define VR_XS_PCS_DIG_CTRL1_PWRSV_OFFSET  11
	#define VR_XS_PCS_DIG_CTRL1_PWRSV_LEN     1
	#define VR_XS_PCS_DIG_CTRL1_PWRSV_DEFAULT 0x0
	/*[field] CL37_BP*/
	#define VR_XS_PCS_DIG_CTRL1_CL37_BP
	#define VR_XS_PCS_DIG_CTRL1_CL37_BP_OFFSET  12
	#define VR_XS_PCS_DIG_CTRL1_CL37_BP_LEN     1
	#define VR_XS_PCS_DIG_CTRL1_CL37_BP_DEFAULT 0x0
	/*[field] EN_VSMMD1*/
	#define VR_XS_PCS_DIG_CTRL1_EN_VSMMD1
	#define VR_XS_PCS_DIG_CTRL1_EN_VSMMD1_OFFSET  13
	#define VR_XS_PCS_DIG_CTRL1_EN_VSMMD1_LEN     1
	#define VR_XS_PCS_DIG_CTRL1_EN_VSMMD1_DEFAULT 0x0
	/*[field] R2TLBE*/
	#define VR_XS_PCS_DIG_CTRL1_R2TLBE
	#define VR_XS_PCS_DIG_CTRL1_R2TLBE_OFFSET  14
	#define VR_XS_PCS_DIG_CTRL1_R2TLBE_LEN     1
	#define VR_XS_PCS_DIG_CTRL1_R2TLBE_DEFAULT 0x0
	/*[field] VR_RST*/
	#define VR_XS_PCS_DIG_CTRL1_VR_RST
	#define VR_XS_PCS_DIG_CTRL1_VR_RST_OFFSET  15
	#define VR_XS_PCS_DIG_CTRL1_VR_RST_LEN     1
	#define VR_XS_PCS_DIG_CTRL1_VR_RST_DEFAULT 0x0

struct vr_xs_pcs_dig_ctrl1 {
	a_uint32_t  dskbyp:1;
	a_uint32_t  byp_pwrup:1;
	a_uint32_t  en_2_5g_mode:1;
	a_uint32_t  cr_cjn:1;
	a_uint32_t  dtxlaned_0:1;
	a_uint32_t  dtxlaned_3_1:3;
	a_uint32_t  init:1;
	a_uint32_t  usxg_en:1;
	a_uint32_t  usra_rst:1;
	a_uint32_t  pwrsv:1;
	a_uint32_t  cl37_bp:1;
	a_uint32_t  en_vsmmd1:1;
	a_uint32_t  r2tlbe:1;
	a_uint32_t  vr_rst:1;
	a_uint32_t  _reserved0:16;
};

union vr_xs_pcs_dig_ctrl1_u {
	a_uint32_t val;
	struct vr_xs_pcs_dig_ctrl1 bf;
};

/*[register] VR_XS_PCS_EEE_MCTRL0 */
#define VR_XS_PCS_EEE_MCTRL0
#define VR_XS_PCS_EEE_MCTRL0_ADDRESS 0x38006
#define VR_XS_PCS_EEE_MCTRL0_NUM     3
#define VR_XS_PCS_EEE_MCTRL0_INC     0x1
#define VR_XS_PCS_EEE_MCTRL0_TYPE    REG_TYPE_RW
#define VR_XS_PCS_EEE_MCTRL0_DEFAULT 0x0

struct vr_xs_pcs_eee_ctrl0 {
	a_uint32_t  ltx_en:1;
	a_uint32_t  lrx_en:1;
	a_uint32_t  tx_quiet_en:1;
	a_uint32_t  rx_quiet_en:1;
	a_uint32_t  tx_en_ctrl:1;
	a_uint32_t  eee_slr_byp:1;
	a_uint32_t  sign_bit:1;
	a_uint32_t  rx_en_ctrl:1;
	a_uint32_t  mult_fact_100ns:4;
	a_uint32_t  clkstop:4;
	a_uint32_t  _reserved0:16;
};

union vr_xs_pcs_eee_ctrl0_u {
	a_uint32_t val;
	struct vr_xs_pcs_eee_ctrl0 bf;
};

/*[register] VR_XS_PCS_EEE_TXTIMER */
#define VR_XS_PCS_EEE_TXTIMER
#define VR_XS_PCS_EEE_TXTIMER_ADDRESS 0x38008
#define VR_XS_PCS_EEE_TXTIMER_NUM     3
#define VR_XS_PCS_EEE_TXTIMER_INC     0x1
#define VR_XS_PCS_EEE_TXTIMER_TYPE    REG_TYPE_RW
#define VR_XS_PCS_EEE_TXTIMER_DEFAULT 0x0

struct vr_xs_pcs_eee_txtimer {
	a_uint32_t  tsl_res:6;
	a_uint32_t  t1u_res:2;
	a_uint32_t  twl_res:5;
	a_uint32_t  _reserved0:19;
};

union vr_xs_pcs_eee_txtimer_u {
	a_uint32_t val;
	struct vr_xs_pcs_eee_txtimer bf;
};

/*[register] VR_XS_PCS_EEE_RXTIMER  */
#define VR_XS_PCS_EEE_RXTIMER
#define VR_XS_PCS_EEE_RXTIMER_ADDRESS 0x38009
#define VR_XS_PCS_EEE_RXTIMER_NUM     3
#define VR_XS_PCS_EEE_RXTIMER_INC     0x1
#define VR_XS_PCS_EEE_RXTIMER_TYPE    REG_TYPE_RW
#define VR_XS_PCS_EEE_RXTIMER_DEFAULT 0x0

struct vr_xs_pcs_eee_rxtimer {
	a_uint32_t  res_100u:8;
	a_uint32_t  twr_res:6;
	a_uint32_t  _reserved0:18;
};

union vr_xs_pcs_eee_rxtimer_u {
	a_uint32_t val;
	struct vr_xs_pcs_eee_rxtimer bf;
};

/*[register] VR_XS_PCS_EEE_MCTRL1 */
#define VR_XS_PCS_EEE_MCTRL1
#define VR_XS_PCS_EEE_MCTRL1_ADDRESS 0x3800b
#define VR_XS_PCS_EEE_MCTRL1_NUM     3
#define VR_XS_PCS_EEE_MCTRL1_INC     0x1
#define VR_XS_PCS_EEE_MCTRL1_TYPE    REG_TYPE_RW
#define VR_XS_PCS_EEE_MCTRL1_DEFAULT 0x0

struct vr_xs_pcs_eee_ctrl1 {
	a_uint32_t  trn_lpi:1;
	a_uint32_t  txen_ea_tmr:6;
	a_uint32_t  _reserved0:1;
	a_uint32_t  trn_rxlpi:1;
	a_uint32_t  _reserved1:23;
};

union vr_xs_pcs_eee_ctrl1_u {
	a_uint32_t val;
	struct vr_xs_pcs_eee_ctrl1 bf;
};

/*[register] VR_XS_PCS_KR_CTRL */
#define VR_XS_PCS_KR_CTRL
#define VR_XS_PCS_KR_CTRL_ADDRESS 0x38007
#define VR_XS_PCS_KR_CTRL_NUM     3
#define VR_XS_PCS_KR_CTRL_INC     0x1
#define VR_XS_PCS_KR_CTRL_TYPE    REG_TYPE_RW
#define VR_XS_PCS_KR_CTRL_DEFAULT 0x0

struct vr_xs_pcs_kr_ctrl {
	a_uint32_t  vr_tp_en:1;
	a_uint32_t  pr_data:1;
	a_uint32_t  nval_sel:3;
	a_uint32_t  prbs9rxen:3;
	a_uint32_t  dis_scr:1;
	a_uint32_t  dis_descr:1;
	a_uint32_t  usxg_mode:3;
	a_uint32_t  usxg_2pt5g_gmii:1;
	a_uint32_t  _reserved0:18;
};

union vr_xs_pcs_kr_ctrl_u {
	a_uint32_t val;
	struct vr_xs_pcs_kr_ctrl bf;
};

/*[register] VR_XS_PCS_DIG_STS */
#define VR_XS_PCS_DIG_STS
#define VR_XS_PCS_DIG_STS_ADDRESS 0x3800a
#define VR_XS_PCS_DIG_STS_NUM     3
#define VR_XS_PCS_DIG_STS_INC     0x1
#define VR_XS_PCS_DIG_STS_TYPE    REG_TYPE_RW
#define VR_XS_PCS_DIG_STS_DEFAULT 0x0

struct vr_xs_pcs_dig_sts {
	a_uint32_t  am_count:15;
	a_uint32_t  _reserved0:17;
};

union vr_xs_pcs_dig_sts_u {
	a_uint32_t val;
	struct vr_xs_pcs_dig_sts bf;
};

/*[register] VR_MII_1_DIG_CTRL1 */
#define VR_MII_DIG_CTRL1_CHANNEL2_ADDRESS 0x1b8000
#define VR_MII_DIG_CTRL1_CHANNEL3_ADDRESS 0x1c8000

#define VR_MII_DIG_CTRL1_CHANNEL1
#define VR_MII_DIG_CTRL1_CHANNEL1_ADDRESS 0x1a8000
#define VR_MII_DIG_CTRL1_CHANNEL1_NUM     3
#define VR_MII_DIG_CTRL1_CHANNEL1_INC     0x1
#define VR_MII_DIG_CTRL1_CHANNEL1_TYPE    REG_TYPE_RW
#define VR_MII_DIG_CTRL1_CHANNEL1_DEFAULT 0x0

struct vr_mii_dig_ctrl1 {
	a_uint32_t  phy_mode:1;
	a_uint32_t  _reserved0:1;
	a_uint32_t  en_2_5g_mode:1;
	a_uint32_t  cr_cjn:1;
	a_uint32_t  dtxlaned:1;
	a_uint32_t  usra_rst:1;
	a_uint32_t  pre_emp:1;
	a_uint32_t  msk_rd_err:1;
	a_uint32_t  init:1;
	a_uint32_t  mac_auto_sw:1;
	a_uint32_t  cs_en:1;
	a_uint32_t  _reserved1:1;
	a_uint32_t  cl37_bp:1;
	a_uint32_t  en_vsmmd1:1;
	a_uint32_t  r2tlbe:1;
	a_uint32_t  vr_rst:1;
	a_uint32_t  _reserved2:16;
};

union vr_mii_dig_ctrl1_u {
	a_uint32_t val;
	struct vr_mii_dig_ctrl1 bf;
};

/*[register] SR_MII_CTRL*/
#define SR_MII_CTRL_CHANNEL1_ADDRESS 0x1a0000
#define SR_MII_CTRL_CHANNEL2_ADDRESS 0x1b0000
#define SR_MII_CTRL_CHANNEL3_ADDRESS 0x1c0000
#define SR_MII_CTRL
#define SR_MII_CTRL_ADDRESS 0x1f0000
#define SR_MII_CTRL_NUM     3
#define SR_MII_CTRL_INC     0x1
#define SR_MII_CTRL_TYPE    REG_TYPE_RW
#define SR_MII_CTRL_DEFAULT 0x0
	/*[field] SS5*/
	#define SR_MII_CTRL_SS5
	#define SR_MII_CTRL_SS5_OFFSET  5
	#define SR_MII_CTRL_SS5_LEN     1
	#define SR_MII_CTRL_SS5_DEFAULT 0x0
	/*[field] SS6*/
	#define SR_MII_CTRL_SS6
	#define SR_MII_CTRL_SS6_OFFSET  6
	#define SR_MII_CTRL_SS6_LEN     1
	#define SR_MII_CTRL_SS6_DEFAULT 0x0
	/*[field] DUPLEX_MODE*/
	#define SR_MII_CTRL_DUPLEX_MODE
	#define SR_MII_CTRL_DUPLEX_MODE_OFFSET  8
	#define SR_MII_CTRL_DUPLEX_MODE_LEN     1
	#define SR_MII_CTRL_DUPLEX_MODE_DEFAULT 0x0
	/*[field] RESTART_AN*/
	#define SR_MII_CTRL_RESTART_AN
	#define SR_MII_CTRL_RESTART_AN_OFFSET  9
	#define SR_MII_CTRL_RESTART_AN_LEN     1
	#define SR_MII_CTRL_RESTART_AN_DEFAULT 0x0
	/*[field] LPM*/
	#define SR_MII_CTRL_LPM
	#define SR_MII_CTRL_LPM_OFFSET  11
	#define SR_MII_CTRL_LPM_LEN     1
	#define SR_MII_CTRL_LPM_DEFAULT 0x0
	/*[field] AN_ENABLE*/
	#define SR_MII_CTRL_AN_ENABLE
	#define SR_MII_CTRL_AN_ENABLE_OFFSET  12
	#define SR_MII_CTRL_AN_ENABLE_LEN     1
	#define SR_MII_CTRL_AN_ENABLE_DEFAULT 0x0
	/*[field] SS13*/
	#define SR_MII_CTRL_SS13
	#define SR_MII_CTRL_SS13_OFFSET  13
	#define SR_MII_CTRL_SS13_LEN     1
	#define SR_MII_CTRL_SS13_DEFAULT 0x0
	/*[field] LBE*/
	#define SR_MII_CTRL_LBE
	#define SR_MII_CTRL_LBE_OFFSET  14
	#define SR_MII_CTRL_LBE_LEN     1
	#define SR_MII_CTRL_LBE_DEFAULT 0x0
	/*[field] RST*/
	#define SR_MII_CTRL_RST
	#define SR_MII_CTRL_RST_OFFSET  15
	#define SR_MII_CTRL_RST_LEN     1
	#define SR_MII_CTRL_RST_DEFAULT 0x0

struct sr_mii_ctrl {
	a_uint32_t  _reserved0:5;
	a_uint32_t  ss5:1;
	a_uint32_t  ss6:1;
	a_uint32_t  _reserved1:1;
	a_uint32_t  duplex_mode:1;
	a_uint32_t  restart_an:1;
	a_uint32_t  _reserved2:1;
	a_uint32_t  lpm:1;
	a_uint32_t  an_enable:1;
	a_uint32_t  ss13:1;
	a_uint32_t  lbe:1;
	a_uint32_t  rst:1;
	a_uint32_t  _reserved3:16;
};

union sr_mii_ctrl_u {
	a_uint32_t val;
	struct sr_mii_ctrl bf;
};

#define VR_MII_AN_CTRL_CHANNEL1_ADDRESS 0x1a8001
#define VR_MII_AN_CTRL_CHANNEL2_ADDRESS 0x1b8001
#define VR_MII_AN_CTRL_CHANNEL3_ADDRESS 0x1c8001
/*[register] VR_MII_AN_CTRL*/
#define VR_MII_AN_CTRL
#define VR_MII_AN_CTRL_ADDRESS 0x1f8001
#define VR_MII_AN_CTRL_NUM     3
#define VR_MII_AN_CTRL_INC     0x1
#define VR_MII_AN_CTRL_TYPE    REG_TYPE_RW
#define VR_MII_AN_CTRL_DEFAULT 0x0
	/*[field] MII_AN_INTR_EN*/
	#define VR_MII_AN_CTRL_MII_AN_INTR_EN
	#define VR_MII_AN_CTRL_MII_AN_INTR_EN_OFFSET  0
	#define VR_MII_AN_CTRL_MII_AN_INTR_EN_LEN     1
	#define VR_MII_AN_CTRL_MII_AN_INTR_EN_DEFAULT 0x0
	/*[field] PCS_MODE*/
	#define VR_MII_AN_CTRL_PCS_MODE
	#define VR_MII_AN_CTRL_PCS_MODE_OFFSET  1
	#define VR_MII_AN_CTRL_PCS_MODE_LEN     2
	#define VR_MII_AN_CTRL_PCS_MODE_DEFAULT 0x0
	/*[field] TX_CONFIG*/
	#define VR_MII_AN_CTRL_TX_CONFIG
	#define VR_MII_AN_CTRL_TX_CONFIG_OFFSET  3
	#define VR_MII_AN_CTRL_TX_CONFIG_LEN     1
	#define VR_MII_AN_CTRL_TX_CONFIG_DEFAULT 0x0
	/*[field] SGMII_LINK_STS*/
	#define VR_MII_AN_CTRL_SGMII_LINK_STS
	#define VR_MII_AN_CTRL_SGMII_LINK_STS_OFFSET  4
	#define VR_MII_AN_CTRL_SGMII_LINK_STS_LEN     1
	#define VR_MII_AN_CTRL_SGMII_LINK_STS_DEFAULT 0x0
	/*[field] MII_CTRL*/
	#define VR_MII_AN_CTRL_MII_CTRL
	#define VR_MII_AN_CTRL_MII_CTRL_OFFSET  8
	#define VR_MII_AN_CTRL_MII_CTRL_LEN     1
	#define VR_MII_AN_CTRL_MII_CTRL_DEFAULT 0x0

struct vr_mii_an_ctrl {
	a_uint32_t  mii_an_intr_en:1;
	a_uint32_t  pcs_mode:2;
	a_uint32_t  tx_config:1;
	a_uint32_t  sgmii_link_sts:1;
	a_uint32_t  _reserved0:3;
	a_uint32_t  mii_ctrl:1;
	a_uint32_t  _reserved1:23;
};

union vr_mii_an_ctrl_u {
	a_uint32_t val;
	struct vr_mii_an_ctrl bf;
};

/*[register] VR_MII_AN_INTR_STS*/
#define VR_MII_AN_INTR_STS_CHANNEL1_ADDRESS 0x1a8002
#define VR_MII_AN_INTR_STS_CHANNEL2_ADDRESS 0x1b8002
#define VR_MII_AN_INTR_STS_CHANNEL3_ADDRESS 0x1c8002
#define VR_MII_AN_INTR_STS
#define VR_MII_AN_INTR_STS_ADDRESS 0x1f8002
#define VR_MII_AN_INTR_STS_NUM     3
#define VR_MII_AN_INTR_STS_INC     0x1
#define VR_MII_AN_INTR_STS_TYPE    REG_TYPE_RW
#define VR_MII_AN_INTR_STS_DEFAULT 0x0
	/*[field] CL37_ANCMPLT_INTR*/
	#define VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR
	#define VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR_OFFSET  0
	#define VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR_LEN     1
	#define VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR_DEFAULT 0x0
	/*[field] CL37_ANSGM_STS*/
	#define VR_MII_AN_INTR_STS_CL37_ANSGM_STS
	#define VR_MII_AN_INTR_STS_CL37_ANSGM_STS_OFFSET  1
	#define VR_MII_AN_INTR_STS_CL37_ANSGM_STS_LEN     4
	#define VR_MII_AN_INTR_STS_CL37_ANSGM_STS_DEFAULT 0x0
	/*[field] USXG_AN_STS*/
	#define VR_MII_AN_INTR_STS_USXG_AN_STS
	#define VR_MII_AN_INTR_STS_USXG_AN_STS_OFFSET  8
	#define VR_MII_AN_INTR_STS_USXG_AN_STS_LEN     7
	#define VR_MII_AN_INTR_STS_USXG_AN_STS_DEFAULT 0x0

struct vr_mii_an_intr_sts {
	a_uint32_t  cl37_ancmplt_intr:1;
	a_uint32_t  cl37_ansgm_sts:4;
	a_uint32_t  _reserved0:3;
	a_uint32_t  usxg_an_sts:7;
	a_uint32_t  _reserved1:17;
};

union vr_mii_an_intr_sts_u {
	a_uint32_t val;
	struct vr_mii_an_intr_sts bf;
};

/*[register] VR_XAUI_MODE_CTRL*/
#define VR_XAUI_MODE_CTRL_CHANNEL1_ADDRESS 0x1a8004
#define VR_XAUI_MODE_CTRL_CHANNEL2_ADDRESS 0x1b8004
#define VR_XAUI_MODE_CTRL_CHANNEL3_ADDRESS 0x1c8004

#define VR_XAUI_MODE_CTRL_ADDRESS 0x1f8004
#define VR_XAUI_MODE_CTRL_NUM     3
#define VR_XAUI_MODE_CTRL_INC     0x1
#define VR_XAUI_MODE_CTRL_TYPE    REG_TYPE_RW
#define VR_XAUI_MODE_CTRL_DEFAULT 0x0

struct vr_xaui_mode_ctrl {
	a_uint32_t  ipg_check:1;
	a_uint32_t  _reserved0:31;
};

union vr_xaui_mode_ctrl_u {
	a_uint32_t val;
	struct vr_xaui_mode_ctrl bf;
};

/*[register] UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION*/
#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION
#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_ADDRESS 0x14
#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_NUM     3
#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_INC     0x1
#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_TYPE    REG_TYPE_RW
#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_DEFAULT 0x0
	/*[field] MMD1_REG_SRC_UPHY_PLL_VCO_TEMP_CMP*/
	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_TEMP_CMP
	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_TEMP_CMP_OFFSET  2
	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_TEMP_CMP_LEN     2
	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_TEMP_CMP_DEFAULT 0x0
	/*[field] MMD1_REG_SRC_UPHY_PLL_VCO_AMP*/
	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_AMP
	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_AMP_OFFSET  4
	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_AMP_LEN     2
	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_AMP_DEFAULT 0x0
	/*[field] MMD1_REG_SRC_UPHY_PLL_VCO_GAIN*/
	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_GAIN
	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_GAIN_OFFSET  6
	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_GAIN_LEN     2
	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_GAIN_DEFAULT 0x0
	/*[field] MMD1_REG_SRC_UPHY_PLL_LPF_C2*/
	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_C2
	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_C2_OFFSET  8
	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_C2_LEN     2
	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_C2_DEFAULT 0x0
	/*[field] MMD1_REG_SRC_UPHY_PLL_LPF_RES*/
	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_RES
	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_RES_OFFSET  10
	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_RES_LEN     2
	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_RES_DEFAULT 0x0
	/*[field] MMD1_REG_SRC_UPHY_PLL_CP_SEL*/
	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_CP_SEL
	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_CP_SEL_OFFSET  12
	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_CP_SEL_LEN     2
	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_CP_SEL_DEFAULT 0x0
	/*[field] MMD1_REG_SRC_UPHY_PLL_LPF_DC*/
	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_DC
	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_DC_OFFSET  14
	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_DC_LEN     2
	#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_DC_DEFAULT 0x0

struct uniphy_pll_control_vco_related_selection {
	a_uint32_t  mmd1_reg_src_uphy_pll_vco_temp_cmp:2;
	a_uint32_t  mmd1_reg_src_uphy_pll_vco_amp:2;
	a_uint32_t  mmd1_reg_src_uphy_pll_vco_gain:2;
	a_uint32_t  mmd1_reg_src_uphy_pll_lpf_c2:2;
	a_uint32_t  mmd1_reg_src_uphy_pll_lpf_res:2;
	a_uint32_t  mmd1_reg_src_uphy_pll_cp_sel:2;
	a_uint32_t  mmd1_reg_src_uphy_pll_lpf_dc:2;
	a_uint32_t  _reserved0:16;
};

union uniphy_pll_control_vco_related_selection_u {
	a_uint32_t val;
	struct uniphy_pll_control_vco_related_selection bf;
};

/*[register] UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION*/
#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION
#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_ADDRESS 0x24
#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_NUM     3
#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_INC     0x1
#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_TYPE    REG_TYPE_RW
#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_DEFAULT 0x0
	/*[field] MMD1_REG_SRC_UPHY_TX_EMP_LSB_EN*/
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EMP_LSB_EN
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EMP_LSB_EN_OFFSET  0
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EMP_LSB_EN_LEN     2
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EMP_LSB_EN_DEFAULT 0x0
	/*[field] MMD1_REG_SRC_UPHY_TX_RESCAL_CODE*/
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_RESCAL_CODE
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_RESCAL_CODE_OFFSET  2
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_RESCAL_CODE_LEN     2
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_RESCAL_CODE_DEFAULT 0x0
	/*[field] MMD1_REG_SRC_UPHY_TX_EMP_LVL*/
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EMP_LVL
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EMP_LVL_OFFSET  4
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EMP_LVL_LEN     2
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EMP_LVL_DEFAULT 0x0
	/*[field] MMD1_REG_SRC_UPHY_TX_AMP*/
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_AMP
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_AMP_OFFSET  6
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_AMP_LEN     2
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_AMP_DEFAULT 0x0
	/*[field] MMD1_REG_SRC_UPHY_TX_VCM_DELTA*/
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_VCM_DELTA
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_VCM_DELTA_OFFSET  8
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_VCM_DELTA_LEN     2
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_VCM_DELTA_DEFAULT 0x0
	/*[field] MMD1_REG_SRC_UPHY_TX_EN*/
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EN
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EN_OFFSET  10
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EN_LEN     2
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EN_DEFAULT 0x0
	/*[field] MMD1_REG_SRC_UPHY_TXD_BIT_WIDTH*/
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TXD_BIT_WIDTH
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TXD_BIT_WIDTH_OFFSET  12
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TXD_BIT_WIDTH_LEN     2
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TXD_BIT_WIDTH_DEFAULT 0x0
	/*[field] MMD1_REG_SRC_UPHY_TX_ACJTAG_BEACON_EN*/
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_ACJTAG_BEACON_EN
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_ACJTAG_BEACON_EN_OFFSET  14
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_ACJTAG_BEACON_EN_LEN     2
	#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_ACJTAG_BEACON_EN_DEFAULT 0x0

struct uniphy_tx_ac_jtag_mux_driver_selection {
	a_uint32_t  mmd1_reg_src_uphy_tx_emp_lsb_en:2;
	a_uint32_t  mmd1_reg_src_uphy_tx_rescal_code:2;
	a_uint32_t  mmd1_reg_src_uphy_tx_emp_lvl:2;
	a_uint32_t  mmd1_reg_src_uphy_tx_amp:2;
	a_uint32_t  mmd1_reg_src_uphy_tx_vcm_delta:2;
	a_uint32_t  mmd1_reg_src_uphy_tx_en:2;
	a_uint32_t  mmd1_reg_src_uphy_txd_bit_width:2;
	a_uint32_t  mmd1_reg_src_uphy_tx_acjtag_beacon_en:2;
	a_uint32_t  _reserved0:16;
};

union uniphy_tx_ac_jtag_mux_driver_selection_u {
	a_uint32_t val;
	struct uniphy_tx_ac_jtag_mux_driver_selection bf;
};

/*[register] UNIPHY_RESISTOR_CALIBRATION_1*/
#define UNIPHY_RESISTOR_CALIBRATION_1
#define UNIPHY_RESISTOR_CALIBRATION_1_ADDRESS 0x170
#define UNIPHY_RESISTOR_CALIBRATION_1_NUM     3
#define UNIPHY_RESISTOR_CALIBRATION_1_INC     0x1
#define UNIPHY_RESISTOR_CALIBRATION_1_TYPE    REG_TYPE_RW
#define UNIPHY_RESISTOR_CALIBRATION_1_DEFAULT 0x0
	/*[field] MMD1_REG_CALIB_RX_REG*/
	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_CALIB_RX_REG
	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_CALIB_RX_REG_OFFSET  0
	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_CALIB_RX_REG_LEN     5
	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_CALIB_RX_REG_DEFAULT 0x0
	/*[field] MMD1_REG_CALIB_TX_REG*/
	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_CALIB_TX_REG
	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_CALIB_TX_REG_OFFSET  5
	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_CALIB_TX_REG_LEN     5
	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_CALIB_TX_REG_DEFAULT 0x0
	/*[field] MMD1_REG_VREF_LVL*/
	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_VREF_LVL
	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_VREF_LVL_OFFSET  10
	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_VREF_LVL_LEN     5
	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_VREF_LVL_DEFAULT 0x0
	/*[field] MMD1_REG_DISABLE_LOAD_RES_TXRX*/
	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_DISABLE_LOAD_RES_TXRX
	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_DISABLE_LOAD_RES_TXRX_OFFSET  15
	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_DISABLE_LOAD_RES_TXRX_LEN     1
	#define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_DISABLE_LOAD_RES_TXRX_DEFAULT 0x0

struct uniphy_resistor_calibration_1 {
	a_uint32_t  mmd1_reg_calib_rx_reg:5;
	a_uint32_t  mmd1_reg_calib_tx_reg:5;
	a_uint32_t  mmd1_reg_vref_lvl:5;
	a_uint32_t  mmd1_reg_disable_load_res_txrx:1;
	a_uint32_t  _reserved0:16;
};

union uniphy_resistor_calibration_1_u {
	a_uint32_t val;
	struct uniphy_resistor_calibration_1 bf;
};

/*[register] UNIPHY_PLL_VCO_RELATED_CONTROL_1*/
#define UNIPHY_PLL_VCO_RELATED_CONTROL_1
#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_ADDRESS 0x78c
#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_NUM     3
#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_INC     0x1
#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_TYPE    REG_TYPE_RW
#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_DEFAULT 0x0
	/*[field] MIIREG_REG_UPHY_PLL_VCO_TEMP_CMP*/
	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_TEMP_CMP
	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_TEMP_CMP_OFFSET  0
	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_TEMP_CMP_LEN     6
	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_TEMP_CMP_DEFAULT 0x0
	/*[field] MIIREG_REG_UPHY_PLL_VCO_CALIB_READY*/
	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_CALIB_READY
	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_CALIB_READY_OFFSET  6
	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_CALIB_READY_LEN     1
	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_CALIB_READY_DEFAULT 0x0
	/*[field] MIIREG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY*/
	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY
	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY_OFFSET  7
	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY_LEN     1
	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY_DEFAULT 0x0
	/*[field] MIIREG_REG_UPHY_PLL_VCO_AMP*/
	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_AMP
	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_AMP_OFFSET  8
	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_AMP_LEN     4
	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_AMP_DEFAULT 0x0
	/*[field] MIIREG_REG_UPHY_PLL_VCO_GAIN*/
	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_GAIN
	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_GAIN_OFFSET  12
	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_GAIN_LEN     3
	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_GAIN_DEFAULT 0x0
	/*[field] MIIREG_UPHY_PLL_LCKDT_EN*/
	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_UPHY_PLL_LCKDT_EN
	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_UPHY_PLL_LCKDT_EN_OFFSET  15
	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_UPHY_PLL_LCKDT_EN_LEN     1
	#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_UPHY_PLL_LCKDT_EN_DEFAULT 0x0

struct uniphy_pll_vco_related_control_1 {
	a_uint32_t  miireg_reg_uphy_pll_vco_temp_cmp:6;
	a_uint32_t  miireg_reg_uphy_pll_vco_calib_ready:1;
	a_uint32_t  miireg_autoload_sel_pll_vco_calib_ready:1;
	a_uint32_t  miireg_reg_uphy_pll_vco_amp:4;
	a_uint32_t  miireg_reg_uphy_pll_vco_gain:3;
	a_uint32_t  miireg_uphy_pll_lckdt_en:1;
	a_uint32_t  _reserved0:16;
};

union uniphy_pll_vco_related_control_1_u {
	a_uint32_t val;
	struct uniphy_pll_vco_related_control_1 bf;
};

/*[register] UNIPHY_RX_AFE_2*/
#define UNIPHY_RX_AFE_2
#define UNIPHY_RX_AFE_2_ADDRESS 0x7c4
#define UNIPHY_RX_AFE_2_NUM     3
#define UNIPHY_RX_AFE_2_INC     0x1
#define UNIPHY_RX_AFE_2_TYPE    REG_TYPE_RW
#define UNIPHY_RX_AFE_2_DEFAULT 0x0
	/*[field] MIIREG_REG_UPHY_RX_AFE_RES1*/
	#define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_AFE_RES1
	#define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_AFE_RES1_OFFSET  0
	#define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_AFE_RES1_LEN     4
	#define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_AFE_RES1_DEFAULT 0x0
	/*[field] MIIREG_REG_UPHY_RX_AFE_CAP1*/
	#define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_AFE_CAP1
	#define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_AFE_CAP1_OFFSET  4
	#define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_AFE_CAP1_LEN     3
	#define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_AFE_CAP1_DEFAULT 0x0
	/*[field] MIIREG_REG_UPHY_RX_RESCAL_CODE*/
	#define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_RESCAL_CODE
	#define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_RESCAL_CODE_OFFSET  8
	#define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_RESCAL_CODE_LEN     5
	#define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_RESCAL_CODE_DEFAULT 0x0

struct uniphy_rx_afe_2 {
	a_uint32_t  miireg_reg_uphy_rx_afe_res1:4;
	a_uint32_t  miireg_reg_uphy_rx_afe_cap1:3;
	a_uint32_t  _reserved0:1;
	a_uint32_t  miireg_reg_uphy_rx_rescal_code:5;
	a_uint32_t  _reserved1:19;
};

union uniphy_rx_afe_2_u {
	a_uint32_t val;
	struct uniphy_rx_afe_2 bf;
};

/*[register] BANDGAP_IP_MBIAS_2*/
#define BANDGAP_IP_MBIAS_2
#define BANDGAP_IP_MBIAS_2_ADDRESS 0x9b004
#define BANDGAP_IP_MBIAS_2_NUM     4
#define BANDGAP_IP_MBIAS_2_INC     0x1
#define BANDGAP_IP_MBIAS_2_TYPE    REG_TYPE_RW
#define BANDGAP_IP_MBIAS_2_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_CMN_BG_RSV*/
	#define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_CMN_BG_RSV
	#define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_CMN_BG_RSV_OFFSET  0
	#define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_CMN_BG_RSV_LEN     8
	#define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_CMN_BG_RSV_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_CMN_ICC_RESCODE*/
	#define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_CMN_ICC_RESCODE
	#define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_CMN_ICC_RESCODE_OFFSET  8
	#define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_CMN_ICC_RESCODE_LEN     7
	#define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_CMN_ICC_RESCODE_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_MBIAS_EN*/
	#define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_MBIAS_EN
	#define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_MBIAS_EN_OFFSET  15
	#define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_MBIAS_EN_LEN     1
	#define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_MBIAS_EN_DEFAULT 0x0

struct bandgap_ip_mbias_2 {
	a_uint32_t  cmn_mmd1_reg_cmn_bg_rsv:8;
	a_uint32_t  cmn_mmd1_reg_cmn_icc_rescode:7;
	a_uint32_t  cmn_mmd1_reg_mbias_en:1;
	a_uint32_t  _reserved0:16;
};

union bandgap_ip_mbias_2_u {
	a_uint32_t val;
	struct bandgap_ip_mbias_2 bf;
};

/*[register] LDO_0P9V_RELATED_1*/
#define LDO_0P9V_RELATED_1
#define LDO_0P9V_RELATED_1_ADDRESS 0x9b054
#define LDO_0P9V_RELATED_1_NUM     4
#define LDO_0P9V_RELATED_1_INC     0x1
#define LDO_0P9V_RELATED_1_TYPE    REG_TYPE_RW
#define LDO_0P9V_RELATED_1_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_CMN_LDO_INT_RES_CTRL*/
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_INT_RES_CTRL
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_INT_RES_CTRL_OFFSET  0
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_INT_RES_CTRL_LEN     2
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_INT_RES_CTRL_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_CMN_LDO_INT_LOAD_EN*/
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_INT_LOAD_EN
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_INT_LOAD_EN_OFFSET  2
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_INT_LOAD_EN_LEN     1
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_INT_LOAD_EN_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_CMN_LDO_OCP_CURRENT_SEL*/
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_OCP_CURRENT_SEL
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_OCP_CURRENT_SEL_OFFSET  3
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_OCP_CURRENT_SEL_LEN     1
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_OCP_CURRENT_SEL_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_CMN_LDO_OCP_EN*/
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_OCP_EN
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_OCP_EN_OFFSET  4
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_OCP_EN_LEN     1
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_OCP_EN_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_CMN_LDO_BIAS_CTRL*/
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_BIAS_CTRL
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_BIAS_CTRL_OFFSET  5
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_BIAS_CTRL_LEN     2
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_BIAS_CTRL_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_CMN_LDO_VOUT_CTRL*/
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_VOUT_CTRL
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_VOUT_CTRL_OFFSET  7
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_VOUT_CTRL_LEN     4
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_VOUT_CTRL_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_CMN_LDO_EN*/
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_EN
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_EN_OFFSET  11
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_EN_LEN     1
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_EN_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_CMN_LDO_COMP_CURRENT_EN*/
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_COMP_CURRENT_EN
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_COMP_CURRENT_EN_OFFSET  12
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_COMP_CURRENT_EN_LEN     1
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_COMP_CURRENT_EN_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_CMN_VTT_LDO_BIASGEN_SEL*/
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_VTT_LDO_BIASGEN_SEL
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_VTT_LDO_BIASGEN_SEL_OFFSET  13
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_VTT_LDO_BIASGEN_SEL_LEN     3
	#define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_VTT_LDO_BIASGEN_SEL_DEFAULT 0x0

struct ldo_0p9v_related_1 {
	a_uint32_t  cmn_mmd1_reg_cmn_ldo_int_res_ctrl:2;
	a_uint32_t  cmn_mmd1_reg_cmn_ldo_int_load_en:1;
	a_uint32_t  cmn_mmd1_reg_cmn_ldo_ocp_current_sel:1;
	a_uint32_t  cmn_mmd1_reg_cmn_ldo_ocp_en:1;
	a_uint32_t  cmn_mmd1_reg_cmn_ldo_bias_ctrl:2;
	a_uint32_t  cmn_mmd1_reg_cmn_ldo_vout_ctrl:4;
	a_uint32_t  cmn_mmd1_reg_cmn_ldo_en:1;
	a_uint32_t  cmn_mmd1_reg_cmn_ldo_comp_current_en:1;
	a_uint32_t  cmn_mmd1_reg_cmn_vtt_ldo_biasgen_sel:3;
	a_uint32_t  _reserved0:16;
};

union ldo_0p9v_related_1_u {
	a_uint32_t val;
	struct ldo_0p9v_related_1 bf;
};

/*[register] OTP_VTT_LDO_RELATED*/
#define OTP_VTT_LDO_RELATED
#define OTP_VTT_LDO_RELATED_ADDRESS 0x9b05c
#define OTP_VTT_LDO_RELATED_NUM     4
#define OTP_VTT_LDO_RELATED_INC     0x1
#define OTP_VTT_LDO_RELATED_TYPE    REG_TYPE_RW
#define OTP_VTT_LDO_RELATED_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_CMN_VTT_LDO_RSV*/
	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_RSV
	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_RSV_OFFSET  0
	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_RSV_LEN     8
	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_RSV_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_CMN_VTT_LDO_INT_LOAD_CTRL*/
	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_INT_LOAD_CTRL
	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_INT_LOAD_CTRL_OFFSET  8
	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_INT_LOAD_CTRL_LEN     2
	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_INT_LOAD_CTRL_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_CMN_VTT_LDO_OCP_CURRENT_SEL*/
	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_OCP_CURRENT_SEL
	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_OCP_CURRENT_SEL_OFFSET  10
	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_OCP_CURRENT_SEL_LEN     1
	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_OCP_CURRENT_SEL_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_CMN_VTT_LDO_OCP_EN*/
	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_OCP_EN
	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_OCP_EN_OFFSET  11
	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_OCP_EN_LEN     1
	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_OCP_EN_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_CMN_VTT_LDO_BIAS_CTRL*/
	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_BIAS_CTRL
	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_BIAS_CTRL_OFFSET  12
	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_BIAS_CTRL_LEN     2
	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_BIAS_CTRL_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_CMN_VTT_LDO_EN*/
	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_EN
	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_EN_OFFSET  14
	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_EN_LEN     1
	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_EN_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_CMN_ANA_ISOLATION*/
	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_ANA_ISOLATION
	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_ANA_ISOLATION_OFFSET  15
	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_ANA_ISOLATION_LEN     1
	#define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_ANA_ISOLATION_DEFAULT 0x0

struct otp_vtt_ldo_related {
	a_uint32_t  cmn_mmd1_reg_cmn_vtt_ldo_rsv:8;
	a_uint32_t  cmn_mmd1_reg_cmn_vtt_ldo_int_load_ctrl:2;
	a_uint32_t  cmn_mmd1_reg_cmn_vtt_ldo_ocp_current_sel:1;
	a_uint32_t  cmn_mmd1_reg_cmn_vtt_ldo_ocp_en:1;
	a_uint32_t  cmn_mmd1_reg_cmn_vtt_ldo_bias_ctrl:2;
	a_uint32_t  cmn_mmd1_reg_cmn_vtt_ldo_en:1;
	a_uint32_t  cmn_mmd1_reg_cmn_ana_isolation:1;
	a_uint32_t  _reserved0:16;
};

union otp_vtt_ldo_related_u {
	a_uint32_t val;
	struct otp_vtt_ldo_related bf;
};

/*[register] OTP_TEMPERATURE_COMPENSATE_1*/
#define OTP_TEMPERATURE_COMPENSATE_1
#define OTP_TEMPERATURE_COMPENSATE_1_ADDRESS 0x9b08c
#define OTP_TEMPERATURE_COMPENSATE_1_NUM     4
#define OTP_TEMPERATURE_COMPENSATE_1_INC     0x1
#define OTP_TEMPERATURE_COMPENSATE_1_TYPE    REG_TYPE_RW
#define OTP_TEMPERATURE_COMPENSATE_1_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_UPHY_ICTAT100U_CTRL0*/
	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL0
	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL0_OFFSET  0
	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL0_LEN     3
	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL0_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_UPHY_ICTAT100U_CTRL1*/
	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL1
	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL1_OFFSET  4
	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL1_LEN     3
	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL1_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_UPHY_ICTAT100U_CTRL2*/
	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL2
	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL2_OFFSET  8
	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL2_LEN     3
	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL2_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_UPHY_ICTAT100U_EN*/
	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_EN
	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_EN_OFFSET  12
	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_EN_LEN     3
	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_EN_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_CMN_PLL_ICTAT100U_EN*/
	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_CMN_PLL_ICTAT100U_EN
	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_CMN_PLL_ICTAT100U_EN_OFFSET  15
	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_CMN_PLL_ICTAT100U_EN_LEN     1
	#define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_CMN_PLL_ICTAT100U_EN_DEFAULT 0x0

struct otp_temperature_compensate_1 {
	a_uint32_t  cmn_mmd1_reg_uphy_ictat100u_ctrl0:3;
	a_uint32_t  _reserved0:1;
	a_uint32_t  cmn_mmd1_reg_uphy_ictat100u_ctrl1:3;
	a_uint32_t  _reserved1:1;
	a_uint32_t  cmn_mmd1_reg_uphy_ictat100u_ctrl2:3;
	a_uint32_t  _reserved2:1;
	a_uint32_t  cmn_mmd1_reg_uphy_ictat100u_en:3;
	a_uint32_t  cmn_mmd1_reg_cmn_pll_ictat100u_en:1;
	a_uint32_t  _reserved3:16;
};

union otp_temperature_compensate_1_u {
	a_uint32_t val;
	struct otp_temperature_compensate_1 bf;
};

/*[register] PLL_VCO_RELATED_CONTROL_1*/
#define PLL_VCO_RELATED_CONTROL_1
#define PLL_VCO_RELATED_CONTROL_1_ADDRESS 0x9b78c
#define PLL_VCO_RELATED_CONTROL_1_NUM     4
#define PLL_VCO_RELATED_CONTROL_1_INC     0x1
#define PLL_VCO_RELATED_CONTROL_1_TYPE    REG_TYPE_RW
#define PLL_VCO_RELATED_CONTROL_1_DEFAULT 0x0
	/*[field] CMN_MII_REG_REG_CMN_PLL_VCO_TEMP_CMP*/
	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_TEMP_CMP
	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_TEMP_CMP_OFFSET  0
	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_TEMP_CMP_LEN     6
	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_TEMP_CMP_DEFAULT 0x0
	/*[field] CMN_MII_REG_REG_CMN_PLL_VCO_CALIB_READY*/
	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_CALIB_READY
	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_CALIB_READY_OFFSET  6
	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_CALIB_READY_LEN     1
	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_CALIB_READY_DEFAULT 0x0
	/*[field] CMN_MII_REG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY*/
	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY
	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY_OFFSET  7
	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY_LEN     1
	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY_DEFAULT 0x0
	/*[field] CMN_MII_REG_REG_CMN_PLL_VCO_AMP*/
	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_AMP
	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_AMP_OFFSET  8
	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_AMP_LEN     4
	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_AMP_DEFAULT 0x0
	/*[field] CMN_MII_REG_CMN_PLL_LCKDT_EN*/
	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_CMN_PLL_LCKDT_EN
	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_CMN_PLL_LCKDT_EN_OFFSET  15
	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_CMN_PLL_LCKDT_EN_LEN     1
	#define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_CMN_PLL_LCKDT_EN_DEFAULT 0x0

struct pll_vco_related_control_1 {
	a_uint32_t  cmn_mii_reg_reg_cmn_pll_vco_temp_cmp:6;
	a_uint32_t  cmn_mii_reg_reg_cmn_pll_vco_calib_ready:1;
	a_uint32_t  cmn_mii_reg_autoload_sel_pll_vco_calib_ready:1;
	a_uint32_t  cmn_mii_reg_reg_cmn_pll_vco_amp:4;
	a_uint32_t  _reserved0:3;
	a_uint32_t  cmn_mii_reg_cmn_pll_lckdt_en:1;
	a_uint32_t  _reserved1:16;
};

union pll_vco_related_control_1_u {
	a_uint32_t val;
	struct pll_vco_related_control_1 bf;
};

/*[register] PLL_CONTROL_VCO_RELATED_SELECTION_2*/
#define PLL_CONTROL_VCO_RELATED_SELECTION_2
#define PLL_CONTROL_VCO_RELATED_SELECTION_2_ADDRESS 0x9b02c
#define PLL_CONTROL_VCO_RELATED_SELECTION_2_NUM     4
#define PLL_CONTROL_VCO_RELATED_SELECTION_2_INC     0x1
#define PLL_CONTROL_VCO_RELATED_SELECTION_2_TYPE    REG_TYPE_RW
#define PLL_CONTROL_VCO_RELATED_SELECTION_2_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_SRC_CMN_PLL_VCO_TEMP_CMP*/
	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_TEMP_CMP
	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_TEMP_CMP_OFFSET  0
	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_TEMP_CMP_LEN     2
	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_TEMP_CMP_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_SRC_CMN_PLL_VCO_AMP*/
	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_AMP
	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_AMP_OFFSET  2
	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_AMP_LEN     2
	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_AMP_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_SRC_CMN_PLL_FBCLK_DIV*/
	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_FBCLK_DIV
	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_FBCLK_DIV_OFFSET  4
	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_FBCLK_DIV_LEN     2
	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_FBCLK_DIV_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_READY*/
	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_READY
	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_READY_OFFSET  6
	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_READY_LEN     2
	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_READY_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_CODE*/
	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_CODE
	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_CODE_OFFSET  8
	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_CODE_LEN     2
	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_CODE_DEFAULT 0x0
	/*[field] CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_START*/
	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_START
	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_START_OFFSET  10
	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_START_LEN     2
	#define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_START_DEFAULT 0x0

struct pll_control_vco_related_selection_2 {
	a_uint32_t  cmn_mmd1_reg_src_cmn_pll_vco_temp_cmp:2;
	a_uint32_t  cmn_mmd1_reg_src_cmn_pll_vco_amp:2;
	a_uint32_t  cmn_mmd1_reg_src_cmn_pll_fbclk_div:2;
	a_uint32_t  cmn_mmd1_reg_src_cmn_pll_vco_calib_ready:2;
	a_uint32_t  cmn_mmd1_reg_src_cmn_pll_vco_calib_code:2;
	a_uint32_t  cmn_mmd1_reg_src_cmn_pll_vco_calib_start:2;
	a_uint32_t  _reserved0:20;
};

union pll_control_vco_related_selection_2_u {
	a_uint32_t val;
	struct pll_control_vco_related_selection_2 bf;
};

/*[register] PLL_POWER_ON_AND_RESET*/
#define PLL_POWER_ON_AND_RESET
#define PLL_POWER_ON_AND_RESET_ADDRESS 0x780
#define PLL_POWER_ON_AND_RESET_NUM     4
#define PLL_POWER_ON_AND_RESET_INC     0x1
#define PLL_POWER_ON_AND_RESET_TYPE    REG_TYPE_RW
#define PLL_POWER_ON_AND_RESET_DEFAULT 0x2ff
	/*[field] MIIREG_UPHY_PLL_RSTN*/
	#define MIIREG_UPHY_PLL_RSTN_MIIREG_UPHY_PLL_RSTN
	#define MIIREG_UPHY_PLL_RSTN_MIIREG_UPHY_PLL_RSTN_OFFSET  0
	#define MIIREG_UPHY_PLL_RSTN_MIIREG_UPHY_PLL_RSTN_LEN     1
	#define MIIREG_UPHY_PLL_RSTN_MIIREG_UPHY_PLL_RSTN_DEFAULT 0x1
	/*[field] MIIREG_REG_UPHY_PLL_EN*/
	#define PLL_POWER_ON_AND_RESET_MIIREG_REG_UPHY_PLL_EN
	#define PLL_POWER_ON_AND_RESET_MIIREG_REG_UPHY_PLL_EN_OFFSET  1
	#define PLL_POWER_ON_AND_RESET_MIIREG_REG_UPHY_PLL_EN_LEN     1
	#define PLL_POWER_ON_AND_RESET_MIIREG_REG_UPHY_PLL_EN_DEFAULT 0x1
	/*[field] MIIREG_UPHY_RXCLK_SW_RSTN*/
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_SW_RSTN
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_SW_RSTN_OFFSET  2
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_SW_RSTN_LEN     1
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_SW_RSTN_DEFAULT 0x1
	/*[field] MIIREG_UPHY_RXCLK_FLOOP_SW_RSTN*/
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_FLOOP_SW_RSTN
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_FLOOP_SW_RSTN_OFFSET  3
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_FLOOP_SW_RSTN_LEN     1
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_FLOOP_SW_RSTN_DEFAULT 0x1
	/*[field] MIIREG_UPHY_TXCLK_SW_RSTN*/
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_TXCLK_SW_RSTN
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_TXCLK_SW_RSTN_OFFSET  4
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_TXCLK_SW_RSTN_LEN     1
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_TXCLK_SW_RSTN_DEFAULT 0x0
	/*[field] MIIREG_UPHY_SSC_CTRL_CLK_SW_RSTN*/
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_SSC_CTRL_CLK_SW_RSTN
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_SSC_CTRL_CLK_SW_RSTN_OFFSET  5
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_SSC_CTRL_CLK_SW_RSTN_LEN     1
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_SSC_CTRL_CLK_SW_RSTN_DEFAULT 0x0
	/*[field] MIIREG_UPHY_ANA_EN_SW_RSTN*/
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_ANA_EN_SW_RSTN
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_ANA_EN_SW_RSTN_OFFSET  6
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_ANA_EN_SW_RSTN_LEN     1
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_ANA_EN_SW_RSTN_DEFAULT 0x0
	/*[field] MIIREG_UPHY_PLL_MMDIV_RSTN*/
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PLL_MMDIV_RSTN
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PLL_MMDIV_RSTN_OFFSET  7
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PLL_MMDIV_RSTN_LEN     1
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PLL_MMDIV_RSTN_DEFAULT 0x0
	/*[field] MIIREG_UPHY_CMN_12GPLL_ISOLATION*/
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_CMN_12GPLL_ISOLATION
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_CMN_12GPLL_ISOLATION_OFFSET  8
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_CMN_12GPLL_ISOLATION_LEN     1
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_CMN_12GPLL_ISOLATION_DEFAULT 0x0
	/*[field] MIIREG_UPHY_PCS_SW_RSTN*/
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PCS_SW_RSTN
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PCS_SW_RSTN_OFFSET  9
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PCS_SW_RSTN_LEN     1
	#define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PCS_SW_RSTN_DEFAULT 0x0

struct pll_power_on_and_reset {
	a_uint32_t  pll_reset:1;
	a_uint32_t  pll_power_on:1;
	a_uint32_t  software_reset_rxclk:1;
	a_uint32_t  software_reset_rxclk_floop:1;
	a_uint32_t  software_reset_txclk:1;
	a_uint32_t  software_reset_ctrlclk:1;
	a_uint32_t  software_reset_analog_reset:1;
	a_uint32_t  reference_clock_reset:1;
	a_uint32_t  cmn_12gpll_isolation:1;
	a_uint32_t  pqsgmii_pcs_reset:1;
	a_uint32_t  _reserved0:22;
};

union pll_power_on_and_reset_u {
	a_uint32_t val;
	struct pll_power_on_and_reset bf;
};

/*[register] UNIPHY_MISC2_PHY_MODE*/
#define UNIPHY_MISC2_PHY_MODE
#define UNIPHY_MISC2_PHY_MODE_ADDRESS 0x218
#define UNIPHY_MISC2_PHY_MODE_NUM     4
#define UNIPHY_MISC2_PHY_MODE_INC     0x1
#define UNIPHY_MISC2_PHY_MODE_TYPE    REG_TYPE_RW
#define UNIPHY_MISC2_PHY_MODE_DEFAULT 0x0
	/*[field] MMD1_REG_REG_RATE*/
	#define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_RATE
	#define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_RATE_OFFSET  0
	#define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_RATE_LEN     2
	#define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_RATE_DEFAULT 0x1
	/*[field] MMD1_REG_REG_PHY_MODE*/
	#define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_PHY_MODE
	#define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_PHY_MODE_OFFSET  4
	#define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_PHY_MODE_LEN     3
	#define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_PHY_MODE_DEFAULT 0x1


struct uniphy_misc2_phy_mode {
	a_uint32_t  phy_rate:2;
	a_uint32_t  _reserved0:2;
	a_uint32_t  phy_mode:3;
	a_uint32_t  _reserved1:25;
};

union uniphy_misc2_phy_mode_u {
	a_uint32_t val;
	struct uniphy_misc2_phy_mode bf;
};

#ifdef MPPE
/*[register] UNIPHY_CLKOUT_50M_CTRL*/
#define UNIPHY_CLKOUT_50M_CTRL
#define UNIPHY_CLKOUT_50M_CTRL_ADDRESS 0x610
#define UNIPHY_CLKOUT_50M_CTRL_NUM     2
#define UNIPHY_CLKOUT_50M_CTRL_INC     0x1
#define UNIPHY_CLKOUT_50M_CTRL_TYPE    REG_TYPE_RW
#define UNIPHY_CLKOUT_50M_CTRL_DEFAULT 0x31c
	/*[field] UNIPHY_CLKOUT_50M_CTRL_CLK_50M_25M_EN*/
	#define UNIPHY_CLKOUT_50M_CTRL_EN
	#define UNIPHY_CLKOUT_50M_CTRL_CLK_50M_25M_EN_OFFSET  0
	#define UNIPHY_CLKOUT_50M_CTRL_CLK_50M_25M_EN_LEN     1
	#define UNIPHY_CLKOUT_50M_CTRL_CLK_50M_25M_EN_DEFAULT 0
	/*[field] UNIPHY_CLKOUT_50M_CTRL_CLK_50M_25M_DRV_SEL*/
	#define UNIPHY_CLKOUT_50M_CTRL_CLK_50M_25M_DRV_SEL
	#define UNIPHY_CLKOUT_50M_CTRL_CLK_50M_25M_DRV_SEL_OFFSET  1
	#define UNIPHY_CLKOUT_50M_CTRL_CLK_50M_25M_DRV_SEL_LEN     2
	#define UNIPHY_CLKOUT_50M_CTRL_CLK_50M_25M_DRV_SEL_DEFAULT 0x2
	/*[field] UNIPHY_CLKOUT_50M_CTRL_CLK_50M_25M_DRV_PULLDN*/
	#define UNIPHY_CLKOUT_50M_CTRL_CLK_50M_25M_DRV_PULLDN
	#define UNIPHY_CLKOUT_50M_CTRL_CLK_50M_25M_DRV_PULLDN_OFFSET  3
	#define UNIPHY_CLKOUT_50M_CTRL_CLK_50M_25M_DRV_PULLDN_LEN     1
	#define UNIPHY_CLKOUT_50M_CTRL_CLK_50M_25M_DRV_PULLDN_DEFAULT 0x1
	/*[field] UNIPHY_CLKOUT_50M_CTRL_CLK_50M_25M_DRV_R_SEL*/
	#define UNIPHY_CLKOUT_50M_CTRL_CLK_50M_25M_DRV_R_SEL
	#define UNIPHY_CLKOUT_50M_CTRL_CLK_50M_25M_DRV_R_SEL_OFFSET  4
	#define UNIPHY_CLKOUT_50M_CTRL_CLK_50M_25M_DRV_R_SEL_LEN     1
	#define UNIPHY_CLKOUT_50M_CTRL_CLK_50M_25M_DRV_R_SEL_DEFAULT 0x1
	/*[field] UNIPHY_CLKOUT_50M_CTRL_CLK_50M_DIV2_SEL*/
	#define UNIPHY_CLKOUT_50M_CTRL_CLK_50M_DIV2_SEL
	#define UNIPHY_CLKOUT_50M_CTRL_CLK_50M_DIV2_SEL_OFFSET  5
	#define UNIPHY_CLKOUT_50M_CTRL_CLK_50M_DIV2_SEL_LEN     1
	#define UNIPHY_CLKOUT_50M_CTRL_CLK_50M_DIV2_SEL_DEFAULT 0
	/*[field] UNIPHY_CLKOUT_50M_CTRL_CLK_50M_25M_LDOLVL*/
	#define UNIPHY_CLKOUT_50M_CTRL_CLK_50M_25M_LDOLVL
	#define UNIPHY_CLKOUT_50M_CTRL_CLK_50M_25M_LDOLVL_OFFSET  8
	#define UNIPHY_CLKOUT_50M_CTRL_CLK_50M_25M_LDOLVL_LEN     3
	#define UNIPHY_CLKOUT_50M_CTRL_CLK_50M_25M_LDOLVL_DEFAULT 3
struct uniphy_clkout_50m_ctrl {
	a_uint32_t  clk_50m_25m_en:1;
	a_uint32_t  clk_50m_25m_drv_sel:2;
	a_uint32_t  clk_50m_25m_drv_pulldn:1;
	a_uint32_t  clk_50m_25m_r_sel:1;
	a_uint32_t  clk_50m_div2_sel:1;
	a_uint32_t  _reserved0:2;
	a_uint32_t  clk_50m_25m_ldolvl:3;
	a_uint32_t  _reserved1:22;
};

union uniphy_clkout_50m_ctrl_u {
	a_uint32_t val;
	struct uniphy_clkout_50m_ctrl bf;
};
/*[register] UNIPHY_VCO_CALIBRATION_CONTROL_REGISTER*/
#define UNIPHY_VCO_CALIBRATION_CONTROL
#define UNIPHY_VCO_CALIBRATION_CONTROL_ADDRESS 0xb4
#define UNIPHY_VCO_CALIBRATION_CONTROL_NUM     2
#define UNIPHY_VCO_CALIBRATION_CONTROL_INC     0x1
#define UNIPHY_VCO_CALIBRATION_CONTROL_TYPE    REG_TYPE_RW
#define UNIPHY_VCO_CALIBRATION_CONTROL_DEFAULT 0x281a
	/*[field] MMD1_REG_PLL_VCO_CALIB_MANU_CAL*/
	#define UNIPHY_PLL_VCO_CALIB_MANU_CAL
	#define UNIPHY_PLL_VCO_CALIB_MANU_CAL_OFFSET  0
	#define UNIPHY_PLL_VCO_CALIB_MANU_CAL_LEN     6
	#define UNIPHY_PLL_VCO_CALIB_MANU_CAL_DEFAULT 0x1a
	/*[field] MMD1_REG_PLL_VCO_CALIB_AUTO*/
	#define UNIPHY_PLL_VCO_CALIB_AUTO
	#define UNIPHY_PLL_VCO_CALIB_AUTO_OFFSET  6
	#define UNIPHY_PLL_VCO_CALIB_AUTO_LEN     6
	#define UNIPHY_PLL_VCO_CALIB_AUTO_DEFAULT 0x20
	/*[field] MMD1_REG_PLL_VCO_CALIB_MANU_EN*/
	#define UNIPHY_PLL_VCO_CALIB_MANU_EN
	#define UNIPHY_PLL_VCO_CALIB_MANU_EN_OFFSET  12
	#define UNIPHY_PLL_VCO_CALIB_MANU_EN_LEN     1
	#define UNIPHY_PLL_VCO_CALIB_MANU_EN_DEFAULT 0
	/*[field] MMD1_REG_SPEED_MODE*/
	#define UNIPHY_PLL_SPEED_MODE
	#define UNIPHY_PLL_SPEED_MODE_OFFSET  13
	#define UNIPHY_PLL_SPEED_MODE_LEN     1
	#define UNIPHY_PLL_SPEED_MODE_DEFAULT 1
	/*[field] MMD1_REG_PLL_VCO_CALIB_RESTART*/
	#define UNIPHY_PLL_VCO_CALIB_RESTART
	#define UNIPHY_PLL_VCO_CALIB_RESTART_OFFSET  14
	#define UNIPHY_PLL_VCO_CALIB_RESTART_LEN     1
	#define UNIPHY_PLL_VCO_CALIB_RESTART_DEFAULT 0
	/*[field] MMD1_REG_PLL_VCO_CALIB_FREQ_COEFF*/
	#define UNIPHY_PLL_VCO_CALIB_FREQ_COEFF
	#define UNIPHY_PLL_VCO_CALIB_FREQ_COEFF_OFFSET  15
	#define UNIPHY_PLL_VCO_CALIB_FREQ_COEFF_LEN     1
	#define UNIPHY_PLL_VCO_CALIB_FREQ_COEFF_DEFAULT 0


struct uniphy_vco_cal_control {
	a_uint32_t  calib_manu:6;
	a_uint32_t  calib_auto:6;
	a_uint32_t  calib_manu_en:1;
	a_uint32_t  speed_mode : 1;
	a_uint32_t  calib_restart:1;
	a_uint32_t  calib_freq:1;
	a_uint32_t  _reserved0:16;
};

union uniphy_vco_cal_control_u {
	a_uint32_t val;
	struct uniphy_vco_cal_control bf;
};
#endif
#endif
#endif
