/*
 * Copyright 2018-2020 NXP
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */

#ifndef _SOC_H
#define	_SOC_H

/* Chassis specific defines - common across SoC's of a particular platform */
#include <dcfg_lsch2.h>
#include <soc_default_base_addr.h>
#include <soc_default_helper_macros.h>


#define NUM_DRAM_REGIONS		3
#define	NXP_DRAM0_ADDR			0x80000000
#define NXP_DRAM0_MAX_SIZE		0x80000000	/*  2 GB  */

#define	NXP_DRAM1_ADDR			0x880000000
#define NXP_DRAM1_MAX_SIZE		0x780000000	/* 30 GB  */

#define	NXP_DRAM2_ADDR			0x8800000000
#define NXP_DRAM2_MAX_SIZE		0x7800000000	/* 480 GB */

/*DRAM0 Size defined in platform_def.h */
#define	NXP_DRAM0_SIZE			PLAT_DEF_DRAM0_SIZE

/* Start: Macros used by soc.c: get_boot_dev */
#define PORSR1_RCW_MASK		0xff800000
#define PORSR1_RCW_SHIFT	23
/* End: Macros used by soc.c: get_boot_dev */

/*
 * SVR Definition (not include major and minor rev)
 * A: without security
 * AE: with security
 */
#define SVR_LS1026A		0x870709
#define SVR_LS1026AE		0x870708
#define SVR_LS1046A		0x870701
#define SVR_LS1046AE		0x870700

/* Number of cores in platform */
/* Used by common code for array initialization */
#define NUMBER_OF_CLUSTERS		1
#define CORES_PER_CLUSTER		4
#define PLATFORM_CORE_COUNT		NUMBER_OF_CLUSTERS * CORES_PER_CLUSTER

/*
 * Required LS standard platform porting definitions
 * for CCI-400
 */
#define NXP_CCI_CLUSTER0_SL_IFACE_IX	4


/* Defines required for using XLAT tables from ARM common code */
#define PLAT_PHY_ADDR_SPACE_SIZE	(1ull << 40)
#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ull << 40)

/* Clock Divisors */
#define NXP_PLATFORM_CLK_DIVIDER	1
#define NXP_UART_CLK_DIVIDER		2

/* Start: Macros used by lx2160.S */
/* set to 0 if the clusters are not symmetrical */
#define SYMMETRICAL_CLUSTERS			1
/* End: Macros used by lx2160.S */

 /* set this switch to 1 if you need to keep the debug block
  * clocked during system power-down
  */
#define DEBUG_ACTIVE  0

 /* pwr mgmt features supported in the soc-specific code:
  *   value == 0x0  the soc code does not support this feature
  *   value != 0x0  the soc code supports this feature
  */
#define SOC_CORE_RELEASE       0x1
#define SOC_CORE_RESTART       0x1
#define SOC_CORE_OFF           0x1
#define SOC_CORE_STANDBY       0x1
#define SOC_CORE_PWR_DWN       0x1
#define SOC_CLUSTER_STANDBY    0x1
#define SOC_CLUSTER_PWR_DWN    0x1
#define SOC_SYSTEM_STANDBY     0x1
#define SOC_SYSTEM_PWR_DWN     0x1
#define SOC_SYSTEM_OFF         0x1
#define SOC_SYSTEM_RESET       0x1

/* Start: Macros used by lib/psci files */
#define SYSTEM_PWR_DOMAINS 1
#define PLAT_NUM_PWR_DOMAINS   (PLATFORM_CORE_COUNT + \
				NUMBER_OF_CLUSTERS  + \
				SYSTEM_PWR_DOMAINS)

/* Power state coordination occurs at the system level */
#define PLAT_MAX_PWR_LVL  MPIDR_AFFLVL2

/* define retention state */
#define PLAT_MAX_RET_STATE  (PSCI_LOCAL_STATE_RUN + 1)

/* define power-down state */
#define PLAT_MAX_OFF_STATE  (PLAT_MAX_RET_STATE + 1)
/* End: Macros used by lib/psci files */

/* Some data must be aligned on the biggest cache line size in the platform.
 * This is known only to the platform as it might have a combination of
 * integrated and external caches.
 *
 * CACHE_WRITEBACK_GRANULE is defined in soc.def
 *
 * One cache line needed for bakery locks on ARM platforms
 */

 /* One cache line needed for bakery locks on ARM platforms */
#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)

#ifndef WDOG_RESET_FLAG
#define WDOG_RESET_FLAG DEFAULT_SET_VALUE
#endif

#ifndef WARM_BOOT_SUCCESS
#define WARM_BOOT_SUCCESS DEFAULT_SET_VALUE
#endif

#ifndef __ASSEMBLER__
/* CCI slave interfaces */
static const int cci_map[] = {
	NXP_CCI_CLUSTER0_SL_IFACE_IX,
};

void soc_init_lowlevel(void);
void soc_init_percpu(void);
void _soc_set_start_addr(unsigned long addr);
#endif

#endif /* _SOC_H */
