#
# Copyright (c) 2015, 2016 Freescale Semiconductor, Inc.
# Copyright 2017-2018 NXP Semiconductors
#
# SPDX-License-Identifier: BSD-3-Clause
#
# Author Rod Dorris <rod.dorris@nxp.com>
#	 Ruchika Gupta <ruchika.gupta@nxp.com>
#
#------------------------------------------------------------------------------
#
# This file contains the basic architecture definitions that drive the build
#
# -----------------------------------------------------------------------------

CORE_TYPE=a53

 # set to GIC400 or GIC500
GIC=GIC400

 # set to CCI400 or CCN504
INTERCONNECT=CCI400
ICNNCT_ID := 0x420
$(eval $(call add_define,ICNNCT_ID))

 # ddr controller - set to MMDC or NXP
DDRCNTLR=MMDC

 # Select the DDR PHY generation to be used
 # ddr phy - set to NXP or SNPS or ""
PLAT_DDR_PHY=

 # indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
CHASSIS=2

 # TZC IP Details TZC used is TZC380 or TZC400 or NONE
TZC_ID=NONE

 # CONSOLE Details available is NS16550 or PL011
CONSOLE=NS16550

 # ARM Erratas
ERRATA_A53_855873              :=      1

 # Location of BL2 on OCRAM
 # Required by create_pbl tool.
 # Should match with BL2_BASE in platform_def.h
BL2_BASE		:=	0x10000000

 # Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def
 # Input to CST create_hdr_esbc tool
CSF_HDR_SZ	?= 0x3000
$(eval $(call add_define,CSF_HDR_SZ))

 # Area of OCRAM reserved by ROM code
NXP_ROM_RSVD		:= 0x8000
$(eval $(call add_define,NXP_ROM_RSVD))

 # BL2_HDR_LOC has to be (BL2_BASE + OCRAM_SIZE - NXP_ROM_RSVD - CSF_HDR_SZ)
 # This value should be greater than BL2_TEXT_LIMIT
 # Input to CST create_hdr_isbc tool
BL2_HDR_LOC		?= 0x10015000

# -----------------------------------------------------------------------------
