#
# Copyright (c) 2015, 2016 Freescale Semiconductor, Inc.
# Copyright 2017-2021 NXP Semiconductors
#
# SPDX-License-Identifier: BSD-3-Clause
#
#
#------------------------------------------------------------------------------
#
# This file contains the basic architecture definitions that drive the build
#
# -----------------------------------------------------------------------------

CORE_TYPE		:=	a72

CACHE_LINE		:=	6

# set to GIC400 or GIC500
GIC			:=	GIC500

# set to CCI400 or CCN504 or CCN508
INTERCONNECT		:=	CCN504

# indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
CHASSIS			:=	3

# TZC IP Details TZC used is TZC380 or TZC400
TZC_ID			:=	TZC400

# CONSOLE Details available is NS16550 or PL011
CONSOLE			:=	NS16550

# Select the DDR PHY generation to be used
PLAT_DDR_PHY		:=	PHY_GEN1

PHYS_SYS		:=	64

# Area of OCRAM reserved by ROM code
NXP_ROM_RSVD		:=	0xa000

# Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def
# Input to CST create_hdr_esbc tool
CSF_HDR_SZ		:=	0x3000

NXP_SFP_VER		:=	3_4

# In IMAGE_BL2, compile time flag for handling Cache coherency
# with CAAM for BL2 running from OCRAM
SEC_MEM_NON_COHERENT	:= yes

# Endianness definitions for NXP modules.
#   The default is BE. Specify LE if the module is not. For example,
#   NXP_ESDHC_ENDIANNESS := LE

NXP_ESDHC_ENDIANNESS	:=	LE
NXP_SFP_ENDIANNESS	:=	LE
NXP_GPIO_ENDIANNESS	:=	LE
NXP_SNVS_ENDIANNESS	:=	LE
NXP_GUR_ENDIANNESS	:=	LE
NXP_QSPI_ENDIANNESS	:=	LE
NXP_SEC_ENDIANNESS	:=	LE
NXP_DDR_ENDIANNESS	:=	LE
NXP_IFC_ENDIANNESS	:=	LE

NXP_DDR_INTLV_256B	:=	1

# OCRAM MAP for BL2
# 0x18000000 - 0x18009fff -> Used by ROM code
# 0x1800a000 - 0x1801Cfff -> Reserved for BL2 binary (76 KB)
# 0x1801D000 - 0x1801ffff -> CSF header for BL2 (12 KB)
OCRAM_START_ADDR	:=	0x18000000
OCRAM_SIZE		:=	0x20000

# Location of BL2 on OCRAM
BL2_BASE_ADDR	:=	$(shell echo $$(( $(OCRAM_START_ADDR) + $(NXP_ROM_RSVD))))
# Covert to HEX to be used by create_pbl.mk
BL2_BASE	:=	$(shell echo "0x"$$(echo "obase=16; ${BL2_BASE_ADDR}" | bc))

BL2_HDR_LOC_HDR	?=	$(shell echo $$(( $(OCRAM_START_ADDR) + $(OCRAM_SIZE) - $(CSF_HDR_SZ))))
# Covert to HEX to be used by create_pbl.mk
BL2_HDR_LOC	:=	$(shell echo "0x"$$(echo "obase=16; ${BL2_HDR_LOC_HDR}" | bc))

# SoC ERRATAS to be enabled
#
# Core Errata

# SoC Errata

# DDR Errata
ERRATA_DDR_A008511	:=	1
ERRATA_DDR_A009803	:=	1
ERRATA_DDR_A009942	:=	1
ERRATA_DDR_A010165	:=	1
ERRATA_DDR_A009663	:=	1

# enable dynamic memory mapping
PLAT_XLAT_TABLES_DYNAMIC :=	1

# OCRAM ECC Enabled
OCRAM_ECC_EN            :=      yes
