#
# Copyright (c) 2015, 2016 Freescale Semiconductor, Inc.
# Copyright 2017-2018 NXP Semiconductors
#
# SPDX-License-Identifier: BSD-3-Clause
#
# Author Ruchika Guota <ruchika.gupta@nxp.com>
#
#------------------------------------------------------------------------------
#
# This file contains the basic architecture definitions that drive the build
#
# -----------------------------------------------------------------------------

CORE_TYPE=a53

 # set to GIC400 or GIC500
GIC=GIC500

 # set to CCI400 or CCN504 or CCN508
INTERCONNECT=CCI400

 # indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
CHASSIS=3

 # TZC IP Details TZC used is TZC380 or TZC400
TZC_ID=TZC400

 # CONSOLE Details available is NS16550 or PL011
CONSOLE=NS16550

 # Platform ERRATAS to be enabled
ERRATA_PLAT_A008850         :=      1

 # ARM Erratas
ERRATA_A53_855873              :=      1

 # Select the DDR PHY generation to be used
PLAT_DDR_PHY=phy-gen1

 # Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def
 # Input to CST create_hdr_esbc tool
CSF_HDR_SZ	?= 0x3000
$(eval $(call add_define,CSF_HDR_SZ))

# OCRAM MAP for BL2
# Before BL2
# 0x18000000 - 0x18009fff -> Used by ROM code, (TBD - can it be used for xlat tables)
# 0x1800a000 - 0x1801C000 -> Reserved for BL2 binary (73K)
# 0x1801C000 - 0x1801ffff -> CSF header for BL2 and later used for SD buffer (16K)

# Area of OCRAM reserved by ROM code
NXP_ROM_RSVD		:= 0xa000
$(eval $(call add_define,NXP_ROM_RSVD))

 # BL2_HDR_LOC is at  (BL2_BASE + NXP_ROM_RSVD)
 # This value BL2_HDR_LOC + CSF_HDR_SZ should not
 # overalp with BL2_BASE
 # Input to CST create_hdr_isbc tool
BL2_HDR_LOC		?= 0x1801D000

 # Location of BL2 on OCRAM
 # Required by create_pbl tool.
 # Should match with BL2_BASE in platform_def.h
BL2_BASE		:=	0x1800A000

# -----------------------------------------------------------------------------

