// SPDX-License-Identifier: GPL-2.0+
/*
   Copyright (c) 2015 Broadcom Corporation
   All Rights Reserved

    
*/

#include "ru.h"

#if RU_INCLUDE_FIELD_DB
/******************************************************************************
 * Field: LPORT_INTR_0_CPU_STATUS_RESERVED0
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_STATUS_RESERVED0_FIELD =
{
    "RESERVED0",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    LPORT_INTR_0_CPU_STATUS_RESERVED0_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_STATUS_RESERVED0_FIELD_WIDTH,
    LPORT_INTR_0_CPU_STATUS_RESERVED0_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_STATUS_XLMAC_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_STATUS_XLMAC_INTR_FIELD =
{
    "XLMAC_INTR",
#if RU_INCLUDE_DESC
    "",
    "Interrupt generated by XLMAC signaling various events as described in XLMAC_INTR_STATUS.\n"
    "Bits [7:4] correspond to XLMAC1 and bits [3:0] to XLMAC0.",
#endif
    LPORT_INTR_0_CPU_STATUS_XLMAC_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_STATUS_XLMAC_INTR_FIELD_WIDTH,
    LPORT_INTR_0_CPU_STATUS_XLMAC_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD =
{
    "TX_TIMESYNC_FIFO_ENTRY_VALID_INTR",
#if RU_INCLUDE_DESC
    "",
    "tx_timesync_fifo_entry_valid_intr[7:0].\n"
    "PTP timestamp available for read. Bits [7:4] correspond to XLMAC1 and bits [3:0] to XLMAC0.",
#endif
    LPORT_INTR_0_CPU_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH,
    LPORT_INTR_0_CPU_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_OFF_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD =
{
    "QGPHY_ENERGY_OFF_INTR",
#if RU_INCLUDE_DESC
    "",
    "Active high energy detect interrupt signal (signals presence of the link partner) asserted "
    "when any of PHYs within QGPHY detects loss of energy. Based on QGPHY energy_det_apd.",
#endif
    LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD_WIDTH,
    LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_ON_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_ON_INTR_FIELD =
{
    "QGPHY_ENERGY_ON_INTR",
#if RU_INCLUDE_DESC
    "",
    "Active high energy detect interrupt signal (signals presence of the link partner) asserted "
    "when any of PHYs within QGPHY detects the energy. Based on QGPHY energy_det_apd.",
#endif
    LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_ON_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_ON_INTR_FIELD_WIDTH,
    LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_ON_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_STATUS_MDIO_ERR_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_STATUS_MDIO_ERR_INTR_FIELD =
{
    "MDIO_ERR_INTR",
#if RU_INCLUDE_DESC
    "",
    "MDIO read error. No response to MDIO read.",
#endif
    LPORT_INTR_0_CPU_STATUS_MDIO_ERR_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_STATUS_MDIO_ERR_INTR_FIELD_WIDTH,
    LPORT_INTR_0_CPU_STATUS_MDIO_ERR_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_STATUS_MDIO_DONE_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_STATUS_MDIO_DONE_INTR_FIELD =
{
    "MDIO_DONE_INTR",
#if RU_INCLUDE_DESC
    "",
    "MDIO transaction completed.",
#endif
    LPORT_INTR_0_CPU_STATUS_MDIO_DONE_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_STATUS_MDIO_DONE_INTR_FIELD_WIDTH,
    LPORT_INTR_0_CPU_STATUS_MDIO_DONE_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_STATUS_MIB_REG_ERR_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_STATUS_MIB_REG_ERR_INTR_FIELD =
{
    "MIB_REG_ERR_INTR",
#if RU_INCLUDE_DESC
    "",
    "mib_reg_err_intr[1:0].\n"
    "MIB register transaction error. Bit 1 corresponds to MIB1 and bit 0 to MIB0.",
#endif
    LPORT_INTR_0_CPU_STATUS_MIB_REG_ERR_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_STATUS_MIB_REG_ERR_INTR_FIELD_WIDTH,
    LPORT_INTR_0_CPU_STATUS_MIB_REG_ERR_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_STATUS_MAC_REG_ERR_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_STATUS_MAC_REG_ERR_INTR_FIELD =
{
    "MAC_REG_ERR_INTR",
#if RU_INCLUDE_DESC
    "",
    "mac_reg_err_int[1:0].\n"
    "XLMAC register transaction error. Bit 1 corresponds to XLMAC1 and bit 0 to XLMAC0.",
#endif
    LPORT_INTR_0_CPU_STATUS_MAC_REG_ERR_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_STATUS_MAC_REG_ERR_INTR_FIELD_WIDTH,
    LPORT_INTR_0_CPU_STATUS_MAC_REG_ERR_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_STATUS_UBUS_ERR_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_STATUS_UBUS_ERR_INTR_FIELD =
{
    "UBUS_ERR_INTR",
#if RU_INCLUDE_DESC
    "",
    "UBUS transaction error.",
#endif
    LPORT_INTR_0_CPU_STATUS_UBUS_ERR_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_STATUS_UBUS_ERR_INTR_FIELD_WIDTH,
    LPORT_INTR_0_CPU_STATUS_UBUS_ERR_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_SET_RESERVED0
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_SET_RESERVED0_FIELD =
{
    "RESERVED0",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    LPORT_INTR_0_CPU_SET_RESERVED0_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_SET_RESERVED0_FIELD_WIDTH,
    LPORT_INTR_0_CPU_SET_RESERVED0_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_SET_XLMAC_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_SET_XLMAC_INTR_FIELD =
{
    "XLMAC_INTR",
#if RU_INCLUDE_DESC
    "",
    "Interrupt generated by XLMAC signaling various events as described in XLMAC_INTR_STATUS.\n"
    "Bits [7:4] correspond to XLMAC1 and bits [3:0] to XLMAC0.",
#endif
    LPORT_INTR_0_CPU_SET_XLMAC_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_SET_XLMAC_INTR_FIELD_WIDTH,
    LPORT_INTR_0_CPU_SET_XLMAC_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD =
{
    "TX_TIMESYNC_FIFO_ENTRY_VALID_INTR",
#if RU_INCLUDE_DESC
    "",
    "tx_timesync_fifo_entry_valid_intr[7:0].\n"
    "PTP timestamp available for read. Bits [7:4] correspond to XLMAC1 and bits [3:0] to XLMAC0.",
#endif
    LPORT_INTR_0_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH,
    LPORT_INTR_0_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_OFF_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_OFF_INTR_FIELD =
{
    "QGPHY_ENERGY_OFF_INTR",
#if RU_INCLUDE_DESC
    "",
    "Active high energy detect interrupt signal (signals presence of the link partner) asserted "
    "when any of PHYs within QGPHY detects loss of energy. Based on QGPHY energy_det_apd.",
#endif
    LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_OFF_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_OFF_INTR_FIELD_WIDTH,
    LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_OFF_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_ON_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_ON_INTR_FIELD =
{
    "QGPHY_ENERGY_ON_INTR",
#if RU_INCLUDE_DESC
    "",
    "Active high energy detect interrupt signal (signals presence of the link partner) asserted "
    "when any of PHYs within QGPHY detects the energy. Based on QGPHY energy_det_apd.",
#endif
    LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_ON_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_ON_INTR_FIELD_WIDTH,
    LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_ON_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_SET_MDIO_ERR_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_SET_MDIO_ERR_INTR_FIELD =
{
    "MDIO_ERR_INTR",
#if RU_INCLUDE_DESC
    "",
    "MDIO read error. No response to MDIO read.",
#endif
    LPORT_INTR_0_CPU_SET_MDIO_ERR_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_SET_MDIO_ERR_INTR_FIELD_WIDTH,
    LPORT_INTR_0_CPU_SET_MDIO_ERR_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_SET_MDIO_DONE_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_SET_MDIO_DONE_INTR_FIELD =
{
    "MDIO_DONE_INTR",
#if RU_INCLUDE_DESC
    "",
    "MDIO transaction completed.",
#endif
    LPORT_INTR_0_CPU_SET_MDIO_DONE_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_SET_MDIO_DONE_INTR_FIELD_WIDTH,
    LPORT_INTR_0_CPU_SET_MDIO_DONE_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_SET_MIB_REG_ERR_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_SET_MIB_REG_ERR_INTR_FIELD =
{
    "MIB_REG_ERR_INTR",
#if RU_INCLUDE_DESC
    "",
    "mib_reg_err_intr[1:0].\n"
    "MIB register transaction error. Bit 1 corresponds to MIB1 and bit 0 to MIB0.",
#endif
    LPORT_INTR_0_CPU_SET_MIB_REG_ERR_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_SET_MIB_REG_ERR_INTR_FIELD_WIDTH,
    LPORT_INTR_0_CPU_SET_MIB_REG_ERR_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_SET_MAC_REG_ERR_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_SET_MAC_REG_ERR_INTR_FIELD =
{
    "MAC_REG_ERR_INTR",
#if RU_INCLUDE_DESC
    "",
    "mac_reg_err_int[1:0].\n"
    "XLMAC register transaction error. Bit 1 corresponds to XLMAC1 and bit 0 to XLMAC0.",
#endif
    LPORT_INTR_0_CPU_SET_MAC_REG_ERR_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_SET_MAC_REG_ERR_INTR_FIELD_WIDTH,
    LPORT_INTR_0_CPU_SET_MAC_REG_ERR_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_SET_UBUS_ERR_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_SET_UBUS_ERR_INTR_FIELD =
{
    "UBUS_ERR_INTR",
#if RU_INCLUDE_DESC
    "",
    "UBUS transaction error.",
#endif
    LPORT_INTR_0_CPU_SET_UBUS_ERR_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_SET_UBUS_ERR_INTR_FIELD_WIDTH,
    LPORT_INTR_0_CPU_SET_UBUS_ERR_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_CLEAR_RESERVED0
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_CLEAR_RESERVED0_FIELD =
{
    "RESERVED0",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    LPORT_INTR_0_CPU_CLEAR_RESERVED0_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_CLEAR_RESERVED0_FIELD_WIDTH,
    LPORT_INTR_0_CPU_CLEAR_RESERVED0_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_CLEAR_XLMAC_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_CLEAR_XLMAC_INTR_FIELD =
{
    "XLMAC_INTR",
#if RU_INCLUDE_DESC
    "",
    "Interrupt generated by XLMAC signaling various events as described in XLMAC_INTR_STATUS.\n"
    "Bits [7:4] correspond to XLMAC1 and bits [3:0] to XLMAC0.",
#endif
    LPORT_INTR_0_CPU_CLEAR_XLMAC_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_CLEAR_XLMAC_INTR_FIELD_WIDTH,
    LPORT_INTR_0_CPU_CLEAR_XLMAC_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD =
{
    "TX_TIMESYNC_FIFO_ENTRY_VALID_INTR",
#if RU_INCLUDE_DESC
    "",
    "tx_timesync_fifo_entry_valid_intr[7:0].\n"
    "PTP timestamp available for read. Bits [7:4] correspond to XLMAC1 and bits [3:0] to XLMAC0.",
#endif
    LPORT_INTR_0_CPU_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH,
    LPORT_INTR_0_CPU_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_OFF_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD =
{
    "QGPHY_ENERGY_OFF_INTR",
#if RU_INCLUDE_DESC
    "",
    "Active high energy detect interrupt signal (signals presence of the link partner) asserted "
    "when any of PHYs within QGPHY detects loss of energy. Based on QGPHY energy_det_apd.",
#endif
    LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD_WIDTH,
    LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_ON_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD =
{
    "QGPHY_ENERGY_ON_INTR",
#if RU_INCLUDE_DESC
    "",
    "Active high energy detect interrupt signal (signals presence of the link partner) asserted "
    "when any of PHYs within QGPHY detects the energy. Based on QGPHY energy_det_apd.",
#endif
    LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD_WIDTH,
    LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_CLEAR_MDIO_ERR_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_CLEAR_MDIO_ERR_INTR_FIELD =
{
    "MDIO_ERR_INTR",
#if RU_INCLUDE_DESC
    "",
    "MDIO read error. No response to MDIO read.",
#endif
    LPORT_INTR_0_CPU_CLEAR_MDIO_ERR_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_CLEAR_MDIO_ERR_INTR_FIELD_WIDTH,
    LPORT_INTR_0_CPU_CLEAR_MDIO_ERR_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_CLEAR_MDIO_DONE_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_CLEAR_MDIO_DONE_INTR_FIELD =
{
    "MDIO_DONE_INTR",
#if RU_INCLUDE_DESC
    "",
    "MDIO transaction completed.",
#endif
    LPORT_INTR_0_CPU_CLEAR_MDIO_DONE_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_CLEAR_MDIO_DONE_INTR_FIELD_WIDTH,
    LPORT_INTR_0_CPU_CLEAR_MDIO_DONE_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_CLEAR_MIB_REG_ERR_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_CLEAR_MIB_REG_ERR_INTR_FIELD =
{
    "MIB_REG_ERR_INTR",
#if RU_INCLUDE_DESC
    "",
    "mib_reg_err_intr[1:0].\n"
    "MIB register transaction error. Bit 1 corresponds to MIB1 and bit 0 to MIB0.",
#endif
    LPORT_INTR_0_CPU_CLEAR_MIB_REG_ERR_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_CLEAR_MIB_REG_ERR_INTR_FIELD_WIDTH,
    LPORT_INTR_0_CPU_CLEAR_MIB_REG_ERR_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_CLEAR_MAC_REG_ERR_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_CLEAR_MAC_REG_ERR_INTR_FIELD =
{
    "MAC_REG_ERR_INTR",
#if RU_INCLUDE_DESC
    "",
    "mac_reg_err_int[1:0].\n"
    "XLMAC register transaction error. Bit 1 corresponds to XLMAC1 and bit 0 to XLMAC0.",
#endif
    LPORT_INTR_0_CPU_CLEAR_MAC_REG_ERR_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_CLEAR_MAC_REG_ERR_INTR_FIELD_WIDTH,
    LPORT_INTR_0_CPU_CLEAR_MAC_REG_ERR_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_CLEAR_UBUS_ERR_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_CLEAR_UBUS_ERR_INTR_FIELD =
{
    "UBUS_ERR_INTR",
#if RU_INCLUDE_DESC
    "",
    "UBUS transaction error.",
#endif
    LPORT_INTR_0_CPU_CLEAR_UBUS_ERR_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_CLEAR_UBUS_ERR_INTR_FIELD_WIDTH,
    LPORT_INTR_0_CPU_CLEAR_UBUS_ERR_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_STATUS_RESERVED0
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_RESERVED0_FIELD =
{
    "RESERVED0",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    LPORT_INTR_0_CPU_MASK_STATUS_RESERVED0_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_STATUS_RESERVED0_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_STATUS_RESERVED0_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD =
{
    "MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mac rx cdc single bit error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD =
{
    "MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mac rx cdc double bit error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD =
{
    "MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mac tx cdc single bit error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD =
{
    "MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for  mac tx cdc double bit error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD =
{
    "TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for  tx timesync fifo entry valid interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD =
{
    "QGPHY_ENERGY_OFF_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for qgphy energy off interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD =
{
    "QGPHY_ENERGY_ON_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for qgphy energy on interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_STATUS_MDIO_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD =
{
    "MDIO_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mdio error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_STATUS_MDIO_DONE_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD =
{
    "MDIO_DONE_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mdio done interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_STATUS_MIB_REG_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD =
{
    "MIB_REG_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mib register error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_STATUS_MAC_REG_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD =
{
    "MAC_REG_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mac register error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_STATUS_UBUS_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD =
{
    "UBUS_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for ubus error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_SET_RESERVED0
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_RESERVED0_FIELD =
{
    "RESERVED0",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    LPORT_INTR_0_CPU_MASK_SET_RESERVED0_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_SET_RESERVED0_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_SET_RESERVED0_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD =
{
    "MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mac rx cdc single bit error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD =
{
    "MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mac rx cdc double bit error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD =
{
    "MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mac tx cdc single bit error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD =
{
    "MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for  mac tx cdc double bit error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD =
{
    "TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for  tx timesync fifo entry valid interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD =
{
    "QGPHY_ENERGY_OFF_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for qgphy energy off interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD =
{
    "QGPHY_ENERGY_ON_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for qgphy energy on interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_SET_MDIO_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MDIO_ERR_INTR_MASK_FIELD =
{
    "MDIO_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mdio error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_SET_MDIO_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_SET_MDIO_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_SET_MDIO_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_SET_MDIO_DONE_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MDIO_DONE_INTR_MASK_FIELD =
{
    "MDIO_DONE_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mdio done interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_SET_MDIO_DONE_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_SET_MDIO_DONE_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_SET_MDIO_DONE_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_SET_MIB_REG_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD =
{
    "MIB_REG_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mib register error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_SET_MAC_REG_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD =
{
    "MAC_REG_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mac register error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_SET_UBUS_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_UBUS_ERR_INTR_MASK_FIELD =
{
    "UBUS_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for ubus error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_CLEAR_RESERVED0
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_RESERVED0_FIELD =
{
    "RESERVED0",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    LPORT_INTR_0_CPU_MASK_CLEAR_RESERVED0_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_CLEAR_RESERVED0_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_CLEAR_RESERVED0_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD =
{
    "MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mac rx cdc single bit error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD =
{
    "MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mac rx cdc double bit error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD =
{
    "MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mac tx cdc single bit error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD =
{
    "MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for  mac tx cdc double bit error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD =
{
    "TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for  tx timesync fifo entry valid interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD =
{
    "QGPHY_ENERGY_OFF_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for qgphy energy off interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD =
{
    "QGPHY_ENERGY_ON_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for qgphy energy on interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD =
{
    "MDIO_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mdio error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_DONE_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD =
{
    "MDIO_DONE_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mdio done interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_CLEAR_MIB_REG_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD =
{
    "MIB_REG_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mib register error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_CLEAR_MAC_REG_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD =
{
    "MAC_REG_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mac register error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_CPU_MASK_CLEAR_UBUS_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD =
{
    "UBUS_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for ubus error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_CPU_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_CPU_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_CPU_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_STATUS_RESERVED0
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_STATUS_RESERVED0_FIELD =
{
    "RESERVED0",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    LPORT_INTR_0_PCI_STATUS_RESERVED0_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_STATUS_RESERVED0_FIELD_WIDTH,
    LPORT_INTR_0_PCI_STATUS_RESERVED0_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_STATUS_XLMAC_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_STATUS_XLMAC_INTR_FIELD =
{
    "XLMAC_INTR",
#if RU_INCLUDE_DESC
    "",
    "Interrupt generated by XLMAC signaling various events as described in XLMAC_INTR_STATUS.\n"
    "Bits [7:4] correspond to XLMAC1 and bits [3:0] to XLMAC0.",
#endif
    LPORT_INTR_0_PCI_STATUS_XLMAC_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_STATUS_XLMAC_INTR_FIELD_WIDTH,
    LPORT_INTR_0_PCI_STATUS_XLMAC_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD =
{
    "TX_TIMESYNC_FIFO_ENTRY_VALID_INTR",
#if RU_INCLUDE_DESC
    "",
    "tx_timesync_fifo_entry_valid_intr[7:0].\n"
    "PTP timestamp available for read. Bits [7:4] correspond to XLMAC1 and bits [3:0] to XLMAC0.",
#endif
    LPORT_INTR_0_PCI_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH,
    LPORT_INTR_0_PCI_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_OFF_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD =
{
    "QGPHY_ENERGY_OFF_INTR",
#if RU_INCLUDE_DESC
    "",
    "Active high energy detect interrupt signal (signals presence of the link partner) asserted "
    "when any of PHYs within QGPHY detects loss of energy. Based on QGPHY energy_det_apd.",
#endif
    LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD_WIDTH,
    LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_ON_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_ON_INTR_FIELD =
{
    "QGPHY_ENERGY_ON_INTR",
#if RU_INCLUDE_DESC
    "",
    "Active high energy detect interrupt signal (signals presence of the link partner) asserted "
    "when any of PHYs within QGPHY detects the energy. Based on QGPHY energy_det_apd.",
#endif
    LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_ON_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_ON_INTR_FIELD_WIDTH,
    LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_ON_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_STATUS_MDIO_ERR_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_STATUS_MDIO_ERR_INTR_FIELD =
{
    "MDIO_ERR_INTR",
#if RU_INCLUDE_DESC
    "",
    "MDIO read error. No response to MDIO read.",
#endif
    LPORT_INTR_0_PCI_STATUS_MDIO_ERR_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_STATUS_MDIO_ERR_INTR_FIELD_WIDTH,
    LPORT_INTR_0_PCI_STATUS_MDIO_ERR_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_STATUS_MDIO_DONE_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_STATUS_MDIO_DONE_INTR_FIELD =
{
    "MDIO_DONE_INTR",
#if RU_INCLUDE_DESC
    "",
    "MDIO transaction completed.",
#endif
    LPORT_INTR_0_PCI_STATUS_MDIO_DONE_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_STATUS_MDIO_DONE_INTR_FIELD_WIDTH,
    LPORT_INTR_0_PCI_STATUS_MDIO_DONE_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_STATUS_MIB_REG_ERR_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_STATUS_MIB_REG_ERR_INTR_FIELD =
{
    "MIB_REG_ERR_INTR",
#if RU_INCLUDE_DESC
    "",
    "mib_reg_err_intr[1:0].\n"
    "MIB register transaction error. Bit 1 corresponds to MIB1 and bit 0 to MIB0.",
#endif
    LPORT_INTR_0_PCI_STATUS_MIB_REG_ERR_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_STATUS_MIB_REG_ERR_INTR_FIELD_WIDTH,
    LPORT_INTR_0_PCI_STATUS_MIB_REG_ERR_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_STATUS_MAC_REG_ERR_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_STATUS_MAC_REG_ERR_INTR_FIELD =
{
    "MAC_REG_ERR_INTR",
#if RU_INCLUDE_DESC
    "",
    "mac_reg_err_int[1:0].\n"
    "XLMAC register transaction error. Bit 1 corresponds to XLMAC1 and bit 0 to XLMAC0.",
#endif
    LPORT_INTR_0_PCI_STATUS_MAC_REG_ERR_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_STATUS_MAC_REG_ERR_INTR_FIELD_WIDTH,
    LPORT_INTR_0_PCI_STATUS_MAC_REG_ERR_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_STATUS_UBUS_ERR_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_STATUS_UBUS_ERR_INTR_FIELD =
{
    "UBUS_ERR_INTR",
#if RU_INCLUDE_DESC
    "",
    "UBUS transaction error.",
#endif
    LPORT_INTR_0_PCI_STATUS_UBUS_ERR_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_STATUS_UBUS_ERR_INTR_FIELD_WIDTH,
    LPORT_INTR_0_PCI_STATUS_UBUS_ERR_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_SET_RESERVED0
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_SET_RESERVED0_FIELD =
{
    "RESERVED0",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    LPORT_INTR_0_PCI_SET_RESERVED0_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_SET_RESERVED0_FIELD_WIDTH,
    LPORT_INTR_0_PCI_SET_RESERVED0_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_SET_XLMAC_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_SET_XLMAC_INTR_FIELD =
{
    "XLMAC_INTR",
#if RU_INCLUDE_DESC
    "",
    "Interrupt generated by XLMAC signaling various events as described in XLMAC_INTR_STATUS.\n"
    "Bits [7:4] correspond to XLMAC1 and bits [3:0] to XLMAC0.",
#endif
    LPORT_INTR_0_PCI_SET_XLMAC_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_SET_XLMAC_INTR_FIELD_WIDTH,
    LPORT_INTR_0_PCI_SET_XLMAC_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD =
{
    "TX_TIMESYNC_FIFO_ENTRY_VALID_INTR",
#if RU_INCLUDE_DESC
    "",
    "tx_timesync_fifo_entry_valid_intr[7:0].\n"
    "PTP timestamp available for read. Bits [7:4] correspond to XLMAC1 and bits [3:0] to XLMAC0.",
#endif
    LPORT_INTR_0_PCI_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH,
    LPORT_INTR_0_PCI_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_OFF_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_OFF_INTR_FIELD =
{
    "QGPHY_ENERGY_OFF_INTR",
#if RU_INCLUDE_DESC
    "",
    "Active high energy detect interrupt signal (signals presence of the link partner) asserted "
    "when any of PHYs within QGPHY detects loss of energy. Based on QGPHY energy_det_apd.",
#endif
    LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_OFF_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_OFF_INTR_FIELD_WIDTH,
    LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_OFF_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_ON_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_ON_INTR_FIELD =
{
    "QGPHY_ENERGY_ON_INTR",
#if RU_INCLUDE_DESC
    "",
    "Active high energy detect interrupt signal (signals presence of the link partner) asserted "
    "when any of PHYs within QGPHY detects the energy. Based on QGPHY energy_det_apd.",
#endif
    LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_ON_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_ON_INTR_FIELD_WIDTH,
    LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_ON_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_SET_MDIO_ERR_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_SET_MDIO_ERR_INTR_FIELD =
{
    "MDIO_ERR_INTR",
#if RU_INCLUDE_DESC
    "",
    "MDIO read error. No response to MDIO read.",
#endif
    LPORT_INTR_0_PCI_SET_MDIO_ERR_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_SET_MDIO_ERR_INTR_FIELD_WIDTH,
    LPORT_INTR_0_PCI_SET_MDIO_ERR_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_SET_MDIO_DONE_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_SET_MDIO_DONE_INTR_FIELD =
{
    "MDIO_DONE_INTR",
#if RU_INCLUDE_DESC
    "",
    "MDIO transaction completed.",
#endif
    LPORT_INTR_0_PCI_SET_MDIO_DONE_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_SET_MDIO_DONE_INTR_FIELD_WIDTH,
    LPORT_INTR_0_PCI_SET_MDIO_DONE_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_SET_MIB_REG_ERR_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_SET_MIB_REG_ERR_INTR_FIELD =
{
    "MIB_REG_ERR_INTR",
#if RU_INCLUDE_DESC
    "",
    "mib_reg_err_intr[1:0].\n"
    "MIB register transaction error. Bit 1 corresponds to MIB1 and bit 0 to MIB0.",
#endif
    LPORT_INTR_0_PCI_SET_MIB_REG_ERR_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_SET_MIB_REG_ERR_INTR_FIELD_WIDTH,
    LPORT_INTR_0_PCI_SET_MIB_REG_ERR_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_SET_MAC_REG_ERR_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_SET_MAC_REG_ERR_INTR_FIELD =
{
    "MAC_REG_ERR_INTR",
#if RU_INCLUDE_DESC
    "",
    "mac_reg_err_int[1:0].\n"
    "XLMAC register transaction error. Bit 1 corresponds to XLMAC1 and bit 0 to XLMAC0.",
#endif
    LPORT_INTR_0_PCI_SET_MAC_REG_ERR_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_SET_MAC_REG_ERR_INTR_FIELD_WIDTH,
    LPORT_INTR_0_PCI_SET_MAC_REG_ERR_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_SET_UBUS_ERR_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_SET_UBUS_ERR_INTR_FIELD =
{
    "UBUS_ERR_INTR",
#if RU_INCLUDE_DESC
    "",
    "UBUS transaction error.",
#endif
    LPORT_INTR_0_PCI_SET_UBUS_ERR_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_SET_UBUS_ERR_INTR_FIELD_WIDTH,
    LPORT_INTR_0_PCI_SET_UBUS_ERR_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_CLEAR_RESERVED0
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_CLEAR_RESERVED0_FIELD =
{
    "RESERVED0",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    LPORT_INTR_0_PCI_CLEAR_RESERVED0_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_CLEAR_RESERVED0_FIELD_WIDTH,
    LPORT_INTR_0_PCI_CLEAR_RESERVED0_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_CLEAR_XLMAC_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_CLEAR_XLMAC_INTR_FIELD =
{
    "XLMAC_INTR",
#if RU_INCLUDE_DESC
    "",
    "Interrupt generated by XLMAC signaling various events as described in XLMAC_INTR_STATUS.\n"
    "Bits [7:4] correspond to XLMAC1 and bits [3:0] to XLMAC0.",
#endif
    LPORT_INTR_0_PCI_CLEAR_XLMAC_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_CLEAR_XLMAC_INTR_FIELD_WIDTH,
    LPORT_INTR_0_PCI_CLEAR_XLMAC_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD =
{
    "TX_TIMESYNC_FIFO_ENTRY_VALID_INTR",
#if RU_INCLUDE_DESC
    "",
    "tx_timesync_fifo_entry_valid_intr[7:0].\n"
    "PTP timestamp available for read. Bits [7:4] correspond to XLMAC1 and bits [3:0] to XLMAC0.",
#endif
    LPORT_INTR_0_PCI_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH,
    LPORT_INTR_0_PCI_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_OFF_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD =
{
    "QGPHY_ENERGY_OFF_INTR",
#if RU_INCLUDE_DESC
    "",
    "Active high energy detect interrupt signal (signals presence of the link partner) asserted "
    "when any of PHYs within QGPHY detects loss of energy. Based on QGPHY energy_det_apd.",
#endif
    LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD_WIDTH,
    LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_ON_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD =
{
    "QGPHY_ENERGY_ON_INTR",
#if RU_INCLUDE_DESC
    "",
    "Active high energy detect interrupt signal (signals presence of the link partner) asserted "
    "when any of PHYs within QGPHY detects the energy. Based on QGPHY energy_det_apd.",
#endif
    LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD_WIDTH,
    LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_CLEAR_MDIO_ERR_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_CLEAR_MDIO_ERR_INTR_FIELD =
{
    "MDIO_ERR_INTR",
#if RU_INCLUDE_DESC
    "",
    "MDIO read error. No response to MDIO read.",
#endif
    LPORT_INTR_0_PCI_CLEAR_MDIO_ERR_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_CLEAR_MDIO_ERR_INTR_FIELD_WIDTH,
    LPORT_INTR_0_PCI_CLEAR_MDIO_ERR_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_CLEAR_MDIO_DONE_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_CLEAR_MDIO_DONE_INTR_FIELD =
{
    "MDIO_DONE_INTR",
#if RU_INCLUDE_DESC
    "",
    "MDIO transaction completed.",
#endif
    LPORT_INTR_0_PCI_CLEAR_MDIO_DONE_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_CLEAR_MDIO_DONE_INTR_FIELD_WIDTH,
    LPORT_INTR_0_PCI_CLEAR_MDIO_DONE_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_CLEAR_MIB_REG_ERR_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_CLEAR_MIB_REG_ERR_INTR_FIELD =
{
    "MIB_REG_ERR_INTR",
#if RU_INCLUDE_DESC
    "",
    "mib_reg_err_intr[1:0].\n"
    "MIB register transaction error. Bit 1 corresponds to MIB1 and bit 0 to MIB0.",
#endif
    LPORT_INTR_0_PCI_CLEAR_MIB_REG_ERR_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_CLEAR_MIB_REG_ERR_INTR_FIELD_WIDTH,
    LPORT_INTR_0_PCI_CLEAR_MIB_REG_ERR_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_CLEAR_MAC_REG_ERR_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_CLEAR_MAC_REG_ERR_INTR_FIELD =
{
    "MAC_REG_ERR_INTR",
#if RU_INCLUDE_DESC
    "",
    "mac_reg_err_int[1:0].\n"
    "XLMAC register transaction error. Bit 1 corresponds to XLMAC1 and bit 0 to XLMAC0.",
#endif
    LPORT_INTR_0_PCI_CLEAR_MAC_REG_ERR_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_CLEAR_MAC_REG_ERR_INTR_FIELD_WIDTH,
    LPORT_INTR_0_PCI_CLEAR_MAC_REG_ERR_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_CLEAR_UBUS_ERR_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_CLEAR_UBUS_ERR_INTR_FIELD =
{
    "UBUS_ERR_INTR",
#if RU_INCLUDE_DESC
    "",
    "UBUS transaction error.",
#endif
    LPORT_INTR_0_PCI_CLEAR_UBUS_ERR_INTR_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_CLEAR_UBUS_ERR_INTR_FIELD_WIDTH,
    LPORT_INTR_0_PCI_CLEAR_UBUS_ERR_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_STATUS_RESERVED0
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_RESERVED0_FIELD =
{
    "RESERVED0",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    LPORT_INTR_0_PCI_MASK_STATUS_RESERVED0_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_STATUS_RESERVED0_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_STATUS_RESERVED0_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD =
{
    "MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mac rx cdc single bit error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD =
{
    "MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mac rx cdc double bit error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD =
{
    "MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mac tx cdc single bit error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD =
{
    "MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for  mac tx cdc double bit error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD =
{
    "TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for  tx timesync fifo entry valid interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD =
{
    "QGPHY_ENERGY_OFF_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for qgphy energy off interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD =
{
    "QGPHY_ENERGY_ON_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for qgphy energy on interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_STATUS_MDIO_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD =
{
    "MDIO_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mdio error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_STATUS_MDIO_DONE_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD =
{
    "MDIO_DONE_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mdio done interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_STATUS_MIB_REG_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD =
{
    "MIB_REG_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mib register error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_STATUS_MAC_REG_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD =
{
    "MAC_REG_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mac register error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_STATUS_UBUS_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD =
{
    "UBUS_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for ubus error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_SET_RESERVED0
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_RESERVED0_FIELD =
{
    "RESERVED0",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    LPORT_INTR_0_PCI_MASK_SET_RESERVED0_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_SET_RESERVED0_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_SET_RESERVED0_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD =
{
    "MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mac rx cdc single bit error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD =
{
    "MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mac rx cdc double bit error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD =
{
    "MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mac tx cdc single bit error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD =
{
    "MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for  mac tx cdc double bit error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD =
{
    "TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for  tx timesync fifo entry valid interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD =
{
    "QGPHY_ENERGY_OFF_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for qgphy energy off interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD =
{
    "QGPHY_ENERGY_ON_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for qgphy energy on interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_SET_MDIO_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MDIO_ERR_INTR_MASK_FIELD =
{
    "MDIO_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mdio error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_SET_MDIO_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_SET_MDIO_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_SET_MDIO_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_SET_MDIO_DONE_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MDIO_DONE_INTR_MASK_FIELD =
{
    "MDIO_DONE_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mdio done interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_SET_MDIO_DONE_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_SET_MDIO_DONE_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_SET_MDIO_DONE_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_SET_MIB_REG_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD =
{
    "MIB_REG_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mib register error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_SET_MAC_REG_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD =
{
    "MAC_REG_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mac register error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_SET_UBUS_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_UBUS_ERR_INTR_MASK_FIELD =
{
    "UBUS_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for ubus error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_CLEAR_RESERVED0
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_RESERVED0_FIELD =
{
    "RESERVED0",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    LPORT_INTR_0_PCI_MASK_CLEAR_RESERVED0_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_CLEAR_RESERVED0_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_CLEAR_RESERVED0_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD =
{
    "MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mac rx cdc single bit error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD =
{
    "MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mac rx cdc double bit error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD =
{
    "MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mac tx cdc single bit error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD =
{
    "MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for  mac tx cdc double bit error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD =
{
    "TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for  tx timesync fifo entry valid interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD =
{
    "QGPHY_ENERGY_OFF_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for qgphy energy off interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD =
{
    "QGPHY_ENERGY_ON_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for qgphy energy on interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD =
{
    "MDIO_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mdio error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_DONE_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD =
{
    "MDIO_DONE_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mdio done interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_CLEAR_MIB_REG_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD =
{
    "MIB_REG_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mib register error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_CLEAR_MAC_REG_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD =
{
    "MAC_REG_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for mac register error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_0_PCI_MASK_CLEAR_UBUS_ERR_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD =
{
    "UBUS_ERR_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for ubus error interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_0_PCI_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_0_PCI_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_0_PCI_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_STATUS_RESERVED0
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_STATUS_RESERVED0_FIELD =
{
    "RESERVED0",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    LPORT_INTR_1_CPU_STATUS_RESERVED0_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_STATUS_RESERVED0_FIELD_WIDTH,
    LPORT_INTR_1_CPU_STATUS_RESERVED0_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_STATUS_MAB_STATUS_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_STATUS_MAB_STATUS_INTR_FIELD =
{
    "MAB_STATUS_INTR",
#if RU_INCLUDE_DESC
    "",
    "Asserted when any of statuses get set in MSBUS Adaptation Block Status Register(s).\n"
    "Index 1 corresponds to MSBUS Adaptation Block 1 (i.e. XLMAC1) and index 0 to MSBUS Adaptation Block 0 (i.e. XLMAC0).",
#endif
    LPORT_INTR_1_CPU_STATUS_MAB_STATUS_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_STATUS_MAB_STATUS_INTR_FIELD_WIDTH,
    LPORT_INTR_1_CPU_STATUS_MAB_STATUS_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_STATUS_RX_REMOTE_FAULT_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_STATUS_RX_REMOTE_FAULT_INTR_FIELD =
{
    "RX_REMOTE_FAULT_INTR",
#if RU_INCLUDE_DESC
    "",
    "RX Remote Fault Interrupt for P4 and P0.",
#endif
    LPORT_INTR_1_CPU_STATUS_RX_REMOTE_FAULT_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_STATUS_RX_REMOTE_FAULT_INTR_FIELD_WIDTH,
    LPORT_INTR_1_CPU_STATUS_RX_REMOTE_FAULT_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_STATUS_DSERDES_SD_OFF_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_STATUS_DSERDES_SD_OFF_INTR_FIELD =
{
    "DSERDES_SD_OFF_INTR",
#if RU_INCLUDE_DESC
    "",
    "Inverted sd_on interrupt. Interrupt to serdes lane mapping is same as for dserdes_sd_on_intr[3:0]. "
    "Based on filtered signal detect.",
#endif
    LPORT_INTR_1_CPU_STATUS_DSERDES_SD_OFF_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_STATUS_DSERDES_SD_OFF_INTR_FIELD_WIDTH,
    LPORT_INTR_1_CPU_STATUS_DSERDES_SD_OFF_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_STATUS_DSERDES_SD_ON_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_STATUS_DSERDES_SD_ON_INTR_FIELD =
{
    "DSERDES_SD_ON_INTR",
#if RU_INCLUDE_DESC
    "",
    "Active high signal detect interrupt (signals presence of the link partner).\n"
    "dserdes_sd_on_intr[3] corresponds to MERLIN 1, lane 1.\n"
    "dserdes_sd_on_intr[2] corresponds to MERLIN 1, lane 0.\n"
    "dserdes_sd_on_intr[1] corresponds to MERLIN 0, lane 1.\n"
    "dserdes_sd_on_intr[0] corresponds to MERLIN 0, lane 0.\n"
    "Based on filtered signal detect.",
#endif
    LPORT_INTR_1_CPU_STATUS_DSERDES_SD_ON_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_STATUS_DSERDES_SD_ON_INTR_FIELD_WIDTH,
    LPORT_INTR_1_CPU_STATUS_DSERDES_SD_ON_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD =
{
    "LINK_DOWN_INTR",
#if RU_INCLUDE_DESC
    "",
    "Link down interrupt for P7:P0. Interrupt corresponds to the attached PHY/interface link down event.",
#endif
    LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD_WIDTH,
    LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD =
{
    "LINK_UP_INTR",
#if RU_INCLUDE_DESC
    "",
    "Link up interrupt for P7:P0. Interrupt corresponds to the attached PHY/interface link up event.",
#endif
    LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD_WIDTH,
    LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_SET_RESERVED0
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_SET_RESERVED0_FIELD =
{
    "RESERVED0",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    LPORT_INTR_1_CPU_SET_RESERVED0_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_SET_RESERVED0_FIELD_WIDTH,
    LPORT_INTR_1_CPU_SET_RESERVED0_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_SET_MAB_STATUS_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_SET_MAB_STATUS_INTR_FIELD =
{
    "MAB_STATUS_INTR",
#if RU_INCLUDE_DESC
    "",
    "Asserted when any of statuses get set in MSBUS Adaptation Block Status Register(s).\n"
    "Index 1 corresponds to MSBUS Adaptation Block 1 (i.e. XLMAC1) and index 0 to MSBUS Adaptation Block 0 (i.e. XLMAC0).",
#endif
    LPORT_INTR_1_CPU_SET_MAB_STATUS_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_SET_MAB_STATUS_INTR_FIELD_WIDTH,
    LPORT_INTR_1_CPU_SET_MAB_STATUS_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_SET_RX_REMOTE_FAULT_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_SET_RX_REMOTE_FAULT_INTR_FIELD =
{
    "RX_REMOTE_FAULT_INTR",
#if RU_INCLUDE_DESC
    "",
    "RX Remote Fault Interrupt for P4 and P0.",
#endif
    LPORT_INTR_1_CPU_SET_RX_REMOTE_FAULT_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_SET_RX_REMOTE_FAULT_INTR_FIELD_WIDTH,
    LPORT_INTR_1_CPU_SET_RX_REMOTE_FAULT_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_SET_DSERDES_SD_OFF_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_SET_DSERDES_SD_OFF_INTR_FIELD =
{
    "DSERDES_SD_OFF_INTR",
#if RU_INCLUDE_DESC
    "",
    "Inverted sd_on interrupt. Interrupt to serdes lane mapping is same as for dserdes_sd_on_intr[3:0]. "
    "Based on filtered signal detect.",
#endif
    LPORT_INTR_1_CPU_SET_DSERDES_SD_OFF_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_SET_DSERDES_SD_OFF_INTR_FIELD_WIDTH,
    LPORT_INTR_1_CPU_SET_DSERDES_SD_OFF_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_SET_DSERDES_SD_ON_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_SET_DSERDES_SD_ON_INTR_FIELD =
{
    "DSERDES_SD_ON_INTR",
#if RU_INCLUDE_DESC
    "",
    "Active high signal detect interrupt (signals presence of the link partner).\n"
    "dserdes_sd_on_intr[3] corresponds to MERLIN 1, lane 1.\n"
    "dserdes_sd_on_intr[2] corresponds to MERLIN 1, lane 0.\n"
    "dserdes_sd_on_intr[1] corresponds to MERLIN 0, lane 1.\n"
    "dserdes_sd_on_intr[0] corresponds to MERLIN 0, lane 0.\n"
    "Based on filtered signal detect.",
#endif
    LPORT_INTR_1_CPU_SET_DSERDES_SD_ON_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_SET_DSERDES_SD_ON_INTR_FIELD_WIDTH,
    LPORT_INTR_1_CPU_SET_DSERDES_SD_ON_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_SET_LINK_DOWN_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_SET_LINK_DOWN_INTR_FIELD =
{
    "LINK_DOWN_INTR",
#if RU_INCLUDE_DESC
    "",
    "Link down interrupt for P7:P0. Interrupt corresponds to the attached PHY/interface link down event.",
#endif
    LPORT_INTR_1_CPU_SET_LINK_DOWN_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_SET_LINK_DOWN_INTR_FIELD_WIDTH,
    LPORT_INTR_1_CPU_SET_LINK_DOWN_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_SET_LINK_UP_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_SET_LINK_UP_INTR_FIELD =
{
    "LINK_UP_INTR",
#if RU_INCLUDE_DESC
    "",
    "Link up interrupt for P7:P0. Interrupt corresponds to the attached PHY/interface link up event.",
#endif
    LPORT_INTR_1_CPU_SET_LINK_UP_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_SET_LINK_UP_INTR_FIELD_WIDTH,
    LPORT_INTR_1_CPU_SET_LINK_UP_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_CLEAR_RESERVED0
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_CLEAR_RESERVED0_FIELD =
{
    "RESERVED0",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    LPORT_INTR_1_CPU_CLEAR_RESERVED0_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_CLEAR_RESERVED0_FIELD_WIDTH,
    LPORT_INTR_1_CPU_CLEAR_RESERVED0_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_CLEAR_MAB_STATUS_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_CLEAR_MAB_STATUS_INTR_FIELD =
{
    "MAB_STATUS_INTR",
#if RU_INCLUDE_DESC
    "",
    "Asserted when any of statuses get set in MSBUS Adaptation Block Status Register(s).\n"
    "Index 1 corresponds to MSBUS Adaptation Block 1 (i.e. XLMAC1) and index 0 to MSBUS Adaptation Block 0 (i.e. XLMAC0).",
#endif
    LPORT_INTR_1_CPU_CLEAR_MAB_STATUS_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_CLEAR_MAB_STATUS_INTR_FIELD_WIDTH,
    LPORT_INTR_1_CPU_CLEAR_MAB_STATUS_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_CLEAR_RX_REMOTE_FAULT_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_CLEAR_RX_REMOTE_FAULT_INTR_FIELD =
{
    "RX_REMOTE_FAULT_INTR",
#if RU_INCLUDE_DESC
    "",
    "RX Remote Fault Interrupt for P4 and P0.",
#endif
    LPORT_INTR_1_CPU_CLEAR_RX_REMOTE_FAULT_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_CLEAR_RX_REMOTE_FAULT_INTR_FIELD_WIDTH,
    LPORT_INTR_1_CPU_CLEAR_RX_REMOTE_FAULT_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_OFF_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_OFF_INTR_FIELD =
{
    "DSERDES_SD_OFF_INTR",
#if RU_INCLUDE_DESC
    "",
    "Inverted sd_on interrupt. Interrupt to serdes lane mapping is same as for dserdes_sd_on_intr[3:0]. "
    "Based on filtered signal detect.",
#endif
    LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_OFF_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_OFF_INTR_FIELD_WIDTH,
    LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_OFF_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_ON_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_ON_INTR_FIELD =
{
    "DSERDES_SD_ON_INTR",
#if RU_INCLUDE_DESC
    "",
    "Active high signal detect interrupt (signals presence of the link partner).\n"
    "dserdes_sd_on_intr[3] corresponds to MERLIN 1, lane 1.\n"
    "dserdes_sd_on_intr[2] corresponds to MERLIN 1, lane 0.\n"
    "dserdes_sd_on_intr[1] corresponds to MERLIN 0, lane 1.\n"
    "dserdes_sd_on_intr[0] corresponds to MERLIN 0, lane 0.\n"
    "Based on filtered signal detect.",
#endif
    LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_ON_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_ON_INTR_FIELD_WIDTH,
    LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_ON_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_CLEAR_LINK_DOWN_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_CLEAR_LINK_DOWN_INTR_FIELD =
{
    "LINK_DOWN_INTR",
#if RU_INCLUDE_DESC
    "",
    "Link down interrupt for P7:P0. Interrupt corresponds to the attached PHY/interface link down event.",
#endif
    LPORT_INTR_1_CPU_CLEAR_LINK_DOWN_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_CLEAR_LINK_DOWN_INTR_FIELD_WIDTH,
    LPORT_INTR_1_CPU_CLEAR_LINK_DOWN_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_CLEAR_LINK_UP_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_CLEAR_LINK_UP_INTR_FIELD =
{
    "LINK_UP_INTR",
#if RU_INCLUDE_DESC
    "",
    "Link up interrupt for P7:P0. Interrupt corresponds to the attached PHY/interface link up event.",
#endif
    LPORT_INTR_1_CPU_CLEAR_LINK_UP_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_CLEAR_LINK_UP_INTR_FIELD_WIDTH,
    LPORT_INTR_1_CPU_CLEAR_LINK_UP_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_MASK_STATUS_RESERVED0
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_MASK_STATUS_RESERVED0_FIELD =
{
    "RESERVED0",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    LPORT_INTR_1_CPU_MASK_STATUS_RESERVED0_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_MASK_STATUS_RESERVED0_FIELD_WIDTH,
    LPORT_INTR_1_CPU_MASK_STATUS_RESERVED0_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD =
{
    "RX_REMOTE_FAULT_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for rx remote fault interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_CPU_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_1_CPU_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_OFF_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD =
{
    "DSERDES_SD_OFF_INTR",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for dual serdes signal detect off interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD_WIDTH,
    LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_ON_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD =
{
    "DSERDES_SD_ON_INTR",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for dual serdes signal detect on interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD_WIDTH,
    LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_MASK_STATUS_LINK_DOWN_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD =
{
    "LINK_DOWN_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for link down interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_CPU_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_1_CPU_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_MASK_STATUS_LINK_UP_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_MASK_STATUS_LINK_UP_INTR_MASK_FIELD =
{
    "LINK_UP_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for link up interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_CPU_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_1_CPU_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_MASK_SET_RESERVED0
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_MASK_SET_RESERVED0_FIELD =
{
    "RESERVED0",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    LPORT_INTR_1_CPU_MASK_SET_RESERVED0_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_MASK_SET_RESERVED0_FIELD_WIDTH,
    LPORT_INTR_1_CPU_MASK_SET_RESERVED0_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_MASK_SET_RX_REMOTE_FAULT_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD =
{
    "RX_REMOTE_FAULT_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for rx remote fault interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_CPU_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_1_CPU_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_OFF_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_OFF_INTR_FIELD =
{
    "DSERDES_SD_OFF_INTR",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for dual serdes signal detect off interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_OFF_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_OFF_INTR_FIELD_WIDTH,
    LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_OFF_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_ON_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_ON_INTR_FIELD =
{
    "DSERDES_SD_ON_INTR",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for dual serdes signal detect on interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_ON_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_ON_INTR_FIELD_WIDTH,
    LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_ON_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_MASK_SET_LINK_DOWN_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_MASK_SET_LINK_DOWN_INTR_MASK_FIELD =
{
    "LINK_DOWN_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for link down interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_CPU_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_1_CPU_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_MASK_SET_LINK_UP_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_MASK_SET_LINK_UP_INTR_MASK_FIELD =
{
    "LINK_UP_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for link up interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_CPU_MASK_SET_LINK_UP_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_MASK_SET_LINK_UP_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_1_CPU_MASK_SET_LINK_UP_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_MASK_CLEAR_RESERVED0
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_MASK_CLEAR_RESERVED0_FIELD =
{
    "RESERVED0",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    LPORT_INTR_1_CPU_MASK_CLEAR_RESERVED0_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_MASK_CLEAR_RESERVED0_FIELD_WIDTH,
    LPORT_INTR_1_CPU_MASK_CLEAR_RESERVED0_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD =
{
    "RX_REMOTE_FAULT_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for rx remote fault interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_CPU_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_1_CPU_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_OFF_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD =
{
    "DSERDES_SD_OFF_INTR",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for dual serdes signal detect off interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD_WIDTH,
    LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_ON_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD =
{
    "DSERDES_SD_ON_INTR",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for dual serdes signal detect on interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD_WIDTH,
    LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_MASK_CLEAR_LINK_DOWN_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD =
{
    "LINK_DOWN_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for link down interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_CPU_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_1_CPU_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_CPU_MASK_CLEAR_LINK_UP_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_CPU_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD =
{
    "LINK_UP_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for link up interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_CPU_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_1_CPU_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_1_CPU_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_STATUS_RESERVED0
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_STATUS_RESERVED0_FIELD =
{
    "RESERVED0",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    LPORT_INTR_1_PCI_STATUS_RESERVED0_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_STATUS_RESERVED0_FIELD_WIDTH,
    LPORT_INTR_1_PCI_STATUS_RESERVED0_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_STATUS_MAB_STATUS_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_STATUS_MAB_STATUS_INTR_FIELD =
{
    "MAB_STATUS_INTR",
#if RU_INCLUDE_DESC
    "",
    "Asserted when any of statuses get set in MSBUS Adaptation Block Status Register(s).\n"
    "Index 1 corresponds to MSBUS Adaptation Block 1 (i.e. XLMAC1) and index 0 to MSBUS Adaptation Block 0 (i.e. XLMAC0).",
#endif
    LPORT_INTR_1_PCI_STATUS_MAB_STATUS_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_STATUS_MAB_STATUS_INTR_FIELD_WIDTH,
    LPORT_INTR_1_PCI_STATUS_MAB_STATUS_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_STATUS_RX_REMOTE_FAULT_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_STATUS_RX_REMOTE_FAULT_INTR_FIELD =
{
    "RX_REMOTE_FAULT_INTR",
#if RU_INCLUDE_DESC
    "",
    "RX Remote Fault Interrupt for P4 and P0.",
#endif
    LPORT_INTR_1_PCI_STATUS_RX_REMOTE_FAULT_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_STATUS_RX_REMOTE_FAULT_INTR_FIELD_WIDTH,
    LPORT_INTR_1_PCI_STATUS_RX_REMOTE_FAULT_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_STATUS_DSERDES_SD_OFF_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_STATUS_DSERDES_SD_OFF_INTR_FIELD =
{
    "DSERDES_SD_OFF_INTR",
#if RU_INCLUDE_DESC
    "",
    "Inverted sd_on interrupt. Interrupt to serdes lane mapping is same as for dserdes_sd_on_intr[3:0]. "
    "Based on filtered signal detect.",
#endif
    LPORT_INTR_1_PCI_STATUS_DSERDES_SD_OFF_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_STATUS_DSERDES_SD_OFF_INTR_FIELD_WIDTH,
    LPORT_INTR_1_PCI_STATUS_DSERDES_SD_OFF_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_STATUS_DSERDES_SD_ON_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_STATUS_DSERDES_SD_ON_INTR_FIELD =
{
    "DSERDES_SD_ON_INTR",
#if RU_INCLUDE_DESC
    "",
    "Active high signal detect interrupt (signals presence of the link partner).\n"
    "dserdes_sd_on_intr[3] corresponds to MERLIN 1, lane 1.\n"
    "dserdes_sd_on_intr[2] corresponds to MERLIN 1, lane 0.\n"
    "dserdes_sd_on_intr[1] corresponds to MERLIN 0, lane 1.\n"
    "dserdes_sd_on_intr[0] corresponds to MERLIN 0, lane 0.\n"
    "Based on filtered signal detect.",
#endif
    LPORT_INTR_1_PCI_STATUS_DSERDES_SD_ON_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_STATUS_DSERDES_SD_ON_INTR_FIELD_WIDTH,
    LPORT_INTR_1_PCI_STATUS_DSERDES_SD_ON_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_STATUS_LINK_DOWN_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_STATUS_LINK_DOWN_INTR_FIELD =
{
    "LINK_DOWN_INTR",
#if RU_INCLUDE_DESC
    "",
    "Link down interrupt for P7:P0. Interrupt corresponds to the attached PHY/interface link down event.",
#endif
    LPORT_INTR_1_PCI_STATUS_LINK_DOWN_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_STATUS_LINK_DOWN_INTR_FIELD_WIDTH,
    LPORT_INTR_1_PCI_STATUS_LINK_DOWN_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_STATUS_LINK_UP_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_STATUS_LINK_UP_INTR_FIELD =
{
    "LINK_UP_INTR",
#if RU_INCLUDE_DESC
    "",
    "Link up interrupt for P7:P0. Interrupt corresponds to the attached PHY/interface link up event.",
#endif
    LPORT_INTR_1_PCI_STATUS_LINK_UP_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_STATUS_LINK_UP_INTR_FIELD_WIDTH,
    LPORT_INTR_1_PCI_STATUS_LINK_UP_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_SET_RESERVED0
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_SET_RESERVED0_FIELD =
{
    "RESERVED0",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    LPORT_INTR_1_PCI_SET_RESERVED0_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_SET_RESERVED0_FIELD_WIDTH,
    LPORT_INTR_1_PCI_SET_RESERVED0_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_SET_MAB_STATUS_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_SET_MAB_STATUS_INTR_FIELD =
{
    "MAB_STATUS_INTR",
#if RU_INCLUDE_DESC
    "",
    "Asserted when any of statuses get set in MSBUS Adaptation Block Status Register(s).\n"
    "Index 1 corresponds to MSBUS Adaptation Block 1 (i.e. XLMAC1) and index 0 to MSBUS Adaptation Block 0 (i.e. XLMAC0).",
#endif
    LPORT_INTR_1_PCI_SET_MAB_STATUS_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_SET_MAB_STATUS_INTR_FIELD_WIDTH,
    LPORT_INTR_1_PCI_SET_MAB_STATUS_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_SET_RX_REMOTE_FAULT_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_SET_RX_REMOTE_FAULT_INTR_FIELD =
{
    "RX_REMOTE_FAULT_INTR",
#if RU_INCLUDE_DESC
    "",
    "RX Remote Fault Interrupt for P4 and P0.",
#endif
    LPORT_INTR_1_PCI_SET_RX_REMOTE_FAULT_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_SET_RX_REMOTE_FAULT_INTR_FIELD_WIDTH,
    LPORT_INTR_1_PCI_SET_RX_REMOTE_FAULT_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_SET_DSERDES_SD_OFF_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_SET_DSERDES_SD_OFF_INTR_FIELD =
{
    "DSERDES_SD_OFF_INTR",
#if RU_INCLUDE_DESC
    "",
    "Inverted sd_on interrupt. Interrupt to serdes lane mapping is same as for dserdes_sd_on_intr[3:0]. "
    "Based on filtered signal detect.",
#endif
    LPORT_INTR_1_PCI_SET_DSERDES_SD_OFF_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_SET_DSERDES_SD_OFF_INTR_FIELD_WIDTH,
    LPORT_INTR_1_PCI_SET_DSERDES_SD_OFF_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_SET_DSERDES_SD_ON_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_SET_DSERDES_SD_ON_INTR_FIELD =
{
    "DSERDES_SD_ON_INTR",
#if RU_INCLUDE_DESC
    "",
    "Active high signal detect interrupt (signals presence of the link partner).\n"
    "dserdes_sd_on_intr[3] corresponds to MERLIN 1, lane 1.\n"
    "dserdes_sd_on_intr[2] corresponds to MERLIN 1, lane 0.\n"
    "dserdes_sd_on_intr[1] corresponds to MERLIN 0, lane 1.\n"
    "dserdes_sd_on_intr[0] corresponds to MERLIN 0, lane 0.\n"
    "Based on filtered signal detect.",
#endif
    LPORT_INTR_1_PCI_SET_DSERDES_SD_ON_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_SET_DSERDES_SD_ON_INTR_FIELD_WIDTH,
    LPORT_INTR_1_PCI_SET_DSERDES_SD_ON_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_SET_LINK_DOWN_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_SET_LINK_DOWN_INTR_FIELD =
{
    "LINK_DOWN_INTR",
#if RU_INCLUDE_DESC
    "",
    "Link down interrupt for P7:P0. Interrupt corresponds to the attached PHY/interface link down event.",
#endif
    LPORT_INTR_1_PCI_SET_LINK_DOWN_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_SET_LINK_DOWN_INTR_FIELD_WIDTH,
    LPORT_INTR_1_PCI_SET_LINK_DOWN_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_SET_LINK_UP_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_SET_LINK_UP_INTR_FIELD =
{
    "LINK_UP_INTR",
#if RU_INCLUDE_DESC
    "",
    "Link up interrupt for P7:P0. Interrupt corresponds to the attached PHY/interface link up event.",
#endif
    LPORT_INTR_1_PCI_SET_LINK_UP_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_SET_LINK_UP_INTR_FIELD_WIDTH,
    LPORT_INTR_1_PCI_SET_LINK_UP_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_CLEAR_RESERVED0
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_CLEAR_RESERVED0_FIELD =
{
    "RESERVED0",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    LPORT_INTR_1_PCI_CLEAR_RESERVED0_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_CLEAR_RESERVED0_FIELD_WIDTH,
    LPORT_INTR_1_PCI_CLEAR_RESERVED0_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_CLEAR_MAB_STATUS_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_CLEAR_MAB_STATUS_INTR_FIELD =
{
    "MAB_STATUS_INTR",
#if RU_INCLUDE_DESC
    "",
    "Asserted when any of statuses get set in MSBUS Adaptation Block Status Register(s).\n"
    "Index 1 corresponds to MSBUS Adaptation Block 1 (i.e. XLMAC1) and index 0 to MSBUS Adaptation Block 0 (i.e. XLMAC0).",
#endif
    LPORT_INTR_1_PCI_CLEAR_MAB_STATUS_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_CLEAR_MAB_STATUS_INTR_FIELD_WIDTH,
    LPORT_INTR_1_PCI_CLEAR_MAB_STATUS_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_CLEAR_RX_REMOTE_FAULT_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_CLEAR_RX_REMOTE_FAULT_INTR_FIELD =
{
    "RX_REMOTE_FAULT_INTR",
#if RU_INCLUDE_DESC
    "",
    "RX Remote Fault Interrupt for P4 and P0.",
#endif
    LPORT_INTR_1_PCI_CLEAR_RX_REMOTE_FAULT_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_CLEAR_RX_REMOTE_FAULT_INTR_FIELD_WIDTH,
    LPORT_INTR_1_PCI_CLEAR_RX_REMOTE_FAULT_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_OFF_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_OFF_INTR_FIELD =
{
    "DSERDES_SD_OFF_INTR",
#if RU_INCLUDE_DESC
    "",
    "Inverted sd_on interrupt. Interrupt to serdes lane mapping is same as for dserdes_sd_on_intr[3:0]. "
    "Based on filtered signal detect.",
#endif
    LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_OFF_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_OFF_INTR_FIELD_WIDTH,
    LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_OFF_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_ON_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_ON_INTR_FIELD =
{
    "DSERDES_SD_ON_INTR",
#if RU_INCLUDE_DESC
    "",
    "Active high signal detect interrupt (signals presence of the link partner).\n"
    "dserdes_sd_on_intr[3] corresponds to MERLIN 1, lane 1.\n"
    "dserdes_sd_on_intr[2] corresponds to MERLIN 1, lane 0.\n"
    "dserdes_sd_on_intr[1] corresponds to MERLIN 0, lane 1.\n"
    "dserdes_sd_on_intr[0] corresponds to MERLIN 0, lane 0.\n"
    "Based on filtered signal detect.",
#endif
    LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_ON_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_ON_INTR_FIELD_WIDTH,
    LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_ON_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_CLEAR_LINK_DOWN_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_CLEAR_LINK_DOWN_INTR_FIELD =
{
    "LINK_DOWN_INTR",
#if RU_INCLUDE_DESC
    "",
    "Link down interrupt for P7:P0. Interrupt corresponds to the attached PHY/interface link down event.",
#endif
    LPORT_INTR_1_PCI_CLEAR_LINK_DOWN_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_CLEAR_LINK_DOWN_INTR_FIELD_WIDTH,
    LPORT_INTR_1_PCI_CLEAR_LINK_DOWN_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_CLEAR_LINK_UP_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_CLEAR_LINK_UP_INTR_FIELD =
{
    "LINK_UP_INTR",
#if RU_INCLUDE_DESC
    "",
    "Link up interrupt for P7:P0. Interrupt corresponds to the attached PHY/interface link up event.",
#endif
    LPORT_INTR_1_PCI_CLEAR_LINK_UP_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_CLEAR_LINK_UP_INTR_FIELD_WIDTH,
    LPORT_INTR_1_PCI_CLEAR_LINK_UP_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_MASK_STATUS_RESERVED0
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_MASK_STATUS_RESERVED0_FIELD =
{
    "RESERVED0",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    LPORT_INTR_1_PCI_MASK_STATUS_RESERVED0_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_MASK_STATUS_RESERVED0_FIELD_WIDTH,
    LPORT_INTR_1_PCI_MASK_STATUS_RESERVED0_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD =
{
    "RX_REMOTE_FAULT_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for rx remote fault interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_PCI_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_1_PCI_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_OFF_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD =
{
    "DSERDES_SD_OFF_INTR",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for dual serdes signal detect off interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD_WIDTH,
    LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_ON_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD =
{
    "DSERDES_SD_ON_INTR",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for dual serdes signal detect on interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD_WIDTH,
    LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_MASK_STATUS_LINK_DOWN_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD =
{
    "LINK_DOWN_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for link down interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_PCI_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_1_PCI_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_MASK_STATUS_LINK_UP_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_MASK_STATUS_LINK_UP_INTR_MASK_FIELD =
{
    "LINK_UP_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for link up interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_PCI_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_1_PCI_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_MASK_SET_RESERVED0
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_MASK_SET_RESERVED0_FIELD =
{
    "RESERVED0",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    LPORT_INTR_1_PCI_MASK_SET_RESERVED0_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_MASK_SET_RESERVED0_FIELD_WIDTH,
    LPORT_INTR_1_PCI_MASK_SET_RESERVED0_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_MASK_SET_RX_REMOTE_FAULT_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD =
{
    "RX_REMOTE_FAULT_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for rx remote fault interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_PCI_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_1_PCI_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_OFF_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_OFF_INTR_FIELD =
{
    "DSERDES_SD_OFF_INTR",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for dual serdes signal detect off interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_OFF_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_OFF_INTR_FIELD_WIDTH,
    LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_OFF_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_ON_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_ON_INTR_FIELD =
{
    "DSERDES_SD_ON_INTR",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for dual serdes signal detect on interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_ON_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_ON_INTR_FIELD_WIDTH,
    LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_ON_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_MASK_SET_LINK_DOWN_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_MASK_SET_LINK_DOWN_INTR_MASK_FIELD =
{
    "LINK_DOWN_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for link down interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_PCI_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_1_PCI_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_MASK_SET_LINK_UP_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_MASK_SET_LINK_UP_INTR_MASK_FIELD =
{
    "LINK_UP_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for link up interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_PCI_MASK_SET_LINK_UP_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_MASK_SET_LINK_UP_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_1_PCI_MASK_SET_LINK_UP_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_MASK_CLEAR_RESERVED0
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_MASK_CLEAR_RESERVED0_FIELD =
{
    "RESERVED0",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    LPORT_INTR_1_PCI_MASK_CLEAR_RESERVED0_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_MASK_CLEAR_RESERVED0_FIELD_WIDTH,
    LPORT_INTR_1_PCI_MASK_CLEAR_RESERVED0_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD =
{
    "RX_REMOTE_FAULT_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for rx remote fault interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_PCI_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_1_PCI_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_OFF_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD =
{
    "DSERDES_SD_OFF_INTR",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for dual serdes signal detect off interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD_WIDTH,
    LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_ON_INTR
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD =
{
    "DSERDES_SD_ON_INTR",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for dual serdes signal detect on interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD_WIDTH,
    LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_MASK_CLEAR_LINK_DOWN_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD =
{
    "LINK_DOWN_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for link down interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_PCI_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_1_PCI_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: LPORT_INTR_1_PCI_MASK_CLEAR_LINK_UP_INTR_MASK
 ******************************************************************************/
const ru_field_rec LPORT_INTR_1_PCI_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD =
{
    "LINK_UP_INTR_MASK",
#if RU_INCLUDE_DESC
    "",
    "This bit corresponds to the mask for link up interrupt. See register description above for details of how to use this bit.",
#endif
    LPORT_INTR_1_PCI_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_MASK,
    0,
    LPORT_INTR_1_PCI_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_WIDTH,
    LPORT_INTR_1_PCI_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

#endif /* RU_INCLUDE_FIELD_DB */

/******************************************************************************
 * Register: LPORT_INTR_0_CPU_STATUS
 ******************************************************************************/
#if RU_INCLUDE_FIELD_DB
static const ru_field_rec *LPORT_INTR_0_CPU_STATUS_FIELDS[] =
{
    &LPORT_INTR_0_CPU_STATUS_RESERVED0_FIELD,
    &LPORT_INTR_0_CPU_STATUS_XLMAC_INTR_FIELD,
    &LPORT_INTR_0_CPU_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD,
    &LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD,
    &LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_ON_INTR_FIELD,
    &LPORT_INTR_0_CPU_STATUS_MDIO_ERR_INTR_FIELD,
    &LPORT_INTR_0_CPU_STATUS_MDIO_DONE_INTR_FIELD,
    &LPORT_INTR_0_CPU_STATUS_MIB_REG_ERR_INTR_FIELD,
    &LPORT_INTR_0_CPU_STATUS_MAC_REG_ERR_INTR_FIELD,
    &LPORT_INTR_0_CPU_STATUS_UBUS_ERR_INTR_FIELD,
};

#endif /* RU_INCLUDE_FIELD_DB */

const ru_reg_rec LPORT_INTR_0_CPU_STATUS_REG = 
{
    "0_CPU_STATUS",
#if RU_INCLUDE_DESC
    "PCI interrupt Clear Register",
    "This read-only register shows the current status of the interrupts for the CPU processor.  There is one "
    "bit per interrupt source.  The assertion of any of these interrupts will cause an interrupt to the CPU "
    "processor if the interrupt's mask bit is zero."
    "\nFor each bit: 1 = asserted. 0 = not asserted."
    "This write-only register is used to set interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
    "This write-only register is used to clear interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change."
    "This read-only register shows the current status of the interrupts for the PCI bus.  There is one bit per "
    "interrupt source.  The assertion of any of these interrupts will cause an interrupt to the PCI bus if the"
    "interrupt's mask bit is zero."
    "\nFor each bit: 1 = asserted. 0 = not asserted."
    "This write-only register is used to set interrupts for the PCI bus.  There is one bit per interrupt source."
    "Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing a 0 has "
    "no effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros "
    "written to them are not affected."
    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
    "This write-only register is used to clear interrupts for the PCI bus.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change.",
#endif
    LPORT_INTR_0_CPU_STATUS_REG_OFFSET,
    0,
    0,
    271,
#if RU_INCLUDE_ACCESS
    ru_access_rw,
#endif
#if RU_INCLUDE_FIELD_DB
    10,
    LPORT_INTR_0_CPU_STATUS_FIELDS,
#endif /* RU_INCLUDE_FIELD_DB */
    ru_reg_size_32
};

/******************************************************************************
 * Register: LPORT_INTR_0_CPU_SET
 ******************************************************************************/
#if RU_INCLUDE_FIELD_DB
static const ru_field_rec *LPORT_INTR_0_CPU_SET_FIELDS[] =
{
    &LPORT_INTR_0_CPU_SET_RESERVED0_FIELD,
    &LPORT_INTR_0_CPU_SET_XLMAC_INTR_FIELD,
    &LPORT_INTR_0_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD,
    &LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_OFF_INTR_FIELD,
    &LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_ON_INTR_FIELD,
    &LPORT_INTR_0_CPU_SET_MDIO_ERR_INTR_FIELD,
    &LPORT_INTR_0_CPU_SET_MDIO_DONE_INTR_FIELD,
    &LPORT_INTR_0_CPU_SET_MIB_REG_ERR_INTR_FIELD,
    &LPORT_INTR_0_CPU_SET_MAC_REG_ERR_INTR_FIELD,
    &LPORT_INTR_0_CPU_SET_UBUS_ERR_INTR_FIELD,
};

#endif /* RU_INCLUDE_FIELD_DB */

const ru_reg_rec LPORT_INTR_0_CPU_SET_REG = 
{
    "0_CPU_SET",
#if RU_INCLUDE_DESC
    "PCI interrupt Clear Register",
    "This read-only register shows the current status of the interrupts for the CPU processor.  There is one "
    "bit per interrupt source.  The assertion of any of these interrupts will cause an interrupt to the CPU "
    "processor if the interrupt's mask bit is zero."
    "\nFor each bit: 1 = asserted. 0 = not asserted."
    "This write-only register is used to set interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
    "This write-only register is used to clear interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change."
    "This read-only register shows the current status of the interrupts for the PCI bus.  There is one bit per "
    "interrupt source.  The assertion of any of these interrupts will cause an interrupt to the PCI bus if the"
    "interrupt's mask bit is zero."
    "\nFor each bit: 1 = asserted. 0 = not asserted."
    "This write-only register is used to set interrupts for the PCI bus.  There is one bit per interrupt source."
    "Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing a 0 has "
    "no effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros "
    "written to them are not affected."
    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
    "This write-only register is used to clear interrupts for the PCI bus.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change.",
#endif
    LPORT_INTR_0_CPU_SET_REG_OFFSET,
    0,
    0,
    272,
#if RU_INCLUDE_ACCESS
    ru_access_rw,
#endif
#if RU_INCLUDE_FIELD_DB
    10,
    LPORT_INTR_0_CPU_SET_FIELDS,
#endif /* RU_INCLUDE_FIELD_DB */
    ru_reg_size_32
};

/******************************************************************************
 * Register: LPORT_INTR_0_CPU_CLEAR
 ******************************************************************************/
#if RU_INCLUDE_FIELD_DB
static const ru_field_rec *LPORT_INTR_0_CPU_CLEAR_FIELDS[] =
{
    &LPORT_INTR_0_CPU_CLEAR_RESERVED0_FIELD,
    &LPORT_INTR_0_CPU_CLEAR_XLMAC_INTR_FIELD,
    &LPORT_INTR_0_CPU_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD,
    &LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD,
    &LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD,
    &LPORT_INTR_0_CPU_CLEAR_MDIO_ERR_INTR_FIELD,
    &LPORT_INTR_0_CPU_CLEAR_MDIO_DONE_INTR_FIELD,
    &LPORT_INTR_0_CPU_CLEAR_MIB_REG_ERR_INTR_FIELD,
    &LPORT_INTR_0_CPU_CLEAR_MAC_REG_ERR_INTR_FIELD,
    &LPORT_INTR_0_CPU_CLEAR_UBUS_ERR_INTR_FIELD,
};

#endif /* RU_INCLUDE_FIELD_DB */

const ru_reg_rec LPORT_INTR_0_CPU_CLEAR_REG = 
{
    "0_CPU_CLEAR",
#if RU_INCLUDE_DESC
    "PCI interrupt Clear Register",
    "This read-only register shows the current status of the interrupts for the CPU processor.  There is one "
    "bit per interrupt source.  The assertion of any of these interrupts will cause an interrupt to the CPU "
    "processor if the interrupt's mask bit is zero."
    "\nFor each bit: 1 = asserted. 0 = not asserted."
    "This write-only register is used to set interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
    "This write-only register is used to clear interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change."
    "This read-only register shows the current status of the interrupts for the PCI bus.  There is one bit per "
    "interrupt source.  The assertion of any of these interrupts will cause an interrupt to the PCI bus if the"
    "interrupt's mask bit is zero."
    "\nFor each bit: 1 = asserted. 0 = not asserted."
    "This write-only register is used to set interrupts for the PCI bus.  There is one bit per interrupt source."
    "Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing a 0 has "
    "no effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros "
    "written to them are not affected."
    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
    "This write-only register is used to clear interrupts for the PCI bus.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change.",
#endif
    LPORT_INTR_0_CPU_CLEAR_REG_OFFSET,
    0,
    0,
    273,
#if RU_INCLUDE_ACCESS
    ru_access_rw,
#endif
#if RU_INCLUDE_FIELD_DB
    10,
    LPORT_INTR_0_CPU_CLEAR_FIELDS,
#endif /* RU_INCLUDE_FIELD_DB */
    ru_reg_size_32
};

/******************************************************************************
 * Register: LPORT_INTR_0_CPU_MASK_STATUS
 ******************************************************************************/
#if RU_INCLUDE_FIELD_DB
static const ru_field_rec *LPORT_INTR_0_CPU_MASK_STATUS_FIELDS[] =
{
    &LPORT_INTR_0_CPU_MASK_STATUS_RESERVED0_FIELD,
    &LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD,
};

#endif /* RU_INCLUDE_FIELD_DB */

const ru_reg_rec LPORT_INTR_0_CPU_MASK_STATUS_REG = 
{
    "0_CPU_MASK_STATUS",
#if RU_INCLUDE_DESC
    "PCI interrupt Mask Clear Register",
    "This read-only register shows the current masking of the interrupts for the CPU processor.  There is one "
    "bit per interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to "
    "that bit is currently masked.  Masking does not prevent the interrupt from appearing in the status register."
    "\nFor each bit: 1 = masked. 0 = not masked."
    "This write-only register is used to disable interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
    "This write-only register is used to enable interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change."
    "This read-only register shows the current masking of the interrupts for the PCI bus.  There is one bit per"
    "interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to that bit is"
    "currently masked.  Masking does not prevent the interrupt from appearing in the status register."
    "\nFor each bit: 1 = masked. 0 = not masked."
    "This write-only register is used to disable interrupts for the PCI bus.  There is one bit per interrupt source."
    "Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing a 0 has no"
    "effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros written "
    "to them are not affected."
    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
    "This write-only register is used to enable interrupts for the PCI bus.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change.",
#endif
    LPORT_INTR_0_CPU_MASK_STATUS_REG_OFFSET,
    0,
    0,
    274,
#if RU_INCLUDE_ACCESS
    ru_access_rw,
#endif
#if RU_INCLUDE_FIELD_DB
    13,
    LPORT_INTR_0_CPU_MASK_STATUS_FIELDS,
#endif /* RU_INCLUDE_FIELD_DB */
    ru_reg_size_32
};

/******************************************************************************
 * Register: LPORT_INTR_0_CPU_MASK_SET
 ******************************************************************************/
#if RU_INCLUDE_FIELD_DB
static const ru_field_rec *LPORT_INTR_0_CPU_MASK_SET_FIELDS[] =
{
    &LPORT_INTR_0_CPU_MASK_SET_RESERVED0_FIELD,
    &LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_SET_MDIO_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_SET_MDIO_DONE_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_SET_UBUS_ERR_INTR_MASK_FIELD,
};

#endif /* RU_INCLUDE_FIELD_DB */

const ru_reg_rec LPORT_INTR_0_CPU_MASK_SET_REG = 
{
    "0_CPU_MASK_SET",
#if RU_INCLUDE_DESC
    "PCI interrupt Mask Clear Register",
    "This read-only register shows the current masking of the interrupts for the CPU processor.  There is one "
    "bit per interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to "
    "that bit is currently masked.  Masking does not prevent the interrupt from appearing in the status register."
    "\nFor each bit: 1 = masked. 0 = not masked."
    "This write-only register is used to disable interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
    "This write-only register is used to enable interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change."
    "This read-only register shows the current masking of the interrupts for the PCI bus.  There is one bit per"
    "interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to that bit is"
    "currently masked.  Masking does not prevent the interrupt from appearing in the status register."
    "\nFor each bit: 1 = masked. 0 = not masked."
    "This write-only register is used to disable interrupts for the PCI bus.  There is one bit per interrupt source."
    "Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing a 0 has no"
    "effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros written "
    "to them are not affected."
    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
    "This write-only register is used to enable interrupts for the PCI bus.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change.",
#endif
    LPORT_INTR_0_CPU_MASK_SET_REG_OFFSET,
    0,
    0,
    275,
#if RU_INCLUDE_ACCESS
    ru_access_rw,
#endif
#if RU_INCLUDE_FIELD_DB
    13,
    LPORT_INTR_0_CPU_MASK_SET_FIELDS,
#endif /* RU_INCLUDE_FIELD_DB */
    ru_reg_size_32
};

/******************************************************************************
 * Register: LPORT_INTR_0_CPU_MASK_CLEAR
 ******************************************************************************/
#if RU_INCLUDE_FIELD_DB
static const ru_field_rec *LPORT_INTR_0_CPU_MASK_CLEAR_FIELDS[] =
{
    &LPORT_INTR_0_CPU_MASK_CLEAR_RESERVED0_FIELD,
    &LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_CPU_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD,
};

#endif /* RU_INCLUDE_FIELD_DB */

const ru_reg_rec LPORT_INTR_0_CPU_MASK_CLEAR_REG = 
{
    "0_CPU_MASK_CLEAR",
#if RU_INCLUDE_DESC
    "PCI interrupt Mask Clear Register",
    "This read-only register shows the current masking of the interrupts for the CPU processor.  There is one "
    "bit per interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to "
    "that bit is currently masked.  Masking does not prevent the interrupt from appearing in the status register."
    "\nFor each bit: 1 = masked. 0 = not masked."
    "This write-only register is used to disable interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
    "This write-only register is used to enable interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change."
    "This read-only register shows the current masking of the interrupts for the PCI bus.  There is one bit per"
    "interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to that bit is"
    "currently masked.  Masking does not prevent the interrupt from appearing in the status register."
    "\nFor each bit: 1 = masked. 0 = not masked."
    "This write-only register is used to disable interrupts for the PCI bus.  There is one bit per interrupt source."
    "Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing a 0 has no"
    "effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros written "
    "to them are not affected."
    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
    "This write-only register is used to enable interrupts for the PCI bus.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change.",
#endif
    LPORT_INTR_0_CPU_MASK_CLEAR_REG_OFFSET,
    0,
    0,
    276,
#if RU_INCLUDE_ACCESS
    ru_access_rw,
#endif
#if RU_INCLUDE_FIELD_DB
    13,
    LPORT_INTR_0_CPU_MASK_CLEAR_FIELDS,
#endif /* RU_INCLUDE_FIELD_DB */
    ru_reg_size_32
};

/******************************************************************************
 * Register: LPORT_INTR_0_PCI_STATUS
 ******************************************************************************/
#if RU_INCLUDE_FIELD_DB
static const ru_field_rec *LPORT_INTR_0_PCI_STATUS_FIELDS[] =
{
    &LPORT_INTR_0_PCI_STATUS_RESERVED0_FIELD,
    &LPORT_INTR_0_PCI_STATUS_XLMAC_INTR_FIELD,
    &LPORT_INTR_0_PCI_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD,
    &LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD,
    &LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_ON_INTR_FIELD,
    &LPORT_INTR_0_PCI_STATUS_MDIO_ERR_INTR_FIELD,
    &LPORT_INTR_0_PCI_STATUS_MDIO_DONE_INTR_FIELD,
    &LPORT_INTR_0_PCI_STATUS_MIB_REG_ERR_INTR_FIELD,
    &LPORT_INTR_0_PCI_STATUS_MAC_REG_ERR_INTR_FIELD,
    &LPORT_INTR_0_PCI_STATUS_UBUS_ERR_INTR_FIELD,
};

#endif /* RU_INCLUDE_FIELD_DB */

const ru_reg_rec LPORT_INTR_0_PCI_STATUS_REG = 
{
    "0_PCI_STATUS",
#if RU_INCLUDE_DESC
    "PCI interrupt Clear Register",
    "This read-only register shows the current status of the interrupts for the CPU processor.  There is one "
    "bit per interrupt source.  The assertion of any of these interrupts will cause an interrupt to the CPU "
    "processor if the interrupt's mask bit is zero."
    "\nFor each bit: 1 = asserted. 0 = not asserted."
    "This write-only register is used to set interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
    "This write-only register is used to clear interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change."
    "This read-only register shows the current status of the interrupts for the PCI bus.  There is one bit per "
    "interrupt source.  The assertion of any of these interrupts will cause an interrupt to the PCI bus if the"
    "interrupt's mask bit is zero."
    "\nFor each bit: 1 = asserted. 0 = not asserted."
    "This write-only register is used to set interrupts for the PCI bus.  There is one bit per interrupt source."
    "Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing a 0 has "
    "no effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros "
    "written to them are not affected."
    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
    "This write-only register is used to clear interrupts for the PCI bus.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change.",
#endif
    LPORT_INTR_0_PCI_STATUS_REG_OFFSET,
    0,
    0,
    277,
#if RU_INCLUDE_ACCESS
    ru_access_rw,
#endif
#if RU_INCLUDE_FIELD_DB
    10,
    LPORT_INTR_0_PCI_STATUS_FIELDS,
#endif /* RU_INCLUDE_FIELD_DB */
    ru_reg_size_32
};

/******************************************************************************
 * Register: LPORT_INTR_0_PCI_SET
 ******************************************************************************/
#if RU_INCLUDE_FIELD_DB
static const ru_field_rec *LPORT_INTR_0_PCI_SET_FIELDS[] =
{
    &LPORT_INTR_0_PCI_SET_RESERVED0_FIELD,
    &LPORT_INTR_0_PCI_SET_XLMAC_INTR_FIELD,
    &LPORT_INTR_0_PCI_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD,
    &LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_OFF_INTR_FIELD,
    &LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_ON_INTR_FIELD,
    &LPORT_INTR_0_PCI_SET_MDIO_ERR_INTR_FIELD,
    &LPORT_INTR_0_PCI_SET_MDIO_DONE_INTR_FIELD,
    &LPORT_INTR_0_PCI_SET_MIB_REG_ERR_INTR_FIELD,
    &LPORT_INTR_0_PCI_SET_MAC_REG_ERR_INTR_FIELD,
    &LPORT_INTR_0_PCI_SET_UBUS_ERR_INTR_FIELD,
};

#endif /* RU_INCLUDE_FIELD_DB */

const ru_reg_rec LPORT_INTR_0_PCI_SET_REG = 
{
    "0_PCI_SET",
#if RU_INCLUDE_DESC
    "PCI interrupt Clear Register",
    "This read-only register shows the current status of the interrupts for the CPU processor.  There is one "
    "bit per interrupt source.  The assertion of any of these interrupts will cause an interrupt to the CPU "
    "processor if the interrupt's mask bit is zero."
    "\nFor each bit: 1 = asserted. 0 = not asserted."
    "This write-only register is used to set interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
    "This write-only register is used to clear interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change."
    "This read-only register shows the current status of the interrupts for the PCI bus.  There is one bit per "
    "interrupt source.  The assertion of any of these interrupts will cause an interrupt to the PCI bus if the"
    "interrupt's mask bit is zero."
    "\nFor each bit: 1 = asserted. 0 = not asserted."
    "This write-only register is used to set interrupts for the PCI bus.  There is one bit per interrupt source."
    "Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing a 0 has "
    "no effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros "
    "written to them are not affected."
    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
    "This write-only register is used to clear interrupts for the PCI bus.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change.",
#endif
    LPORT_INTR_0_PCI_SET_REG_OFFSET,
    0,
    0,
    278,
#if RU_INCLUDE_ACCESS
    ru_access_rw,
#endif
#if RU_INCLUDE_FIELD_DB
    10,
    LPORT_INTR_0_PCI_SET_FIELDS,
#endif /* RU_INCLUDE_FIELD_DB */
    ru_reg_size_32
};

/******************************************************************************
 * Register: LPORT_INTR_0_PCI_CLEAR
 ******************************************************************************/
#if RU_INCLUDE_FIELD_DB
static const ru_field_rec *LPORT_INTR_0_PCI_CLEAR_FIELDS[] =
{
    &LPORT_INTR_0_PCI_CLEAR_RESERVED0_FIELD,
    &LPORT_INTR_0_PCI_CLEAR_XLMAC_INTR_FIELD,
    &LPORT_INTR_0_PCI_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD,
    &LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD,
    &LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD,
    &LPORT_INTR_0_PCI_CLEAR_MDIO_ERR_INTR_FIELD,
    &LPORT_INTR_0_PCI_CLEAR_MDIO_DONE_INTR_FIELD,
    &LPORT_INTR_0_PCI_CLEAR_MIB_REG_ERR_INTR_FIELD,
    &LPORT_INTR_0_PCI_CLEAR_MAC_REG_ERR_INTR_FIELD,
    &LPORT_INTR_0_PCI_CLEAR_UBUS_ERR_INTR_FIELD,
};

#endif /* RU_INCLUDE_FIELD_DB */

const ru_reg_rec LPORT_INTR_0_PCI_CLEAR_REG = 
{
    "0_PCI_CLEAR",
#if RU_INCLUDE_DESC
    "PCI interrupt Clear Register",
    "This read-only register shows the current status of the interrupts for the CPU processor.  There is one "
    "bit per interrupt source.  The assertion of any of these interrupts will cause an interrupt to the CPU "
    "processor if the interrupt's mask bit is zero."
    "\nFor each bit: 1 = asserted. 0 = not asserted."
    "This write-only register is used to set interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
    "This write-only register is used to clear interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change."
    "This read-only register shows the current status of the interrupts for the PCI bus.  There is one bit per "
    "interrupt source.  The assertion of any of these interrupts will cause an interrupt to the PCI bus if the"
    "interrupt's mask bit is zero."
    "\nFor each bit: 1 = asserted. 0 = not asserted."
    "This write-only register is used to set interrupts for the PCI bus.  There is one bit per interrupt source."
    "Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing a 0 has "
    "no effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros "
    "written to them are not affected."
    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
    "This write-only register is used to clear interrupts for the PCI bus.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change.",
#endif
    LPORT_INTR_0_PCI_CLEAR_REG_OFFSET,
    0,
    0,
    279,
#if RU_INCLUDE_ACCESS
    ru_access_rw,
#endif
#if RU_INCLUDE_FIELD_DB
    10,
    LPORT_INTR_0_PCI_CLEAR_FIELDS,
#endif /* RU_INCLUDE_FIELD_DB */
    ru_reg_size_32
};

/******************************************************************************
 * Register: LPORT_INTR_0_PCI_MASK_STATUS
 ******************************************************************************/
#if RU_INCLUDE_FIELD_DB
static const ru_field_rec *LPORT_INTR_0_PCI_MASK_STATUS_FIELDS[] =
{
    &LPORT_INTR_0_PCI_MASK_STATUS_RESERVED0_FIELD,
    &LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD,
};

#endif /* RU_INCLUDE_FIELD_DB */

const ru_reg_rec LPORT_INTR_0_PCI_MASK_STATUS_REG = 
{
    "0_PCI_MASK_STATUS",
#if RU_INCLUDE_DESC
    "PCI interrupt Mask Clear Register",
    "This read-only register shows the current masking of the interrupts for the CPU processor.  There is one "
    "bit per interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to "
    "that bit is currently masked.  Masking does not prevent the interrupt from appearing in the status register."
    "\nFor each bit: 1 = masked. 0 = not masked."
    "This write-only register is used to disable interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
    "This write-only register is used to enable interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change."
    "This read-only register shows the current masking of the interrupts for the PCI bus.  There is one bit per"
    "interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to that bit is"
    "currently masked.  Masking does not prevent the interrupt from appearing in the status register."
    "\nFor each bit: 1 = masked. 0 = not masked."
    "This write-only register is used to disable interrupts for the PCI bus.  There is one bit per interrupt source."
    "Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing a 0 has no"
    "effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros written "
    "to them are not affected."
    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
    "This write-only register is used to enable interrupts for the PCI bus.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change.",
#endif
    LPORT_INTR_0_PCI_MASK_STATUS_REG_OFFSET,
    0,
    0,
    280,
#if RU_INCLUDE_ACCESS
    ru_access_rw,
#endif
#if RU_INCLUDE_FIELD_DB
    13,
    LPORT_INTR_0_PCI_MASK_STATUS_FIELDS,
#endif /* RU_INCLUDE_FIELD_DB */
    ru_reg_size_32
};

/******************************************************************************
 * Register: LPORT_INTR_0_PCI_MASK_SET
 ******************************************************************************/
#if RU_INCLUDE_FIELD_DB
static const ru_field_rec *LPORT_INTR_0_PCI_MASK_SET_FIELDS[] =
{
    &LPORT_INTR_0_PCI_MASK_SET_RESERVED0_FIELD,
    &LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_SET_MDIO_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_SET_MDIO_DONE_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_SET_UBUS_ERR_INTR_MASK_FIELD,
};

#endif /* RU_INCLUDE_FIELD_DB */

const ru_reg_rec LPORT_INTR_0_PCI_MASK_SET_REG = 
{
    "0_PCI_MASK_SET",
#if RU_INCLUDE_DESC
    "PCI interrupt Mask Clear Register",
    "This read-only register shows the current masking of the interrupts for the CPU processor.  There is one "
    "bit per interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to "
    "that bit is currently masked.  Masking does not prevent the interrupt from appearing in the status register."
    "\nFor each bit: 1 = masked. 0 = not masked."
    "This write-only register is used to disable interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
    "This write-only register is used to enable interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change."
    "This read-only register shows the current masking of the interrupts for the PCI bus.  There is one bit per"
    "interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to that bit is"
    "currently masked.  Masking does not prevent the interrupt from appearing in the status register."
    "\nFor each bit: 1 = masked. 0 = not masked."
    "This write-only register is used to disable interrupts for the PCI bus.  There is one bit per interrupt source."
    "Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing a 0 has no"
    "effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros written "
    "to them are not affected."
    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
    "This write-only register is used to enable interrupts for the PCI bus.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change.",
#endif
    LPORT_INTR_0_PCI_MASK_SET_REG_OFFSET,
    0,
    0,
    281,
#if RU_INCLUDE_ACCESS
    ru_access_rw,
#endif
#if RU_INCLUDE_FIELD_DB
    13,
    LPORT_INTR_0_PCI_MASK_SET_FIELDS,
#endif /* RU_INCLUDE_FIELD_DB */
    ru_reg_size_32
};

/******************************************************************************
 * Register: LPORT_INTR_0_PCI_MASK_CLEAR
 ******************************************************************************/
#if RU_INCLUDE_FIELD_DB
static const ru_field_rec *LPORT_INTR_0_PCI_MASK_CLEAR_FIELDS[] =
{
    &LPORT_INTR_0_PCI_MASK_CLEAR_RESERVED0_FIELD,
    &LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD,
    &LPORT_INTR_0_PCI_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD,
};

#endif /* RU_INCLUDE_FIELD_DB */

const ru_reg_rec LPORT_INTR_0_PCI_MASK_CLEAR_REG = 
{
    "0_PCI_MASK_CLEAR",
#if RU_INCLUDE_DESC
    "PCI interrupt Mask Clear Register",
    "This read-only register shows the current masking of the interrupts for the CPU processor.  There is one "
    "bit per interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to "
    "that bit is currently masked.  Masking does not prevent the interrupt from appearing in the status register."
    "\nFor each bit: 1 = masked. 0 = not masked."
    "This write-only register is used to disable interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
    "This write-only register is used to enable interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change."
    "This read-only register shows the current masking of the interrupts for the PCI bus.  There is one bit per"
    "interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to that bit is"
    "currently masked.  Masking does not prevent the interrupt from appearing in the status register."
    "\nFor each bit: 1 = masked. 0 = not masked."
    "This write-only register is used to disable interrupts for the PCI bus.  There is one bit per interrupt source."
    "Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing a 0 has no"
    "effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros written "
    "to them are not affected."
    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
    "This write-only register is used to enable interrupts for the PCI bus.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change.",
#endif
    LPORT_INTR_0_PCI_MASK_CLEAR_REG_OFFSET,
    0,
    0,
    282,
#if RU_INCLUDE_ACCESS
    ru_access_rw,
#endif
#if RU_INCLUDE_FIELD_DB
    13,
    LPORT_INTR_0_PCI_MASK_CLEAR_FIELDS,
#endif /* RU_INCLUDE_FIELD_DB */
    ru_reg_size_32
};

/******************************************************************************
 * Register: LPORT_INTR_1_CPU_STATUS
 ******************************************************************************/
#if RU_INCLUDE_FIELD_DB
static const ru_field_rec *LPORT_INTR_1_CPU_STATUS_FIELDS[] =
{
    &LPORT_INTR_1_CPU_STATUS_RESERVED0_FIELD,
    &LPORT_INTR_1_CPU_STATUS_MAB_STATUS_INTR_FIELD,
    &LPORT_INTR_1_CPU_STATUS_RX_REMOTE_FAULT_INTR_FIELD,
    &LPORT_INTR_1_CPU_STATUS_DSERDES_SD_OFF_INTR_FIELD,
    &LPORT_INTR_1_CPU_STATUS_DSERDES_SD_ON_INTR_FIELD,
    &LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD,
    &LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD,
};

#endif /* RU_INCLUDE_FIELD_DB */

const ru_reg_rec LPORT_INTR_1_CPU_STATUS_REG = 
{
    "1_CPU_STATUS",
#if RU_INCLUDE_DESC
    "PCI interrupt Clear Register",
    "This read-only register shows the current status of the interrupts for the CPU processor.  There is one "
    "bit per interrupt source.  The assertion of any of these interrupts will cause an interrupt to the CPU "
    "processor if the interrupt's mask bit is zero."
    "\nFor each bit: 1 = asserted. 0 = not asserted."
    "This write-only register is used to set interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
    "This write-only register is used to clear interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change."
    "This read-only register shows the current status of the interrupts for the PCI bus.  There is one bit per "
    "interrupt source.  The assertion of any of these interrupts will cause an interrupt to the PCI bus if the"
    "interrupt's mask bit is zero."
    "\nFor each bit: 1 = asserted. 0 = not asserted."
    "This write-only register is used to set interrupts for the PCI bus.  There is one bit per interrupt source."
    "Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing a 0 has "
    "no effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros "
    "written to them are not affected."
    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
    "This write-only register is used to clear interrupts for the PCI bus.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change.",
#endif
    LPORT_INTR_1_CPU_STATUS_REG_OFFSET,
    0,
    0,
    283,
#if RU_INCLUDE_ACCESS
    ru_access_rw,
#endif
#if RU_INCLUDE_FIELD_DB
    7,
    LPORT_INTR_1_CPU_STATUS_FIELDS,
#endif /* RU_INCLUDE_FIELD_DB */
    ru_reg_size_32
};

/******************************************************************************
 * Register: LPORT_INTR_1_CPU_SET
 ******************************************************************************/
#if RU_INCLUDE_FIELD_DB
static const ru_field_rec *LPORT_INTR_1_CPU_SET_FIELDS[] =
{
    &LPORT_INTR_1_CPU_SET_RESERVED0_FIELD,
    &LPORT_INTR_1_CPU_SET_MAB_STATUS_INTR_FIELD,
    &LPORT_INTR_1_CPU_SET_RX_REMOTE_FAULT_INTR_FIELD,
    &LPORT_INTR_1_CPU_SET_DSERDES_SD_OFF_INTR_FIELD,
    &LPORT_INTR_1_CPU_SET_DSERDES_SD_ON_INTR_FIELD,
    &LPORT_INTR_1_CPU_SET_LINK_DOWN_INTR_FIELD,
    &LPORT_INTR_1_CPU_SET_LINK_UP_INTR_FIELD,
};

#endif /* RU_INCLUDE_FIELD_DB */

const ru_reg_rec LPORT_INTR_1_CPU_SET_REG = 
{
    "1_CPU_SET",
#if RU_INCLUDE_DESC
    "PCI interrupt Clear Register",
    "This read-only register shows the current status of the interrupts for the CPU processor.  There is one "
    "bit per interrupt source.  The assertion of any of these interrupts will cause an interrupt to the CPU "
    "processor if the interrupt's mask bit is zero."
    "\nFor each bit: 1 = asserted. 0 = not asserted."
    "This write-only register is used to set interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
    "This write-only register is used to clear interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change."
    "This read-only register shows the current status of the interrupts for the PCI bus.  There is one bit per "
    "interrupt source.  The assertion of any of these interrupts will cause an interrupt to the PCI bus if the"
    "interrupt's mask bit is zero."
    "\nFor each bit: 1 = asserted. 0 = not asserted."
    "This write-only register is used to set interrupts for the PCI bus.  There is one bit per interrupt source."
    "Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing a 0 has "
    "no effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros "
    "written to them are not affected."
    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
    "This write-only register is used to clear interrupts for the PCI bus.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change.",
#endif
    LPORT_INTR_1_CPU_SET_REG_OFFSET,
    0,
    0,
    284,
#if RU_INCLUDE_ACCESS
    ru_access_rw,
#endif
#if RU_INCLUDE_FIELD_DB
    7,
    LPORT_INTR_1_CPU_SET_FIELDS,
#endif /* RU_INCLUDE_FIELD_DB */
    ru_reg_size_32
};

/******************************************************************************
 * Register: LPORT_INTR_1_CPU_CLEAR
 ******************************************************************************/
#if RU_INCLUDE_FIELD_DB
static const ru_field_rec *LPORT_INTR_1_CPU_CLEAR_FIELDS[] =
{
    &LPORT_INTR_1_CPU_CLEAR_RESERVED0_FIELD,
    &LPORT_INTR_1_CPU_CLEAR_MAB_STATUS_INTR_FIELD,
    &LPORT_INTR_1_CPU_CLEAR_RX_REMOTE_FAULT_INTR_FIELD,
    &LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_OFF_INTR_FIELD,
    &LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_ON_INTR_FIELD,
    &LPORT_INTR_1_CPU_CLEAR_LINK_DOWN_INTR_FIELD,
    &LPORT_INTR_1_CPU_CLEAR_LINK_UP_INTR_FIELD,
};

#endif /* RU_INCLUDE_FIELD_DB */

const ru_reg_rec LPORT_INTR_1_CPU_CLEAR_REG = 
{
    "1_CPU_CLEAR",
#if RU_INCLUDE_DESC
    "PCI interrupt Clear Register",
    "This read-only register shows the current status of the interrupts for the CPU processor.  There is one "
    "bit per interrupt source.  The assertion of any of these interrupts will cause an interrupt to the CPU "
    "processor if the interrupt's mask bit is zero."
    "\nFor each bit: 1 = asserted. 0 = not asserted."
    "This write-only register is used to set interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
    "This write-only register is used to clear interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change."
    "This read-only register shows the current status of the interrupts for the PCI bus.  There is one bit per "
    "interrupt source.  The assertion of any of these interrupts will cause an interrupt to the PCI bus if the"
    "interrupt's mask bit is zero."
    "\nFor each bit: 1 = asserted. 0 = not asserted."
    "This write-only register is used to set interrupts for the PCI bus.  There is one bit per interrupt source."
    "Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing a 0 has "
    "no effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros "
    "written to them are not affected."
    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
    "This write-only register is used to clear interrupts for the PCI bus.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change.",
#endif
    LPORT_INTR_1_CPU_CLEAR_REG_OFFSET,
    0,
    0,
    285,
#if RU_INCLUDE_ACCESS
    ru_access_rw,
#endif
#if RU_INCLUDE_FIELD_DB
    7,
    LPORT_INTR_1_CPU_CLEAR_FIELDS,
#endif /* RU_INCLUDE_FIELD_DB */
    ru_reg_size_32
};

/******************************************************************************
 * Register: LPORT_INTR_1_CPU_MASK_STATUS
 ******************************************************************************/
#if RU_INCLUDE_FIELD_DB
static const ru_field_rec *LPORT_INTR_1_CPU_MASK_STATUS_FIELDS[] =
{
    &LPORT_INTR_1_CPU_MASK_STATUS_RESERVED0_FIELD,
    &LPORT_INTR_1_CPU_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD,
    &LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD,
    &LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD,
    &LPORT_INTR_1_CPU_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD,
    &LPORT_INTR_1_CPU_MASK_STATUS_LINK_UP_INTR_MASK_FIELD,
};

#endif /* RU_INCLUDE_FIELD_DB */

const ru_reg_rec LPORT_INTR_1_CPU_MASK_STATUS_REG = 
{
    "1_CPU_MASK_STATUS",
#if RU_INCLUDE_DESC
    "PCI interrupt Mask Clear Register",
    "This read-only register shows the current masking of the interrupts for the CPU processor.  There is one "
    "bit per interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to "
    "that bit is currently masked.  Masking does not prevent the interrupt from appearing in the status register."
    "\nFor each bit: 1 = masked. 0 = not masked."
    "This write-only register is used to disable interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
    "This write-only register is used to enable interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change."
    "This read-only register shows the current masking of the interrupts for the PCI bus.  There is one bit per"
    "interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to that bit is"
    "currently masked.  Masking does not prevent the interrupt from appearing in the status register."
    "\nFor each bit: 1 = masked. 0 = not masked."
    "This write-only register is used to disable interrupts for the PCI bus.  There is one bit per interrupt source."
    "Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing a 0 has no"
    "effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros written "
    "to them are not affected."
    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
    "This write-only register is used to enable interrupts for the PCI bus.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change.",
#endif
    LPORT_INTR_1_CPU_MASK_STATUS_REG_OFFSET,
    0,
    0,
    286,
#if RU_INCLUDE_ACCESS
    ru_access_rw,
#endif
#if RU_INCLUDE_FIELD_DB
    6,
    LPORT_INTR_1_CPU_MASK_STATUS_FIELDS,
#endif /* RU_INCLUDE_FIELD_DB */
    ru_reg_size_32
};

/******************************************************************************
 * Register: LPORT_INTR_1_CPU_MASK_SET
 ******************************************************************************/
#if RU_INCLUDE_FIELD_DB
static const ru_field_rec *LPORT_INTR_1_CPU_MASK_SET_FIELDS[] =
{
    &LPORT_INTR_1_CPU_MASK_SET_RESERVED0_FIELD,
    &LPORT_INTR_1_CPU_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD,
    &LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_OFF_INTR_FIELD,
    &LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_ON_INTR_FIELD,
    &LPORT_INTR_1_CPU_MASK_SET_LINK_DOWN_INTR_MASK_FIELD,
    &LPORT_INTR_1_CPU_MASK_SET_LINK_UP_INTR_MASK_FIELD,
};

#endif /* RU_INCLUDE_FIELD_DB */

const ru_reg_rec LPORT_INTR_1_CPU_MASK_SET_REG = 
{
    "1_CPU_MASK_SET",
#if RU_INCLUDE_DESC
    "PCI interrupt Mask Clear Register",
    "This read-only register shows the current masking of the interrupts for the CPU processor.  There is one "
    "bit per interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to "
    "that bit is currently masked.  Masking does not prevent the interrupt from appearing in the status register."
    "\nFor each bit: 1 = masked. 0 = not masked."
    "This write-only register is used to disable interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
    "This write-only register is used to enable interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change."
    "This read-only register shows the current masking of the interrupts for the PCI bus.  There is one bit per"
    "interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to that bit is"
    "currently masked.  Masking does not prevent the interrupt from appearing in the status register."
    "\nFor each bit: 1 = masked. 0 = not masked."
    "This write-only register is used to disable interrupts for the PCI bus.  There is one bit per interrupt source."
    "Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing a 0 has no"
    "effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros written "
    "to them are not affected."
    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
    "This write-only register is used to enable interrupts for the PCI bus.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change.",
#endif
    LPORT_INTR_1_CPU_MASK_SET_REG_OFFSET,
    0,
    0,
    287,
#if RU_INCLUDE_ACCESS
    ru_access_rw,
#endif
#if RU_INCLUDE_FIELD_DB
    6,
    LPORT_INTR_1_CPU_MASK_SET_FIELDS,
#endif /* RU_INCLUDE_FIELD_DB */
    ru_reg_size_32
};

/******************************************************************************
 * Register: LPORT_INTR_1_CPU_MASK_CLEAR
 ******************************************************************************/
#if RU_INCLUDE_FIELD_DB
static const ru_field_rec *LPORT_INTR_1_CPU_MASK_CLEAR_FIELDS[] =
{
    &LPORT_INTR_1_CPU_MASK_CLEAR_RESERVED0_FIELD,
    &LPORT_INTR_1_CPU_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD,
    &LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD,
    &LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD,
    &LPORT_INTR_1_CPU_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD,
    &LPORT_INTR_1_CPU_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD,
};

#endif /* RU_INCLUDE_FIELD_DB */

const ru_reg_rec LPORT_INTR_1_CPU_MASK_CLEAR_REG = 
{
    "1_CPU_MASK_CLEAR",
#if RU_INCLUDE_DESC
    "PCI interrupt Mask Clear Register",
    "This read-only register shows the current masking of the interrupts for the CPU processor.  There is one "
    "bit per interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to "
    "that bit is currently masked.  Masking does not prevent the interrupt from appearing in the status register."
    "\nFor each bit: 1 = masked. 0 = not masked."
    "This write-only register is used to disable interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
    "This write-only register is used to enable interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change."
    "This read-only register shows the current masking of the interrupts for the PCI bus.  There is one bit per"
    "interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to that bit is"
    "currently masked.  Masking does not prevent the interrupt from appearing in the status register."
    "\nFor each bit: 1 = masked. 0 = not masked."
    "This write-only register is used to disable interrupts for the PCI bus.  There is one bit per interrupt source."
    "Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing a 0 has no"
    "effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros written "
    "to them are not affected."
    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
    "This write-only register is used to enable interrupts for the PCI bus.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change.",
#endif
    LPORT_INTR_1_CPU_MASK_CLEAR_REG_OFFSET,
    0,
    0,
    288,
#if RU_INCLUDE_ACCESS
    ru_access_rw,
#endif
#if RU_INCLUDE_FIELD_DB
    6,
    LPORT_INTR_1_CPU_MASK_CLEAR_FIELDS,
#endif /* RU_INCLUDE_FIELD_DB */
    ru_reg_size_32
};

/******************************************************************************
 * Register: LPORT_INTR_1_PCI_STATUS
 ******************************************************************************/
#if RU_INCLUDE_FIELD_DB
static const ru_field_rec *LPORT_INTR_1_PCI_STATUS_FIELDS[] =
{
    &LPORT_INTR_1_PCI_STATUS_RESERVED0_FIELD,
    &LPORT_INTR_1_PCI_STATUS_MAB_STATUS_INTR_FIELD,
    &LPORT_INTR_1_PCI_STATUS_RX_REMOTE_FAULT_INTR_FIELD,
    &LPORT_INTR_1_PCI_STATUS_DSERDES_SD_OFF_INTR_FIELD,
    &LPORT_INTR_1_PCI_STATUS_DSERDES_SD_ON_INTR_FIELD,
    &LPORT_INTR_1_PCI_STATUS_LINK_DOWN_INTR_FIELD,
    &LPORT_INTR_1_PCI_STATUS_LINK_UP_INTR_FIELD,
};

#endif /* RU_INCLUDE_FIELD_DB */

const ru_reg_rec LPORT_INTR_1_PCI_STATUS_REG = 
{
    "1_PCI_STATUS",
#if RU_INCLUDE_DESC
    "PCI interrupt Clear Register",
    "This read-only register shows the current status of the interrupts for the CPU processor.  There is one "
    "bit per interrupt source.  The assertion of any of these interrupts will cause an interrupt to the CPU "
    "processor if the interrupt's mask bit is zero."
    "\nFor each bit: 1 = asserted. 0 = not asserted."
    "This write-only register is used to set interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
    "This write-only register is used to clear interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change."
    "This read-only register shows the current status of the interrupts for the PCI bus.  There is one bit per "
    "interrupt source.  The assertion of any of these interrupts will cause an interrupt to the PCI bus if the"
    "interrupt's mask bit is zero."
    "\nFor each bit: 1 = asserted. 0 = not asserted."
    "This write-only register is used to set interrupts for the PCI bus.  There is one bit per interrupt source."
    "Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing a 0 has "
    "no effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros "
    "written to them are not affected."
    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
    "This write-only register is used to clear interrupts for the PCI bus.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change.",
#endif
    LPORT_INTR_1_PCI_STATUS_REG_OFFSET,
    0,
    0,
    289,
#if RU_INCLUDE_ACCESS
    ru_access_rw,
#endif
#if RU_INCLUDE_FIELD_DB
    7,
    LPORT_INTR_1_PCI_STATUS_FIELDS,
#endif /* RU_INCLUDE_FIELD_DB */
    ru_reg_size_32
};

/******************************************************************************
 * Register: LPORT_INTR_1_PCI_SET
 ******************************************************************************/
#if RU_INCLUDE_FIELD_DB
static const ru_field_rec *LPORT_INTR_1_PCI_SET_FIELDS[] =
{
    &LPORT_INTR_1_PCI_SET_RESERVED0_FIELD,
    &LPORT_INTR_1_PCI_SET_MAB_STATUS_INTR_FIELD,
    &LPORT_INTR_1_PCI_SET_RX_REMOTE_FAULT_INTR_FIELD,
    &LPORT_INTR_1_PCI_SET_DSERDES_SD_OFF_INTR_FIELD,
    &LPORT_INTR_1_PCI_SET_DSERDES_SD_ON_INTR_FIELD,
    &LPORT_INTR_1_PCI_SET_LINK_DOWN_INTR_FIELD,
    &LPORT_INTR_1_PCI_SET_LINK_UP_INTR_FIELD,
};

#endif /* RU_INCLUDE_FIELD_DB */

const ru_reg_rec LPORT_INTR_1_PCI_SET_REG = 
{
    "1_PCI_SET",
#if RU_INCLUDE_DESC
    "PCI interrupt Clear Register",
    "This read-only register shows the current status of the interrupts for the CPU processor.  There is one "
    "bit per interrupt source.  The assertion of any of these interrupts will cause an interrupt to the CPU "
    "processor if the interrupt's mask bit is zero."
    "\nFor each bit: 1 = asserted. 0 = not asserted."
    "This write-only register is used to set interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
    "This write-only register is used to clear interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change."
    "This read-only register shows the current status of the interrupts for the PCI bus.  There is one bit per "
    "interrupt source.  The assertion of any of these interrupts will cause an interrupt to the PCI bus if the"
    "interrupt's mask bit is zero."
    "\nFor each bit: 1 = asserted. 0 = not asserted."
    "This write-only register is used to set interrupts for the PCI bus.  There is one bit per interrupt source."
    "Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing a 0 has "
    "no effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros "
    "written to them are not affected."
    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
    "This write-only register is used to clear interrupts for the PCI bus.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change.",
#endif
    LPORT_INTR_1_PCI_SET_REG_OFFSET,
    0,
    0,
    290,
#if RU_INCLUDE_ACCESS
    ru_access_rw,
#endif
#if RU_INCLUDE_FIELD_DB
    7,
    LPORT_INTR_1_PCI_SET_FIELDS,
#endif /* RU_INCLUDE_FIELD_DB */
    ru_reg_size_32
};

/******************************************************************************
 * Register: LPORT_INTR_1_PCI_CLEAR
 ******************************************************************************/
#if RU_INCLUDE_FIELD_DB
static const ru_field_rec *LPORT_INTR_1_PCI_CLEAR_FIELDS[] =
{
    &LPORT_INTR_1_PCI_CLEAR_RESERVED0_FIELD,
    &LPORT_INTR_1_PCI_CLEAR_MAB_STATUS_INTR_FIELD,
    &LPORT_INTR_1_PCI_CLEAR_RX_REMOTE_FAULT_INTR_FIELD,
    &LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_OFF_INTR_FIELD,
    &LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_ON_INTR_FIELD,
    &LPORT_INTR_1_PCI_CLEAR_LINK_DOWN_INTR_FIELD,
    &LPORT_INTR_1_PCI_CLEAR_LINK_UP_INTR_FIELD,
};

#endif /* RU_INCLUDE_FIELD_DB */

const ru_reg_rec LPORT_INTR_1_PCI_CLEAR_REG = 
{
    "1_PCI_CLEAR",
#if RU_INCLUDE_DESC
    "PCI interrupt Clear Register",
    "This read-only register shows the current status of the interrupts for the CPU processor.  There is one "
    "bit per interrupt source.  The assertion of any of these interrupts will cause an interrupt to the CPU "
    "processor if the interrupt's mask bit is zero."
    "\nFor each bit: 1 = asserted. 0 = not asserted."
    "This write-only register is used to set interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
    "This write-only register is used to clear interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change."
    "This read-only register shows the current status of the interrupts for the PCI bus.  There is one bit per "
    "interrupt source.  The assertion of any of these interrupts will cause an interrupt to the PCI bus if the"
    "interrupt's mask bit is zero."
    "\nFor each bit: 1 = asserted. 0 = not asserted."
    "This write-only register is used to set interrupts for the PCI bus.  There is one bit per interrupt source."
    "Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing a 0 has "
    "no effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros "
    "written to them are not affected."
    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
    "This write-only register is used to clear interrupts for the PCI bus.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change.",
#endif
    LPORT_INTR_1_PCI_CLEAR_REG_OFFSET,
    0,
    0,
    291,
#if RU_INCLUDE_ACCESS
    ru_access_rw,
#endif
#if RU_INCLUDE_FIELD_DB
    7,
    LPORT_INTR_1_PCI_CLEAR_FIELDS,
#endif /* RU_INCLUDE_FIELD_DB */
    ru_reg_size_32
};

/******************************************************************************
 * Register: LPORT_INTR_1_PCI_MASK_STATUS
 ******************************************************************************/
#if RU_INCLUDE_FIELD_DB
static const ru_field_rec *LPORT_INTR_1_PCI_MASK_STATUS_FIELDS[] =
{
    &LPORT_INTR_1_PCI_MASK_STATUS_RESERVED0_FIELD,
    &LPORT_INTR_1_PCI_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD,
    &LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD,
    &LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD,
    &LPORT_INTR_1_PCI_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD,
    &LPORT_INTR_1_PCI_MASK_STATUS_LINK_UP_INTR_MASK_FIELD,
};

#endif /* RU_INCLUDE_FIELD_DB */

const ru_reg_rec LPORT_INTR_1_PCI_MASK_STATUS_REG = 
{
    "1_PCI_MASK_STATUS",
#if RU_INCLUDE_DESC
    "PCI interrupt Mask Clear Register",
    "This read-only register shows the current masking of the interrupts for the CPU processor.  There is one "
    "bit per interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to "
    "that bit is currently masked.  Masking does not prevent the interrupt from appearing in the status register."
    "\nFor each bit: 1 = masked. 0 = not masked."
    "This write-only register is used to disable interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
    "This write-only register is used to enable interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change."
    "This read-only register shows the current masking of the interrupts for the PCI bus.  There is one bit per"
    "interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to that bit is"
    "currently masked.  Masking does not prevent the interrupt from appearing in the status register."
    "\nFor each bit: 1 = masked. 0 = not masked."
    "This write-only register is used to disable interrupts for the PCI bus.  There is one bit per interrupt source."
    "Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing a 0 has no"
    "effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros written "
    "to them are not affected."
    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
    "This write-only register is used to enable interrupts for the PCI bus.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change.",
#endif
    LPORT_INTR_1_PCI_MASK_STATUS_REG_OFFSET,
    0,
    0,
    292,
#if RU_INCLUDE_ACCESS
    ru_access_rw,
#endif
#if RU_INCLUDE_FIELD_DB
    6,
    LPORT_INTR_1_PCI_MASK_STATUS_FIELDS,
#endif /* RU_INCLUDE_FIELD_DB */
    ru_reg_size_32
};

/******************************************************************************
 * Register: LPORT_INTR_1_PCI_MASK_SET
 ******************************************************************************/
#if RU_INCLUDE_FIELD_DB
static const ru_field_rec *LPORT_INTR_1_PCI_MASK_SET_FIELDS[] =
{
    &LPORT_INTR_1_PCI_MASK_SET_RESERVED0_FIELD,
    &LPORT_INTR_1_PCI_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD,
    &LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_OFF_INTR_FIELD,
    &LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_ON_INTR_FIELD,
    &LPORT_INTR_1_PCI_MASK_SET_LINK_DOWN_INTR_MASK_FIELD,
    &LPORT_INTR_1_PCI_MASK_SET_LINK_UP_INTR_MASK_FIELD,
};

#endif /* RU_INCLUDE_FIELD_DB */

const ru_reg_rec LPORT_INTR_1_PCI_MASK_SET_REG = 
{
    "1_PCI_MASK_SET",
#if RU_INCLUDE_DESC
    "PCI interrupt Mask Clear Register",
    "This read-only register shows the current masking of the interrupts for the CPU processor.  There is one "
    "bit per interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to "
    "that bit is currently masked.  Masking does not prevent the interrupt from appearing in the status register."
    "\nFor each bit: 1 = masked. 0 = not masked."
    "This write-only register is used to disable interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
    "This write-only register is used to enable interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change."
    "This read-only register shows the current masking of the interrupts for the PCI bus.  There is one bit per"
    "interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to that bit is"
    "currently masked.  Masking does not prevent the interrupt from appearing in the status register."
    "\nFor each bit: 1 = masked. 0 = not masked."
    "This write-only register is used to disable interrupts for the PCI bus.  There is one bit per interrupt source."
    "Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing a 0 has no"
    "effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros written "
    "to them are not affected."
    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
    "This write-only register is used to enable interrupts for the PCI bus.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change.",
#endif
    LPORT_INTR_1_PCI_MASK_SET_REG_OFFSET,
    0,
    0,
    293,
#if RU_INCLUDE_ACCESS
    ru_access_rw,
#endif
#if RU_INCLUDE_FIELD_DB
    6,
    LPORT_INTR_1_PCI_MASK_SET_FIELDS,
#endif /* RU_INCLUDE_FIELD_DB */
    ru_reg_size_32
};

/******************************************************************************
 * Register: LPORT_INTR_1_PCI_MASK_CLEAR
 ******************************************************************************/
#if RU_INCLUDE_FIELD_DB
static const ru_field_rec *LPORT_INTR_1_PCI_MASK_CLEAR_FIELDS[] =
{
    &LPORT_INTR_1_PCI_MASK_CLEAR_RESERVED0_FIELD,
    &LPORT_INTR_1_PCI_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD,
    &LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD,
    &LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD,
    &LPORT_INTR_1_PCI_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD,
    &LPORT_INTR_1_PCI_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD,
};

#endif /* RU_INCLUDE_FIELD_DB */

const ru_reg_rec LPORT_INTR_1_PCI_MASK_CLEAR_REG = 
{
    "1_PCI_MASK_CLEAR",
#if RU_INCLUDE_DESC
    "PCI interrupt Mask Clear Register",
    "This read-only register shows the current masking of the interrupts for the CPU processor.  There is one "
    "bit per interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to "
    "that bit is currently masked.  Masking does not prevent the interrupt from appearing in the status register."
    "\nFor each bit: 1 = masked. 0 = not masked."
    "This write-only register is used to disable interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
    "This write-only register is used to enable interrupts for the CPU processor.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change."
    "This read-only register shows the current masking of the interrupts for the PCI bus.  There is one bit per"
    "interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to that bit is"
    "currently masked.  Masking does not prevent the interrupt from appearing in the status register."
    "\nFor each bit: 1 = masked. 0 = not masked."
    "This write-only register is used to disable interrupts for the PCI bus.  There is one bit per interrupt source."
    "Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing a 0 has no"
    "effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros written "
    "to them are not affected."
    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
    "This write-only register is used to enable interrupts for the PCI bus.  There is one bit per interrupt "
    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
    "zeros written to them are not affected."
    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change.",
#endif
    LPORT_INTR_1_PCI_MASK_CLEAR_REG_OFFSET,
    0,
    0,
    294,
#if RU_INCLUDE_ACCESS
    ru_access_rw,
#endif
#if RU_INCLUDE_FIELD_DB
    6,
    LPORT_INTR_1_PCI_MASK_CLEAR_FIELDS,
#endif /* RU_INCLUDE_FIELD_DB */
    ru_reg_size_32
};

/******************************************************************************
 * Block: LPORT_INTR
 ******************************************************************************/
static const ru_reg_rec *LPORT_INTR_REGS[] =
{
    &LPORT_INTR_0_CPU_STATUS_REG,
    &LPORT_INTR_0_CPU_SET_REG,
    &LPORT_INTR_0_CPU_CLEAR_REG,
    &LPORT_INTR_0_CPU_MASK_STATUS_REG,
    &LPORT_INTR_0_CPU_MASK_SET_REG,
    &LPORT_INTR_0_CPU_MASK_CLEAR_REG,
    &LPORT_INTR_0_PCI_STATUS_REG,
    &LPORT_INTR_0_PCI_SET_REG,
    &LPORT_INTR_0_PCI_CLEAR_REG,
    &LPORT_INTR_0_PCI_MASK_STATUS_REG,
    &LPORT_INTR_0_PCI_MASK_SET_REG,
    &LPORT_INTR_0_PCI_MASK_CLEAR_REG,
    &LPORT_INTR_1_CPU_STATUS_REG,
    &LPORT_INTR_1_CPU_SET_REG,
    &LPORT_INTR_1_CPU_CLEAR_REG,
    &LPORT_INTR_1_CPU_MASK_STATUS_REG,
    &LPORT_INTR_1_CPU_MASK_SET_REG,
    &LPORT_INTR_1_CPU_MASK_CLEAR_REG,
    &LPORT_INTR_1_PCI_STATUS_REG,
    &LPORT_INTR_1_PCI_SET_REG,
    &LPORT_INTR_1_PCI_CLEAR_REG,
    &LPORT_INTR_1_PCI_MASK_STATUS_REG,
    &LPORT_INTR_1_PCI_MASK_SET_REG,
    &LPORT_INTR_1_PCI_MASK_CLEAR_REG,
};

unsigned long LPORT_INTR_ADDRS[] =
{
    0x8013d500,
};

const ru_block_rec LPORT_INTR_BLOCK = 
{
    "LPORT_INTR",
    LPORT_INTR_ADDRS,
    1,
    24,
    LPORT_INTR_REGS
};

/* End of file BCM6858_A0LPORT_INTR.c */
